Method for setting operating parameters of an inductive amplifier and electronic device

Abstract

The present disclosure provides an inductive amplifier operating parameter setting method and an electronic device. By obtaining test condition parameters and corresponding test result data of a plurality of sample chips, the influence of each inductive amplifier operating parameter on the inductive margin index can be evaluated, and then a plurality of candidate inductive amplifier operating parameters that can maximize the inductive margin of most chips are selected. When producing a target chip, the candidate inductive amplifier operating parameters are used to test the target chip, so as to select an inductive amplifier operating parameter that can maximize the inductive margin of the target chip.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit manufacturing technology, and more specifically, to a method for setting operating parameters of an induction amplifier and an electronic device. Background Technology

[0002] Induction amplifiers are important circuit modules in Dynamic Random Access Memory (DRAM) used to amplify minute voltage changes on bit lines to write or read data from memory cells.

[0003] During bit-line data amplification, the process of data transfer between the bit line and the memory cell (i.e., the voltage change process of the bit line) is called the charge sharing process. During charge sharing, negative factors such as voltage bias, array noise, and timing all consume the charge involved in the transfer. The remaining charge during the charge sharing process is called the sense margin of the induction amplifier. Increasing the sense margin is an important goal in DRAM circuit design.

[0004] During DRAM product testing, the operating parameters of the inductors on all chips are typically set to default values. However, due to differences in manufacturing processes, the circuit performance of inductors located on different chips and wafers varies significantly. For example, the switching speed of transistors on chips with different process corners differs. The same parameter settings can lead to different sensing margins for inductors on different chips, reducing the yield of wafers with relatively poor process parameters.

[0005] Therefore, a new dynamic adjustment scheme for the operating parameters of the induction amplifier needs to be developed so that chips with different process angles can have sufficient sensing margin and improve the yield of chip manufacturing.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this disclosure is to provide a method and electronic device for setting the operating parameters of an induction amplifier, which can at least to some extent overcome the problem that the induction margin of chips with different process angles cannot be maximized due to setting uniform operating parameters of the induction amplifier.

[0008] According to a first aspect of the present disclosure, a method for setting operating parameters of an inductive amplifier is provided, comprising: acquiring multiple sets of test result data of a sample chip under multiple sets of test condition parameters; determining a first parameter value corresponding to each set of test condition parameters based on each set of test result data, and selecting candidate test condition parameters corresponding to the sample chip based on the first parameter value; acquiring multiple candidate test condition parameters corresponding to multiple sample chips under the multiple sets of test condition parameters, and determining multiple sets of candidate inductive amplifier operating parameters based on the multiple sets of candidate test condition parameters corresponding to the multiple sample chips; performing online testing on a target chip using the multiple sets of candidate inductive amplifier operating parameters to obtain online test result data corresponding to each set of candidate inductive amplifier operating parameters; calculating a loss function value corresponding to each set of online test result data, and setting a set of inductive amplifier operating parameters corresponding to the online test result data with the smallest loss function value as the inductive amplifier operating parameters of the target chip.

[0009] In an exemplary embodiment of this disclosure, the test condition parameters include a first level, a second level, and an offset elimination duration. Determining the first parameter value corresponding to each set of test condition parameters based on each set of test result data includes: constructing a first virtual cube based on the multiple sets of test condition parameters. The first virtual cube is composed of multiple second virtual cubes, with one second virtual cube corresponding to one set of test condition parameters. Two adjacent second virtual cubes in the first virtual cube correspond to two sets of test condition parameters with two identical parameters. Calculating the second parameter value of each second virtual cube based on the test result data corresponding to each second virtual cube, and determining the first parameter value of each second virtual cube based on the second parameter value of each second virtual cube and the second parameter values ​​of its multiple adjacent second virtual cubes. That is, the first parameter value of the set of test condition parameters corresponding to the second virtual cube.

[0010] In one exemplary embodiment of this disclosure, determining the first parameter value of each second virtual cube based on the second parameter value of each second virtual cube and the second parameter values ​​of its neighboring plurality of second virtual cubes includes: determining a second virtual cube to be tested; determining a plurality of neighboring second virtual cubes of the second virtual cube to be tested in the first virtual cube; and determining the first parameter value of the second virtual cube to be tested based on the second parameter value of the second virtual cube to be tested and the second parameter values ​​of the plurality of neighboring second virtual cubes.

[0011] In an exemplary embodiment of this disclosure, determining the first parameter value of each second virtual cube based on the second parameter value of each second virtual cube and the second parameter values ​​of its neighboring second virtual cubes includes: determining a second virtual cube to be tested; determining a plurality of neighboring second virtual cubes of the second virtual cube to be tested in the first virtual cube; setting another second virtual cube adjacent to the neighboring second virtual cube in the line connecting the neighboring second virtual cube and the second virtual cube to be tested as the outer second virtual cube of the second virtual cube to be tested; and determining the first parameter value of the second virtual cube to be tested based on the second parameter value of the second virtual cube to be tested, the second parameter value of the neighboring second virtual cubes, and the second parameter value of the outer second virtual cube.

[0012] In one exemplary embodiment of this disclosure, the multiple sets of test condition parameters include a total of 7 first levels, 7 second levels, and 16 offset elimination durations. The first level, second level, and offset elimination duration in different test condition parameters are not completely the same.

[0013] In an exemplary embodiment of this disclosure, the first axis direction of the first virtual cube corresponds to the seven first levels, the second axis direction of the first virtual cube corresponds to the seven second levels, and the third axis direction of the first virtual cube corresponds to the 16 offset elimination durations. The first axis, the second axis, and the third axis are orthogonal to each other.

[0014] In one exemplary embodiment of this disclosure, selecting candidate test condition parameters corresponding to the sample chip based on the first parameter value includes: setting the preset proportion group test condition parameter with the smallest first parameter value as the candidate test condition parameter corresponding to the sample chip.

[0015] In an exemplary embodiment of this disclosure, determining multiple sets of candidate inductive amplifier operating parameters based on the candidate test condition parameters corresponding to the multiple sample chips includes: determining multiple power parameter groups and offset elimination durations corresponding to each power parameter group based on the candidate test condition parameters corresponding to the multiple sample chips, wherein each power parameter group includes a first level and a second level; determining the number of candidate test condition parameters corresponding to each power parameter group as a first evaluation value of the power parameter group, and determining the power parameter group with the largest first preset value as a preferred power parameter group; determining the number of preferred power parameter groups corresponding to each offset elimination duration as a second evaluation value of the offset elimination duration, and determining the offset elimination duration with the largest first preset value as a selected offset elimination duration; and determining the first preset value group of inductive amplifier operating parameters based on the selected offset elimination duration and the preferred power parameter group corresponding to the selected offset elimination duration.

[0016] In one exemplary embodiment of this disclosure, obtaining the candidate test condition parameters corresponding to multiple sample chips under the multiple sets of test condition parameters includes: periodically reselecting multiple sample chips, wherein the multiple sample chips belong to multiple sample wafers, and each sample wafer corresponds to multiple sample chips.

[0017] In one exemplary embodiment of this disclosure, the step of performing online testing on the target chip using the multiple sets of candidate induction amplifier operating parameters to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters includes: performing online testing on the target chip using the multiple sets of candidate induction amplifier operating parameters to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters; obtaining the standard induction amplifier operating parameters of the wafer to which the target chip belongs; and performing the online testing on the target chip using the standard induction amplifier operating parameters to obtain online test result data corresponding to the standard induction amplifier operating parameters.

[0018] In one exemplary embodiment of this disclosure, the step of calculating the loss function value corresponding to each of the online test result data and setting the candidate sensor amplifier operating parameter corresponding to the online test result data with the smallest loss function value as the sensor amplifier operating parameter of the target chip includes: calculating multiple first loss function values ​​of multiple online test result data corresponding to multiple sets of candidate sensor amplifier operating parameters; calculating a second loss function value of the online test result data corresponding to the standard sensor amplifier operating parameter; and setting the candidate sensor amplifier operating parameter or the standard sensor amplifier operating parameter corresponding to the minimum value among the multiple first loss function values ​​and the second loss function values ​​as the sensor amplifier operating parameter of the target chip.

[0019] In one exemplary embodiment of this disclosure, the step of calculating the second parameter value of each second virtual cube based on the test result data corresponding to each second virtual cube includes calculating the second parameter value of the second virtual cube according to the following formula: f=α×(λFR1+FR0)+(1-a)×|λFR1-FR0|, where f is the second parameter value, FR1 is the proportion of data 1 read failure bits in the test result data corresponding to the second virtual cube, FR0 is the proportion of data 0 read failure bits in the test result data corresponding to the second virtual cube, a is the sum and difference adjustment parameter, and λ is the zero-one bias parameter.

[0020] In one exemplary embodiment of this disclosure, determining the first parameter value of the second virtual cube under test based on the second parameter value of the second virtual cube under test and the second parameter values ​​of the plurality of adjacent second virtual cubes includes calculating according to the following formula: Wherein, Ω is the first parameter value of the second virtual cube to be tested, f(cb) is the second parameter value of the second virtual cube to be tested, f(sb) is the second parameter value of the adjacent second virtual cubes, and n is the number of adjacent second virtual cubes.

[0021] In an exemplary embodiment of this disclosure, the peripheral second virtual cube is categorized into multiple types based on its distance from the second virtual cube to be tested within the first virtual cube. Determining the first parameter value of the second virtual cube to be tested based on the second parameter value of the second virtual cube to be tested, the second parameter values ​​of the adjacent second virtual cubes, and the second parameter value of the peripheral second virtual cube includes calculation according to the following formula: Wherein, Ω is the first parameter value, f(cb) is the second parameter value of the second virtual cube to be tested, f(sb) is the second parameter value of the adjacent second virtual cube, n is the number of the adjacent second virtual cube, i is the type number of the outer second virtual cube, mi is the number of the i-th type of outer second virtual cube, wi is the calculated weight of the i-th type of outer second virtual cube, and f(obi) is the second parameter value of the i-th type of outer second virtual cube.

[0022] In one exemplary embodiment of this disclosure, calculating the loss function value corresponding to each of the online test result data includes calculating it according to the following formula: Where g is the loss function value, a is the sum and difference adjustment parameter, λ is the zero-one bias parameter, FR1 is the proportion of data 1 read failure bits in the online test result data, FR0 is the proportion of data 0 read failure bits in the online test result data, FR1POR is the proportion of data 1 read failure bits in the online test result data corresponding to the standard inductive amplifier operating parameters, and FR0POR is the proportion of data 0 read failure bits in the online test result data corresponding to the standard inductive amplifier operating parameters.

[0023] According to a second aspect of this disclosure, an electronic device is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to perform the method as described in any one of the preceding methods based on instructions stored in the memory.

[0024] This disclosure, by acquiring test condition parameters and corresponding test result data from multiple sample chips, enables the evaluation of the impact of each induction amplifier operating parameter on the induction margin index. It then selects multiple sets of candidate induction amplifier operating parameters that maximize the induction margin of most chips. During the production of the target chip, these candidate induction amplifier operating parameters are used to test the target chip, thereby selecting the induction amplifier operating parameters that maximize the induction margin of the target chip. Therefore, it overcomes the problem in related technologies where setting the induction amplifier operating parameters of all chips to default values ​​results in some chips failing to achieve maximum induction margin. By setting individual induction amplifier operating parameters for each chip to maximize its induction margin, the yield rate of chip production is improved.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a flowchart of a method for setting operating parameters of an induction amplifier in an exemplary embodiment of this disclosure.

[0028] Figure 2A This is a circuit diagram of an offset cancellation inductive amplifier.

[0029] Figure 2B This is a schematic diagram of the proportion of data 1 read failure bits and the proportion of data 0 read failure bits in one embodiment of this disclosure.

[0030] Figure 3 This is a sub-flowchart of step S2 in one embodiment of this disclosure.

[0031] Figure 4 This is a schematic diagram of a first virtual cube and a second virtual cube in one embodiment of this disclosure.

[0032] Figure 5 yes Figure 4 A schematic diagram of the second virtual cube corresponding to an offset elimination duration value in the embodiment shown.

[0033] Figure 6 yes Figure 4 A schematic diagram of the adjacent second virtual cubes of the second virtual cube in the embodiment shown.

[0034] Figure 7 This is a sub-flowchart of step S22 in one embodiment of this disclosure.

[0035] Figure 8 This is a schematic diagram of the outer second virtual cube of the second virtual cube to be tested.

[0036] Figure 9 This is a sub-flowchart of step S3 in one embodiment of this disclosure. Detailed Implementation

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0038] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0039] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a flowchart of a method for setting operating parameters of an induction amplifier in an exemplary embodiment of this disclosure.

[0041] refer to Figure 1 The induction amplifier operating parameter setting method 100 may include:

[0042] Step S1: Obtain multiple sets of test result data for the sample chip under multiple sets of test conditions and parameters;

[0043] Step S2: Determine the first parameter value corresponding to each group of test condition parameters based on each group of test result data, and select candidate test condition parameters corresponding to the sample chip based on the first parameter value;

[0044] Step S3: Under the multiple sets of test condition parameters, obtain the candidate test condition parameters corresponding to multiple sample chips, and determine multiple sets of candidate induction amplifier operating parameters based on the candidate test condition parameters corresponding to the multiple sample chips.

[0045] Step S4: Use the multiple sets of candidate induction amplifier operating parameters to perform online testing on the target chip to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters;

[0046] Step S5: Calculate the loss function value corresponding to each of the online test result data, and set the set of induction amplifier operating parameters corresponding to the online test result data with the smallest loss function value as the induction amplifier operating parameters of the target chip.

[0047] This disclosure, by acquiring test condition parameters and corresponding test result data from multiple sample chips, enables the evaluation of the impact of each induction amplifier operating parameter on the induction margin index. It then selects multiple sets of candidate induction amplifier operating parameters that maximize the induction margin of most chips. During the production of the target chip, these candidate induction amplifier operating parameters are used to test the target chip, thereby selecting the induction amplifier operating parameters that maximize the induction margin of the target chip. Therefore, it overcomes the problem in related technologies where setting the induction amplifier operating parameters of all chips to default values ​​results in some chips failing to achieve maximum induction margin. By setting individual induction amplifier operating parameters for each chip to maximize its induction margin, the yield rate of chip production is improved.

[0048] The following is a detailed explanation of each step in the method 100 for setting the operating parameters of the inductive amplifier.

[0049] In step S1, multiple sets of test result data of the sample chip under multiple sets of test conditions and parameters are obtained.

[0050] In this embodiment of the disclosure, when the inductive amplifier of the sample chip is an offset cancellation inductive amplifier, the test result data may include data 1 reading the failure bit ratio 1 and data 0 reading the failure bit ratio FR0.

[0051] As the linewidth of semiconductor memory shrinks, the capacitance of semiconductor memory cells decreases accordingly. Noise in the circuitry within the semiconductor memory can severely affect the sensing resolution of the sensing amplifier. Therefore, offset cancellation sensing amplifiers (OCSA) are typically used in semiconductor memories.

[0052] Figure 2A This is a circuit diagram of an offset cancellation inductive amplifier.

[0053] refer to Figure 2AThe offset cancellation inductive amplifier 200, i.e., OCSA, may include a first N-type transistor N1, a second N-type transistor N2, a first P-type transistor P1, a second P-type transistor P2, and a first control transistor C1 to a fifth control transistor C5.

[0054] In this configuration, the first terminals of both the first P-type transistor P1 and the second P-type transistor P2 are connected to a first level PCS, and the first terminals of both the first N-type transistor N1 and the second N-type transistor N2 are connected to a second level NCS. The second terminals of both the first P-type transistor P1 and the first N-type transistor N1 are connected to bit line BL via a fourth control transistor C4. The second terminals of both the second P-type transistor P2 and the second N-type transistor N2 are connected to complementary bit line BLB via a fifth control transistor C5. Bit line BL and complementary bit line BLB are connected via first control transistor C1 and second control transistor C2, both controlled by control signal ISO. Simultaneously, the second terminal of the second P-type transistor P2 is also connected to the upper plate Vad of the storage capacitor C in the storage cell 21 via a third control transistor C3. The fourth control transistor C4 and the fifth control transistor C5 are both controlled by control signal NcEN, and the third control transistor C3 is controlled by pre-charge control signal Pre.

[0055] Depend on Figure 2A It can be seen that the bit line BL of the OCSA can be connected to the upper plate Vap of the storage capacitor C in the storage cell 21 through the storage transistor MC. Compared with the conventional inductive amplifier, the OCSA adds an offset cancellation stage to the readout circuit before data readout, so as to eliminate the conduction difference between the first N-type transistor N1 and the second N-type transistor N2 in the amplifier circuit, as well as the conduction difference between the first P-type transistor P1 and the second P-type transistor P2.

[0056] In this embodiment of the disclosure, a set of test condition parameters constitutes a set of OCSA operating parameters. These OCSA operating parameters may include, for example, a first level (PCS), a second level (NCS), offset cancellation time (tNC), etc. The offset cancellation time (tNC) is the time taken for the OCSA to perform offset cancellation.

[0057] Figure 2B This is a schematic diagram of the proportion of data 1 read failure bits and the proportion of data 0 read failure bits in one embodiment of this disclosure.

[0058] refer to Figure 2BUsing the voltage VAP on the electrode plate of the storage capacitor as the horizontal axis and the FBC (Fail Bit Count) or the failure rate (FR) of the storage cells during data reading as the vertical axis (in this embodiment, the vertical axis is FR), a sense margin curve (SM) of the chip is plotted. Figure 2B As can be seen, the SM curve exhibits a distinct bathtub shape, and the failure at the bottom of the curve is caused by a hard failure. The FR variation at the curve boundaries (upper and lower edges) is caused by the induction margin.

[0059] For OCSA, before data readout, the bit line BL, complementary bit line BLB, readout bit line SABL, and complementary readout bit line SABLB are pre-charged to a preset voltage via the pre-charge signal PRE. The preset voltage is VDD / 2, where VDD is the chip's internal power supply voltage, approximately 1V. In other embodiments, the preset voltage can be set according to the specific application scenario. (See reference) Figure 2B FR0 is the bit failure ratio (FR) corresponding to the read data "0" when the voltage value of the upper plate Vap of the memory cell capacitor is the set value V0, that is, the failure bit ratio read by data 0, where the voltage value of V0 is less than the pre-charge voltage VDD / 2; FR1 is the bit failure ratio (FR) corresponding to the read data "1" when the voltage value of the upper plate Vap of the memory cell capacitor is the set value V1, that is, the failure bit ratio read by data 1, where the voltage value of V1 is greater than the preset voltage VDD / 2.

[0060] Based on the SM curve, the relationship between the voltage VAP and FR on the upper electrode plate of the storage capacitor can be obtained. When the storage cell stores data "0" and VAP is less than V0, or when the storage cell stores data "1" and VAP is greater than V1, the corresponding FR is greater than 1 / 10. 4 This means that more than 1 / 10 of the chip is... 4 The probability of damage is too high, making it impossible to adjust the sensing margin to enable normal data amplification and readout of the chip. Therefore, the FR is set to 1 / 10. 4 The VAP range (V0, V1) corresponding to the time is set as the sensing boundary range of the OCSA. The difference between V0 and VDD / 2 is the sensing boundary SM0 for data 0, and the difference between V1 and VDD / 2 is the sensing boundary SM1 for data 1. The sum of SM0 and SM1 is the sensing boundary SM of the current OCSA under the current operating parameters. In the SM curve shown in Figure 2, FR0 and FR1 are the FR values ​​corresponding to V0 and V1, respectively, with FR0 = FR1 = 1 / 10. 4 .

[0061] Specifically, in this embodiment of the disclosure, the FR is measured to be 1 / 10 by writing to the chip's memory array and then reading it. 4 The V0 and V1 data are used to measure the SA sensing boundary using the following formula:

[0062]

[0063] Where SM is the sensing boundary of the chip, and C cell It is the capacitance value of the memory cell capacitor in the chip, C BL It is the coupling capacitor that connects the bit lines of the memory cell.

[0064] Since the coupling capacitance of the bit line is small and can be ignored, it can be seen from formula (1) that SM is approximately equal to V1-V0.

[0065] For an OCSA, the values ​​that can be measured in the test are only the proportion of failed bits when reading data 0 with Vap set to a fixed value Vx and the proportion of failed bits when reading data 1 with Vap set to a fixed value Vy. The proportion of failed bits FR = 1 / 10 cannot be directly obtained. 4 The corresponding Vx and Vy. If you want to find the proportion of failed bits FR = 1 / 10 4 The corresponding Vx and Vy, namely V0 and V1 used to calculate the OCSA sensing margin, require continuous adjustment of Vx and Vy for multiple tests, resulting in high testing costs.

[0066] Therefore, in this embodiment of the disclosure, Vx and Vy are set to ideal values ​​V0 and V1, respectively, and the sensing margin of the OCSA under different OCSA operating parameters is evaluated by using FR0 and FR1 obtained from tests under different OCSA operating parameters.

[0067] In step S2, the first parameter value corresponding to each set of test condition parameters is determined based on the test result data of each set, and candidate test condition parameters corresponding to the sample chip are selected based on the first parameter value.

[0068] In one embodiment, step S2 can be implemented using a cubic algorithm.

[0069] Figure 3 This is a sub-flowchart of step S2 in one embodiment of this disclosure.

[0070] refer to Figure 3 In one embodiment of this disclosure, when each set of test condition parameters includes three values ​​(e.g., the first level (PCS), the second level (NCS), and the offset elimination duration (tNC) mentioned above), step S2 may include:

[0071] Step S21: Construct a first virtual cube based on multiple sets of test condition parameters. The first virtual cube is composed of multiple second virtual cubes. Each second virtual cube corresponds to a set of test condition parameters. In the first virtual cube, two adjacent second virtual cubes correspond to two sets of test condition parameters with two parameters being the same.

[0072] Step S22: Calculate the second parameter value of each second virtual cube based on the test result data corresponding to each second virtual cube, and determine the first parameter value of each second virtual cube based on the second parameter value of each second virtual cube and the second parameter values ​​of its multiple adjacent second virtual cubes, that is, the first parameter value of a set of test condition parameters corresponding to the second virtual cube.

[0073] Figure 3 The example shown is an application of the cube algorithm.

[0074] exist Figure 3 In the tests shown, each set of test results (FR0, FR1) was obtained under its corresponding test condition parameters (PCS, NCS, tNC), with the voltage Vap of the upper plate of the storage capacitor C set to... Figure 2B The values ​​V0 and V1 shown are obtained.

[0075] Figure 4 This is a schematic diagram of a first virtual cube and a second virtual cube in one embodiment of this disclosure.

[0076] refer to Figure 4 ,exist Figure 4 In the three-dimensional coordinate system on the right, multiple second virtual cubes 42 are constructed with the first level (PCS) value as the first axis, the second level (NCS) value as the second axis, and the offset elimination duration (tNC) value as the third axis. Each second virtual cube 42 corresponds to a set of test condition parameters (PCS, NCS, tNC), representing the test result data (FR0, FR1) corresponding to that set of test condition parameters. Multiple second virtual cubes 42 form a first virtual cube 41. One first virtual cube 41 corresponds to the test result data of one sample chip.

[0077] Figure 4The left side shows the test data curve matrix 400 of the sample chip. Test data curve matrix 400 includes multiple sets of test result data curves 401. Each set of test result data curves corresponds to a PCS value and an NCS value. The horizontal axis of each set of test result data curves 401 represents the offset elimination time, and the vertical axis represents the proportion of read failure bits. Specifically, the first curve 4011 corresponds to the process of the proportion of read failure bits FR1 for data 1 changing with the offset elimination time tNC under the current PCS and NCS values; the second curve 4012 corresponds to the process of the proportion of read failure bits FR1 for data 0 changing with the offset elimination time tNC under the current PCS and NCS values.

[0078] The curve corresponding to the change in tNC is as follows Figure 4 The first virtual cube 41 on the right is followed by a column of 16 second virtual cubes 42 along the third axis (tNC direction).

[0079] exist Figure 4 In the illustrated embodiment, the multiple sets of test condition parameters include a total of 7 first level PCS, 7 second level NCS, and 16 offset elimination duration tNC. The first level PCS, second level NCS, and offset elimination duration tNC in different test condition parameters are not completely the same.

[0080] Correspondingly, Figure 4 The left side includes 49 sets of test result data curves, 401.

[0081] exist Figure 4 On the right side, the first virtual cube 41 corresponds to 7 first levels PCS1 to PCS7 along its first axis, 7 second levels NCS1 to NCS7 along its second axis, and 16 offset elimination durations tNC1 to tNC16 along its third axis. The first, second, and third axes are orthogonal to each other. That is, the first virtual cube 41 is composed of 7*7*16 = 784 second virtual cubes 42.

[0082] In the first axis direction, PCS1 to PCS7 can increase gradually, and the increase can be either arithmetic progression (i.e., the difference between any two adjacent PCS values ​​is equal) or non-arithmetic progression; in the second axis direction, NCS1 to NCS7 can increase gradually, and the increase can be either arithmetic progression or non-arithmetic progression; in the third axis direction, tNC1 to tNC16 can increase gradually, and the increase can be either arithmetic progression or non-arithmetic progression.

[0083] Figure 5 yes Figure 4 A schematic diagram of the second virtual cube corresponding to an offset elimination duration value in the embodiment shown.

[0084] refer to Figure 5 ,by Figure 4 Taking the offset elimination time tNC1 in the example of the second virtual cube 42, the test condition parameters corresponding to a second virtual cube B1 are (PCS1, NCS3, tNC1), and the test condition parameters corresponding to a second virtual cube B2 are (PCS7, NCS1, tNC1). This pattern continues, allowing us to understand the test condition parameters for each second virtual cube.

[0085] observe Figure 4 and Figure 5 It can be seen that two of the two sets of test condition parameters corresponding to two adjacent second virtual cubes 42 in the first virtual cube 41 are the same. For example, if the test condition parameters corresponding to a second virtual cube are (PCS1, NCS1, tNC1), then the test condition parameters corresponding to the second virtual cubes adjacent to it in the first axis direction are (PCS2, NCS1, tNC1), the test condition parameters corresponding to the second virtual cubes adjacent to it in the second axis direction are (PCS1, NCS2, tNC1), and the test condition parameters corresponding to the second virtual cubes adjacent to it in the third axis direction are (PCS1, NCS1, tNC2).

[0086] Figure 6 yes Figure 4 A schematic diagram of the adjacent second virtual cubes of the second virtual cube in the embodiment shown.

[0087] refer to Figure 6 In the three-dimensional coordinate system, each second virtual cube 42 has 6 adjacent second virtual cubes Sb (Surrounding Block) in the first virtual cube 41.

[0088] After constructing the first virtual cube 41, in step S22, the second parameter value of each second virtual cube 42 is calculated based on the test result data (FR0, FR1) corresponding to each second virtual cube 42.

[0089] In one embodiment, the second parameter value of the second virtual cube can be calculated according to the following formula:

[0090] f=α×(λFR1+FR0)+(1-a)×|λFR1-FR0| (2)

[0091] Where f is the second parameter value, FR1 is the proportion of data 1 read failure bits corresponding to the second virtual cube, FR0 is the proportion of data 0 read failure bits corresponding to the second virtual cube, a is the sum and difference adjustment parameter, representing the weight of FR0+FR1 or |FR1-FR0|, and the value range of a is [0,1]; λ is the zero-one bias parameter, representing the weight of FR0 and FR1, and the value range of λ is [0,1].

[0092] After obtaining the second parameter value f of each second virtual cube 42, the first parameter value Ω of the second virtual cube 42 can be obtained based on the second parameter value f of each second virtual cube 42 and its adjacent second virtual cube Sb. The first parameter value Ω is used to evaluate the sensing margin of the sensing amplifier of the sample chip when the operating parameters of the sensing amplifier of the sample chip are set to the test condition parameters corresponding to a second virtual cube 42.

[0093] In one embodiment, a second virtual cube to be tested that is currently calculating the first parameter value Ω can be determined firstly, then multiple adjacent second virtual cubes Sb of the second virtual cube to be tested in the first virtual cube 41 can be determined, and finally the first parameter value Ω of the second virtual cube to be tested can be determined based on the second parameter value f of the second virtual cube to be tested and the second parameter values ​​f of the multiple adjacent second virtual cubes Sb.

[0094] The value of the first parameter Ω can be calculated using the following formula:

[0095]

[0096] Where Ω is the first parameter value of the second virtual cube to be tested, f(cb) is the second parameter value of the second virtual cube to be tested, f(sb) is the second parameter value of the adjacent second virtual cube Sb, and n is the number of adjacent second virtual cubes Sb.

[0097] exist Figure 6 In the illustrated embodiment, n can be set to 6. Alternatively, n can be set to a value such as 4 or 2, calculating only the adjacent second virtual cubes in two or one axis direction. Those skilled in the art can set the value according to their actual needs.

[0098] By using the second parameter value f corresponding to the adjacent second virtual cube Sb to calculate the first parameter value Ω of the second virtual cube under test, the impact of a test condition parameter on the sensing margin performance of the inductive amplifier within a certain numerical fluctuation range can be evaluated more accurately.

[0099] Figure 7 This is a sub-flowchart of step S22 in one embodiment of this disclosure.

[0100] refer to Figure 7 In one embodiment of this disclosure, step S22 may further include:

[0101] Step S221: Determine a second virtual cube to be tested;

[0102] Step S222: Determine multiple adjacent second virtual cubes of the second virtual cube to be tested within the first virtual cube;

[0103] Step S223: Set the second virtual cube that is adjacent to the adjacent second virtual cube in the direction of the line connecting the adjacent second virtual cube and the second virtual cube to be tested as the outer second virtual cube of the second virtual cube to be tested;

[0104] Step S224: Determine the first parameter value of the second virtual cube to be tested based on the second parameter value of the second virtual cube to be tested, the second parameter value of the adjacent second virtual cubes, and the second parameter value of the outer second virtual cubes.

[0105] exist Figure 7 In the illustrated embodiment, in addition to the adjacent second virtual cube, the second parameter values ​​of various peripheral second virtual cubes are also used to participate in the calculation of the first parameter value of the second virtual cube under test.

[0106] Figure 8 This is a schematic diagram of the outer second virtual cube of the second virtual cube to be tested.

[0107] refer to Figure 8 Depending on the direction of the line connecting the adjacent second virtual cube Sb and the second virtual cube to be tested (first axis direction, second axis direction, third axis direction), there can be multiple second virtual cubes Ob1 that are adjacent to the adjacent second virtual cube Sb, for example, Figure 8 Six of them.

[0108] Furthermore, depending on their distance from the virtual cube being measured, the outer second virtual cube can be categorized into several types, such as... Figure 8 The closer outer second virtual cube Ob1 and the farther outer second virtual cube Ob2.

[0109] refer to Figure 8 , Figure 7 In the illustrated embodiment, the first parameter value of the second virtual cube to be tested can be calculated according to the following formula:

[0110]

[0111] Where Ω is the first parameter value, f(cb) is the second parameter value of the second virtual cube to be tested, f(sb) is the second parameter value of the adjacent second virtual cubes, n is the number of adjacent second virtual cubes, i is the type number of the outer second virtual cubes, mi is the number of the i-th type of outer second virtual cubes, wi is the calculated weight of the i-th type of outer second virtual cubes, and f(obi) is the second parameter value of the i-th type of outer second virtual cubes.

[0112] In one embodiment, for the outer second virtual cube Ob1, w1 can be set to 1 / m1, where m1 is the number of outer second virtual cubes Ob1; for the outer second virtual cube Ob2, w2 can be set to 1 / m2, where m2 is the number of outer second virtual cubes Ob2. Figure 8 In the embodiment shown, n = m1 = m2 = 6, w1 = w2 = 1 / 6.

[0113] Those skilled in the art can set which second virtual cubes are peripheral second virtual cubes and set the number of each type of peripheral second virtual cube. For example, peripheral second virtual cubes Ob1 and Ob2 can be set as the same type of peripheral second virtual cube, thereby setting the number of peripheral second virtual cubes to 12. Alternatively, only the second virtual cubes with the same tNC value as the second virtual cube under test can be set as peripheral second virtual cubes. Or, the second virtual cubes located on different axes from the second virtual cube under test can be set as different types of peripheral second virtual cubes. This disclosure does not impose any special restrictions in this regard.

[0114] After calculating the first parameter value of each second virtual cube 42 corresponding to a sample chip, one or more sets of test condition parameters that can optimize the sensing margin of the sample chip can be selected based on the first parameter value.

[0115] Calculating the Ω value yields the test condition parameter with the minimum Ω value, representing the optimal sensing margin. However, many other test condition parameters may have Ω values ​​close to this minimum, and these parameters with similar Ω values ​​exhibit similar sensing margin performance. If only extreme values ​​are considered, the algorithm and model may overfit. Therefore, to avoid overfitting, the minimum Ω value can be fuzzed, selecting multiple sets of test condition parameters with smaller Ω values.

[0116] In one embodiment, the test condition parameters of a preset proportion group with the smallest first parameter value can be set as candidate test condition parameters corresponding to the sample chip. For example, the test condition parameters corresponding to the second virtual cube with the smallest Ω value (5%) can all be set as candidate test condition parameters. Figure 4 In the embodiment shown, the number of candidate test condition parameters corresponding to one sample chip is approximately 39 sets (784 * 0.05).

[0117] By fuzzing the optimal test condition parameters, the model's ability to resist overfitting can be improved.

[0118] In step S3, candidate test condition parameters corresponding to multiple sample chips are obtained under multiple sets of test condition parameters, and multiple sets of candidate induction amplifier operating parameters are determined based on the candidate test condition parameters corresponding to multiple sample chips.

[0119] Sample chips from different batches of wafers, or from different process corners of the same wafer, can be periodically selected as sample chips. This means multiple sample chips belong to multiple sample wafers, and each sample wafer corresponds to multiple sample chips. Candidate test condition parameters are collected for each sample chip to form a candidate test condition parameter pool. This method of selecting candidate test condition parameters ensures that chips from multiple process corners under the current production conditions have good sensing margins. To ensure real-time data quality, multiple sample chips can be periodically reselected.

[0120] All sample chips were tested using the same set of test condition parameters, for example, all were tested using... Figure 4 The 768 test condition parameter groups shown were tested to obtain multiple sets of test result data, namely multiple sets of FR0 values ​​and FR1 values, so as to obtain the influence of the 768 test parameters on the sensing margin of each sample chip.

[0121] After forming a pool of candidate test condition parameters using the candidate test condition parameters corresponding to each sample chip, multiple sets of candidate induction amplifier operating parameters that can enable most sample chips to achieve good induction margin can be selected from them.

[0122] The method shown in step S3 can be implemented using machine learning techniques.

[0123] Figure 9 This is a sub-flowchart of step S3 in one embodiment of this disclosure.

[0124] refer to Figure 9 In one embodiment, step S3 may include:

[0125] Step S31: Determine multiple power parameter groups and offset elimination time corresponding to each power parameter group based on the candidate test condition parameters corresponding to multiple sample chips. Each power parameter group includes a first level and a second level.

[0126] Step S32: Determine the number of candidate test condition parameters corresponding to each power parameter group as the first evaluation value of the power parameter group, and determine the first preset value of the power parameter group with the largest first evaluation value as the preferred power parameter group.

[0127] Step S33: In determining the offset elimination time corresponding to the preferred power parameter group, the number of preferred power parameter groups corresponding to each offset elimination time is determined as the second evaluation value of the offset elimination time, and the second preset value offset elimination time with the largest first evaluation value is determined as the selected offset elimination time.

[0128] Step S34: Determine the first preset value group of induction amplifier operating parameters based on the selected offset elimination time and the preferred power supply parameter group corresponding to the selected offset elimination time.

[0129] exist Figure 9 In the illustrated embodiment, it is assumed that there are N sets of candidate test condition parameters Refer1-ReferN in the candidate test condition parameter pool determined according to multiple sets of candidate test condition parameters corresponding to multiple sample chips, where Referi = (PCSi, NCSi, tNCi), i is the sequence number of the candidate test condition parameter in the candidate test condition parameter pool, 1≤i≤N.

[0130] Based on Refer1-ReferN, we obtain N power parameter groups Rpi(PCSi, NCSi) and N offset elimination times tNCi corresponding to each power parameter group Rpi(PCSi, NCSi).

[0131] Since all sample chips are tested using the same set of test conditions and parameters, there may be multiple duplicate values ​​in the N power parameter sets Rpi(PCSi, NCSi), that is, (PCSi, NCSi) may be equal to (PCSi+n, NCSi+n). A power parameter set with one value may correspond to multiple chips, where n is a natural number.

[0132] Next, determine the number of chips corresponding to each power parameter group. For example, when there are 1000 sample chips, (PCS4, NCS5) might correspond to 600 sample chips, (PCS3, NCS4) might correspond to 100 sample chips, and (PCS4, NCS3) might correspond to 200 sample chips. The first evaluation values ​​for these power parameter groups are 600, 100, and 200, respectively. Since each sample chip has multiple sets of candidate test condition parameters, different power parameter groups may correspond to one or more identical sample chips. Therefore, it is only necessary to count the number of sample chips corresponding to each power parameter group.

[0133] Finally, let the first preset value be m (m < N) and the second preset value be n (n < N). Select the m power parameter groups with the most corresponding sample chips as the preferred power parameter groups. Based on the offset elimination time tNCi corresponding to each power parameter group Rpi(PCSi, NCSi), determine the n tNC values ​​corresponding to these m preferred power parameter groups.

[0134] For example, m = 2, where (PCS4, NCS5) and (PCS3, NCS4) are the power parameter groups with the most sampled chips, respectively. In the candidate test condition parameter pool, those involving these two power parameter groups include the following candidate test condition parameters: (PCS4, NCS5, tNC1), (PCS3, NCS4, tNC1), (PCS3, NCS4, tNC2), (PCS3, NCS4, tNC3), and (PCS4, NCS5, tNC1). Therefore, the offset elimination times corresponding to these two power parameter groups are tNC1, tNC2, and tNC3, with corresponding second evaluation values ​​of 3, 1, and 1, respectively. Here, tNC1 is the offset elimination time corresponding to the chip with the most sampled chips. Assuming n = 1, tNC1 can be selected as the offset elimination time.

[0135] Finally, m sets of induction amplifier operating parameters are formed. For example, in the above example, m=2 and n=1. The induction amplifier operating parameters include (PCS4, NCS5, tNC1) and (PCS3, NCS4, tNC1).

[0136] In some embodiments, m is, for example, equal to 5, to cover chips corresponding to multiple process corners. These multiple process corners include nine process corners: TT, TS, TF, FF, FS, FT, SF, ST, and SS. Process corners are a concept used to evaluate the impact of global deviations. Each process corner represents an extreme case. For the fastest process corner, all process deviations increase the transistor's drive current, resulting in the fastest speed. However, for the slowest process corner, device speed is slowed down by process deviations. T represents the typical value. Besides the fastest and slowest process corners, there are also some cross-process corners, such as those composed of the fastest P-channel transistor (P-FET) and the slowest N-channel transistor (N-FET), or vice versa. Specifically, FF Fast-Fast (Fast NMOS-Fast PMOS) indicates that the circuit consists of the fastest P-FET and the fastest N-FET; TT Typical-Typical indicates that the circuit consists of a typical P-FET and a typical N-FET; SS Slow-Slow (Slow NMOS-Slow PMOS) indicates that the circuit consists of the slowest P-FET and the slowest N-FET; FS Fast-Slow (Fast NMOS-Slow PMOS) and SF Slow-Fast (Slow NMOS-Fast PMOS) belong to cross process corners, where FS indicates that the circuit consists of the slowest P-FET and the fastest N-FET; and SF indicates that the circuit consists of the fastest P-FET and the slowest N-FET.

[0137] based on Figure 9The machine learning algorithm shown selects the operating parameters of the induction amplifier that maximize the induction margin of most sample chips (including chips with multiple process corners).

[0138] In step S4, the target chip is tested online using multiple sets of candidate induction amplifier operating parameters to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters.

[0139] In actual production, the operating parameters of the induction amplifier selected through the above steps can be used to test a target chip, allowing for the setting of induction amplifier operating parameters that maximize the sensing margin of the target chip. By selecting a small number of induction amplifier operating parameters for testing, dynamic adjustment of the induction amplifier parameters can be completed within a limited time, avoiding a large amount of testing time.

[0140] In related technologies, process engineers typically manually set the current operating parameters of the induction amplifier based on experimental results and statistical distribution information; this is called POR setting or default setting.

[0141] In this embodiment of the disclosure, in addition to testing a target chip using the induction amplifier operating parameters selected in the above steps, the target chip can also be tested using the default induction amplifier operating parameters, so as to avoid the induction amplifier operating parameters selected in the above steps deviating too much from the default induction amplifier operating parameters.

[0142] For example, multiple sets of candidate induction amplifier operating parameters can be used to perform online testing on the target chip to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters. Then, the standard induction amplifier operating parameters of the wafer to which the target chip belongs can be obtained, and the target chip can be tested online using the standard induction amplifier operating parameters to obtain online test result data corresponding to the standard induction amplifier operating parameters.

[0143] In step S5, the loss function value corresponding to each online test result data is calculated, and the set of induction amplifier operating parameters corresponding to the online test result data with the smallest loss function value is set as the induction amplifier operating parameters of the target chip.

[0144] First, multiple first loss function values ​​can be calculated for multiple online test result data corresponding to multiple sets of candidate inductive amplifier operating parameters. When the online test result data corresponding to the standard inductive amplifier operating parameters is obtained in step S4, a second loss function value can be calculated for the online test result data corresponding to the standard inductive amplifier operating parameters.

[0145] Finally, the candidate sensor amplifier operating parameters or standard sensor amplifier operating parameters corresponding to the minimum value among multiple first loss function values ​​and second loss function values ​​are set as the sensor amplifier operating parameters of the target chip.

[0146] In one embodiment, the first loss function value and the second loss function value are calculated according to the following formula:

[0147]

[0148] Where g is the loss function value, a is the sum and difference adjustment parameter, λ is the zero-one bias parameter, FR1 is the proportion of data 1 read failure bits in the online test result data, FR0 is the proportion of data 0 read failure bits in the online test result data, FR1POR is the proportion of data 1 read failure bits in the online test result data corresponding to the standard induction amplifier operating parameters, and FR0POR is the proportion of data 0 read failure bits in the online test result data corresponding to the standard induction amplifier operating parameters.

[0149] When calculating the second loss function value, since FR0 = FR0POR and FR1 = FR1POR, the second loss function value g2 is:

[0150] g2=a×(λ+1)+(1-a)×|λ-1| (6)

[0151] The inclusion of POR data can prevent algorithm failures in extreme cases, thus avoiding the possibility of degradation.

[0152] Finally, the loss function values ​​(whether the first or the second loss function value) corresponding to each set of induction amplifier operating parameters are compared together, and the induction amplifier operating parameters with the smallest loss function value are set as the induction amplifier operating parameters of the target chip, so that the induction margin performance of the target chip is optimal.

[0153] The method provided in this disclosure allows each chip to be designated as a target chip, and the operating parameters of the sensing amplifier to be set according to the actual situation of the target chip to optimize its sensing margin performance. Existing POR data only analyzes the sensing amplifier operating parameters corresponding to chips in the TT process corner, which cannot meet the sensing margin requirements of chips in other process corners. However, the m sets of sensing amplifier operating parameters selected in this disclosure can cover chips in multiple process corners, meeting the sensing margin requirements of chips in different process corners, avoiding failures caused by product differences due to default configurations, thereby improving product yield.

[0154] Table 1 shows the experimental data on the influence of this method on the sensing margin of wafers and chips at various process corners.

[0155]

[0156] Table 1

[0157] Wherein, SM0 is the data 0 sensing margin, SM1 is the data 1 sensing margin, and SM is the total sensing margin, SM = SM0 + SM1. As shown in Table 1, the sensing margin of the chip corresponding to each process corner has significantly increased, proving that the method of this embodiment can effectively improve the sensing margin of the sensing amplifier, and maintains stability and consistency on wafers and chips at various process corners, as well as in high-temperature and low-temperature tests. In actual testing, the chip sensing margin test yield increased from 20% to 46%.

[0158] In summary, by combining test patterns and machine learning techniques to improve the sensing margin of the sensing amplifiers of each chip, the system can quickly and reliably measure the index characterizing the sensing margin during testing, automatically identify optimized parameter configurations from a limited dataset using machine learning methods, and propose a dynamic parameter setting test scheme that can be practically applied to the production line. This approach can significantly improve the sensing margin of chips at various process corners.

[0159] In exemplary embodiments of this disclosure, an electronic device capable of implementing the above-described methods is also provided. The electronic device may include: a memory; and a processor coupled to the memory, the processor being configured to execute the methods described in any of the above embodiments based on instructions stored in the memory.

[0160] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0161] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0162] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A method for setting operating parameters of an inductive amplifier, characterized in that, include: Obtain multiple sets of test result data for the sample chip under multiple sets of test conditions and parameters; Based on the test result data of each group, determine the first parameter value corresponding to the test condition parameter of each group, and select the candidate test condition parameter corresponding to the sample chip based on the first parameter value; Under the multiple sets of test condition parameters, obtain the candidate test condition parameters corresponding to multiple sample chips, and determine the multiple sets of candidate induction amplifier operating parameters based on the candidate test condition parameters corresponding to the multiple sample chips. The target chip was tested online using the multiple sets of candidate induction amplifier operating parameters to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters. Calculate the loss function value corresponding to each of the online test result data, and set the set of inductive amplifier operating parameters corresponding to the online test result data with the smallest loss function value as the inductive amplifier operating parameters of the target chip; the test condition parameters include a first level, a second level, and offset elimination duration, and determining the first parameter value corresponding to each set of test condition parameters based on each set of test result data includes: A first virtual cube is constructed based on the multiple sets of test condition parameters. The first virtual cube is composed of multiple second virtual cubes. Each second virtual cube corresponds to a set of test condition parameters. In the first virtual cube, two adjacent second virtual cubes correspond to two sets of test condition parameters with two parameters being the same. The second parameter value of each second virtual cube is calculated based on the test result data corresponding to each second virtual cube. The first parameter value of each second virtual cube is determined based on the second parameter value of each second virtual cube and the second parameter values ​​of its multiple neighboring second virtual cubes. That is, the first parameter value of a set of test condition parameters corresponding to the second virtual cube.

2. The method for setting operating parameters of an inductive amplifier as described in claim 1, characterized in that, Determining the first parameter value of each second virtual cube based on the second parameter value of each second virtual cube and the second parameter values ​​of its neighboring second virtual cubes includes: Determine a second virtual cube to be tested; Determine multiple adjacent second virtual cubes of the second virtual cube to be tested within the first virtual cube; The first parameter value of the second virtual cube to be tested is determined based on the second parameter value of the second virtual cube to be tested and the second parameter values ​​of the plurality of adjacent second virtual cubes.

3. The method for setting operating parameters of an inductive amplifier as described in claim 1, characterized in that, Determining the first parameter value of each second virtual cube based on the second parameter value of each second virtual cube and the second parameter values ​​of its neighboring second virtual cubes includes: Determine a second virtual cube to be tested; Determine multiple adjacent second virtual cubes of the second virtual cube to be tested within the first virtual cube; The adjacent second virtual cube is set as the outer second virtual cube of the second virtual cube to be tested, with the other second virtual cube adjacent to it in the direction of the line connecting the adjacent second virtual cube and the second virtual cube to be tested. The first parameter value of the second virtual cube to be tested is determined based on the second parameter value of the second virtual cube to be tested, the second parameter value of the adjacent second virtual cube, and the second parameter value of the outer second virtual cube.

4. The method for setting operating parameters of an inductive amplifier as described in claim 1, characterized in that, The multiple sets of test condition parameters include a total of 7 first levels, 7 second levels, and 16 offset elimination durations. The first level, second level, and offset elimination duration in different test condition parameters are not exactly the same.

5. The method for setting operating parameters of an inductive amplifier as described in claim 4, characterized in that, The first axis of the first virtual cube corresponds to the seven first levels, the second axis of the first virtual cube corresponds to the seven second levels, and the third axis of the first virtual cube corresponds to the 16 offset elimination durations. The first axis, the second axis, and the third axis are orthogonal to each other.

6. The method for setting operating parameters of an inductive amplifier as described in any one of claims 1-5, characterized in that, The step of selecting candidate test condition parameters corresponding to the sample chip based on the first parameter value includes: Set the preset ratio group test condition parameter with the smallest first parameter value as the candidate test condition parameter corresponding to the sample chip.

7. The method for setting operating parameters of an inductive amplifier as described in claim 1, characterized in that, The step of determining multiple sets of candidate induction amplifier operating parameters based on the candidate test condition parameters corresponding to the multiple sample chips includes: Based on the candidate test condition parameters corresponding to the multiple sample chips, multiple power parameter groups and offset elimination durations corresponding to each power parameter group are determined. Each power parameter group includes the first level and the second level. The number of candidate test condition parameters corresponding to each power parameter group is determined as the first evaluation value of the power parameter group, and the power parameter group with the largest first preset value is determined as the preferred power parameter group. In determining the offset elimination time corresponding to the preferred power parameter group, the number of preferred power parameter groups corresponding to each offset elimination time is determined as the second evaluation value of the offset elimination time, and the second preset value of offset elimination time with the largest first evaluation value is determined as the selected offset elimination time. The operating parameters of the first preset value group of induction amplifiers are determined based on the selected offset elimination time and the preferred power supply parameter group corresponding to the selected offset elimination time.

8. The method for setting operating parameters of an inductive amplifier as described in claim 1, characterized in that, The step of obtaining the candidate test condition parameters corresponding to multiple sample chips under the multiple sets of test condition parameters includes: Multiple sample chips are periodically reselected. These multiple sample chips belong to multiple sample wafers, and each sample wafer corresponds to multiple sample chips.

9. The method for setting operating parameters of an inductive amplifier as described in claim 1, characterized in that, The step of performing online testing on the target chip using the multiple sets of candidate induction amplifier operating parameters to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters includes: The target chip was tested online using the multiple sets of candidate induction amplifier operating parameters to obtain online test result data corresponding to each set of candidate induction amplifier operating parameters. Obtain the standard inductive amplifier operating parameters of the wafer to which the target chip belongs; The target chip is subjected to the online test using the standard inductive amplifier operating parameters to obtain the online test result data corresponding to the standard inductive amplifier operating parameters.

10. The method for setting operating parameters of an inductive amplifier as described in claim 9, characterized in that, The step of calculating the loss function value corresponding to each of the online test result data, and setting the candidate induction amplifier operating parameters corresponding to the online test result data with the smallest loss function value as the induction amplifier operating parameters of the target chip, includes: Calculate multiple first loss function values ​​for multiple online test result data corresponding to the multiple sets of candidate inductive amplifier operating parameters; Calculate the second loss function value of the online test result data corresponding to the operating parameters of the standard inductive amplifier; The candidate inductive amplifier operating parameters or the standard inductive amplifier operating parameters corresponding to the minimum value among multiple first loss function values ​​and second loss function values ​​are set as the inductive amplifier operating parameters of the target chip.

11. The method for setting operating parameters of an inductive amplifier as described in claim 1, characterized in that, The step of calculating the second parameter value of each second virtual cube based on the test result data corresponding to each second virtual cube includes calculating the second parameter value of the second virtual cube according to the following formula: f=α×(λFR1+FR0)+(1-a)×|λFR1-FR0|, Where f is the second parameter value, FR1 is the proportion of data 1 read failure bits in the test result data corresponding to the second virtual cube, FR0 is the proportion of data 0 read failure bits in the test result data corresponding to the second virtual cube, a is the sum and difference adjustment parameter, and λ is the zero-one bias parameter.

12. The method for setting operating parameters of an inductive amplifier as described in claim 2, characterized in that, Determining the first parameter value of the second virtual cube under test based on the second parameter value of the second virtual cube under test and the second parameter values ​​of the plurality of adjacent second virtual cubes includes calculation according to the following formula: ， Wherein, Ω is the first parameter value of the second virtual cube to be tested, f(cb) is the second parameter value of the second virtual cube to be tested, f(sb) is the second parameter value of the adjacent second virtual cubes, and n is the number of adjacent second virtual cubes.

13. The method for setting operating parameters of an inductive amplifier as described in claim 3, characterized in that, The peripheral second virtual cube is categorized into multiple types based on its distance from the second virtual cube to be tested within the first virtual cube. Determining the first parameter value of the second virtual cube to be tested based on the second parameter value of the second virtual cube to be tested, the second parameter values ​​of the adjacent second virtual cubes, and the second parameter value of the peripheral second virtual cube includes calculation using the following formula: ， Wherein, Ω is the first parameter value, f(cb) is the second parameter value of the second virtual cube to be tested, f(sb) is the second parameter value of the adjacent second virtual cube, n is the number of the adjacent second virtual cube, i is the type number of the outer second virtual cube, mi is the number of the i-th type of outer second virtual cube, wi is the calculated weight of the i-th type of outer second virtual cube, and f(obi) is the second parameter value of the i-th type of outer second virtual cube.

14. The method for setting operating parameters of an inductive amplifier as described in claim 9, characterized in that, The calculation of the loss function value corresponding to each of the online test result data includes calculation according to the following formula: ， Where g is the loss function value, a is the sum and difference adjustment parameter, λ is the zero-one bias parameter, FR1 is the proportion of data 1 read failure bits in the online test result data, FR0 is the proportion of data 0 read failure bits in the online test result data, FR1POR is the proportion of data 1 read failure bits in the online test result data corresponding to the standard inductive amplifier operating parameters, and FR0POR is the proportion of data 0 read failure bits in the online test result data corresponding to the standard inductive amplifier operating parameters.

15. An electronic device, characterized in that, include: Memory; as well as A processor coupled to the memory, the processor being configured to execute the induction amplifier operating parameter setting method as described in any one of claims 1-14 based on instructions stored in the memory.

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