LED circuit substrate structure and LED test packaging method

Abstract

An LED circuit substrate structure includes first color LEDs, second color LEDs, third color LEDs, a carrier plate, first test lines, first connecting lines, second test lines, and second connecting lines. Each first test line is located on the carrier plate and electrically connects two first color LEDs in the same pixel front pattern area in parallel. The first connecting line electrically connects two first test lines in adjacent pixel front pattern areas. Each second test line is located on the carrier plate and electrically connects two second color LEDs in the same pixel front pattern area in parallel. The second connecting line electrically connects two second test lines in adjacent pixel front pattern areas. Thus, the LED can be tested before cutting and packaging, and the failed LED can be found. The present application also relates to an LED testing and packaging method and an LED pixel package.

Claims

1. An LED circuit board structure, characterized in that, Include: Multiple first-color LEDs, each first-color LED including a first P-type electrode and a first N-type electrode; Multiple second-color LEDs, each second-color LED including a second P-type electrode and a second N-type electrode; Multiple third-color LEDs, each third-color LED comprising a third P-type electrode and a third N-type electrode; A carrier board includes a bearing surface and a bottom surface that are opposite to each other. The bearing surface includes a plurality of pixel front pattern areas that are spaced apart. The bottom surface includes a plurality of pixel back pattern areas that correspond to the plurality of pixel front pattern areas respectively. A pixel front pattern area is provided with at least two first color LEDs, at least two second color LEDs and at least two third color LEDs, and the first color LED, the second color LED and the third color LED in the pixel front pattern area form a sub-pixel. Multiple first test lines are located on the carrier board, and each of the first test lines is electrically connected in parallel to at least two first color LEDs located in the same front pattern area of ​​the pixel; Multiple first connection lines electrically connect two first test lines in adjacent frontal pattern areas of the two pixels; Multiple second test lines are located on the carrier board, and each of the second test lines is electrically connected in parallel to at least two second color LEDs located in the same front pattern area of ​​the pixel; Multiple second connection lines electrically connect two second test lines in adjacent two front pattern areas of the pixel; as well as Multiple cutting channels are located on the carrier plate and between the front pattern areas of each pixel; The plurality of first connecting lines and the plurality of second connecting lines are located in the plurality of cutting channels, the sum of the width of the cutting channel and the width of the front pattern area of ​​the pixel defines a pitch, and the ratio of the width of the cutting channel to the pitch is in the range of 0.11 to 0.

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2. The LED circuit board structure as described in claim 1, characterized in that, It also includes: Multiple third test lines are located on the bottom surface of the carrier board, and each of the third test lines is electrically connected in parallel to at least two third-color LEDs located in the same front pattern area of ​​the pixel; as well as Multiple third connection lines electrically connect two third test lines in adjacent reverse pattern areas of the two pixels.

3. The LED circuit board structure as described in claim 2, characterized in that, It also includes: Multiple front electrode pads are located on the bearing surface of the carrier plate, and at least one front electrode pad is located in the front pattern area of ​​each pixel. The at least one front electrode pad in the front pattern area of ​​a pixel is electrically connected to the first color LED, the second color LED and the third color LED in a sub-pixel of the front pattern area of ​​the pixel. Multiple conductive holes penetrate the carrier plate, with the upper end of at least one conductive hole located in the front pattern area of ​​each pixel and electrically connected to the at least one front electrode pad in the front pattern area of ​​each pixel, and the lower end of at least one conductive hole located in the back pattern area of ​​each pixel. as well as Multiple fourth connection lines are located on the bottom surface of the carrier plate and electrically connect the lower end of at least one conductive hole of two adjacent pixel reverse pattern areas.

4. The LED circuit board structure as described in claim 3, characterized in that, The plurality of third connecting lines and the plurality of fourth connecting lines are located in the plurality of cutting channels.

5. The LED circuit board structure as described in claim 3, characterized in that, It further includes a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of fourth signal lines, which are electrically connected to the plurality of first connecting lines, the plurality of second connecting lines, the plurality of third connecting lines, and the plurality of fourth connecting lines, respectively. Each of the first signal lines and each of the second signal lines extends along a first direction to two opposite edges of the carrier plate and is arranged at intervals along a second direction between the plurality of pixel front pattern areas. Each of the third signal lines and each of the fourth signal lines extends along the second direction to another two opposite edges of the carrier plate and is arranged at intervals along the first direction between the plurality of pixel back pattern areas.

6. The LED circuit board structure as described in claim 5, characterized in that, The line width of each of the first signal lines, the second signal lines, the third signal lines, and the fourth signal lines is in the range of 25μm to 40μm, and the line spacing between adjacent first signal lines and second signal lines and between adjacent third signal lines and fourth signal lines is in the range of 40μm to 50μm.

7. The LED circuit board structure as described in claim 1, characterized in that, It further includes multiple first reverse electrode pads, multiple second reverse electrode pads, multiple third reverse electrode pads, and multiple reverse electrode contact pads located on the bottom surface of the carrier board. At least one first reverse electrode pad, at least one second reverse electrode pad, at least one third reverse electrode pad, and at least one reverse electrode contact pad are located in the reverse pattern area of ​​each pixel. The at least one first reverse electrode pad in the reverse pattern area of ​​a pixel is electrically connected to at least two first-color LEDs located in the front pattern area of ​​a pixel. The at least one second reverse electrode pad in the reverse pattern area of ​​a pixel is electrically connected to at least two second-color LEDs located in the front pattern area of ​​a pixel. The at least one third reverse electrode pad in the reverse pattern area of ​​a pixel is electrically connected to at least two third-color LEDs located in the front pattern area of ​​a pixel. The at least one reverse electrode contact pad in the reverse pattern area of ​​a pixel is electrically connected to at least two first-color LEDs, at least two second-color LEDs, and at least two third-color LEDs located in the front pattern area of ​​a pixel.

8. An LED testing and packaging method, characterized in that, Include: In an LED fabrication step, a plurality of first-color LEDs, a plurality of second-color LEDs, and a plurality of third-color LEDs are fabricated onto a circuit board, wherein the circuit board comprises: A carrier board includes a bearing surface and a bottom surface that are opposite to each other. The bearing surface includes a plurality of pixel front pattern areas that are spaced apart. The bottom surface includes a plurality of pixel back pattern areas that correspond to the plurality of pixel front pattern areas. Each pixel front pattern area is provided with at least two first color LED mounting pads, at least two second color LED mounting pads and at least two third color LED mounting pads. Each first color LED mounting pad, each second color LED mounting pad and each third color LED mounting pad is adapted to mount electrodes of the same electrical nature of each of the plurality of first color LEDs, each of the plurality of second color LEDs and each of the plurality of third color LEDs. Multiple first groups of wiring, each first group of wiring includes a first test line and a first connecting line, each first test line is electrically connected in parallel to at least two first color LEDs located in the same front pattern area of ​​the pixel, and each first connecting line is electrically connected to two first test lines in two adjacent front pattern areas of the pixel. Multiple second sets of wiring, each second set of wiring including a second test line and a second connecting line, each second test line being electrically connected in parallel to at least two second color LEDs located in the same front pattern area of ​​the pixel, and each second connecting line being electrically connected to two second test lines in adjacent front pattern areas of the pixel; and Multiple cutting channels are located on the carrier board and between the front pattern areas of each pixel, wherein the multiple first test lines of the multiple first sets of wiring and the multiple second test lines of the multiple second sets of wiring are located on the multiple cutting channels; An LED testing procedure involves energizing the plurality of first sets of wiring to test each of the first color LEDs, and energizing the plurality of second sets of wiring to test each of the second color LEDs. as well as A substrate cutting step involves cutting the substrate along the plurality of cutting tracks to separate the plurality of pixel front pattern areas from each other, and cutting the plurality of first sets of wiring and second sets of wiring to form a plurality of pixels to be packaged. The sum of the width of one of the cuts and the width of the front pattern area of ​​the pixel defines a pitch, and the ratio of the width of the cut to the pitch is in the range of 0.11 to 0.

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9. The LED testing and packaging method as described in claim 8, characterized in that, It also includes: The one-pixel encapsulation step involves sealing the multiple pixel regions to be encapsulated, which are separated from each other, to form multiple LED pixel packages.

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