Display substrate and display device

Abstract

A display substrate and a display device. The display substrate has a display side, and includes a substrate (110), a drive circuit layer (120), a first electrode layer, and a pixel definition layer (1017). The drive circuit layer (120) is disposed on the substrate (110) and includes a plurality of first gaps (D1) allowing light from the display side to pass through. The first electrode layer is disposed on a side of the drive circuit layer (120) away from the substrate (110) and includes a plurality of first electrode patterns (1041) and a plurality of light shielding patterns (SH). The pixel definition layer (1017) is disposed on a side of the first electrode layer away from the substrate (110) and includes a plurality of sub-pixel openings (PO) respectively exposing the plurality of first electrode patterns (1041). In a direction perpendicular to the substrate (110), at least part of the light shielding patterns (SH) do not overlap with the plurality of sub-pixel openings (PO), and at least part of the light shielding patterns (SH) respectively correspond to and at least partially overlap with at least part of the plurality of first gaps (D1) to at least partially shield light from the display side.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) display devices have a series of advantages such as self-illumination, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. As a result, they have become one of the key development directions for next-generation display devices and have therefore received increasing attention.

[0003] Currently, display devices often also have multiple functions such as fingerprint recognition. In this case, the structure of the display device can be adjusted accordingly to accommodate these functions. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate having a display side and including a substrate, a driving circuit layer, a first electrode layer, and a pixel defining layer. The driving circuit layer is disposed on the substrate and includes a plurality of first gaps that allow light from the display side to pass through. The first electrode layer is disposed on the side of the driving circuit layer away from the substrate and includes a plurality of first electrode patterns and a plurality of light-shielding patterns. The pixel defining layer is disposed on the side of the first electrode layer away from the substrate and includes a plurality of sub-pixel openings that expose the plurality of first electrode patterns. In a direction perpendicular to the substrate, at least a portion of the plurality of light-shielding patterns does not overlap with the plurality of sub-pixel openings, and at least a portion of the plurality of light-shielding patterns corresponds to and at least partially overlaps with at least a portion of the plurality of first gaps to at least partially block light from the display side.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, the width of the plurality of first gaps is less than or equal to 4.0 micrometers.

[0006] For example, in at least one embodiment of the display substrate provided in this disclosure, the distance between the plurality of first gaps and the center of the plurality of sub-pixel openings is less than 33 micrometers.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, at least some of the plurality of light-shielding patterns are integrally connected with the plurality of first electrode patterns.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, each of the plurality of first electrode patterns includes a main body and a connecting part, the planar shape of the main body is a polygon or a pattern with an arc edge, and the planar shape of the plurality of light-shielding patterns is a polygon.

[0009] For example, in at least one embodiment of the present disclosure, the display substrate has a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting device, and the plurality of first electrode patterns respectively serve as the anode of the light-emitting device of the plurality of sub-pixels.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels, wherein the planar shape of the main body of the first electrode pattern of the light-emitting device of the red sub-pixel is hexagonal, and the light-shielding pattern integrally connected with the first electrode pattern of the light-emitting device of the red sub-pixel is triangular.

[0011] For example, in at least one embodiment of the present disclosure, the number of light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel is two, and the two light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel are symmetrically distributed.

[0012] For example, in the display substrate provided in at least one embodiment of this disclosure, the planar shape of the main body of the first electrode pattern of the light-emitting device of the blue sub-pixel is hexagonal, and the light-shielding pattern integrally connected with the first electrode pattern of the light-emitting device of the blue sub-pixel is triangular or rectangular.

[0013] For example, in the display substrate provided in at least one embodiment of this disclosure, the number of light-shielding patterns integrally connected with the first electrode pattern of the light-emitting device of the blue sub-pixel is three, and the three light-shielding patterns integrally connected with the first electrode pattern of the light-emitting device of the blue sub-pixel are respectively integrally connected with the three sides of the first electrode pattern of the light-emitting device of the blue sub-pixel.

[0014] For example, in the display substrate provided in at least one embodiment of this disclosure, the planar shape of the main body of the first electrode pattern of the light-emitting device of the green sub-pixel is pentagonal, and the light-shielding pattern integrally connected with the first electrode pattern of the light-emitting device of the green sub-pixel is rectangular.

[0015] For example, in the display substrate provided in at least one embodiment of this disclosure, the number of light-shielding patterns integrally connected with the first electrode pattern of the light-emitting device of the green sub-pixel is one or two, and the one or two light-shielding patterns integrally connected with the first electrode pattern of the light-emitting device of the green sub-pixel are respectively integrally connected with one or two edges of the first electrode pattern of the light-emitting device of the green sub-pixel.

[0016] For example, in the display substrate provided in at least one embodiment of this disclosure, in the corresponding sub-pixel opening and the first electrode pattern, the shape of the sub-pixel opening is the same as that of the main body of the first electrode pattern, the first orthographic projection of the sub-pixel opening on the substrate is located inside the second orthographic projection of the main body of the first electrode pattern on the substrate, and the minimum distance between the edges of the first orthographic projection and the second orthographic projection is 1.5 micrometers to 3.5 micrometers.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the light-emitting devices of the red sub-pixel and the blue sub-pixel are located in the same row, the light-emitting devices of the green sub-pixel are located in approximately the same row, and the rows in which the light-emitting devices of the red sub-pixel and the blue sub-pixel are located alternately with the rows in which the light-emitting devices of the green sub-pixel are located.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the driving circuit layer further includes a plurality of second gaps, the plurality of second gaps allowing light from the display side to pass through, and in a direction perpendicular to the substrate, the second gaps do not overlap with the plurality of first electrode patterns and the plurality of light-shielding patterns.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the distance between the plurality of second gaps and the center of the plurality of sub-pixel openings is greater than 33 micrometers.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projections of the plurality of second gaps on the substrate are respectively located between the orthographic projections of the light emission control signal line on the substrate and the orthographic projections of the reset voltage line closest to the light emission control signal line on the substrate.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, at least a portion of the plurality of second gaps are projected onto the substrate between the projection of the light emission control signal line for the blue sub-pixel onto the substrate and the projection of the reset voltage line for the red sub-pixel onto the substrate, wherein the red sub-pixel is located in the next row below the blue sub-pixel and is adjacent to the blue sub-pixel; and / or at least a portion of the plurality of second gaps are projected onto the substrate between the projection of the light emission control signal line for the red sub-pixel onto the substrate and the projection of the reset voltage line for the blue sub-pixel onto the substrate, wherein the blue sub-pixel is located in the next row below the red sub-pixel and is adjacent to the red sub-pixel.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, at least a portion of the second gaps have a width greater than 4.0 micrometers.

[0023] For example, in at least one embodiment of the display substrate provided in this disclosure, the driving circuit layer includes a plurality of pixel driving circuits and a first planarization layer. The first planarization layer is disposed on the side of the plurality of pixel driving circuits away from the substrate and includes a plurality of first vias. The plurality of first vias expose the output terminals of the plurality of pixel driving circuits respectively. The first electrode layer is disposed on the side of the first planarization layer away from the substrate, and the plurality of first electrode patterns are electrically connected to the output terminals of the plurality of pixel driving circuits through the plurality of first vias respectively. The display substrate also includes a spacer layer disposed on the side of the pixel defining layer away from the substrate. The spacer layer includes a plurality of spacers. In a direction perpendicular to the substrate, the plurality of spacers do not overlap with the plurality of first vias.

[0024] For example, in a display substrate provided in at least one embodiment of this disclosure, the minimum distance between the plurality of spacers and the plurality of first vias is greater than 2.0 micrometers in a direction parallel to the substrate.

[0025] For example, in at least one embodiment of the display substrate provided in this disclosure, the driving circuit layer includes a plurality of pixel driving circuits, a first planarization layer, a connection electrode layer, and a second planarization layer. The first planarization layer is disposed on the side of the plurality of pixel driving circuits away from the substrate and includes a plurality of first vias, which expose the output terminals of the plurality of pixel driving circuits respectively. The connection electrode layer is disposed on the side of the first planarization layer away from the substrate and includes a plurality of connection electrodes, which are electrically connected to the output terminals of the plurality of pixel driving circuits through the first vias respectively. The second planarization layer is disposed on the side of the connection electrode layer away from the substrate and includes a plurality of second vias, which expose the plurality of connection electrodes respectively. The first electrode layer is disposed on the side of the second planarization layer away from the substrate, and the plurality of first electrode patterns are electrically connected to the plurality of connection electrodes through the plurality of second vias respectively. The display substrate further includes a spacer layer disposed on the side of the pixel defining layer away from the substrate, the spacer layer including a plurality of spacers. In a direction perpendicular to the substrate, the plurality of spacers do not overlap with the plurality of second vias.

[0026] For example, in a display substrate provided in at least one embodiment of this disclosure, the minimum distance between the plurality of spacers and the plurality of second vias is greater than 2.0 micrometers in a direction parallel to the substrate.

[0027] For example, in a display substrate provided in at least one embodiment of this disclosure, the height of the plurality of spacers is 1.8 micrometers to 2.4 micrometers in a direction perpendicular to the substrate.

[0028] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of pixel driving circuits and the plurality of sub-pixel openings at least partially overlap in a direction perpendicular to the substrate.

[0029] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0031] Figure 1 This is a partial planar schematic diagram of a display substrate provided in at least one embodiment of the present disclosure; Figure 2 This is a partial planar schematic diagram of the first electrode layer of a display substrate provided in at least one embodiment of the present disclosure; Figure 3 This is a partial planar schematic diagram of the driving circuit layer of a display substrate provided in at least one embodiment of the present disclosure; Figure 4 This is a partial cross-sectional schematic diagram of a sub-pixel in a display substrate provided in at least one embodiment of the present disclosure; Figure 5 This is a partial planar schematic diagram of the overlapping portion of the first electrode layer and pixel defining layer of a display substrate provided in at least one embodiment of the present disclosure; Figure 6 This is a schematic diagram showing the overlap between the sub-pixel opening of a sub-pixel and the first electrode pattern in a display substrate provided in at least one embodiment of the present disclosure. Figure 7 This is a planar arrangement diagram of a plurality of spacers in a display substrate provided in at least one embodiment of the present disclosure; Figure 8 A cross-sectional schematic diagram of another portion of a sub-pixel in a display substrate provided in at least one embodiment of the present disclosure; Figure 9 A circuit diagram of a pixel driving circuit for a display substrate provided in at least one embodiment of the present disclosure; Figures 10-14 A partial planar schematic diagram of the sequentially stacked conductive layers of the driving circuit layer of a display substrate provided in at least one embodiment of this disclosure; and Figure 15 This is a partial cross-sectional schematic diagram of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0036] In a display device with fingerprint recognition function, the image sensor for fingerprint recognition is usually integrated into the non-display side of the display substrate of the display device. At this time, the display substrate needs to have a light-transmitting gap. When a finger touches the display side surface of the display device, the signal light with fingerprint information reflected by the finger will be transmitted to the image sensor through the light-transmitting gap. The image sensor can then acquire the signal light to perform fingerprint collection and recognition operations.

[0037] In the aforementioned display devices, the display substrate needs to have stable light transmittance to ensure that the image sensor can fully acquire the signal light carrying fingerprint information for fingerprint acquisition and recognition. Typically, the display substrate contains various circuit patterns, which are superimposed to create irregular light-transmitting gaps at certain locations. Larger gaps can transmit the signal light carrying fingerprint information. However, due to errors in the manufacturing process, such as alignment errors of multiple functional layers and dimensional errors in the circuit patterns, smaller gaps are often unstable; their size, number, and even their existence are uncertain. This leads to instability in the overall transmittance of the display substrate, affecting its manufacturing yield.

[0038] At least one embodiment of this disclosure provides a display substrate and a display device. The display substrate has a display side and includes a substrate, a driving circuit layer, a first electrode layer, and a pixel defining layer. The driving circuit layer is disposed on the substrate and includes a plurality of first gaps that allow light from the display side to pass through. The first electrode layer is disposed on the side of the driving circuit layer away from the substrate and includes a plurality of first electrode patterns and a plurality of light-shielding patterns. The pixel defining layer is disposed on the side of the first electrode layer away from the substrate and includes a plurality of sub-pixel openings that expose the plurality of first electrode patterns. In a direction perpendicular to the substrate, at least a portion of the plurality of light-shielding patterns does not overlap with the plurality of sub-pixel openings, and at least a portion of the plurality of light-shielding patterns corresponds to and at least partially overlaps with at least a portion of the plurality of first gaps to at least partially block light from the display side.

[0039] In the display substrate provided in the embodiments of this disclosure, at least a portion of the first gap is blocked by a light-shielding pattern, thereby eliminating the instability of the first gap caused by process fluctuations, thus avoiding the overall light transmittance instability of the display substrate caused by the instability of the first gap, that is, improving the light transmittance stability of the display substrate; on the other hand, the light-shielding pattern and the first electrode pattern are disposed in the same first electrode layer, so that the same materials and the same patterning process can be used in the manufacturing process, thereby simplifying the manufacturing process of the display substrate.

[0040] The following describes in detail the display substrate and display device provided in this disclosure through several specific embodiments.

[0041] This disclosure provides a display substrate in at least one embodiment. Figure 1 A partial planar schematic diagram of the display substrate is shown. Figure 2 It shows Figure 1 A partial planar schematic diagram of the first electrode layer of the display substrate. Figure 3 It shows Figure 1 A partial planar schematic diagram of the pixel driving circuit of the display substrate. Figure 4 It shows Figure 1 A partial cross-sectional diagram of a sub-pixel of the display substrate.

[0042] like Figures 1-4 As shown, the display substrate has a display side, i.e. Figure 4 On the upper side, there is also a non-display side, that is... Figure 4 The lower side of the substrate includes a substrate 110, a driving circuit layer 120, a first electrode layer, and a pixel defining layer 1017.

[0043] A driving circuit layer 120 is disposed on a substrate and includes a plurality of first gaps D1, which allow light from the display side to pass through. A first electrode layer is disposed on the side of the driving circuit layer 120 away from the substrate 110 and includes a plurality of first electrode patterns 1041 and a plurality of light-shielding patterns SH. A pixel defining layer 1017 is disposed on the side of the first electrode layer away from the substrate 110 and includes a plurality of sub-pixel openings PO, which expose the plurality of first electrode patterns 1041 respectively.

[0044] In the direction perpendicular to the substrate 110, that is Figure 4 In the vertical direction, at least part (e.g., all) of the multiple light-shielding patterns SH do not overlap with the multiple sub-pixel openings PO, and at least part of the multiple light-shielding patterns SH correspond to and at least partially overlap with at least part of the multiple first gaps D1, so as to at least partially block the light from the display side.

[0045] Therefore, in the embodiments of this disclosure, at least a portion of the first gap D1 is blocked by the light-shielding pattern SH, thereby avoiding the instability of the overall light transmittance of the display substrate caused by the instability of the size, number, etc. of the first gap D1, thus improving the stability of the light transmittance of the display substrate. On the other hand, the light-shielding pattern and the first electrode pattern are disposed in the same first electrode layer, so that the same materials and the same patterning process can be used in the fabrication process, thereby simplifying the fabrication process of the display substrate.

[0046] For example, in some embodiments, the width of the plurality of first gaps D1 is less than or equal to 4.0 micrometers, such as less than or equal to 3.0 micrometers, less than or equal to 2.0 micrometers, less than or equal to 1.5 micrometers, or less than or equal to 1.0 micrometer. The width of the first gap D1 refers to the dimension of the first gap D1 perpendicular to its extension direction. For example, when the first gap D1 is a rectangle (or approximately a rectangle), its width is the length of the shorter side of the rectangle. When the first gap D1 is an irregular shape, the direction in which the irregular shape has the longest span is the extension direction, and the dimension perpendicular to the extension direction is the width of the first gap D1.

[0047] Since the narrower first gap D1 is more prone to large process fluctuations during the manufacturing process, such as large dimensional deviations, the narrower first gap D1 is more likely to cause large deviations in the overall light transmittance of the display substrate. By using the light-shielding pattern SH to block the narrower first gap D1, the overall light transmittance stability of the display substrate can be improved to a greater extent.

[0048] For example, in some embodiments, the distance W1 between the centers of the plurality of first gaps D1 and the plurality of sub-pixel openings PO is less than 33 micrometers. For example, refer to Figure 1The distance W1 between the edges of the multiple first gaps D1 that are far from the edges of the multiple sub-pixel openings PO and the center of the multiple sub-pixel openings PO is less than 33 micrometers. That is, the multiple first gaps D1 are distributed within a range of 33 micrometers from the center of the multiple sub-pixel openings PO.

[0049] For example, in some embodiments, at least some of the multiple light-shielding patterns SH are integrally connected to the multiple first electrode patterns 1041. In this case, as... Figure 1 and Figure 2 As shown, the first electrode pattern 1041 and the light-shielding pattern SH, which are integrally connected, present an irregular shape.

[0050] For example, in some embodiments, the display substrate has a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels including a light-emitting device (EM), and a plurality of first electrode patterns 1041 respectively serving as the anodes of the light-emitting devices (EM) of the plurality of sub-pixels. Figure 4 As shown, the light-emitting device EM also includes a light-emitting material layer 1042 disposed on the side of the first electrode pattern 1041 away from the substrate 110, and a second electrode layer 1043 disposed on the side of the light-emitting material layer 1042 away from the substrate 110.

[0051] For example, in some embodiments, such as Figure 2 As shown, the first electrode pattern 1041 includes a main body portion M and a connecting portion CL, with the connecting portion CL extending from the main body portion M. The main body portion M is the part used to drive the light-emitting device to emit light. For example, the light-emitting material layer 1042 directly contacts at least a portion of the main body portion M to be driven by the main body portion M. The connecting portion CL is used to electrically connect the main body portion M to the pixel driving circuit, and the connecting portion CL does not directly contact the light-emitting portion of the light-emitting material layer 1042.

[0052] For example, such as Figure 2 As shown, the planar shapes of the main body M of the multiple first electrode patterns 1041 are polygonal (e.g., hexagonal, pentagonal, quadrilateral, etc.) or shapes with curved edges (e.g., circle, ellipse, mango shape, etc.), and the planar shapes of the multiple light-shielding patterns SH are polygonal, such as triangles or quadrilaterals (e.g., rectangles, parallelograms, rhombuses, etc.).

[0053] For example, in some embodiments, the multiple sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. For example, as... Figure 1 and Figure 2As shown, the main body M of the first electrode pattern 1041 of the light-emitting device of the red sub-pixel R has a hexagonal planar shape (hereinafter referred to as the first hexagon), and the light-shielding pattern RSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the red sub-pixel is triangular. For example, there are two light-shielding patterns RSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the red sub-pixel R, and the two light-shielding patterns RSH are symmetrically distributed.

[0054] For example, in some embodiments, such as Figure 1 and Figure 2 As shown, the planar shape of the main body M of the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is hexagonal (hereinafter referred to as the second hexagon). The second hexagon is similar to the first hexagon, for example, but the size of the second hexagon is larger than that of the first hexagon. For example, the light-shielding pattern BSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is triangular or rectangular. For example, the number of light-shielding patterns BSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is three, and the three light-shielding patterns BSH are integrally connected to the three sides of the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B, respectively.

[0055] For example, such as Figure 1 and Figure 2 As shown, the three light-shielding patterns BSH include two triangular light-shielding patterns and one rectangular pattern. The two triangular light-shielding patterns are symmetrically distributed, and the rectangular pattern is connected to the left side of the first electrode pattern 1041 and the left side of the triangle.

[0056] For example, in some embodiments, such as Figure 1 and Figure 2 As shown, the main body M of the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G has a pentagonal planar shape, and the light-shielding pattern GSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is rectangular. For example, the number of light-shielding patterns GSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is one or two, and the one or two light-shielding patterns GSH are respectively integrally connected to one or two sides of the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G.

[0057] For example, in some embodiments, a red sub-pixel R, two green sub-pixels G, and a blue sub-pixel B constitute a pixel unit, and multiple pixel units are arranged in an array on the substrate 110. For example, as Figure 1 and Figure 2As shown, the first electrode pattern 1041 of the light-emitting device of one of the two green sub-pixels G is connected to a rectangular light-shielding pattern GSH, and the first electrode pattern 1041 of the light-emitting device of the other green sub-pixel G is connected to two rectangular light-shielding patterns GSH.

[0058] For example, the light-emitting devices of red sub-pixel R and blue sub-pixel B are located in the same row, and the light-emitting devices of green sub-pixel G are located in roughly the same row. The rows where the light-emitting devices of red sub-pixel R and blue sub-pixel B are located are alternately arranged with the row where the light-emitting device of green sub-pixel G is located, thus forming multiple pixel units arranged periodically.

[0059] For example, in embodiments of this disclosure, the light-emitting devices of the green sub-pixel G being generally located in the same row refers to, as referenced Figure 5 At least part of the light-emitting devices of any two adjacent green sub-pixels G are located on the same straight line. The light-emitting devices of any two adjacent green sub-pixels G may be offset relative to the row direction. That is, the line connecting the centers of any two adjacent green sub-pixels G can be a broken line Z.

[0060] For example, Figure 5 A planar schematic diagram of the stacked layers of the first electrode layer and the pixel defining layer is shown. Figure 6 A planar schematic diagram showing the superposition of the main body and the subpixel opening of the blue subpixel is shown. In some embodiments, such as Figure 5 and Figure 6 As shown, in the corresponding sub-pixel opening PO and the first electrode pattern 1041, the sub-pixel opening PO has the same shape as the main body M of the first electrode pattern 1041. The first orthographic projection of the sub-pixel opening PO on the substrate 110 is located inside the second orthographic projection of the main body M of the first electrode pattern 1041 on the substrate 110, and the minimum distance L1 between the edges of the first and second orthographic projections is 1.5 micrometers to 3.5 micrometers, for example, 2.0 micrometers, 2.5 micrometers, or 3.0 micrometers. Thus, the sub-pixel opening PO fully exposes the first electrode pattern 1041, and the area defined by the sub-pixel opening PO is the effective light-emitting area of ​​the light-emitting device EM. The light-emitting material layer 1042 is in direct contact with the main body M of the first electrode pattern 1041 in this area to be driven.

[0061] For example, in some embodiments, such as Figure 5 As shown, the first electrode pattern 1041 of a green sub-pixel G in each pixel unit may also include a transistor light-shielding pattern TSH, which is used to shield the thin-film transistor (such as the thin-film transistor T2 described later) disposed below it to prevent light from shining on the thin-film transistor and affecting its switching performance.

[0062] For example, in some embodiments, such as Figure 1 and Figure 3 As shown, the driving circuit layer 120 also includes a plurality of second gaps D2, which allow light from the display side to pass through. In a direction perpendicular to the substrate 110, the second gaps D2 do not overlap with the plurality of first electrode patterns 1041 and the plurality of light-shielding patterns SH. Thus, the second gaps D2 can allow light from the display side to pass through to the non-display side of the display substrate. For example, when an image sensor S is disposed on the non-display side of the display substrate, the second gaps D2 can allow signal light carrying fingerprint information to pass through to the image sensor S.

[0063] For example, in some embodiments, at least a portion of the second gaps D2 have a width greater than 1.0 micrometer, or greater than 1.5 micrometer, or greater than 2.0 micrometer, or greater than 3.0 micrometer, or greater than 4.0 micrometer. The width of the second gap D2 refers to its dimension perpendicular to its extension direction. Therefore, the second gap D2 has a relatively large size, which allows for sufficient light transmission; furthermore, due to the large size of the second gap D2, it will not exhibit significant deviations during fabrication, and even if small deviations occur, their impact on the overall transmittance stability of the display substrate is minimal.

[0064] For example, in some embodiments, the distance W2 between the centers of the plurality of second gaps D2 and the plurality of sub-pixel openings PO is greater than 33 micrometers. For example, refer to Figure 1 The distance W2 between the edge of the multiple second gaps D2 away from the sub-pixel opening PO and the center of the sub-pixel opening PO is greater than 33 micrometers.

[0065] For example, in some embodiments, such as Figure 1 As shown, the orthographic projections of the plurality of second gaps D2 on the substrate 110 are respectively located between the orthographic projection of the light-emitting control signal line EM on the substrate 110 and the orthographic projection of the reset voltage line VINT, which is closest to the light-emitting control signal line EM, on the substrate 110. The connection relationship and application of the light-emitting control signal line EM and the reset voltage line VINT will be described in detail later.

[0066] For example, such as Figure 1 As shown, at least a portion of the plurality of second gaps D2 (e.g., the second gap D2 on the right in the figure) are projected onto the substrate 110 between the projection of the light emission control signal line EM for the blue sub-pixel B onto the substrate 110 and the projection of the reset voltage line VINT for the red sub-pixel R onto the substrate 110. The red sub-pixel R is located in the next row after the blue sub-pixel B and is adjacent to the blue sub-pixel B.

[0067] For example, such as Figure 1As shown, at least a portion of the plurality of second gaps D2 (e.g., the second gap D2 on the left in the figure) are projected onto the substrate 110 between the projection of the light emission control signal line EM for the red sub-pixel R onto the substrate 110 and the projection of the reset voltage line VINT for the blue sub-pixel B onto the substrate 110. The blue sub-pixel B is located in the next row below the red sub-pixel R and is adjacent to the red sub-pixel R.

[0068] That is, in the embodiments of this disclosure, a plurality of second gaps D2 are located in the gap between the pixel driving circuits of the blue sub-pixel B and the red sub-pixel R.

[0069] For example, in some embodiments, such as Figure 4 As shown, the driving circuit layer 120 includes multiple pixel driving circuits and a first planarization layer 1016. The pixel driving circuit includes multiple thin-film transistors and at least one storage capacitor, and can be formed as a 2T1C (i.e., two thin-film transistors and one storage capacitor), 7T1C (i.e., seven thin-film transistors and one storage capacitor), or 8T2C (i.e., eight thin-film transistors and one storage capacitor) structure, etc. The embodiments of this disclosure do not limit the specific form of the pixel driving circuit.

[0070] For example, Figure 4 The image shows a thin-film transistor T electrically connected to a light-emitting device EM and a storage capacitor C. (See figure for example.) Figure 4 As shown, the thin-film transistor T includes an active layer 1021, a gate 1022, a first source / drain electrode 1023, and a second source / drain electrode 1024. The storage capacitor C includes a first capacitor electrode 1031 and a second capacitor electrode 1032. The first capacitor electrode 1031 is disposed on the same layer as the gate 1022.

[0071] It should be noted that in the embodiments of this disclosure, "same-layer setting" means that two functional layers or structural layers are formed on the same layer and with the same material in the layer structure of the display substrate. That is, in the manufacturing process, the two functional layers or structural layers can be formed from the same material layer and can be formed with the same patterning process to form the required pattern and structure.

[0072] For example, such as Figure 4As shown, a first planarization layer 1016 is disposed on the side of the plurality of pixel driving circuits away from the substrate 1011, and includes a plurality of first vias VH1. The plurality of first vias VH1 expose the output terminals of the plurality of pixel driving circuits, such as the first source / drain electrodes 1023 of the thin-film transistor T. A first electrode layer is disposed on the side of the first planarization layer 1016 away from the substrate 110, and a plurality of first electrode patterns 1041 are electrically connected to the output terminals of the plurality of pixel driving circuits through the plurality of first vias VH1. Thus, the pixel driving circuits can control the voltage applied to the first electrode patterns 1041 through the thin-film transistor T.

[0073] For example, such as Figure 4 As shown, the display substrate also includes a spacer layer 1018 disposed on the side of the pixel defining layer 1017 away from the substrate 110. The spacer layer 1018 includes a plurality of spacers PS. For example, in the direction perpendicular to the substrate 110, i.e., the vertical direction shown in the figure, the height of the plurality of spacers PS is 1.8 micrometers to 2.4 micrometers, such as 2.0 micrometers or 2.2 micrometers. Thus, the spacers PS can have sufficient height so that during the fabrication process of the display substrate, such as when forming the light-emitting material layer 1042 by means of vapor deposition, the photomask used can be fully supported on the plurality of spacers PS without the photomask deforming and scratching the display substrate structure.

[0074] For example, in some embodiments, in a direction perpendicular to the substrate 110, multiple spacers PS do not overlap with multiple first vias VH1. Since the first vias VH1 are formed by hollowing out a portion of the material in the first planarization layer 1016, the material above the first vias VH1 is prone to depression. If the spacers PS are formed above the first vias VH1, the spacers PS will sink, thus reducing the height of the spacers PS relative to the substrate 110 and affecting their supporting function. By ensuring that the multiple spacers PS do not overlap with the multiple first vias VH1, the multiple spacers PS can effectively provide support.

[0075] For example, Figure 7 A schematic diagram of the planar arrangement of multiple spacers (PS) is shown. For example... Figure 7 As shown, in some embodiments, in a direction parallel to the substrate 110, the minimum distance L2 between the plurality of spacers PS and the plurality of first vias VH1 is greater than 2.0 micrometers. Since the sidewalls of the first vias VH1 are usually sloping, the material formed around and above the first vias VH1 is also prone to depressions. Therefore, by spacing the spacers PS from the first vias VH1 by a certain distance, the potential impact of the first vias VH1 on the spacers PS can be effectively avoided, allowing the spacers PS to have sufficient height to fully achieve their supporting function.

[0076] For example, in some other embodiments, Figure 8 This shows a schematic cross-sectional view of another portion of a sub-pixel on the display substrate. (See diagram below.) Figure 8 As shown, the driving circuit layer includes multiple pixel driving circuits, a first planarization layer 1016, a connection electrode layer, and a second planarization layer 1019. The specific form of the pixel driving circuit can be found in the above embodiments and will not be repeated here.

[0077] like Figure 8 As shown, a first planarization layer 1016 is disposed on the side of the plurality of pixel driving circuits away from the substrate 110, and includes a plurality of first vias VH1, which expose the output terminals of the plurality of pixel driving circuits, such as the first source / drain electrodes 1023 of the thin-film transistor T. A connection electrode layer is disposed on the side of the first planarization layer 1016 away from the substrate 110, and includes a plurality of connection electrodes CEL, which are electrically connected to the output terminals of the plurality of pixel driving circuits through the first vias VH1. A second planarization layer 1019 is disposed on the side of the connection electrode layer away from the substrate 110, and includes a plurality of second vias VH2, which expose the plurality of connection electrodes CEL. A first electrode layer is disposed on the side of the second planarization layer 1019 away from the substrate 110, and a plurality of first electrode patterns 1041 are electrically connected to the plurality of connection electrodes CEL through the plurality of second vias VH2.

[0078] like Figure 8 As shown, the display substrate also includes a spacer layer 1018 disposed on the side of the pixel defining layer 1017 away from the substrate 110. The spacer layer 1018 includes a plurality of spacers PS. For example, in the direction perpendicular to the substrate 110, i.e., the vertical direction shown in the figure, the height of the plurality of spacers PS is 1.8 micrometers to 2.4 micrometers, such as 2.0 micrometers or 2.2 micrometers. For example, in the direction perpendicular to the substrate 110, the plurality of spacers PS do not overlap with the plurality of second vias VH2. For example, refer to... Figure 7 In a direction parallel to the substrate 110, the minimum distance L2 between the multiple spacers PS and the multiple second vias VH2 is greater than 2.0 micrometers. This effectively avoids the potential impact of the second vias VH2 on the spacers PS, ensuring that the spacers PS have sufficient height to fully perform their supporting function.

[0079] For example, in an embodiment of this disclosure, in a direction perpendicular to the substrate 110, a plurality of pixel driving circuits and a plurality of sub-pixel openings PO at least partially overlap. In this case, the light-emitting device formed in the sub-pixel openings PO can be a top-emitting light-emitting device.

[0080] For example, such as Figure 4 and Figure 8As shown, the display substrate may further include a barrier layer 1012 and a buffer layer 1013 disposed on the substrate 110. The barrier layer 1012 and the buffer layer 1013 can prevent impurities in the substrate 110 from entering the multiple functional layers on the display substrate, thereby playing a protective role. For example, the barrier layer 1012 and the buffer layer 1013 may be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0081] For example, such as Figure 4 and Figure 8 As shown, the display substrate may further include a first gate insulating layer 1014A disposed on the side of the active layer 1021 away from the substrate 110, a second gate insulating layer 1014B disposed on the side of the gate electrode 1022 and the first capacitor electrode 1031 away from the substrate 110, and an interlayer insulating layer 1015 disposed on the side of the second capacitor electrode 1032 away from the substrate 110. For example, the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015 may be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0082] For example, such as Figure 4 and Figure 8 As shown, the display substrate may further include an encapsulation layer EN disposed on the side of the light-emitting device EM away from the substrate 110. The encapsulation layer EN may be a composite encapsulation layer, including a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053. The first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The first organic encapsulation layer 1052 may be made of one or more organic insulating materials such as resin or polyimide.

[0083] For example, in one embodiment, the pixel driving circuit of the sub-pixel adopts a 7T1C structure. Figure 9 A circuit diagram of a pixel driving circuit with a 7T1C structure is shown. (For example...) Figure 9 As shown, the pixel driving circuit of the 7T1C structure includes seven thin-film transistors T1-T7 and a storage capacitor C1, and has the connection relationship shown in the attached figure. This pixel driving circuit, for example, has the following four stages of driving process. In the following description, it is assumed that all seven thin-film transistors T1-T7 are P-type transistors, meaning that the gate of each transistor is turned on when a low level is applied and turned off when a high level is applied.

[0084] In initialization phase 1, the first reset signal RST1 is input to turn on the fourth transistor T4 and apply the reset voltage VINT to the control terminal (e.g., the gate) of the driving transistor T1; the first light emission control signal EM1 is input to turn on the fifth transistor T5 and apply the first voltage VDD to the second node N2.

[0085] For example, in initialization phase 1, the fourth transistor T4 is turned on by the low level of the first reset signal RST1, and the fifth transistor T5 is turned on by the low level of the first light emission control signal EM1; at the same time, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are turned off by their respective connected high-level signals.

[0086] During initialization phase 1, since the fourth transistor T4 is turned on, the reset voltage VINT (a low-level signal, such as ground or other low-level signal) can be applied to the gate of the first transistor T1. Simultaneously, since the fifth transistor T5 is turned on, the first voltage VDD (a high-level signal) can be applied to the source of the first transistor T1. Thus, during initialization phase 1, the gate and source voltage VGS of the first transistor T1 can satisfy: |VGS| > |Vth| (Vth is the threshold voltage of the first transistor T1; for example, when the first transistor T1 is a P-type transistor, Vth is negative). This allows the first transistor T1 to be in an on-state with VGS at a fixed bias.

[0087] In the data writing and compensation stage 2, the input scan signal GATE and data signal DATA turn on the second transistor T2, the driving transistor T1 and the third transistor T3. The data signal DATA is written to the driving transistor T1, and the third transistor T3 performs threshold compensation on the driving transistor T1.

[0088] During data writing and compensation phase 2, the second transistor T2 and the third transistor T3 are turned on by the low level of the scan signal GATE. At the same time, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off by their respective connected high-level signals.

[0089] In data writing and compensation phase 2, the data signal DATA charges the first node N1 (i.e., charges the storage capacitor C1) after passing through the second transistor T2, the first transistor T1, and the third transistor T3. This means the potential of the first node N1 gradually increases. It's easy to understand that because the second transistor T2 is on, the potential of the second node N2 remains at Vdata. Simultaneously, according to the characteristics of the first transistor T1, when the potential of the first node N1 increases to Vdata + Vth, the first transistor T1 is turned off, and the charging process ends. It should be noted that Vdata represents the voltage value of the data signal DATA, and Vth represents the threshold voltage of the first transistor.

[0090] After the data writing and compensation stage 2, the potentials of the first node N1 and the third node N3 are both Vdata+Vth. That is, the voltage information with data signal DATA and threshold voltage Vth is stored in the storage capacitor C1, so as to provide grayscale display data and compensate the threshold voltage of the first transistor T1 itself during the light emission stage.

[0091] In reset phase 3, the second light-emitting control signal EM2 and the second reset signal RST2 are input to turn on the sixth transistor T6 and the seventh transistor T7, and to reset the first transistor T1, the third transistor T3 and the sixth transistor T6.

[0092] During reset phase 3, the sixth transistor T6 is turned on by the low level of the second light emission control signal EM2, and the seventh transistor T7 is turned on by the low level of the second reset signal RST2; at the same time, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off by their respective high-level inputs.

[0093] During reset phase 3, since the reset voltage VINT is a low-level signal (e.g., it can be grounded or other low-level signals), the drain of the first transistor T1 discharges through the sixth transistor T6 and the seventh transistor T7, thereby simultaneously resetting the potentials of the third node N3 and the fourth node N4.

[0094] In reset phase 3, the drain of the first transistor T1 is reset, thus maintaining it at a fixed potential and preventing the display effect of the display device using the pixel circuit from being affected by the uncertainty of the drain potential. Simultaneously, the fourth node N4 is also reset, i.e., the OLED is reset, so that the OLED displays as black and does not emit light before light emission phase 4, improving the contrast and other display effects of the display device using the pixel circuit.

[0095] In the light-emitting stage 4, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input to turn on the thin-film transistor T5, thin-film transistor T6 and the driving circuit thin-film transistor T1. The thin-film transistor T6 applies a driving current to the light-emitting element 600 to make it emit light.

[0096] In the light-emitting stage 4, the fifth transistor T5 is turned on by the low level of the first light-emitting control signal EM1, and the sixth transistor T6 is turned on by the low level of the second light-emitting control signal EM2; the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are turned off by their respective high levels; at the same time, the potential of the first node N1 is Vdata+Vth, and the potential of the second node N2 is VDD, so the first transistor T1 also remains on in this stage.

[0097] like Figure 8 As shown, in the light-emitting stage 4, the first electrode pattern (e.g., anode) and the second electrode layer (e.g., cathode) of the light-emitting device D1 are respectively connected to the first voltage VDD (high voltage) and the second voltage VSS (low voltage), thereby emitting light under the action of the driving current flowing through the first transistor T1.

[0098] For example, Figures 10-14 A partial planar schematic diagram of the conductive layers of the driving circuit layer is shown. There are insulating layers between adjacent conductive layers, such as the gate insulating layer and interlayer insulating layer mentioned above. These insulating layers have multiple vias for electrical connection. In the following embodiments, each conductive layer is described in detail, and the insulating layers will not be described in detail.

[0099] For example, Figure 10 A planar schematic diagram of the semiconductor layer of the driving circuit layer is shown, the semiconductor layer including the active layers of each thin-film transistor T1-T7. For example, the active layers of thin-film transistors T1-T7 are interconnected as a single unit, for example... Figure 10 The portion of the semiconductor layer circled by the dashed box represents the active layer of thin-film transistors T1-T7 in the pixel driving circuit of a sub-pixel. For example, a first gate insulating layer 1014A, not shown in the figure, is disposed above the semiconductor layer.

[0100] For example, Figure 11 The first conductive layer of the driving circuit layer is shown superimposed on... Figure 10 A planar schematic diagram of the semiconductor layer, such as Figure 11 As shown, the first conductive layer includes the gate of each transistor, the first capacitor electrode 1031 of the storage capacitor, and a number of scan lines GATE, light emission control lines EM, and reset control lines RST. For example, the gate of each transistor is the portion of the scan line GATE, the light emission control line EM, and the reset control line RST that overlaps with the active layer. For example, each row of sub-pixels is respectively connected to one scan line GATE, two reset control lines RST, and one light emission control line EM. A second gate insulating layer 1014B is disposed above the first conductive layer, which is not shown in the figure.

[0101] For example, Figure 12 The second conductive layer of the driving circuit layer is shown superimposed on... Figure 11 A planar schematic diagram of the stacked structure, as shown below. Figure 12 As shown, the second conductive layer includes a second capacitor electrode 1032 for storing a capacitor and multiple reset voltage lines VINT. An interlayer insulating layer 1015, not shown in the figure, is disposed above the second conductive layer.

[0102] For example, Figure 13 The third conductive layer of the driving circuit layer is shown superimposed on... Figure 12 A planar schematic diagram of the stacked structure, as shown below. Figure 13As shown, the third conductive layer includes the first power line VDD, a portion of the data line Data, and the source and drain electrodes of the thin-film transistors T1-T7. A planarization layer 1016, not shown in the figure, is disposed above the third conductive layer.

[0103] For example, Figure 14 The fourth conductive layer of the driving circuit layer is shown superimposed on... Figure 13 A planar schematic diagram of the stacked structure, as shown below. Figure 13 As shown, the fourth conductive layer includes another portion of the data lines. For example, in some embodiments, the fourth conductive layer may also include a connection electrode CEL. A planarization layer 1019, not shown in the figure, is disposed above the third conductive layer. Thus, in this embodiment, the data lines Data are distributed in two conductive layers to facilitate the arrangement of the data lines Data.

[0104] For example, Figure 1 The first electrode layer is shown stacked on Figure 14 A planar schematic diagram of the stacked structure can be found in the diagram. Figure 1 The description will not be repeated here.

[0105] For example, in embodiments of this disclosure, the substrate 110 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide. The gate electrode 1022 can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The first source / drain electrode 1023 and the second source / drain electrode 1024 can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The materials of the first capacitor electrode 1031 and the second capacitor electrode 1032 include metal or alloy materials such as aluminum, titanium, cobalt, and copper. The active layer 1021 can be made of materials such as polysilicon and metal oxides.

[0106] For example, the first planarization layer 1016, the second planarization layer 1019, the pixel defining layer 1017, the spacer layer 1018, and the first organic encapsulation layer 1052 of the encapsulation layer EN can be made of organic insulating materials such as polyimide and resin.

[0107] For example, the display substrate may also include other structures besides those described above. For details, please refer to the relevant technologies, which will not be elaborated here.

[0108] Furthermore, it should be noted that the embodiments of this disclosure do not limit the materials of each functional layer, and the materials of each functional layer are not limited to the examples described above. In the embodiments of this disclosure, each thin-film transistor can be a P-type thin-film transistor or an N-type thin-film transistor, and the structure can be bottom-gate, top-gate, or dual-gate. The structures shown in the accompanying drawings are merely exemplary, and the embodiments of this disclosure do not limit the specific form of each thin-film transistor. For example, in some embodiments, when the thin-film transistor is a dual-gate type, Figure 4 and Figure 8 The display substrate has at least one additional conductive layer and one additional insulating layer. Another gate is disposed in the conductive layer. In this case, the two gates can be located on the side of the active layer of the thin-film transistor closer to the substrate and the side farther from the substrate, respectively.

[0109] This disclosure provides at least one embodiment of a display device, which includes any of the display substrates described above. For example, Figure 15 A partial cross-sectional schematic diagram of the display device is shown, such as... Figure 15 As shown, the display device may further include an image sensor S, which is integrated on the non-display side of the display substrate and configured to receive light transmitted through the second gap D2. For example, in some embodiments, the orthographic projection of the image sensor S onto the substrate 110 at least partially overlaps with the orthographic projection of the second gap D2 onto the substrate 110.

[0110] For example, the image sensor S can be any suitable type of image sensor, such as a charge-coupled device (CCD) image sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, or a photodiode (e.g., a PIN photodiode). Depending on the needs, the image sensor can sense only a certain wavelength of light (e.g., red or green light) or it can sense all visible light.

[0111] For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0112] The following points also need to be explained: (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0113] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0114] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0115] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate having a display side, and comprising: Substrate A driving circuit layer, disposed on the substrate, includes a plurality of first gaps, the plurality of first gaps allowing light from the display side to pass through. A first electrode layer, disposed on the side of the driving circuit layer away from the substrate, includes multiple first electrode patterns and multiple light-shielding patterns. A pixel defining layer, disposed on the side of the first electrode layer away from the substrate, includes a plurality of sub-pixel openings, each of which exposes a plurality of first electrode patterns. Wherein, in the direction perpendicular to the substrate, at least a portion of the plurality of light-shielding patterns do not overlap with the plurality of sub-pixel openings, and at least a portion of the plurality of light-shielding patterns correspond to and at least partially overlap with at least a portion of the plurality of first gaps, so as to at least partially block light from the display side; The width of the plurality of first gaps is less than or equal to 4.0 micrometers, and the distance between the plurality of first gaps and the center of the plurality of sub-pixel openings is less than 33 micrometers.

2. The display substrate according to claim 1, wherein, At least some of the multiple light-shielding patterns are integrally connected to the multiple first electrode patterns.

3. The display substrate according to claim 1 or 2, wherein, Each of the plurality of first electrode patterns includes a main body and a connecting part, wherein the planar shape of the main body is a polygon or a shape with curved edges. The planar shapes of the multiple light-blocking patterns are each polygonal.

4. The display substrate according to claim 1 or 2, wherein, The display substrate has a plurality of sub-pixels, each of the plurality of sub-pixels including a light-emitting device, and the plurality of first electrode patterns respectively serve as the anodes of the light-emitting devices of the plurality of sub-pixels.

5. The display substrate according to claim 4, wherein, The plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels. The main body of the first electrode pattern of the light-emitting device of the red sub-pixel has a hexagonal planar shape, and the light-shielding pattern integrally connected with the first electrode pattern of the light-emitting device of the red sub-pixel is triangular.

6. The display substrate according to claim 5, wherein, The number of light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel is two, and the two light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel are symmetrically distributed.

7. The display substrate according to claim 5, wherein, The main body of the first electrode pattern of the light-emitting device of the blue sub-pixel has a hexagonal planar shape, and the light-shielding pattern integrally connected with the first electrode pattern of the light-emitting device of the blue sub-pixel is triangular or rectangular.

8. The display substrate according to claim 7, wherein, The number of light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel is three, and the three light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel are respectively integrally connected to the three sides of the first electrode pattern of the light-emitting device of the blue sub-pixel.

9. The display substrate according to claim 5, wherein, The main body of the first electrode pattern of the light-emitting device of the green sub-pixel has a pentagonal planar shape, and the light-shielding pattern integrally connected with the first electrode pattern of the light-emitting device of the green sub-pixel is rectangular.

10. The display substrate according to claim 9, wherein, The number of light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel is one or two, and the one or two light-shielding patterns integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel are respectively integrally connected to one or two sides of the first electrode pattern of the light-emitting device of the green sub-pixel.

11. The display substrate according to claim 1 or 2, wherein, In the corresponding sub-pixel opening and the first electrode pattern, the sub-pixel opening has the same shape as the main body of the first electrode pattern. The first orthographic projection of the sub-pixel opening on the substrate is located inside the second orthographic projection of the main body of the first electrode pattern on the substrate, and the minimum distance between the edges of the first orthographic projection and the second orthographic projection is 1.5 micrometers to 3.5 micrometers.

12. The display substrate according to claim 5, wherein, The light-emitting devices of the red sub-pixel and the blue sub-pixel are located in the same row. The light-emitting devices of the green sub-pixels are generally located in the same row, and at least part of the light-emitting devices of any two adjacent green sub-pixels are located on the same straight line. The rows containing the light-emitting devices of the red and blue sub-pixels are arranged alternately with the rows containing the light-emitting devices of the green sub-pixels.

13. The display substrate according to claim 1 or 2, wherein, The driving circuit layer also includes a plurality of second gaps, which allow light from the display side to pass through. In a direction perpendicular to the substrate, the second gap does not overlap with the plurality of first electrode patterns and the plurality of light-shielding patterns.

14. The display substrate according to claim 13, wherein, The distance between the plurality of second gaps and the center of the plurality of sub-pixel openings is greater than 33 micrometers.

15. The display substrate according to claim 13, wherein, The orthographic projections of the plurality of second gaps on the substrate are respectively located between the orthographic projections of the light emission control signal line on the substrate and the orthographic projections of the reset voltage line closest to the light emission control signal line on the substrate.

16. The display substrate according to claim 15, wherein, At least a portion of the second gaps are projected onto the substrate between the projections of the light-emitting control signal line for the blue sub-pixel onto the substrate and the reset voltage line for the red sub-pixel onto the substrate, wherein the red sub-pixel is located in the next row below and adjacent to the blue sub-pixel; and / or At least a portion of the second gaps are projected onto the substrate between the projection of the light emission control signal line for the red sub-pixel onto the substrate and the projection of the reset voltage line for the blue sub-pixel onto the substrate, wherein the blue sub-pixel is located in the next row below and adjacent to the red sub-pixel.

17. The display substrate according to claim 13, wherein, At least a portion of the plurality of second gaps have a width greater than 4.0 micrometers.

18. The display substrate according to claim 1 or 2, wherein, The driving circuit layer includes: Multiple pixel driving circuits, and A first planarization layer is disposed on the side of the plurality of pixel driving circuits away from the substrate, and includes a plurality of first vias, the plurality of first vias respectively exposing the output terminals of the plurality of pixel driving circuits. The first electrode layer is disposed on the side of the first planarization layer away from the substrate, and the plurality of first electrode patterns are electrically connected to the output terminals of the plurality of pixel driving circuits through the plurality of first vias. The display substrate further includes a spacer layer disposed on the side of the pixel defining layer away from the substrate, and the spacer layer includes a plurality of spacers; Wherein, in a direction perpendicular to the substrate, the plurality of spacers do not overlap with the plurality of first vias.

19. The display substrate according to claim 18, wherein, In a direction parallel to the substrate, the minimum distance between the plurality of spacers and the plurality of first vias is greater than 2.0 micrometers.

20. The display substrate according to claim 1 or 2, wherein, The driving circuit layer includes: Multiple pixel driving circuits A first planarization layer is disposed on the side of the plurality of pixel driving circuits away from the substrate, and includes a plurality of first vias, the plurality of first vias respectively exposing the output terminals of the plurality of pixel driving circuits. A connecting electrode layer, disposed on the side of the first planarization layer away from the substrate, includes multiple connecting electrodes. These multiple connecting electrodes are respectively electrically connected to the output terminals of the multiple pixel driving circuits through the first via. A second planarization layer is disposed on the side of the connection electrode layer away from the substrate, and includes a plurality of second vias, the plurality of second vias exposing the plurality of connection electrodes respectively; The first electrode layer is disposed on the side of the second planarization layer away from the substrate, and the plurality of first electrode patterns are electrically connected to the plurality of connecting electrodes through the plurality of second vias; The display substrate further includes a spacer layer disposed on the side of the pixel defining layer away from the substrate, and the spacer layer includes a plurality of spacers; Wherein, in a direction perpendicular to the substrate, the plurality of spacers do not overlap with the plurality of second vias.

21. The display substrate according to claim 20, wherein, In a direction parallel to the substrate, the minimum distance between the plurality of spacers and the plurality of second vias is greater than 2.0 micrometers.

22. The display substrate according to claim 18, wherein, The height of the plurality of spacers is 1.8 micrometers to 2.4 micrometers in a direction perpendicular to the substrate.

23. The display substrate according to claim 20, wherein, In a direction perpendicular to the substrate, the plurality of pixel driving circuits and the plurality of sub-pixel openings at least partially overlap.

24. A display device comprising the display substrate according to any one of claims 1-23.

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