Membrane-based pressure sensor

Abstract

This invention relates to the field of gas pressure sensors and discloses a MEMS piezoresistive pressure sensor, comprising a silicon substrate, a piezoresistive bridge assembly, a silicon pressure-sensitive membrane assembly, a PMOS transistor assembly, metal pads, and a silicon piezoresistive component. The piezoresistive bridge assembly is connected in series with the silicon piezoresistive component and is disposed on the silicon pressure-sensitive membrane assembly. The PMOS transistor assembly is disposed within the chip frame, and a power supply metal ring and a ground metal ring are respectively connected to the two ends of the piezoresistive bridge assembly. Multiple sets of piezoresistors can be arranged on the circular sensitive membrane to improve the sensor's sensitivity. Furthermore, the voltage signal output by the piezoresistive resistor is directly converted into a current signal on the MEMS chip via the PMOS transistor. Utilizing the superposition characteristic of current signals, multiple sets of piezoresistive output signals are superimposed. Therefore, the sensor can achieve a high signal output level under low pressure input conditions, and the required output amplitude is achieved through superposition by adding a resistor bridge and a PMOS transistor combination.

Description

Technical Field

[0001] This invention relates to the field of sensor technology, specifically to a MEMS piezoresistive pressure sensor. Background Technology

[0002] In existing piezoresistive pressure sensors, the pressure-sensitive diaphragms are mostly square or rectangular, and the number of piezoresistors is usually four, arranged in a Wheatstone bridge structure. This design has low utilization of the surface space of the pressure-sensitive diaphragm because the output signal of the Wheatstone bridge is in the form of a voltage difference, and voltage signals cannot be superimposed. On the other hand, the surface stress distribution of a square pressure-sensitive diaphragm is relatively complex after being subjected to force, and there are not many suitable positions for placing piezoresistors. Therefore, traditional piezoresistive pressure sensors have high requirements for the accuracy of individual piezoresistor positions and the uniformity of pressure resistance changes. However, current silicon wafer processing technology has not yet achieved complete accuracy in piezoresistor position, resulting in significant output deviations. Moreover, the output of existing piezoresistive pressure sensors is mostly a differential voltage signal with an amplitude that can only reach the level of hundreds of millivolts. This signal amplitude needs to be amplified by a back-end amplifier before it can be read by signal processing equipment. However, during the signal amplification process, noise is also amplified by the same factor. Considering that the closed-loop gain of the operational amplifier is above 50V / V, the signal output signal-to-noise ratio is reduced after the noise of the first and second stages of the operational amplifier is amplified by multiple stages. Therefore, the signal-to-noise ratio of the sensor output signal deteriorates during the back-end signal processing. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a MEMS piezoresistive pressure sensor. This solves the problem that existing piezoresistive pressure sensors primarily output differential voltage signals with amplitudes limited to the hundreds of millivolts level. This signal amplitude requires amplification by a back-end amplifier before it can be read by signal processing equipment. However, during signal amplification, noise is also amplified by the same factor. Considering that the closed-loop gain of the operational amplifier is above 50V / V, the signal output signal-to-noise ratio is reduced after multiple stages of noise amplification in the first and second stages of the operational amplifier. Therefore, the signal-to-noise ratio of the sensor output signal deteriorates during back-end signal processing.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a MEMS piezoresistive pressure sensor, comprising a silicon substrate, a piezoresistive bridge assembly, a silicon pressure-sensitive membrane assembly, a PMOS transistor assembly, metal pads, a silicon piezoresistive component, a silicon cavity, and a lever silicon island assembly. The piezoresistive bridge assembly is connected in series with the silicon piezoresistive component. The piezoresistive bridge assembly is disposed on the silicon pressure-sensitive membrane assembly. The PMOS transistor assembly is disposed within the chip frame. A power supply metal ring and a ground metal ring are respectively connected to the two ends of the piezoresistive bridge assembly.

[0005] Preferably, the piezoresistive bridge assembly includes piezoresistive bridge one, piezoresistive bridge two, piezoresistive bridge three, piezoresistive bridge four, piezoresistive bridge five, piezoresistive bridge six, piezoresistive bridge seven and piezoresistive bridge eight;

[0006] The PMOS transistor assembly includes PMOS transistor 1, PMOS transistor 2, PMOS transistor 3, PMOS transistor 4, PMOS transistor 5, PMOS transistor 6, PMOS transistor 7, PMOS transistor 8, and a single PMOS transistor;

[0007] The two piezoresistive connection points of piezoresistive bridge one are connected to the gate of PMOS transistor one, the two piezoresistive connection points of piezoresistive bridge two are connected to the gate of PMOS transistor two, the two piezoresistive connection points of piezoresistive bridge three are connected to the gate of PMOS transistor three, and the two piezoresistive connection points of piezoresistive bridge four are connected to the gate of PMOS transistor four. The sources (S) of PMOS transistors one, two, three, and four are all connected to the power supply metal ring, and the drains (D) of PMOS transistors one, two, three, and four are all connected to the output metal ring. Piezoresistive bridges one, two, three, and four are respectively provided with two silicon piezoresistive bridges one, two, three, and four.

[0008] Preferably, the silicon pressure-sensitive membrane assembly includes a first silicon pressure-sensitive membrane and a second silicon pressure-sensitive membrane. The first and second silicon pressure-sensitive membranes and the central silicon island are all circular. The central silicon island is concentric with the first and second silicon pressure-sensitive membranes and is located at the center of the sensor chip. The outer rings of the first and second silicon pressure-sensitive membranes are connected to the outer frame of the pressure sensor, and the inner rings of the first and second silicon pressure-sensitive membranes are connected to the central silicon island.

[0009] Preferably, the two ends of piezoresistive bridge 1, piezoresistive bridge 2, piezoresistive bridge 3, piezoresistive bridge 4, piezoresistive bridge 5, piezoresistive bridge 6, piezoresistive bridge 7 and piezoresistive bridge 8 are respectively connected to the power supply metal ring and the grounding metal ring. Piezoresistive bridge 1, piezoresistive bridge 2, piezoresistive bridge 3 and piezoresistive bridge 4 are respectively disposed on the first silicon pressure-sensitive membrane. Piezoresistive bridge 5, piezoresistive bridge 6, piezoresistive bridge 7 and piezoresistive bridge 8 are respectively disposed on the second silicon pressure-sensitive membrane. The output voltages of piezoresistive bridge 1, piezoresistive bridge 2, piezoresistive bridge 3, piezoresistive bridge 4, piezoresistive bridge 5, piezoresistive bridge 6, piezoresistive bridge 7 and piezoresistive bridge 8 are respectively connected to the gates of PMOS transistors 1, 2, 3, 4, 5, 6, 7 and 8.

[0010] Preferably, the lever silicon island assembly includes lever silicon island one; lever silicon island one, lever silicon island two, lever silicon island three and lever silicon island four are respectively disposed between piezoresistive bridge one, piezoresistive bridge two, piezoresistive bridge three and piezoresistive bridge four.

[0011] Preferably, the piezoresistive bridge PMOS transistor module is provided in several groups, and the several groups of piezoresistive bridge PMOS transistor modules are arbitrarily arranged with the center of the silicon pressure-sensitive film as the center. Each group of piezoresistive bridge PMOS transistor modules is connected in series with two varistors, and the two ends of each group of piezoresistive bridge PMOS transistor modules are respectively connected to the power supply metal ring and the grounding metal ring.

[0012] Preferably, a single PMOS transistor includes a first metal interconnect, a P-type phosphorus implantation region, a second metal interconnect, and a gate oxide layer.

[0013] Preferably, the metal pads are respectively connected to the power supply metal ring, the grounding metal ring, and the output metal ring, and the power supply metal ring, the grounding metal ring, and the output metal ring are concentric circles.

[0014] Preferably, the back side of the chip is provided with a back cavity, and the back cavity is provided with a first silicon island, a cavity one, a second silicon island and a cavity two.

[0015] This invention provides a MEMS piezoresistive pressure sensor. It has the following advantages:

[0016] 1. This invention improves the sensitivity of the sensor by arranging multiple piezoresistors on a circular sensitive membrane. Furthermore, on the MEMS chip, the voltage signal output by the piezoresistors is directly converted into a current signal via a PMOS transistor. Utilizing the superposition property of current signals, multiple piezoresistor output signals are superimposed, thus enabling the sensor to achieve a high signal output level even with low input pressure. Moreover, by adding a resistor bridge and a PMOS transistor combination, the desired output amplitude is achieved through superposition, increasing the signal amplitude and reducing the noise amplitude between amplifier circuits, thereby improving the signal-to-noise ratio and simplifying the processing circuit. Each signal uses only one field-effect transistor for voltage-to-current conversion, significantly reducing the circuit noise floor. Attached Figure Description

[0017] Figure 1 This is a design block diagram of the present invention;

[0018] Figure 2 This is a cross-sectional view of the gas flow sensor of the present invention along the AA' direction;

[0019] Figure 3 This is a cross-sectional view of the gas flow sensor of the present invention along the BB' direction;

[0020] Figure 4 This is a circuit diagram of the present invention;

[0021] Figure 5 This is a front view of Embodiment 1 of the present invention;

[0022] Figure 6This is a back view of Embodiment 1 of the present invention;

[0023] Figure 7 This is a front view of Embodiment 2 of the present invention;

[0024] Figure 8 This is a back view of Embodiment 2 of the present invention;

[0025] Figure 9 This is a front view of Embodiment 3 of the present invention;

[0026] Figure 10 This is a rear view of Embodiment 3 of the present invention;

[0027] Figure 11 This is a front view of Embodiment 4 of the present invention.

[0028] Among them, 100, silicon substrate; 101, piezoresistive bridge assembly; 1011, piezoresistive bridge one; 1012, piezoresistive bridge two; 1013, piezoresistive bridge three; 1014, piezoresistive bridge four; 1015, piezoresistive bridge five; 1016, piezoresistive bridge six; 1017, piezoresistive bridge seven; 1018, piezoresistive bridge eight; 102, silicon pressure-sensitive membrane assembly; 1021, first silicon pressure-sensitive membrane; 1022, second silicon pressure-sensitive membrane; 103, central silicon island; 104, PMOS transistor assembly; 1041, PMOS transistor one; 1042, PMOS transistor two; 1043, PMOS transistor three; 1044, PMOS transistor four; 1045, PMOS transistor five; 1046, PMOS transistor six; 1047, PMOS transistor seven; 1048, PMOS... 105. Power supply metal ring; 106. Grounding metal ring; 107. Output metal ring; 108. Metal pad; 200. Silicon piezoresistive assembly; 20111. Silicon piezoresistive 1; 20112. Silicon piezoresistive 2; 20121. Silicon piezoresistive 3; 20122. Silicon piezoresistive 4; 202. Silicon cavity; 300. Single PMOS transistor; 301. Metal connection line 1; 302. P-type phosphorus implantation region; 303. Metal connection line 2; 304. Gate oxide layer; 4. Piezoresistive bridge PMOS transistor module; 5. Lever silicon island assembly; 501. Lever silicon island 1; 502. Lever silicon island 2; 503. Lever silicon island 3; 504. Lever silicon island 4; 6. Back cavity; 7. First silicon island; 8. Cavity 1; 9. Second silicon island; 10. Cavity 2. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Example 1:

[0031] Please see the appendix Figure 1-6 This invention provides a MEMS piezoresistive pressure sensor, including a silicon substrate 100, a piezoresistive bridge assembly 101, a silicon pressure-sensitive membrane assembly 102, a PMOS transistor assembly 104, a metal pad 108, a silicon piezoresistive assembly 200, a silicon cavity 202, and a lever silicon island assembly 5. The piezoresistive bridge assembly 101 and the silicon piezoresistive assembly 200 are connected in series. The piezoresistive bridge assembly 101 is disposed on the silicon pressure-sensitive membrane assembly 102. The PMOS transistor assembly 104 is disposed within the chip frame. A power supply metal ring 105 and a grounding metal ring 106 are respectively connected to the two ends of the piezoresistive bridge assembly 101.

[0032] Piezoresistive bridge assembly 101 includes piezoresistive bridge one 1011, piezoresistive bridge two 1012, piezoresistive bridge three 1013, piezoresistive bridge four 1014, piezoresistive bridge five 1015, piezoresistive bridge six 1016, piezoresistive bridge seven 1017 and piezoresistive bridge eight 1018.

[0033] PMOS transistor assembly 104 includes PMOS transistor 1041, PMOS transistor 1042, PMOS transistor 1043, PMOS transistor 1044, PMOS transistor 1045, PMOS transistor 1046, PMOS transistor 1047, PMOS transistor 1048 and a single PMOS transistor 300.

[0034] Piezoresistive bridge 1011 connects to the gate of PMOS transistor 1041; piezoresistive bridge 1012 connects to the gate of PMOS transistor 1042; piezoresistive bridge 1013 connects to the gate of PMOS transistor 1043; and piezoresistive bridge 1014 connects to the gate of PMOS transistor 1044. PMOS transistors 1041, 1042, and 1043 are connected to the gate of PMOS transistor 1044. The source S of transistor 1044 is connected to the power supply metal ring 105. The drain D of PMOS transistors 1041, 1042, 1043 and 1044 is connected to the output metal ring 107. Piezoresistive bridges 1011, 1012, 1013 and 1014 are respectively provided with two silicon piezoresistive bridges 20111, 20112, 20121 and 20122.

[0035] The silicon pressure-sensitive membrane assembly 102 includes a first silicon pressure-sensitive membrane 1021 and a second silicon pressure-sensitive membrane 1022. The first silicon pressure-sensitive membrane 1021, the second silicon pressure-sensitive membrane 1022, and the central silicon island 103 are all circular. The central silicon island 103 is concentric with the first silicon pressure-sensitive membrane 1021 and the second silicon pressure-sensitive membrane 1022 and is located at the center of the sensor chip. The outer rings of the first silicon pressure-sensitive membrane 1021 and the second silicon pressure-sensitive membrane 1022 are connected to the outer frame of the pressure sensor, and the inner rings of the first silicon pressure-sensitive membrane 1021 and the second silicon pressure-sensitive membrane 1022 are connected to the central silicon island 103.

[0036] Piezoresistive bridges 1011, 1012, 1013, 1014, 1015, 1016, 1017, and 1018 are connected at both ends to the power supply metal ring 105 and the grounding metal ring 106, respectively. Piezoresistive bridges 1011, 1012, 1013, and 1014 are respectively mounted on the first silicon pressure-sensitive membrane 1021. Piezoresistive bridges 1015, 1016, 1017, and 1018 are respectively mounted on... The output voltages of piezoresistive bridges 1011, 1012, 1013, 1014, 1015, 1016, 1017, and 1018 are respectively connected to the gates of PMOS transistors 1041, 1042, 1043, 1044, 1045, 1046, 1047, and 1048 on the second silicon pressure-sensitive membrane 1022.

[0037] The lever silicon island assembly 5 includes lever silicon island one 501; lever silicon island one 501, lever silicon island two 502, lever silicon island three 503 and lever silicon island four 504 are respectively disposed between piezoresistive bridge one 1011, piezoresistive bridge two 1012, piezoresistive bridge three 1013 and piezoresistive bridge four 1014.

[0038] The piezoresistive bridge PMOS transistor module 4 is provided in several groups, and the several groups of piezoresistive bridge PMOS transistor modules 4 are arbitrarily arranged with the center of the silicon pressure sensitive film 102 as the center. Each group of piezoresistive bridge PMOS transistor modules 4 is connected in series with two varistors, and the two ends of each group of piezoresistive bridge PMOS transistor modules 4 are respectively connected to the power supply metal ring 105 and the grounding metal ring 106.

[0039] A single PMOS transistor 300 includes a metal interconnect 301, a P-type phosphorus implantation region 302, a metal interconnect 303, and a gate oxide layer 304.

[0040] Metal pads 108 are connected to the power supply metal ring 105, the grounding metal ring 106 and the output metal ring 107 respectively. The power supply metal ring 105, the grounding metal ring 106 and the output metal ring 107 are concentric circles.

[0041] The back of the chip has a back cavity 6, and a first silicon island 7, a cavity one 8, a second silicon island 9 and a cavity two 10 are disposed on the back cavity 6.

[0042] like Figure 5 This is a front view of a chip according to Embodiment 1 of the present invention, including a piezoresistive bridge 1011, a piezoresistive bridge 1012, a piezoresistive bridge 3 1013, a piezoresistive bridge 4 1014, a PMOS transistor 1041, a PMOS transistor 2 1042, a PMOS transistor 3 1043, a PMOS transistor 4 1044, a silicon pressure-sensitive membrane assembly 102, a central silicon island 103, a power supply metal ring 105, a grounding metal ring 106, an output metal ring 107, and a metal solder joint. Disk 108; where piezoresistive bridge one 1011, piezoresistive bridge two 1012, piezoresistive bridge three 1013 and piezoresistive bridge four 1014 are each composed of two implanted silicon piezoresistive transistors connected in series and are located at 0 degrees, 90 degrees, 180 degrees and 270 degrees on the silicon pressure-sensitive membrane assembly 102; PMOS transistor one 1041, PMOS transistor two 1042, PMOS transistor three 1043 and PMOS transistor four 1044 are fabricated within the chip frame using silicon implantation technology; piezoresistive bridge one Piezoresistive bridges 1011, 1012, 1013, and 1014 are connected to the power supply metal ring 105 and the ground metal ring 106, respectively. Two piezoresistive connection points in piezoresistive bridge 1011 are connected to the gate of PMOS transistor 1041; two piezoresistive connection points in piezoresistive bridge 1012 are connected to the gate of PMOS transistor 1042; two piezoresistive connection points in piezoresistive bridge 1013 are connected to the gate of PMOS transistor 1043; and two piezoresistive connection points in piezoresistive bridge 1014 are connected to the gate of PMOS transistor 1044. The sources (S) of PMOS transistors 1041, 1042, 1043, and 1044 are all connected to the power supply metal ring 105, and the drains (D) are all connected to the output metal ring 106. The central silicon island 103 is a single circle, which improves the stress and linearity of the piezoresistive region. Figure 6This is a back view of a chip according to Embodiment 1 of the present invention, which includes a silicon substrate 100, a back cavity 6, and a central silicon island 103. When gas is introduced into this chip, the silicon pressure-sensitive membrane assembly 102 deforms due to the gas pressure. At this time, the central silicon island 103, because its thickness is greater than that of the sensitive membrane assembly 102, only undergoes a small deformation, increasing the stress at its edge. Two piezoresistors in piezoresistance bridges 1011, 1012, 1013, and 1014 are located at the inner edge of the silicon pressure-sensitive membrane assembly 102 and the outer edge of the central silicon island, respectively. Because the stresses at the two locations are opposite, one piezoresistor in each piezoresistance bridge increases while the other decreases, thereby generating a linear voltage output. The output voltages of the above four piezoresistance bridges flow into the gates of PMOS transistors 1041, 1042, 1043, and 1044, respectively. Because the output current of the MOS transistors is saturated, the output current is... And V gs =V 压阻桥 -V 电源 The four PMOS transistors can output currents related to the applied air pressure. All four currents flow into the output metal ring 107. Due to the characteristics of current, the four outputs can be combined into one output, which can be read by an external circuit. The piezoresistive bridges 1011, 1012, 1013, and 1014 are connected to the gates of PMOS transistors 1041, 1042, 1043, and 1044 using a heavily doped silicon connection. When this heavily doped silicon connection is on the silicon pressure-sensitive membrane, it is fabricated using substrate silicon implantation. When it is on the outer frame, it is deposited using low-resistance polysilicon. The power supply metal ring 105, ground metal ring 106, and output metal ring 107 can be made of Al, AlCu, or Al. The metal ring 105 is located on the outer ring of the annular pressure-sensitive membrane assembly 102, with a diameter of 400μm-800μm and a width of 3μm-10μm. The grounding metal ring 106 is located on the inner side of the central silicon island 103, with a diameter of 100μm-300μm and a width of 3μm-10μm. The output metal ring 107 is located on the outer side of the power supply metal ring 105, with a diameter of 500μm-900μm. The metal pads 108 are square in shape, and from left to right are power supply, ground, and output. The material can be selected from single or combined metals such as Al, AlCu, AlSiCu, Au, and AuNi. The square metal pads have a side length of 120μm-200μm and a spacing of 50μm.

[0043] Example 2:

[0044] Please see the appendix Figure 7-8 This invention provides a MEMS piezoresistive pressure sensor, such as... Figure 7 As shown, the front side of the chip includes piezoresistive bridge 1011, piezoresistive bridge 2 1012, piezoresistive bridge 3 1013, piezoresistive bridge 4 1014, piezoresistive bridge 5 1015, piezoresistive bridge 6 1016, piezoresistive bridge 7 1017, and piezoresistive bridge 8 1018. Each of these piezoresistive bridges includes two injected silicon varistor components 102. The two ends of each piezoresistive bridge are respectively connected to a power supply metal ring 105 and a ground metal ring 106. The connection point of the two silicon varistor components 102 in each piezoresistive bridge is for signal output. Piezoresistive bridges 1011, 1012, 1013, and 1014 are located at 0°, 90°, 180°, and 270° on the first silicon pressure-sensitive membrane 1021, respectively; piezoresistive bridges 1015, 1016, 1017, and 1018 are located at 45°, 135°, 225°, and 315° on the second silicon pressure-sensitive membrane 1022, respectively; the first silicon island 7 is annular and located between the first silicon pressure-sensitive membrane 1021 and the second silicon pressure-sensitive membrane 1022. Between the sensitive membranes 1022; the second silicon island 9 is circular and located at the center of the second silicon pressure sensitive membrane 1022; the first silicon pressure sensitive membrane 1021 and the second silicon pressure sensitive membrane 1022 can have different thicknesses to achieve the purpose of balancing the stress in the eight piezoresistive bridges; this method improves the utilization rate of the silicon pressure sensitive membrane surface by reducing the area of ​​the central silicon island; Piezoresistive bridge one 1011, piezoresistive bridge two 1012, piezoresistive bridge three 1013, piezoresistive bridge four 1014, piezoresistive bridge five 1015, piezoresistive bridge six 1016, piezoresistive bridge five 1015, piezoresistive bridge six 1016, piezoresistive bridge five 1012, piezoresistive bridge six 1013, piezoresistive bridge six 1014, piezoresistive bridge six 1015, piezoresistive bridge six 1016, piezoresistive bridge six 1012 ... The output voltages of the piezoresistive bridge 7 (1017) and the piezoresistive bridge 8 (1018) are respectively input to the gates (G) of PMOS transistors 1 (1041), 1042, 1043, 1044, 1045, 1046, 1047, and 1048. The sources (S) of all these PMOS transistors are connected to the power supply metal ring, and the drains (D) are all connected to the output metal ring 107. Because the output current is [missing information] when the MOS transistors are saturated... And V gs =V 压阻桥 -V 电源 The four PMOS transistors can output currents related to the applied air pressure; all four currents flow into the output metal ring 107. Due to the characteristics of current, the four outputs can be combined into one output, which can be read by an external circuit; the back of the chip is shown below. Figure 8 As shown, it contains a silicon substrate 100, a first cavity 8, a first silicon island 7, a second cavity 10, and a second silicon island 9.

[0045] Example 3:

[0046] Please see the appendix Figure 9-10 This invention provides a MEMS piezoresistive pressure sensor. A front view of the chip in this embodiment is shown below. Figure 9It contains piezoresistive bridge 1011, piezoresistive bridge 2012, piezoresistive bridge 3013, and piezoresistive bridge 4014; each piezoresistive bridge contains two injected silicon piezoresistors; the two ends of each piezoresistive bridge are connected to the power supply metal ring 105 and the ground metal ring 106, respectively; the connection point of the two silicon piezoresistors in each piezoresistive bridge is the pressure signal output point; lever silicon islands 1011, 2012, 303, and 404 are located between piezoresistive bridges 1011, 1012, 1013, and 1014, respectively; the central silicon island 103 is located at the center of the silicon pressure-sensitive membrane; the signal output points of piezoresistive bridges 1011, 1012, 1013, and 1014 are connected to PMOS transistors 1041, 1042, 1043, and 1014, respectively. The gates of PMOS transistors 1043 and 1044, and the sources (S) of PMOS transistors 1041, 1042, 1043, and 1044 are all connected to the power supply metal ring 105, and their drains (D) are all connected to the output metal ring 107. When air flows into this chip, the silicon pressure-sensitive membrane assembly 102 deforms. Simultaneously, the lever silicon island assembly 5 and the central silicon island 103, being thicker, deform less, increasing the stress on their edge piezoresistors. Two piezoresistors in piezoresistor bridges 1011, 1012, 1013, and 1014 experience opposite stresses, resulting in increases and decreases in resistance, respectively, generating a linear voltage output. The output voltages of these four piezoresistor bridges are input to their corresponding PMOS transistors to generate current. Since the output current is [missing information] when the MOS transistor is saturated, [missing information]. And V gs =V 压阻桥 -V 电源 The four PMOS transistors can output currents related to the applied air pressure; all four currents flow into the output metal ring 107. Due to the characteristics of current, the four outputs can be combined into one output, which can be read by an external circuit. The back of this chip is shown below. Figure 10 It contains a silicon substrate, a back cavity, a lever silicon island, and a central silicon island.

[0047] Example 4:

[0048] Please see the appendix Figure 11 This invention provides a MEMS piezoresistive pressure sensor. The front side of the chip in this embodiment is shown below. Figure 11Based on the shape characteristics of the circular power supply metal ring 105, the circular grounding metal ring 106, and the output metal ring 107, the piezoresistive bridge + PMOS transistor module can be arranged arbitrarily and skillfully with the center of the silicon pressure-sensitive membrane as the rotation point, taking the piezoresistive bridge + PMOS transistor module as the unit. Since the stress is equal everywhere at the same radius of the inner edge of the circular pressure-sensitive membrane and the stress is equal everywhere at the same radius of the outer edge of the central silicon island 103, the piezoresistive bridge PMOS transistor module 4 can be placed in any position. This design can achieve the required output voltage by increasing or decreasing the number of modules. Figure 11 The diagram shows a configuration of 10 piezoresistive bridge PMOS transistor modules 4. Each piezoresistive bridge module 4 contains two varistors. The two ends of each piezoresistive bridge are connected to the power supply metal ring 105 and the ground metal ring 106, respectively. The two varistors in each piezoresistive bridge are connected in series, with the connection point in the middle serving as the signal output point. The signal output of each piezoresistive bridge is sent to the gate of the corresponding PMOS transistor to be converted into a current signal. The sources (S) of all 10 corresponding PMOS transistors are connected to the power supply metal ring 105, and the drains are connected to the output metal ring 106. When airflow enters this chip, the silicon pressure-sensitive membrane assembly 102 deforms. The output voltages of the ten piezoresistive bridges are input to their corresponding PMOS transistors to generate current. Since the output current is when the MOS transistor is saturated, the output current is... And V gs =V 压阻桥 -V 电源 The above ten PMOS transistors can output current related to the applied air pressure; all ten currents flow into the output metal ring 107. Due to the current characteristics, the above four outputs can be combined into one output, which can be read by the external circuit.

[0049] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A MEMS piezoresistive pressure sensor, characterized in that, The assembly includes a silicon substrate (100), a piezoresistive bridge assembly (101), a silicon pressure-sensitive membrane assembly (102), a PMOS transistor assembly (104), a metal pad (108), a silicon piezoresistive assembly (200), a silicon cavity (202), and a lever silicon island assembly (5). The piezoresistive bridge assembly (101) is connected in series with the silicon piezoresistive assembly (200). The piezoresistive bridge assembly (101) is disposed on the silicon pressure-sensitive membrane assembly (102). The PMOS transistor assembly (104) is disposed within the chip frame. The two ends of the piezoresistive bridge assembly (101) are respectively connected to a power supply metal ring (105) and a ground metal ring (106). The piezoresistive bridge assembly (101) includes piezoresistive bridge one (1011), piezoresistive bridge two (1012), piezoresistive bridge three (1013), piezoresistive bridge four (1014), piezoresistive bridge five (1015), piezoresistive bridge six (1016), piezoresistive bridge seven (1017) and piezoresistive bridge eight (1018); The PMOS transistor assembly (104) includes PMOS transistor one (1041), PMOS transistor two (1042), PMOS transistor three (1043), PMOS transistor four (1044), PMOS transistor five (1045), PMOS transistor six (1046), PMOS transistor seven (1047), PMOS transistor eight (1048) and a single PMOS transistor (300); The two piezoresistive connection points of piezoresistive bridge one (1011) are connected to the gate of PMOS transistor one (1041), the two piezoresistive connection points of piezoresistive bridge two (1012) are connected to the gate of PMOS transistor two (1042), the two piezoresistive connection points of piezoresistive bridge three (1013) are connected to the gate of PMOS transistor three (1043), and the two piezoresistive connection points of piezoresistive bridge four (1014) are connected to the gate of PMOS transistor four (1044). PMOS transistor one (1041), PMOS transistor two (1042), and PMOS transistor three (1043) are connected to PMOS transistor... The source S of the four (1044) are all connected to the power supply metal ring (105). The drain D of the PMOS transistors one (1041), two (1042), three (1043) and four (1044) are all connected to the output metal ring (107). The piezoresistive bridges one (1011), two (1012), three (1013) and four (1014) are respectively provided with two silicon piezoresistive bridges one (20111), two (20112), three (20121) and four (20122). The two ends of the piezoresistive bridges 1 (1011), 2 (1012), 3 (1013), 4 (1014), 5 (1015), 6 (1016), 7 (1017) and 8 (1018) are respectively connected to the power supply metal ring (105) and the grounding metal ring (106); The lever silicon island assembly (5) includes lever silicon island one (501), lever silicon island two (502), lever silicon island three (503) and lever silicon island four (504), which are respectively disposed between the two silicon piezoresistors of piezoresistor bridge one (1011), piezoresistor bridge two (1012), piezoresistor bridge three (1013) and piezoresistor bridge four (1014).

2. The MEMS piezoresistive pressure sensor according to claim 1, characterized in that, The silicon pressure-sensitive membrane assembly (102) includes a first silicon pressure-sensitive membrane (1021) and a second silicon pressure-sensitive membrane (1022). The first silicon pressure-sensitive membrane (1021), the second silicon pressure-sensitive membrane (1022), and the central silicon island (103) are all circular. The central silicon island (103) is concentric with the first silicon pressure-sensitive membrane (1021) and the second silicon pressure-sensitive membrane (1022) and is located at the center of the sensor chip. The outer rings of the first silicon pressure-sensitive membrane (1021) and the second silicon pressure-sensitive membrane (1022) are connected to the outer frame of the pressure sensor, and the inner rings of the first silicon pressure-sensitive membrane (1021) and the second silicon pressure-sensitive membrane (1022) are connected to the central silicon island (103).

3. The MEMS piezoresistive pressure sensor according to claim 2, characterized in that, Piezoresistive bridges one (1011), two (1012), three (1013), and four (1014) are respectively disposed on the first silicon pressure-sensitive membrane (1021). Piezoresistive bridges five (1015), six (1016), seven (1017), and eight (1018) are respectively disposed on the second silicon pressure-sensitive membrane (1022). The output voltages of piezoresistive bridges 4 (1014), 5 (1015), 6 (1016), 7 (1017), and 8 (1018) are respectively connected to the gates of PMOS transistors 1 (1041), 2 (1042), 3 (1043), 4 (1044), 5 (1045), 6 (1046), 7 (1047), and 8 (1048).

4. The MEMS piezoresistive pressure sensor according to claim 1, characterized in that, The piezoresistive bridge PMOS transistor module (4) is provided in several groups, and the several groups of the piezoresistive bridge PMOS transistor module (4) are arranged arbitrarily with the center of the silicon pressure sensitive film component (102) as the center. Each group of the piezoresistive bridge PMOS transistor module (4) is connected in series with two varistors. The two ends of each group of the piezoresistive bridge PMOS transistor module (4) are respectively connected to the power supply metal ring (105) and the grounding metal ring (106). The piezoresistive bridge PMOS module (4) consists of any one piezoresistive bridge in the piezoresistive bridge assembly and a corresponding PMOS transistor in the PMOS transistor assembly connected to it.

5. The MEMS piezoresistive pressure sensor according to claim 1, characterized in that, A single PMOS transistor (300) includes a first metal interconnect (301), a P-type phosphorus implantation region (302), a second metal interconnect (303), and a gate oxide layer (304).

6. The MEMS piezoresistive pressure sensor according to claim 1, characterized in that, The metal pads (108) are respectively connected to the power supply metal ring (105), the grounding metal ring (106) and the output metal ring (107), and the power supply metal ring (105), the grounding metal ring (106) and the output metal ring (107) are concentric circles.

7. The MEMS piezoresistive pressure sensor according to claim 1, characterized in that, The back of the chip is provided with a back cavity (6), and a first silicon island (7), a cavity one (8), a second silicon island (9) and a cavity two (10) are provided on the back cavity (6).

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