A current limiting value self-adaptive adjusting circuit for buck / boost converter

Abstract

The application discloses a current limiting value self-adaptive adjusting circuit for a Buck / Boost converter, which comprises a hysteresis comparator, a slope generation circuit, a sample-and-hold circuit, a V / I conversion circuit and a dynamic hysteresis current output circuit; the slope generation circuit outputs corresponding slope voltages in a Buck mode or a Boost mode; the sample-and-hold circuit collects and holds the maximum value of the slope voltages; the V / I conversion circuit obtains the maximum slope current through a clamping resistor; the dynamic hysteresis current output circuit outputs a dynamic hysteresis current according to the control signal of a power tube in the Buck mode or the Boost mode and the maximum slope current; and the hysteresis comparator outputs an adaptively adjusted current limiting value according to the current limiting threshold value in the Buck mode or the Boost mode, the sampling voltage and the dynamic hysteresis current. The application can adaptively adjust the current limiting value of the Buck / Boost converter according to the size of slope compensation.

Description

Technical Field

[0001] This invention relates to an adaptive current limiting circuit for a Buck / Boost converter, belonging to the field of integrated circuit technology. Background Technology

[0002] Currently, PWM peak / valley current-mode DC-DC chips use a current loop to regulate the output voltage through feedback. However, the conjugate poles generated by the current loop significantly impact loop stability, necessitating the addition of a ramp signal to compensate the sampling signal and avoid subharmonic oscillations when the duty cycle is greater than 50% (peak current mode) / less than 50% (valley current mode). However, for peak current-mode control, the compensation of the sampling signal reduces the peak inductor current; for valley current-mode control, the compensation increases the valley inductor current, thus affecting the current limiting threshold.

[0003] Traditional current-limiting circuits directly avoid the effects of slope compensation by converting the current sampling signal into a voltage signal and comparing it directly with a reference voltage. Traditional Buck or Boost converters can generate a fixed slope to compensate for the current-limiting threshold. However, for Buck / Boost converters that use valley current-mode sensing in Buck mode and peak current-mode sensing in Boost mode, due to their wide input / output range, using a fixed slope to compensate for the current-limiting threshold is ineffective. Summary of the Invention

[0004] To address the issue of slope compensation affecting current limiting values ​​in existing Buck / Boost converters, this invention proposes an adaptive current limiting adjustment circuit for Buck / Boost converters. In the Buck / Boost converter, a dynamic adjustment current is generated by sampling the adaptive slope compensation circuit. The magnitude of this adjustment current varies with the magnitude of the slope compensation. This adjustment current is then added as a hysteresis current to the hysteresis comparator, thereby generating dynamic compensation for the current limiting threshold.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical means:

[0006] This invention proposes an adaptive current limit adjustment circuit for a Buck / Boost converter, comprising a hysteresis comparator, a ramp generation circuit, a sample-and-hold circuit, a V / I conversion circuit, and a dynamic hysteresis current output circuit;

[0007] The ramp generation circuit outputs the corresponding ramp voltage in Buck mode or Boost mode; the sample-and-hold circuit acquires and holds the maximum value of the ramp voltage; the V / I conversion circuit obtains the maximum ramp current through the clamping resistor; the dynamic hysteresis current output circuit outputs the dynamic hysteresis current according to the control signal of the power transistor in Buck mode or Boost mode and the maximum ramp current; the hysteresis comparator outputs an adaptively adjusted current limit value according to the current limiting threshold, the sampled voltage and the dynamic hysteresis current in Buck mode or Boost mode.

[0008] Furthermore, the peripheral circuit includes a first power transistor H1, a second power transistor H2, a first power transistor L1, a second power transistor L2, an inductor L, and a sampling resistor Rs. The drain of the first power transistor H1 is connected to the input Vi, the drain of the second power transistor H2 is connected to the output Vo, the source of the first power transistor H1 and the drain of the first power transistor L1 are respectively connected to one end of the inductor L, the source of the second power transistor H2 and the drain of the second power transistor L2 are respectively connected to the other end of the inductor L, the source of the first power transistor L1 and the source of the second power transistor L2 are respectively connected to one end of the sampling resistor Rs, and the other end of the sampling resistor Rs is grounded.

[0009] The sampling current of the sampling resistor Rs in Buck mode or Boost mode is acquired by a current sampling circuit connected in parallel across the sampling resistor Rs, and the sampling current is converted into a sampling voltage.

[0010] Furthermore, the ramp generation circuit includes a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a transconductance amplifier OTA, a ramp capacitor Cslope, and a ramp switch S0. One end of the fifth switch S5 and one end of the seventh switch S7 are respectively connected to the input Vi. One end of the sixth switch S6 and one end of the eighth switch S8 are respectively connected to the output Vo. The other ends of the fifth switch S5 and the eighth switch S8 are respectively connected to the non-inverting input of the transconductance amplifier OTA. The other ends of the sixth switch S6 and the seventh switch S7 are respectively connected to the inverting input of the transconductance amplifier OTA. The output of the transconductance amplifier OTA is respectively connected to one end of the ramp capacitor Cslope and the sample-and-hold circuit. The other end of the ramp capacitor Cslope is grounded. The ramp switch S0 is connected in parallel across the two ends of the ramp capacitor Cslope.

[0011] Furthermore, the sample-and-hold circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, and a second capacitor C2. One end of the first switch S1 and one end of the third switch S3 are respectively connected to the ramp generation circuit. The other end of the first switch S1 is connected to one end of the second switch S2. The other end of the third switch S3 is connected to one end of the fourth switch S4. The other ends of the second switch S2 and the fourth switch S4 are respectively connected to the V / I conversion circuit. One end of the first capacitor C1 is connected to the other end of the first switch S1 and one end of the second switch S2. One end of the second capacitor C2 is connected to the other end of the third switch S3 and one end of the fourth switch S4. The other ends of the first capacitor C1 and the second capacitor C2 are grounded.

[0012] Furthermore, the V / I conversion circuit includes an operational amplifier U1, a fifth P-type MOSFET P5, a sixth P-type MOSFET P6, a seventh N-type MOSFET N7, a ninth N-type MOSFET N9, an eleventh N-type MOSFET N11, and an eighth resistor R8. The non-inverting input of the operational amplifier U1 is connected to the sample-and-hold circuit, and the output of the operational amplifier U1 is connected to the gate of the eleventh N-type MOSFET N11. The inverting input of the operational amplifier U1 and the source of the eleventh N-type MOSFET N11 are respectively connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is grounded. The drain of the eleventh N-type MOSFET N11 is connected to the fifth P-type MOSFET P6. The drain of MOSFET P5 is connected to the drain of MOSFET N11, and the gate of MOSFET P5 is connected to the gate of MOSFET P6. The source of MOSFET P5 is connected to the source of MOSFET P6. The drain of MOSFET P6 is connected to the drain and gate of MOSFET N9. The source of MOSFET N9 is connected to the drain and gate of MOSFET N7. The source of MOSFET N7 is grounded. The gates of MOSFET N9 and MOSFET N7 are connected to the dynamic hysteresis current output circuit.

[0013] Furthermore, the dynamic hysteresis current output circuit includes a seventh P-type MOSFET P7, an eighth P-type MOSFET P8, a ninth P-type MOSFET P9, a tenth P-type MOSFET P10, an eleventh P-type MOSFET P11, an eighth N-type MOSFET N8, a tenth N-type MOSFET N10, a twelfth N-type MOSFET N12, a thirteenth N-type MOSFET N13, a fourteenth N-type MOSFET N14, and a fifteenth N-type MOSFET N15. The gates of the eighth N-type MOSFET N8 and the tenth N-type MOSFET N10 are connected to the V / I conversion circuit. The drain of the eighth N-type MOSFET N8 is connected to the source of the tenth N-type MOSFET N10. The drain of the tenth N-type MOSFET N10 is connected to the drain of the seventh P-type MOSFET P7. The source of the seventh P-type MOSFET P7 is connected to the source of the eighth P-type MOSFET P8, and then connected to the drain of the eleventh P-type MOSFET P11. The gate of the seventh P-type MOSFET P7 is connected to the gate of the eighth P-type MOSFET P8, and then connected to the drain of the tenth N-type MOSFET N10. The gate of the eleventh P-type MOSFET P11 is connected in Buck mode or Boo mode. In ST mode, the control signal for the power transistors is as follows: the drain of the eighth P-type MOSFET P8 is connected to the drain of the fourteenth N-type MOSFET N14; the source of the fourteenth N-type MOSFET N14 is connected to the drain of the twelfth N-type MOSFET N12; the gate of the fourteenth N-type MOSFET N14 is connected to the gate of the fifteenth N-type MOSFET N15; the source of the fifteenth N-type MOSFET N15 is connected to the drain of the thirteenth N-type MOSFET N13; and the gate of the twelfth N-type MOSFET N12 is connected to the gate of the thirteenth N-type MOSFET N13. The source of the 12th N-type MOSFET N12, the source of the 13th N-type MOSFET N13, and the source of the 8th N-type MOSFET N8 are grounded. The drain of the 15th N-type MOSFET N15 is connected to the drain of the 9th P-type MOSFET P9. The gate of the 9th P-type MOSFET P9 is connected to the gate of the 10th P-type MOSFET P10 and then connected to the drain of the 15th N-type MOSFET N15. The source of the 9th P-type MOSFET P9 is connected to the source of the 10th P-type MOSFET P10. The drain of the 10th P-type MOSFET P10 is connected to the hysteresis comparator.

[0014] Furthermore, the hysteresis comparator includes a first P-type MOSFET P1, a second P-type MOSFET P2, a third P-type MOSFET P3, a fourth P-type MOSFET P4, a first N-type MOSFET N1, a second N-type MOSFET N2, a third N-type MOSFET N3, a fourth N-type MOSFET N4, a fifth N-type MOSFET N5, a sixth N-type MOSFET N6, a Schmitt trigger X1, and an inverter X2. The drain of the fifth N-type MOSFET N5 is connected to the hysteresis current in Buck mode output by the dynamic hysteresis current output circuit, and the drain of the sixth N-type MOSFET N6 is connected to the dynamic hysteresis current output circuit. The output hysteresis current in Boost mode is as follows: the gate of the fifth N-type MOSFET N5 is connected to the Buck mode start signal; the gate of the sixth N-type MOSFET N6 is connected to the Boost mode start signal; the source of the fifth N-type MOSFET N5 is connected to the drain of the second P-type MOSFET P2 and the drain of the first N-type MOSFET N1; the source of the sixth N-type MOSFET N6 is connected to the drain of the third P-type MOSFET P3 and the drain of the second N-type MOSFET N2; the gate of the second P-type MOSFET P2 is connected to the gate of the first P-type MOSFET P1 and then connected to the first... The drain of N-type MOSFET N1 is connected to the drain of the second N-type MOSFET N2. The gates of the third P-type MOSFET P3 and the fourth P-type MOSFET P4 are connected to each other. The sources of the first P-type MOSFET P1, the second P-type MOSFET P2, the third P-type MOSFET P3, and the fourth P-type MOSFET P4 are connected. The gate of the first N-type MOSFET N1 is connected to the current limiting threshold in Buck or Boost mode. The gate of the second N-type MOSFET N2 is connected to the sampling voltage. The sources of the first N-type MOSFET N1 and the second N-type MOSFET N2 are connected to each other. The source of N2 is grounded. The drain of the first P-type MOSFET P1 is connected to the drain and gate of the third N-type MOSFET N3. The gate of the third N-type MOSFET N3 is connected to the gate of the fourth N-type MOSFET N4. The sources of the third N-type MOSFET N3 and the fourth N-type MOSFET N4 are grounded. The drain of the fourth N-type MOSFET N4 and the drain of the fourth P-type MOSFET P4 are connected to the input of the Schmitt trigger X1. The output of the Schmitt trigger X1 is connected to the input of the inverter X2. The output of the inverter X2 outputs an adaptively adjusted current limiting value.

[0015] Furthermore, in the ramp generation circuit, the fifth switch S5 and the sixth switch S6 are turned on in Buck mode, and the seventh switch S7 and the eighth switch S8 are turned on in Boost mode. The ramp voltage signal generated by the ramp generation circuit is:

[0016]

[0017] Where Vslope is the ramp voltage, Gm is the amplification factor of the transconductance amplifier, Vo is the input voltage, Vi is the output voltage, Cslope is the capacitance of the ramp capacitor, and t is the time.

[0018] Furthermore, in the dynamic hysteresis current output circuit, the control signal of the first power transistor L1 or the second power transistor L2 in the peripheral circuit is integrator to generate the control signal of the eleventh P-type MOSFET P11. When the first power transistor L1 or the second power transistor L2 is turned on, the eleventh P-type MOSFET P11 gradually transitions from the linear region to the cutoff region, thereby controlling the maximum slope current Islopemax of the mirror of the ninth N-type MOSFET N9 to gradually decrease. When the slope compensation increases, the maximum slope current Islopemax increases simultaneously, and the dynamic hysteresis current Ihysteresis is output to the hysteresis comparator through the mirror of the tenth P-type MOSFET P10.

[0019] In Buck mode, the first power transistor L1 is turned on, and the dynamic hysteresis output by the dynamic hysteresis current output circuit is used as the hysteresis current Ihys_buck in Buck mode; in Boost mode, the second power transistor L2 is turned on, and the dynamic hysteresis output by the dynamic hysteresis current output circuit is used as the hysteresis current Ihys_boost in Boost mode.

[0020] Furthermore, when the Buck / Boost converter operates in Buck mode, the fifth N-type MOSFET N5 is turned on and the sixth N-type MOSFET N6 is turned off. The hysteresis current Ihys_buck in Buck mode is injected into the drain of the first N-type MOSFET N1, increasing the drain potential of the first N-type MOSFET N1 and reducing the trigger threshold of the sampling voltage Vcs. When the first power transistor L1 is turned on, current flows through the sampling resistor Rs, and at the same time, the eleventh P-type MOSFET P11 begins to switch from the linear region to the cutoff region. The hysteresis current Ihys_buck in Buck mode gradually decreases, offsetting the effect of the valley current mode slope compensation on the current limiting value.

[0021] When the Buck / Boost converter operates in Boost mode, the fifth N-type MOSFET N5 is off, and the sixth N-type MOSFET N6 is on. In Boost mode, the hysteresis current Ihys_boost is injected into the drain of the second N-type MOSFET N2, increasing the drain potential of the second N-type MOSFET N2 and raising the trigger threshold of the sampling voltage Vcs. When the second power transistor L2 is on, current flows through the sampling resistor Rs, and at the same time, the eleventh P-type MOSFET P11 begins to switch from the linear region to the cutoff region. In Boost mode, the hysteresis current Ihys_boost gradually decreases, offsetting the effect of the slope compensation of the peak current mode on the current limiting value.

[0022] The following advantages can be obtained by adopting the above technical means:

[0023] This invention proposes an adaptive current limit adjustment circuit for Buck / Boost converters. Based on the ramp voltage generated in the ramp generation circuit, a dynamic hysteresis current output circuit outputs a hysteresis current that varies with the magnitude of ramp compensation. The hysteresis current is used to dynamically compensate the current limit of the Buck / Boost converter, thereby achieving the function of adaptively adjusting the current limit based on the magnitude of ramp compensation. This solves the problem of the impact of ramp compensation on the current limit in existing Buck / Boost converters. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the current limiting value adaptive adjustment circuit for the Buck / Boost converter of the present invention;

[0025] Figure 2 This is a schematic diagram of the ramp generation circuit in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the sample-and-hold circuit in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the V / I conversion circuit and the dynamic hysteresis current output circuit in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of the result of the hysteresis comparator in an embodiment of the present invention;

[0029] Figure 6 This is a waveform diagram of various parts of the current limiting value adaptive adjustment circuit in an embodiment of the present invention. Detailed Implementation

[0030] The technical solution of the present invention will be further described below with reference to the accompanying drawings:

[0031] To address the impact of slope compensation on current limiting in peak current-mode Buck / Boost converters, this invention samples the adaptive slope compensation circuit to generate a dynamically adjusted current. The magnitude of this current varies with the slope compensation magnitude. This current is then added as a hysteresis current to the hysteresis comparator, thereby generating dynamic compensation for the current limiting threshold.

[0032] This invention proposes an adaptive current limiting circuit for Buck / Boost converters, such as... Figure 1 As shown, it includes a hysteresis comparator, a ramp generation circuit, a sample-and-hold circuit, a V / I conversion circuit, and a dynamic hysteresis current output circuit. The chip used in this invention has some peripheral circuits and current sampling circuits set up around it to implement the Buck / Boost function. To facilitate understanding of the working principle of this invention, Figure 1 The peripheral circuit and current sampling circuit are also shown.

[0033] In this embodiment of the invention, the input power supply Vi and the output voltage Vo are respectively connected to the peripheral circuit and the ramp generation circuit. The input terminal of the current sampling circuit is connected in parallel across the sampling resistor Rs of the peripheral circuit. The output terminal of the current sampling circuit outputs the sampling voltage Vcs and is connected to the inverting input terminal of the hysteresis comparator. The non-inverting input terminal of the hysteresis comparator is connected to the current limiting threshold Vth_buck / Vth_boost in Buck mode or Boost mode. The ramp generation circuit, the sample and hold circuit, the V / I conversion circuit, and the dynamic hysteresis current output circuit are connected in sequence. The dynamic hysteresis current output circuit is also connected to the control signal of the power transistor in the peripheral circuit in Buck mode or Boost mode. The dynamic hysteresis current output circuit outputs the hysteresis current to the hysteresis comparator. The output terminal of the hysteresis comparator outputs the adaptively adjusted current limiting value.

[0034] The working principle of the circuit of this invention is as follows:

[0035] The ramp generation circuit outputs the corresponding ramp voltage in Buck or Boost mode; the sample-and-hold circuit acquires and holds the maximum value of the ramp voltage; the V / I conversion circuit obtains the maximum ramp current through the clamping resistor; the dynamic hysteresis current output circuit outputs the dynamic hysteresis current based on the control signal of the power transistor in the peripheral circuit and the maximum ramp current in Buck or Boost mode; the hysteresis comparator outputs the adaptively adjusted current limit value based on the current limiting threshold in Buck or Boost mode, the sampled voltage output by the current sampling circuit, and the dynamic hysteresis current.

[0036] like Figure 1As shown, the peripheral circuit includes a first power transistor H1, a second power transistor H2, a first power transistor L1, a second power transistor L2, an inductor L, and a sampling resistor Rs. The drain of the first power transistor H1 is connected to the input power supply Vi, and the drain of the second power transistor H2 is connected to the output voltage Vo. The source of the first power transistor H1 and the drain of the first power transistor L1 are respectively connected to one end of the inductor L. The source of the second power transistor H2 and the drain of the second power transistor L2 are respectively connected to the other end of the inductor L. The source of the first power transistor L1 and the source of the second power transistor L2 are respectively connected to one end of the sampling resistor Rs, and the other end of the sampling resistor Rs is grounded.

[0037] The current sampling circuit is connected in parallel across the sampling resistor Rs to collect the sampling current of the sampling resistor Rs in Buck mode or Boost mode, and convert the sampling current into a sampling voltage.

[0038] like Figure 2 As shown, the ramp generation circuit includes a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a transconductance amplifier OTA, a ramp capacitor Cslope, and a ramp switch S0. One end of the fifth switch S5 and one end of the seventh switch S7 are connected to the input Vi, one end of the sixth switch S6 and one end of the eighth switch S8 are connected to the output Vo, the other end of the fifth switch S5 and the other end of the eighth switch S8 are connected to the non-inverting input of the transconductance amplifier OTA, the other end of the sixth switch S6 and the other end of the seventh switch S7 are connected to the inverting input of the transconductance amplifier OTA, the output of the transconductance amplifier OTA is connected to one end of the ramp capacitor Cslope and the sample-and-hold circuit, the other end of the ramp capacitor Cslope is grounded, and the ramp switch S0 is connected in parallel across the ramp capacitor Cslope.

[0039] In the ramp generation circuit, the control signal waveform of ramp switch S0 is as follows: Figure 6 As shown, in Figure 6 In this context, PWM is the signal used by the DC-DC converter to control the switching of the power transistors in the peripheral circuit. Figure 6The diagram illustrates the rising and falling edges of the signal. t0, t2, t4, and t6 represent the rising edges of the clock signal, while t1, t3, t5, and t7 represent the rising edges of the PWM modulation signal. For both Buck and Boost modes, the ramp capacitor Cslope in the ramp generation circuit begins charging when the corresponding lower power transistor L1 (Buck) / lower power transistor L2 (Boost) is turned on, and discharges when the corresponding upper power transistor H1 (Buck) / higher power transistor H2 (Boost) is turned on. Switches S5 and S6 are turned on in Buck mode, and switches S7 and S8 are turned on in Boost mode to ensure the transconductance amplifier outputs the correct current. The ramp generation circuit provides the ramp compensation voltage signal Vslope to the Buck / Boost converter. The waveform of the ramp compensation voltage signal Vslope is shown below. Figure 6 As shown, the formula for calculating the slope voltage signal Vslope is as follows:

[0040]

[0041] Where Gm is the amplification factor of the transconductance amplifier, Vo is the input voltage, Vi is the output voltage, Cslope is the capacitance value of the ramp capacitor, and t is the time.

[0042] like Figure 3 As shown, the sample-and-hold circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, and a second capacitor C2. One end of the first switch S1 and one end of the third switch S3 are respectively connected to the ramp generation circuit. The other end of the first switch S1 is connected to one end of the second switch S2. The other end of the third switch S3 is connected to one end of the fourth switch S4. The other ends of the second switch S2 and the fourth switch S4 are respectively connected to the V / I conversion circuit. One end of the first capacitor C1 is connected to the other end of the first switch S1 and one end of the second switch S2. One end of the second capacitor C2 is connected to the other end of the third switch S3 and one end of the fourth switch S4. The other ends of the first capacitor C1 and the second capacitor C2 are grounded.

[0043] The switching control signals of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 in the sample-and-hold circuit are as follows: Figure 6 The waveform is shown in the diagram. When the first switch S1 is high, the first capacitor C1 charges, and the second capacitor C2 acquires the maximum value of the ramp voltage signal Vslope from the previous cycle, providing the input level Vslopemax to the gate of the V / I conversion circuit. When the first switch S1 is low, the first capacitor C1 charges to the maximum value of the ramp voltage signal Vslope, providing the input level Vslopemax to the gate of the V / I conversion circuit. The magnitude of Vslopemax is:

[0044]

[0045] Where Vslopemax represents the maximum value of the ramp voltage, D is the duty cycle, specifically, D represents the duty cycle of the first power transistor L1 in the valley current mode Buck, and the duty cycle of the second power transistor L2 in the peak current mode Boost, and Ts is the clock period.

[0046] like Figure 4 As shown, the V / I conversion circuit includes operational amplifier U1, fifth P-type MOSFET P5, sixth P-type MOSFET P6, seventh N-type MOSFET N7, ninth N-type MOSFET N9, eleventh N-type MOSFET N11, and eighth resistor R8. The non-inverting input of operational amplifier U1 is connected to a sample-and-hold circuit, and the output of operational amplifier U1 is connected to the gate of eleventh N-type MOSFET N11. The inverting input of operational amplifier U1 and the source of eleventh N-type MOSFET N11 are respectively connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is grounded. The drain of eleventh N-type MOSFET N11 is connected to the fifth P-type MOSFET P6. The drain of MOSFET P5, the gate of the fifth P-type MOSFET P5, and the gate of the sixth P-type MOSFET P6 are connected to the drain of the eleventh N-type MOSFET N11. The source of the fifth P-type MOSFET P5 is connected to the source of the sixth P-type MOSFET P6. The drain of the sixth P-type MOSFET P6 is connected to the drain and gate of the ninth N-type MOSFET N9. The source of the ninth N-type MOSFET N9 is connected to the drain and gate of the seventh N-type MOSFET N7. The source of the seventh N-type MOSFET N7 is grounded. The gates of the ninth N-type MOSFET N9 and the seventh N-type MOSFET N7 are connected to the dynamic hysteresis current output circuit.

[0047] In this embodiment of the invention, the V / I conversion circuit utilizes the virtual short characteristic of the operational amplifier to obtain the maximum slope current Islopemax through a clamping resistor. Let the resistance of the eighth resistor R8 be R, and the magnitude of the maximum slope current Islopemax be:

[0048]

[0049] like Figure 4As shown, the dynamic hysteresis current output circuit includes a seventh P-type MOSFET P7, an eighth P-type MOSFET P8, a ninth P-type MOSFET P9, a tenth P-type MOSFET P10, an eleventh P-type MOSFET P11, an eighth N-type MOSFET N8, a tenth N-type MOSFET N10, a twelfth N-type MOSFET N12, a thirteenth N-type MOSFET N13, a fourteenth N-type MOSFET N14, and a fifteenth N-type MOSFET N15. The gates of the eighth N-type MOSFET N8 and the tenth N-type MOSFET N10 are connected to V... In the / I conversion circuit, the drain of the eighth N-type MOSFET N8 is connected to the source of the tenth N-type MOSFET N10. The drain of the tenth N-type MOSFET N10 is connected to the drain of the seventh P-type MOSFET P7. The source of the seventh P-type MOSFET P7 is connected to the source of the eighth P-type MOSFET P8, and then connected to the drain of the eleventh P-type MOSFET P11. The gate of the seventh P-type MOSFET P7 is connected to the gate of the eighth P-type MOSFET P8, and then connected to the drain of the tenth N-type MOSFET N10. The gate of the eleventh P-type MOSFET P11 is connected to Buc. In k-mode or Boost mode, the control signals for the power transistors are as follows: the drain of the eighth P-type MOSFET P8 is connected to the drain of the fourteenth N-type MOSFET N14; the source of the fourteenth N-type MOSFET N14 is connected to the drain of the twelfth N-type MOSFET N12; the gate of the fourteenth N-type MOSFET N14 is connected to the gate of the fifteenth N-type MOSFET N15; the source of the fifteenth N-type MOSFET N15 is connected to the drain of the thirteenth N-type MOSFET N13; and the gate of the twelfth N-type MOSFET N12 is connected to the gate of the thirteenth N-type MOSFET N13. The source of the twelfth N-type MOSFET N12, the source of the thirteenth N-type MOSFET N13, and the source of the eighth N-type MOSFET N8 are grounded. The drain of the fifteenth N-type MOSFET N15 is connected to the drain of the ninth P-type MOSFET P9. The gate of the ninth P-type MOSFET P9 is connected to the gate of the tenth P-type MOSFET P10 and then connected to the drain of the fifteenth N-type MOSFET N15. The source of the ninth P-type MOSFET P9 is connected to the source of the tenth P-type MOSFET P10. The drain of the tenth P-type MOSFET P10 is connected to the hysteresis comparator.

[0050] In this embodiment of the invention, the feedback signal of the control signal of the first power transistor L1 or the second power transistor L2 is as follows: Figure 6 As shown, the control signal of the first power transistor L1 or the second power transistor L2 is processed by an integrator to generate the control signal of the eleventh P-type MOSFET P11. The output of the integrator is as follows: Figure 6As shown. When the first power transistor L1 or the second power transistor L2 is turned on, the eleventh P-type MOSFET P11 gradually transitions from the linear region to the cutoff region, thereby controlling the maximum slope current Islopemax of the mirror of the ninth N-type MOSFET N9 to gradually decrease. When the slope compensation increases, the maximum slope current Islopemax increases simultaneously, and the dynamic hysteresis current Ihysteresis is output to the hysteresis comparator through the mirror of the tenth P-type MOSFET P10.

[0051] like Figure 5 As shown, in Buck mode, the first power transistor L1 is turned on, and the dynamic hysteresis output by the dynamic hysteresis current output circuit is used as the hysteresis current Ihys_buck in Buck mode; in Boost mode, the second power transistor L2 is turned on, and the dynamic hysteresis output by the dynamic hysteresis current output circuit is used as the hysteresis current Ihys_boost in Boost mode.

[0052] like Figure 5As shown, the hysteresis comparator includes a first P-type MOSFET P1, a second P-type MOSFET P2, a third P-type MOSFET P3, a fourth P-type MOSFET P4, a first N-type MOSFET N1, a second N-type MOSFET N2, a third N-type MOSFET N3, a fourth N-type MOSFET N4, a fifth N-type MOSFET N5, a sixth N-type MOSFET N6, a Schmitt trigger X1, and an inverter X2. The drain of the fifth N-type MOSFET N5 is connected to the hysteresis current Ihys_buck output in Buck mode from the dynamic hysteresis current output circuit, and the drain of the sixth N-type MOSFET N6 is connected to the Boost mode output in Boost mode from the dynamic hysteresis current output circuit. The hysteresis current Ihys_boost is given by the formula. The gate of the fifth N-type MOSFET N5 is connected to the Buck mode start signal Buck_on, and the gate of the sixth N-type MOSFET N6 is connected to the Boost mode start signal Boost_on. The source of the fifth N-type MOSFET N5 is connected to the drain of the second P-type MOSFET P2 and the drain of the first N-type MOSFET N1. The source of the sixth N-type MOSFET N6 is connected to the drain of the third P-type MOSFET P3 and the drain of the second N-type MOSFET N2. The gate of the second P-type MOSFET P2 is connected to the gate of the first P-type MOSFET P1 and then to the drain of the first N-type MOSFET N1. The gate of the third P-type MOSFET P3 is connected to the gate of the fourth P-type MOSFET P4, and then connected to the drain of the second N-type MOSFET N2. The sources of the first P-type MOSFET P1, the second P-type MOSFET P2, the third P-type MOSFET P3, and the fourth P-type MOSFET P4 are connected. The gate of the first N-type MOSFET N1 is connected to the current limiting threshold Vth_buck / Vth_boost in Buck or Boost mode. The gate of the second N-type MOSFET N2 is connected to the sampling voltage Vcs. The sources of the first N-type MOSFET N1 and the second N-type MOSFET N2 are grounded respectively. The source of transistor N1 is connected to the source of the second N-type MOSFET N2, which outputs the bias current source Iss of the hysteresis comparator. The drain of the first P-type MOSFET P1 is connected to the drain and gate of the third N-type MOSFET N3. The gate of the third N-type MOSFET N3 is connected to the gate of the fourth N-type MOSFET N4. The sources of the third N-type MOSFET N3 and the fourth N-type MOSFET N4 are grounded. The drain of the fourth N-type MOSFET N4 and the drain of the fourth P-type MOSFET P4 are connected to the input of Schmitt trigger X1. The output of Schmitt trigger X1 is connected to the input of inverter X2. The output of inverter X2 outputs the adaptively adjusted current limiting value.

[0053] In this embodiment of the invention, the working principle of the hysteresis comparator is as follows:

[0054] When the Buck / Boost converter operates in Buck mode, the fifth N-type MOSFET N5 is turned on, and the sixth N-type MOSFET N6 is turned off. The hysteresis current Ihys_buck in Buck mode is injected into the drain of the first N-type MOSFET N1, increasing the drain potential of the first N-type MOSFET N1 and decreasing the trigger threshold of the sampling voltage Vcs. When the first power transistor L1 is turned on, current flows through the sampling resistor Rs, and at the same time, the eleventh P-type MOSFET P11 begins to switch from the linear region to the cutoff region. The hysteresis current Ihys_buck in Buck mode gradually decreases, offsetting the effect of the valley current mode slope compensation on the current limiting value.

[0055] When the Buck / Boost converter operates in Boost mode, the fifth N-type MOSFET N5 is off, and the sixth N-type MOSFET N6 is on. In Boost mode, the hysteresis current Ihys_boost is injected into the drain of the second N-type MOSFET N2, increasing the drain potential of the second N-type MOSFET N2 and raising the trigger threshold of the sampling voltage Vcs. When the second power transistor L2 is on, current flows through the sampling resistor Rs, and at the same time, the eleventh P-type MOSFET P11 begins to switch from the linear region to the cutoff region. In Boost mode, the hysteresis current Ihys_boost gradually decreases, offsetting the effect of the slope compensation of the peak current mode on the current limiting value.

[0056] In this invention, when the slope compensation increases, Islopemax increases and Ihysteresis increases, resulting in a greater current hysteresis injected into the current limiting comparator, thereby achieving dynamic adjustment of the current limiting value according to the magnitude of the slope compensation.

[0057] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A current limiting value adaptive adjustment circuit for a Buck / Boost converter, characterized in that, It includes a hysteresis comparator, a ramp generation circuit, a sample-and-hold circuit, a V / I conversion circuit, and a dynamic hysteresis current output circuit. The input power supply Vi and the output voltage Vo are connected to the peripheral circuit and the ramp generation circuit, respectively. The input terminal of the current sampling circuit is connected in parallel across the sampling resistor Rs of the peripheral circuit. The output terminal of the current sampling circuit outputs the sampling voltage Vcs and is connected to the inverting input terminal of the hysteresis comparator. The non-inverting input terminal of the hysteresis comparator is connected to the current limiting threshold Vth_buck / Vth_boost in Buck mode or Boost mode. The ramp generation circuit, the sample-and-hold circuit, the V / I conversion circuit, and the dynamic hysteresis current output circuit are connected in sequence. The dynamic hysteresis current output circuit is also connected to the control signal of the power transistor in the peripheral circuit in Buck mode or Boost mode. The ramp generation circuit outputs the corresponding ramp voltage in Buck mode or Boost mode; the sample-and-hold circuit acquires and holds the maximum value of the ramp voltage; the V / I conversion circuit obtains the maximum ramp current through the clamping resistor; the dynamic hysteresis current output circuit outputs the dynamic hysteresis current according to the control signal of the power transistor in Buck mode or Boost mode and the maximum ramp current; the hysteresis comparator outputs an adaptively adjusted current limit value according to the current limiting threshold, the sampled voltage and the dynamic hysteresis current in Buck mode or Boost mode.

2. The adaptive current limiting adjustment circuit for a Buck / Boost converter according to claim 1, characterized in that, The peripheral circuit includes a first power transistor H1, a second power transistor H2, a first power transistor L1, a second power transistor L2, an inductor L, and a sampling resistor Rs. The drain of the first power transistor H1 is connected to the input Vi, and the drain of the second power transistor H2 is connected to the output Vo. The source of the first power transistor H1 and the drain of the first power transistor L1 are respectively connected to one end of the inductor L. The source of the second power transistor H2 and the drain of the second power transistor L2 are respectively connected to the other end of the inductor L. The source of the first power transistor L1 and the source of the second power transistor L2 are respectively connected to one end of the sampling resistor Rs, and the other end of the sampling resistor Rs is grounded. The sampling current of the sampling resistor Rs in Buck mode or Boost mode is acquired by a current sampling circuit connected in parallel across the sampling resistor Rs, and the sampling current is converted into a sampling voltage.

3. The adaptive current limiting adjustment circuit for a Buck / Boost converter according to claim 1, characterized in that, The ramp generation circuit includes a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a transconductance amplifier OTA, a ramp capacitor Cslope, and a ramp switch S0. One end of the fifth switch S5 and one end of the seventh switch S7 are respectively connected to the input Vi. One end of the sixth switch S6 and one end of the eighth switch S8 are respectively connected to the output Vo. The other ends of the fifth switch S5 and the eighth switch S8 are respectively connected to the non-inverting input of the transconductance amplifier OTA. The other ends of the sixth switch S6 and the seventh switch S7 are respectively connected to the inverting input of the transconductance amplifier OTA. The output of the transconductance amplifier OTA is connected to one end of the ramp capacitor Cslope and the sample-and-hold circuit. The other end of the ramp capacitor Cslope is grounded. The ramp switch S0 is connected in parallel across the two ends of the ramp capacitor Cslope.

4. The adaptive current limiting adjustment circuit for a Buck / Boost converter according to claim 1, characterized in that, The sample-and-hold circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, and a second capacitor C2. One end of the first switch S1 and one end of the third switch S3 are respectively connected to the ramp generation circuit. The other end of the first switch S1 is connected to one end of the second switch S2. The other end of the third switch S3 is connected to one end of the fourth switch S4. The other ends of the second switch S2 and the fourth switch S4 are respectively connected to the V / I conversion circuit. One end of the first capacitor C1 is connected to the other end of the first switch S1 and one end of the second switch S2. One end of the second capacitor C2 is connected to the other end of the third switch S3 and one end of the fourth switch S4. The other ends of the first capacitor C1 and the second capacitor C2 are grounded.

5. The adaptive current limiting adjustment circuit for a Buck / Boost converter according to claim 1, characterized in that, The V / I conversion circuit includes an operational amplifier U1, a fifth P-type MOSFET P5, a sixth P-type MOSFET P6, a seventh N-type MOSFET N7, a ninth N-type MOSFET N9, an eleventh N-type MOSFET N11, and an eighth resistor R8. The non-inverting input of the operational amplifier U1 is connected to the sample-and-hold circuit, and the output of the operational amplifier U1 is connected to the gate of the eleventh N-type MOSFET N11. The inverting input of the operational amplifier U1 and the source of the eleventh N-type MOSFET N11 are respectively connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is grounded. The drain of the eleventh N-type MOSFET N11 is connected to the fifth P-type MOSFET. The drain of P5 is connected to the drain of the eleventh N-type MOSFET N11 after the gate of the fifth P-type MOSFET P5 is connected to the gate of the sixth P-type MOSFET P6. The source of the fifth P-type MOSFET P5 is connected to the source of the sixth P-type MOSFET P6. The drain of the sixth P-type MOSFET P6 is connected to the drain and gate of the ninth N-type MOSFET N9. The source of the ninth N-type MOSFET N9 is connected to the drain and gate of the seventh N-type MOSFET N7. The source of the seventh N-type MOSFET N7 is grounded. The gates of the ninth N-type MOSFET N9 and the seventh N-type MOSFET N7 are connected to the dynamic hysteresis current output circuit.

6. The adaptive current limiting adjustment circuit for a Buck / Boost converter according to claim 1, characterized in that, The dynamic hysteresis current output circuit includes a seventh P-type MOSFET P7, an eighth P-type MOSFET P8, a ninth P-type MOSFET P9, a tenth P-type MOSFET P10, an eleventh P-type MOSFET P11, an eighth N-type MOSFET N8, a tenth N-type MOSFET N10, a twelfth N-type MOSFET N12, a thirteenth N-type MOSFET N13, a fourteenth N-type MOSFET N14, and a fifteenth N-type MOSFET N15. The gates of the eighth N-type MOSFET N8 and the tenth N-type MOSFET N10 are connected to the V / I conversion circuit. The drain of type N8 is connected to the source of the tenth type N MOSFET N10. The drain of the tenth type N MOSFET N10 is connected to the drain of the seventh type P MOSFET P7. The source of the seventh type P MOSFET P7 is connected to the source of the eighth type P MOSFET P8, and then connected to the drain of the eleventh type P MOSFET P11. The gate of the seventh type P MOSFET P7 is connected to the gate of the eighth type P MOSFET P8, and then connected to the drain of the tenth type N MOSFET N10. The gate of the eleventh type P MOSFET P11 is connected to either Buck mode or Boost mode. In this mode, the control signal for the power transistors is as follows: the drain of the eighth P-type MOSFET P8 is connected to the drain of the fourteenth N-type MOSFET N14; the source of the fourteenth N-type MOSFET N14 is connected to the drain of the twelfth N-type MOSFET N12; the gate of the fourteenth N-type MOSFET N14 is connected to the gate of the fifteenth N-type MOSFET N15; the source of the fifteenth N-type MOSFET N15 is connected to the drain of the thirteenth N-type MOSFET N13; and the gate of the twelfth N-type MOSFET N12 is connected to the gate of the thirteenth N-type MOSFET N13. The source of the second N-type MOSFET N12, the source of the thirteenth N-type MOSFET N13, and the source of the eighth N-type MOSFET N8 are grounded. The drain of the fifteenth N-type MOSFET N15 is connected to the drain of the ninth P-type MOSFET P9. The gate of the ninth P-type MOSFET P9 is connected to the gate of the tenth P-type MOSFET P10 and then connected to the drain of the fifteenth N-type MOSFET N15. The source of the ninth P-type MOSFET P9 is connected to the source of the tenth P-type MOSFET P10. The drain of the tenth P-type MOSFET P10 is connected to the hysteresis comparator.

7. The adaptive current limiting circuit for a Buck / Boost converter according to claim 1, characterized in that, The hysteresis comparator includes a first P-type MOSFET P1, a second P-type MOSFET P2, a third P-type MOSFET P3, a fourth P-type MOSFET P4, a first N-type MOSFET N1, a second N-type MOSFET N2, a third N-type MOSFET N3, a fourth N-type MOSFET N4, a fifth N-type MOSFET N5, a sixth N-type MOSFET N6, a Schmitt trigger X1, and an inverter X2. The drain of the fifth N-type MOSFET N5 is connected to the hysteresis current in Buck mode output by the dynamic hysteresis current output circuit. The sixth N-type MOSFET... The drain of the MOSFET N6 is connected to the hysteresis current output in Boost mode by the dynamic hysteresis current output circuit. The gate of the fifth N-type MOSFET N5 is connected to the Buck mode start signal. The gate of the sixth N-type MOSFET N6 is connected to the Boost mode start signal. The source of the fifth N-type MOSFET N5 is connected to the drain of the second P-type MOSFET P2 and the drain of the first N-type MOSFET N1. The source of the sixth N-type MOSFET N6 is connected to the drain of the third P-type MOSFET P3 and the drain of the second N-type MOSFET N1. The drain of the first N-type MOSFET N2 is connected to the drain of the first N-type MOSFET N1. The gate of the second P-type MOSFET P2 is connected to the gate of the first P-type MOSFET P1, and then connected to the drain of the first N-type MOSFET N1. The gate of the third P-type MOSFET P3 is connected to the gate of the fourth P-type MOSFET P4, and then connected to the drain of the second N-type MOSFET N2. The sources of the first P-type MOSFET P1, the second P-type MOSFET P2, the third P-type MOSFET P3, and the fourth P-type MOSFET P4 are connected. The first N-type MOSFET N2 is connected to the drain of the first N-type MOSFET N1. The gate of transistor 1 is connected to the current limiting threshold in Buck or Boost mode. The gate of the second N-type MOSFET N2 is connected to the sampling voltage. The source of the first N-type MOSFET N1 and the source of the second N-type MOSFET N2 are grounded. The drain of the first P-type MOSFET P1 is connected to the drain and gate of the third N-type MOSFET N3. The gate of the third N-type MOSFET N3 is connected to the gate of the fourth N-type MOSFET N4. The source of the third N-type MOSFET N3 and the source of the fourth N-type MOSFET N4 are grounded. The drain of the fourth N-type MOSFET N4 and the drain of the fourth P-type MOSFET P4 are connected to the input of the Schmitt trigger X1. The output of the Schmitt trigger X1 is connected to the input of the inverter X2. The output of the inverter X2 outputs the adaptively adjusted current limiting value.

8. The adaptive current limiting circuit for a Buck / Boost converter according to claim 3, characterized in that, In the ramp generation circuit, the fifth switch S5 and the sixth switch S6 are turned on in Buck mode, and the seventh switch S7 and the eighth switch S8 are turned on in Boost mode. The ramp voltage signal generated by the ramp generation circuit is: ； in, For ramp voltage, This is the gain of the transconductance amplifier. Input voltage, For output voltage, This represents the capacitance value of the ramp capacitor. t For a moment.

9. The adaptive current limiting adjustment circuit for a Buck / Boost converter according to claim 2 or 6, characterized in that, In the dynamic hysteresis current output circuit, the control signal of the first power transistor L1 or the second power transistor L2 in the peripheral circuit is integrator to generate the control signal of the eleventh P-type MOSFET P11. When the first power transistor L1 or the second power transistor L2 is turned on, the eleventh P-type MOSFET P11 gradually transitions from the linear region to the cutoff region, thereby controlling the maximum slope current Islopemax of the mirror of the ninth N-type MOSFET N9 to gradually decrease. When the slope compensation increases, the maximum slope current Islopemax increases at the same time, and the dynamic hysteresis current Ihysteresis is output to the hysteresis comparator through the mirror of the tenth P-type MOSFET P10. In Buck mode, the first power transistor L1 is turned on, and the dynamic hysteresis output by the dynamic hysteresis current output circuit is used as the hysteresis current Ihys_buck in Buck mode; in Boost mode, the second power transistor L2 is turned on, and the dynamic hysteresis output by the dynamic hysteresis current output circuit is used as the hysteresis current Ihys_boost in Boost mode.

10. The adaptive current limiting adjustment circuit for a Buck / Boost converter according to claim 7, characterized in that, When the Buck / Boost converter operates in Buck mode, the fifth N-type MOSFET N5 is turned on and the sixth N-type MOSFET N6 is turned off. The hysteresis current Ihys_buck in Buck mode is injected into the drain of the first N-type MOSFET N1, increasing the drain potential of the first N-type MOSFET N1 and reducing the trigger threshold of the sampling voltage Vcs. When the first power transistor L1 is turned on, current flows through the sampling resistor Rs, and at the same time, the eleventh P-type MOSFET P11 begins to switch from the linear region to the cutoff region. The hysteresis current Ihys_buck in Buck mode gradually decreases, offsetting the effect of the valley current mode slope compensation on the current limiting value. When the Buck / Boost converter operates in Boost mode, the fifth N-type MOSFET N5 is off, and the sixth N-type MOSFET N6 is on. In Boost mode, the hysteresis current Ihys_boost is injected into the drain of the second N-type MOSFET N2, increasing the drain potential of the second N-type MOSFET N2 and raising the trigger threshold of the sampling voltage Vcs. When the second power transistor L2 is on, current flows through the sampling resistor Rs, and at the same time, the eleventh P-type MOSFET P11 begins to switch from the linear region to the cutoff region. In Boost mode, the hysteresis current Ihys_boost gradually decreases, offsetting the effect of the slope compensation of the peak current mode on the current limiting value.

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