An open - circuit or short - circuit test method, system and platform for chip pins

Abstract

The present invention discloses an open - circuit or short - circuit test method, system and platform for chip pins. By the method, at least one matrix corresponding to the connection relationship between the network points among the chip pins is created; all the connection relationships between the network points in the matrix are traversed, and test paths corresponding to the network points are generated; according to the test paths, test drive data corresponding to the test paths and used for testing open - circuit or short - circuit between the chip pins is generated; level state data corresponding to the test drive data is obtained, and the connection relationship between the chip pins is determined in real time according to the level state data; and the corresponding system and platform of the method can improve the test path analysis efficiency and the open - circuit and short - circuit test efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of detection and processing, and particularly relates to an open or short circuit test method, system and platform for chip pins. Background Art

[0002] The boundary scan automatic test system software is a test software for the server motherboard or relatively complex PCBA (printed circuit board) in the fixture industry. Its main function is to automatically find the test paths by analyzing the board manufacturing data, generate chip pin drive data according to these paths, drive the Jtag (a communication protocol) signal to the chip under test through the controller. After the chip obtains the corresponding data, it drives the pins to output or receive input, and determines the faulty Pin (pin) or path by parsing the Jtag (a communication protocol) signal.

[0003] Currently, the boundary scan automatic test system analyzes a large amount of data, mainly relying on the test path analysis at the software integration platform level, and its analysis efficiency is not high. The open or short circuit test takes a long time and the test efficiency is low.

[0004] Therefore, aiming at the above technical problems and defects, it is urgent to design and develop an open or short circuit test method, system and platform for chip pins. Summary of the Invention

[0005] To overcome the deficiencies and difficulties of the above-mentioned prior art, the purpose of the present invention is to provide an open or short circuit test method, system and platform for chip pins in view of the technical problems and defects of low test path analysis efficiency, long open or short circuit test time and low test efficiency, so as to improve the test path analysis efficiency and the open and short circuit test efficiency.

[0006] The first object of the present invention is to provide an open or short circuit test method for chip pins; the second object of the present invention is to provide an open or short circuit test system for chip pins; the third object of the present invention is to provide an open or short circuit test platform for chip pins.

[0007] The first object of the present invention is achieved as follows: The method includes the following steps:

[0008] Create at least one matrix corresponding to the connection relationship between the network points among the chip pins;

[0009] Traverse the connection relationships between all network points in the matrix and generate test paths corresponding to the network points;

[0010] Generate test drive data corresponding to the test paths and used for testing open or short circuits between chip pins according to the test paths;

[0011] Level status data corresponding to the test drive data is acquired, and the connection relationship between the chip pins is determined in real time according to the level status data; wherein the connection relationship is an open circuit connection or a short circuit connection between the chip pins.

[0012] Furthermore, the step of creating at least one matrix corresponding to the network point connection relationship between chip pins further includes:

[0013] At least one stack, at least one first array, and at least one second array are created respectively; wherein the first array is used to store index records; and the second array is used to store paths;

[0014] Clearing the stack and the first array, and creating at least one third numerical variable; wherein the third numerical variable is used to store row index data;

[0015] The row data in the third numerical variable is obtained, the row data is pushed into a stack for processing, and the row data is placed in the first array.

[0016] Furthermore, the obtaining of the row data in the third numerical variable, stacking the row data, and placing the row data in the first array further includes:

[0017] Based on the row data, determine whether there is a connection relationship. If there is a connection relationship and the first array does not contain row data, then the row data is incremented; otherwise, traverse and record all elements in the current stack, save the elements to the second array, and remove the top element of the stack.

[0018] Furthermore, the traversing the connection relationships between all network points in the matrix and generating test paths corresponding to the network points further includes:

[0019] According to the connection relationship between the network points, the test paths corresponding to the connection relationship and repeated are eliminated, and at the same time, at least one fourth array is created; wherein the fourth array is used to store the array after the repeated paths are eliminated;

[0020] Traversing the second array and generating a first test path corresponding to the second array; wherein the first test path is the test path before sorting;

[0021] Arrange the first test path in ascending order in combination with the network point subscripts, and generate a second test path corresponding to the first test path; wherein the second test path is the test path after the sorting process;

[0022] Obtain the path data in the fourth array, and determine whether the path data in the fourth array contains the second test path; if not, place the second test path in the fourth array, otherwise, continue to traverse the next path.

[0023] Further, the traversing the connection relationships between all network points in the matrix and generating test paths corresponding to the network points further includes:

[0024] Integrate and merge the test paths, and generate corresponding test paths with unique IDs;

[0025] Create at least one fifth array, and place the test paths with unique IDs in the fifth array; wherein, the fifth array is a key-value pair array.

[0026] Further, the generating test drive data corresponding to the test path and used to test the open or short circuit between chip pins further includes:

[0027] Obtain the row data in the fifth array, and create at least one sixth array; wherein, the sixth array is used to store test drive data;

[0028] Assign values to the sixth array, traverse the fifth array, and binaryize the key data in the fifth array.

[0029] Further, the obtaining the level status data corresponding to the test drive data and determining the connection relationship between chip pins in real time according to the level status data further includes:

[0030] Traverse the column data in the sixth array and the corresponding test path set in sequence;

[0031] Generate chip pin data corresponding to the network points according to the network point information corresponding to the test path set;

[0032] According to the chip pin data, combined with the level signals sent by the pins, send test drive data in sequence.

[0033] The second object of the present invention is achieved as follows: The system is applied to the test method, and the system includes:

[0034] A matrix creation unit, configured to create at least one matrix corresponding to the connection relationships between network points between chip pins;

[0035] A first generation unit, configured to traverse the connection relationships between all network points in the matrix and generate test paths corresponding to the network points;

[0036] A second generation unit, configured to generate test drive data corresponding to the test path and used for testing open or short circuits between chip pins according to the test path;

[0037] A first determination unit, configured to obtain level status data corresponding to the test drive data and determine the connection relationship between chip pins in real time according to the level status data; wherein, the connection relationship is an open connection or a short connection between chip pins.

[0038] Further, the matrix creation unit further includes:

[0039] A first creation module, configured to create at least one stack, at least one first array, and at least one second array respectively; wherein, the first array is used to store index records; the second array is used to store paths;

[0040] A second creation module, configured to clear and process the stack and the first array, and create at least one third numerical variable; wherein, the third numerical variable is used to save row index data;

[0041] A first processing module, configured to obtain the row data in the third numerical variable, push the row data onto the stack, and place the row data in the first array at the same time;

[0042] And / or, the first processing module further includes:

[0043] A first determination module, configured to determine whether there is a connection relationship according to the row data;

[0044] And / or, the first generation unit further includes:

[0045] A third creation module, configured to eliminate duplicate test paths corresponding to the connection relationship according to the connection relationship between network points, and create at least one fourth array at the same time; wherein, the fourth array is used to store the array after eliminating duplicate paths;

[0046] A first generation module, configured to traverse the second array and generate a first test path corresponding to the second array; wherein, the first test path is the test path before sorting;

[0047] A second generation module, configured to perform ascending sorting processing in combination with the network point subscripts according to the first test path, and generate a second test path corresponding to the first test path; wherein, the second test path is the test path after sorting;

[0048] A second determination module, configured to obtain the path data in the fourth array and determine whether the path data in the fourth array has the second test path;

[0049] And / or, the first generating unit further includes:

[0050] A third generating module, configured to integrate and process the test paths, and generate corresponding test paths with unique IDs;

[0051] A fourth creating module, configured to create at least one fifth array, and place the test paths with unique IDs in the fifth array; wherein, the fifth array is a key-value pair array;

[0052] And / or, the second generating unit further includes:

[0053] A fifth creating module, configured to obtain row data in the fifth array and create at least one sixth array; wherein, the sixth array is used to store test drive data;

[0054] A second processing module, configured to perform assignment processing on the sixth array, traverse the fifth array, and perform binary processing on the key data in the fifth array;

[0055] And / or, the first determining unit further includes:

[0056] A first traversing module, configured to sequentially traverse the column data in the sixth array and the set of test paths corresponding to the column data;

[0057] A fourth generating module, configured to generate chip pin data corresponding to the network points according to the network point information corresponding to the set of test paths;

[0058] A first sending module, configured to sequentially send test drive data according to the chip pin data in combination with the level signals sent by the pins.

[0059] The third object of the present invention is achieved as follows: It includes a processor, a memory, and a control program for an open or short circuit test platform between chip pins; wherein, when the processor executes the control program for the open or short circuit test platform between chip pins, the control program for the open or short circuit test platform between chip pins is stored in the memory, and the control program for the open or short circuit test platform between chip pins implements the method for open or short circuit test between chip pins.

[0060] The present invention creates at least one matrix corresponding to the connection relationship between the network points and the chip pins; traverses the connection relationships between all network points in the matrix, and generates test paths corresponding to the network points; generates test drive data corresponding to the test paths and used to test the open or short circuit between the chip pins; obtains the level status data corresponding to the test drive data, and determines the connection relationship between the chip pins in real time according to the level status data; and a system and platform corresponding to the method can improve the test path analysis efficiency and the open / short circuit test efficiency.

[0061] That is to say, the present invention solves the problem of finding the open / short circuit test path. Compared with the traditional processing method, the analysis time is greatly reduced, the software experience is enhanced, and the productivity is improved to a certain extent. In addition, the algorithm process involved in the present invention does not depend on the programming language and operating system, and this process can be easily transplanted into any development environment required in practice. The algorithm for generating and processing the open / short circuit test drive data greatly reduces the number of tests. In the actual production process, it is directly reflected that the test time is significantly shortened and the production efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0063] Figure 1 It is a schematic flowchart of a method for testing open or short circuit between chip pins according to the present invention;

[0064] Figure 2 It is a schematic diagram of chip connection in an embodiment of a method for testing open or short circuit between chip pins according to the present invention;

[0065] Figure 3 It is a schematic diagram of a matrix in an embodiment of a method for testing open or short circuit between chip pins according to the present invention;

[0066] Figure 4 It is a schematic diagram of the stack processing process in an embodiment of a method for testing open or short circuit between chip pins according to the present invention;

[0067] Figure 5 It is a schematic diagram of drive data and expected data in an embodiment of a method for testing open or short circuit between chip pins according to the present invention;

[0068] Figure 6Schematic diagram of the chip scan register for an embodiment of a method for open or short circuit testing between chip pins in the present invention;

[0069] Figure 7 Schematic diagram of test data for an embodiment of a method for open or short circuit testing between chip pins in the present invention;

[0070] Figure 8 Schematic diagram of the system architecture for open or short circuit testing between chip pins in the present invention;

[0071] Figure 9 Schematic diagram of the platform architecture for open or short circuit testing between chip pins in the present invention;

[0072] The realization of the object, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0073] To better understand the object, technical solution and advantages of the present invention more clearly, the present invention will be further described below in conjunction with the accompanying drawings and specific implementation manners. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0074] The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If this specific posture changes, the directional indications will also change accordingly.

[0076] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. Secondly, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement it. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0077] Preferably, a method for open - circuit or short - circuit testing between chip pins of the present invention is applied in one or more terminals or servers. The terminal is a device capable of automatically performing numerical calculations and / or information processing according to pre - set or stored instructions. Its hardware includes, but is not limited to, a microprocessor, an application - specific integrated circuit (ASIC), a field - programmable gate array (FPGA), a digital signal processor (DSP), an embedded device, etc.

[0078] The terminal can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server, etc. The terminal can perform human - machine interaction with customers through means such as a keyboard, a mouse, a remote control, a touchpad, or a voice - controlled device.

[0079] The present invention aims to implement a method, a system, and a platform for open - circuit or short - circuit testing between chip pins.

[0080] As Figure 1 shown, it is a flowchart of the method for open - circuit or short - circuit testing between chip pins provided by an embodiment of the present invention.

[0081] In this embodiment, the method for open - circuit or short - circuit testing between chip pins can be applied to a terminal with a display function or a fixed terminal. The terminal is not limited to a personal computer, a smart phone, a tablet computer, a desktop computer or an all - in - one computer equipped with a camera, etc.

[0082] The method for open - circuit or short - circuit testing between chip pins can also be applied to a hardware environment composed of a terminal and a server connected to the terminal through a network. The network includes, but is not limited to, a wide - area network, a metropolitan - area network, or a local - area network. The method for open - circuit or short - circuit testing between chip pins in an embodiment of the present invention can be executed by the server, can be executed by the terminal, or can be jointly executed by the server and the terminal.

[0083] For example, for a terminal that needs to perform open or short circuit tests between chip pins, the open or short circuit test function between chip pins provided by the method of the present invention can be directly integrated on the terminal, or a client for implementing the method of the present invention can be installed. Again, the method provided by the present invention can also run on devices such as servers in the form of a Software Development Kit (SDK), and provide an interface for the open or short circuit test function between chip pins in the form of an SDK. The terminal or other devices can implement the open or short circuit test function between chip pins through the provided interface. The present invention will be further described below with reference to the accompanying drawings.

[0084] As Figures 1-9 shown, the present invention provides a method for open or short circuit testing between chip pins, and the method includes the following steps:

[0085] S1. Create at least one matrix corresponding to the connection relationship between the network points between chip pins;

[0086] S2. Traverse the connection relationships between all network points in the matrix and generate test paths corresponding to the network points;

[0087] S3. Generate test drive data corresponding to the test paths and used for testing open or short circuits between chip pins according to the test paths;

[0088] S4. Obtain the level status data corresponding to the test drive data, and determine the connection relationship between chip pins in real time according to the level status data; wherein, the connection relationship is an open connection or a short connection between chip pins.

[0089] The step of creating at least one matrix corresponding to the connection relationship between the network points between chip pins further includes:

[0090] S11. Create at least one stack, at least one first array, and at least one second array respectively; wherein, the first array is used to store index records; the second array is used to store paths;

[0091] S12. Clear and process the stack and the first array, and create at least one third numerical variable; wherein, the third numerical variable is used to save row index data;

[0092] S13. Obtain the row data in the third numerical variable, push the row data onto the stack, and place the row data in the first array at the same time.

[0093] The step of obtaining the row data in the third numerical variable, pushing the row data onto the stack, and placing the row data in the first array at the same time further includes:

[0094] S131. Determine whether a connection relationship exists based on the row data. If a connection relationship exists and the row data does not exist in the first array, increment the row data. Otherwise, traverse and record all elements in the current stack, save the elements in the second array, and remove the top element of the stack.

[0095] The traversing the connection relationships between all network points in the matrix and generating test paths corresponding to the network points also includes:

[0096] S21. Eliminate duplicate test paths corresponding to the connection relationships between the network points, and create at least one fourth array; wherein the fourth array is used to store arrays after duplicate paths are eliminated;

[0097] S22, traversing the second array and generating a first test path corresponding to the second array; wherein the first test path is the test path before sorting;

[0098] S23. Arrange the first test path in ascending order based on the network point subscripts, and generate a second test path corresponding to the first test path; wherein the second test path is the sorted test path;

[0099] S24 , obtaining the path data in the fourth array, and determining whether the path data in the fourth array contains the second test path; if not, placing the second test path in the fourth array; otherwise, continuing to traverse the next path.

[0100] The traversing the connection relationships between all network points in the matrix and generating test paths corresponding to the network points also includes:

[0101] S25, integrating and merging the test paths, and generating a corresponding test path with a unique ID;

[0102] S26. Create at least one fifth array, and place the test path with the unique ID into the fifth array; wherein the fifth array is a key-value pair array.

[0103] The step of generating test drive data corresponding to the test path and used to test open circuits or short circuits between chip pins according to the test path further includes:

[0104] S31, obtaining row data in the fifth array and creating at least one sixth array; wherein the sixth array is used to store test drive data;

[0105] S32. Assign and process the sixth array, traverse the fifth array, and simultaneously binary-process the key data in the fifth array.

[0106] The step of obtaining the level status data corresponding to the test drive data and determining the connection relationship between chip pins in real time according to the level status data further includes:

[0107] S41. Traverse the column data in the sixth array and the corresponding test path set in sequence;

[0108] S42. Generate chip pin data corresponding to the network points according to the network point information corresponding to the test path set;

[0109] S43. Sequentially send test drive data according to the chip pin data in combination with the level signals sent by the pins.

[0110] Specifically, in the embodiment of the present invention, as Figure 2 shown, these are two examples of chip interconnection. Pin 10 of ChipA and Pin 2 of ChipB are connected through resistors R1 and R2; Pin 8 of ChipA and Pin 4 of ChipB are connected through resistor R3. At the same time, Pin 3 and Pin 4 of ChipB are connected through R4, and Pin 7 of ChipA and Pin 5 of ChipB are connected through resistor R5; Pin 5 of ChipA is connected to GND (ground); the remaining pins are floating. In addition, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T are all network points.

[0111] The specific steps are as follows: S01. As Figure 3 shown, abstract all connection relationships into a matrix a. In practical applications, this matrix may be very large. Here, only a part is extracted as an example. J, K, L, I, H, N, M, G, T represent network points, "1" represents a connection relationship, and "0" represents no connection relationship. For the convenience of expression, this matrix is deformed into matrix b here. The row subscript is referenced by j, and the column subscript is referenced by i.

[0112] S02. Apply for a stack Stack, apply for an array Seen (index record array) (the first array) to store index records, apply for an array TestPaths (test path array) (the second array) to store paths, and initialize.

[0113] S03. Retrieve the data of the j-th row, clear the stack Stack, and clear the array Seen (index record array). At the same time, apply for a temporary RowIndex (row index) (the third numeric variable) to save the row index, and assign the value of j to RowIndex; RowIndex is a numeric variable in the code, used to temporarily save the row index value.

[0114] S04. Retrieve the i-th data of the RowIndex-th row, and denote this value as n[i]. As Figure 4 shown, push n[i] onto the stack Stack, and at the same time add n[i] to the Seen (index record array) array. If n[i]=1, that is, there is a connection relationship, and n[i] does not exist in the Seen (index record array) array, assign i to RowIndex, increment i by 1, and repeat this step. Otherwise, traverse and record all elements in the current stack Stack, save these elements to the path array TestPaths (test path array), and then remove the top element of the stack. When the elements in the Stack stack are empty, increment j by 1, and go back to S03 to perform path search for the next row. When all rows are traversed, continue to the next step.

[0115] S05. From S03, it can be seen that the data of one row is actually a set of all directly connected network points. Since the search is performed for each network point one by one, after executing S04, there are duplicate paths in the test paths. For example, n0→n1→n2 and n2→n1→n0, these two paths are actually the same, just with different directions. It is necessary to remove the duplicate paths. Apply for a new test path array TestPathsRemoval (path array after removing duplicate paths) (the fourth array) to store the array after removing duplicate paths.

[0116] S06. Traverse the TestPaths (test path array) array, sort the traversed paths in ascending order according to the network point subscripts, so as to obtain a new path. Check whether this path exists in the TestPathsRemoval (path array after removing duplicate paths) array. If it does not exist, add this path to the TestPathsRemoval (path array after removing duplicate paths) array. If it exists, ignore this path. Continue to traverse the next one until all paths are traversed.

[0117] S07. So far, all valid and unique paths have been obtained, but they still need to be further integrated here, because these paths exist independently and cannot reflect the true interconnection situation. For example Figure 2As shown, there are interconnections among Pin 8 of Chip A, Pin 3 of Chip B, and Pin 4 of Chip B. Through the aforementioned steps, three paths can be obtained: H→N, H→N→M, and M→N. However, in the TestPathsRemoval array (the array of paths after removing duplicate paths), they exist as three independent elements. From a hardware connection perspective, they are equivalent. Therefore, such paths need to be merged. The merged set has a unique ID, and this ID is called PathBlockID (Path Unique ID). For example, when the above three paths are merged to form a set, the PathBlockID of this set is equal to 1. The specific path merging method is as follows:

[0118] A. Apply for an array of key-value pairs PathBlocks (the array of test path sets) (the fifth array). The key in the array element stores the PathBlockID (Path Unique ID), and the value in the array element stores the merged path set.

[0119] B. Traverse the TestPathsRemoval array (the array of paths after removing duplicate paths), create a new key-value pair, with the key being the PathBlockID (Path Unique ID). Obtain all the network points in the current path, traverse these network points, search for the paths containing this network point in the TestPathsRemoval array (the array of paths after removing duplicate paths), add this path to the key-value pair, and at the same time delete this path from the TestPathsRemoval array (the array of paths after removing duplicate paths). After one traversal of the TestPathsRemoval array (the array of paths after removing duplicate paths), add this key-value pair to the PathBlocks (the array of test path sets) and increment the PathBlockID (Path Unique ID) by 1. Repeat this process until all the paths in the TestPathsRemoval array (the array of paths after removing duplicate paths) have been traversed.

[0120] S08. After obtaining the PathBlocks (the array of test path sets), the open / short circuit test drive data can be generated. The specific steps are as follows. First, obtain the number P of elements in the PathBlocks (the array of test path sets) array, which is the number of tests Apply for a two-dimensional boolean array DriverDatas (drive data) (the sixth array) to store the test drive data. The number of rows is P, and the number of columns is Q.

[0121] S09. Assign values to the two-dimensional array. Traverse the PathBlocks (test path set array), convert the key PathBlockID (unique path ID) in the current key-value pair to binary representation. For example, when PathBlockID (unique path ID) = 2, its binary representation is 10. It should be noted that the number of bits of the binary is equal to Q. Taking the above as an example, the number of elements in PathBlocks (test path set array) is 4. Through it can be known that Q = 2 + 1, that is, Q = 3, indicating that the number of tests is 3 times. Therefore, when PathBlockID (unique path ID) = 2, the corresponding binary should be represented as 010. It should be noted additionally that a copy of the data in the last column needs to be added to the last column of DriverDatas (driver data). So the final result is 0100. The reason for adding this column is described in item 2 of S010.

[0122] S010. As Figure 5 shown, it is the DriverDatas (driver data) in S09. The value of the boolean element in the DriverDatas (driver data) two-dimensional array determines the level state of the corresponding network point. The specific conversion process is to traverse the columns of DriverDatas (driver data) from left to right. The meaning of the column has been mentioned before. The number of columns represents the number of tests. The data in the first column represents the driver data of all network points in the first test. The data in the first column is 1001. The path set with PathBlockID (unique path ID) of 1 needs to drive a high level, the path set with PathBlockID (unique path ID) of 2 needs to drive a low level, the path set with PathBlockID (unique path ID) of 3 needs to drive a low level, and the path set with PathBlockID (unique path ID) of 4 needs to drive a high level. Now we know the level state of each path set during each test, but the following two points need to be noted:

[0123] 1. There are often more than one network point in a path set, but there can be and only one real output! For the convenience of description, in this example, it is stipulated that the first network point in a path set is the output, and the rest are inputs.

[0124] 2. Due to the characteristics of the internal boundary scan register of the chip, the value input this time needs to be obtained next time. In other words, the expected value of the current time is actually the output value of the previous time. As Figure 5 shown, taking the first network point as an example, there are 4 driver data. The output value of the first time is 0, and the expected value is uncertain, denoted as X. The output value of the second time is 0, and the expected value is 0. The output value of the third time is 1, and the expected value is 0. The output value of the fourth time is 1, and the expected value is 1.

[0125] S011. Now it is understood how the DriverDatas (driver data) boolean array is converted into the driving of network points and the expected data. Next, these driver data need to be loaded into the in-chip boundary scan register and output.

[0126] First, traverse the columns of DriverDatas (driver data), and then traverse the set of paths in this column. For example, the first value is 0, the second value is 0, the third value is 0, and the fourth value is 1. According to the network point information in the corresponding path set, it can be known that these network points correspond to chip pins, such as Figure 2 As shown, the chip pin corresponding to network point J is Pin 10 of ChipA (chip A). According to the first principle in S010, Pin 10 of ChipA (chip A) is an output pin, and Pin 2 of ChipB (chip B) is an input pin. From the driver data, Pin 10 of ChipA (chip A) outputs 0, and Pin 2 of ChipB (chip B) should receive an X (don't care). Pin 9 of ChipA (chip A) outputs 0, and Pin 9 of ChipA (chip A) itself should receive an X (don't care). Pin 8 of ChipA (chip A) outputs 0, and Pins 3 and 4 of ChipB (chip B) should receive an X (don't care). Pin 7 of ChipA (chip A) outputs 1, and Pin 5 of ChipB (chip B) should receive an X (don't care). This is the result of traversing the first column. The result of traversing the second column is that Pin 10 of ChipA (chip A) outputs 0, and Pin 2 of ChipB (chip B) should receive a 0. Pin 9 of ChipA (chip A) outputs 1, and Pin 9 of ChipA (chip A) itself should receive a 0. Pin 8 of ChipA (chip A) outputs 1, and Pins 3 and 4 of ChipB (chip B) should receive a 0. Pin 7 of ChipA (chip A) outputs 0, and Pin 5 of ChipB (chip B) should receive a 1, and so on.

[0127] S012. It can be known from the BSDL file of the chip that all the above pins correspond to a set of boundary scan registers, and these registers are called cells (boundary scan registers), such as Figure 6As shown, both ChipA and ChipB have 10 pins, but there are 16 cells (boundary scan registers). According to the actual situation of the chip, these cells (boundary scan registers) all have their own functions. Here, the relationship between these cells (boundary scan registers) and pins will not be introduced separately. In this example, it can be considered that the cell (boundary scan register) directly behind the pin can change the high or low state of the pin. The aforementioned two-dimensional array of DriverDatas needs to load the corresponding data into the cell (boundary scan register) by traversing its column data. For example Figure 7 As shown, it represents the test data for the first time. Pin 10 of ChipA is 0, Pin 9 of ChipA is 0, Pin 8 of ChipA is 0, Pin 7 of ChipA is 1, and the corresponding expected data is X. It should be noted that the values of the cells (boundary scan registers) corresponding to those input pins do not need to be concerned about, and either 0 or 1 can be loaded because these cells (boundary scan registers) will collect the level signals sent from the pins on ChipA, and then these level signals are locked in the corresponding cells (boundary scan registers). The values of these cells (boundary scan registers) can be obtained during the next operation.

[0128] S013. These drive data are sent one by one through the host computer software, and finally the open - short circuit conditions between the chip pins can be detected. The specific determination rule is that during each test execution, the value of the obtained corresponding cell (boundary scan register) is compared with the expected value. If they are the same, it is PASS (test passed); if they are different, it is FAIL (test failed).

[0129] Generally speaking, when the algorithm of this solution processes and analyzes network paths, it is necessary to first establish a large matrix that contains detailed information about network points and the interconnection relationships between these network points. By continuously traversing these network points, all test paths are searched out, and then duplicate paths are removed. Next, set operations are performed on the items that contain the same network points in the paths. Then, based on the number of these sets, the test and expected data for each time of these network points are created. Finally, these data are driven to the pins of the chip one by one, and at the same time, the level states on the pins under those input modes are obtained. The obtained level states are compared with the expected values. If they are the same, it is PASS (the test passes); if they are different, it is FAIL (the test fails). That is, the problem of path finding for open / short circuit tests of PCBA (printed circuit board assembly) is solved through the algorithm, and the analysis efficiency can be greatly improved using this method or idea. At the same time, the present invention involves the algorithm problem of open / short circuit test drive data, and the open / short circuit situation can be detected within a short time using this algorithm.

[0130] To achieve the above object, the present invention further provides an open or short circuit test system for chip pins, and the system is applied to the above test method, as Figure 8 shown, the system specifically includes:

[0131] A matrix creation unit, configured to create at least one matrix corresponding to the connection relationship between network points among chip pins;

[0132] A first generation unit, configured to traverse the connection relationships between all network points in the matrix and generate test paths corresponding to the network points;

[0133] A second generation unit, configured to generate test drive data corresponding to the test paths and used to test the open or short circuit between chip pins according to the test paths;

[0134] A first determination unit, configured to obtain level state data corresponding to the test drive data and determine the connection relationship between chip pins in real time according to the level state data; wherein, the connection relationship is an open connection or a short connection between chip pins.

[0135] The matrix creation unit further includes:

[0136] A first creation module, configured to respectively create at least one stack, at least one first array, and at least one second array; wherein the first array is used to store index records; the second array is used to store paths;

[0137] A second creation module, configured to clear and process the stack and the first array, and create at least one third numerical variable; wherein the third numerical variable is used to save row index data;

[0138] The first processing module is used to obtain the row data in the third numerical variable, perform stack processing on the row data, and at the same time place the row data in the first array;

[0139] And / or, the first processing module further includes:

[0140] The first determination module is used to determine whether there is a connection relationship according to the row data;

[0141] And / or, the first generation unit further includes:

[0142] The third creation module is used to eliminate the corresponding and duplicate test paths according to the connection relationship between the network points, and at the same time create at least one fourth array; wherein, the fourth array is used to store the array after eliminating the duplicate paths;

[0143] The first generation module is used to traverse the second array and generate a first test path corresponding to the second array; wherein, the first test path is the test path before sorting;

[0144] The second generation module is used to perform ascending order arrangement processing according to the first test path in combination with the network point subscripts, and generate a second test path corresponding to the first test path; wherein, the second test path is the test path after sorting;

[0145] The second determination module is used to obtain the path data in the fourth array and determine whether the path data in the fourth array has the second test path;

[0146] And / or, the first generation unit further includes:

[0147] The third generation module is used to integrate and merge the test paths and generate a test path with a unique ID corresponding thereto;

[0148] The fourth creation module is used to create at least one fifth array and place the test path with the unique ID in the fifth array; wherein, the fifth array is a key-value pair array;

[0149] And / or, the second generation unit further includes:

[0150] The fifth creation module is used to obtain the row data in the fifth array and create at least one sixth array; wherein, the sixth array is used to store test drive data;

[0151] The second processing module is used to assign values to the sixth array, traverse the fifth array, and at the same time binaryize the key data in the fifth array;

[0152] And / or, the first determination unit further includes:

[0153] A first traversal module, configured to sequentially traverse the column data in the sixth array and the set of test paths corresponding to the column data;

[0154] A fourth generation module, configured to generate chip pin data corresponding to the network points according to the network point information corresponding to the set of test paths;

[0155] A first sending module, configured to sequentially send test drive data according to the chip pin data in combination with the level signals sent by the pins.

[0156] In the embodiment of the system solution of the present invention, the method steps involved in the open or short circuit test between chip pins have been described in detail above. That is to say, the functional modules in the system are used to implement the steps or sub-steps in the above method embodiment, which will not be elaborated here.

[0157] To achieve the above object, the present invention also provides a test platform for open or short circuit test between chip pins, as Figure 9 shown, including a processor, a memory, and a control program for the open or short circuit test platform between chip pins; wherein, when the processor executes the control program for the open or short circuit test platform between chip pins, the control program for the open or short circuit test platform between chip pins is stored in the memory, and the control program for the open or short circuit test platform between chip pins implements the method steps for the open or short circuit test between chip pins. For example:

[0158] S1. Create at least one matrix corresponding to the connection relationship between the network points between chip pins;

[0159] S2. Traverse the connection relationships between all network points in the matrix and generate test paths corresponding to the network points;

[0160] S3. Generate test drive data corresponding to the test paths and used for testing open or short circuits between chip pins according to the test paths;

[0161] S4. Obtain the level status data corresponding to the test drive data and determine the connection relationship between chip pins in real time according to the level status data; wherein, the connection relationship is an open connection or a short connection between chip pins.

[0162] The specific details of the steps have been described in detail above and will not be elaborated here.

[0163] In an embodiment of the present invention, the built-in processor of the open or short circuit test platform between chip pins may be composed of integrated circuits. For example, it may be composed of a single packaged integrated circuit, or may be composed of multiple integrated circuits with the same or different functions packaged. It includes one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor connects to each component through various interfaces and lines, and executes various functions for testing open or short circuits between chip pins and processes data by running or executing programs or units stored in the memory, and by calling data stored in the memory;

[0164] The memory is used to store program codes and various data, is installed in the open or short circuit test platform between chip pins, and realizes high-speed and automatic access to programs or data during operation.

[0165] The memory includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc memories, magnetic disk memories, tape memories, or any other computer-readable medium capable of carrying or storing data.

[0166] The present invention creates at least one matrix corresponding to the connection relationship between network points between chip pins; traverses the connection relationships between all network points in the matrix, and generates test paths corresponding to the network points; generates test drive data corresponding to the test paths and used for testing open or short circuits between chip pins according to the test paths; obtains level status data corresponding to the test drive data, and determines the connection relationship between chip pins in real time according to the level status data; and a system and platform corresponding to the method can improve the test path analysis efficiency and the open / short circuit test efficiency.

[0167] That is to say, the open - short circuit test path search problem is solved by the solution of the present invention. Compared with the traditional processing method, the analysis time is greatly reduced, the software experience is enhanced, and the productivity is improved to a certain extent. In addition, the algorithm process involved in the present invention does not depend on the programming language and operating system, and this process can be easily transplanted into any development environment required in practice. The algorithm for generating and processing the open - short circuit test drive data greatly reduces the number of tests. In the actual production process, it is directly reflected that the test time is significantly shortened and the production efficiency is improved.

[0168] The above - described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. A method for open or short circuit testing between chip pins, characterized in that, The method includes the steps of: creating at least one matrix corresponding to the connection relationship between the network points among the chip pins; traversing the connection relationships between all network points in the matrix and generating test paths corresponding to the network points; wherein, it further includes: integrating and merging the test paths and generating corresponding test paths with unique IDs; creating at least one fifth array and placing the test paths with unique IDs in the fifth array; the fifth array is a key-value pair array; generating test drive data corresponding to the test paths and used for testing open or short circuits between the chip pins according to the test paths; wherein, it further includes: obtaining the row data in the fifth array and creating at least one sixth array; the sixth array is used for storing the test drive data; performing assignment processing on the sixth array, traversing the fifth array, and performing binary processing on the key data in the fifth array; obtaining the level status data corresponding to the test drive data and determining the connection relationship between the chip pins in real time according to the level status data; wherein, the connection relationship is an open connection or a short connection between the chip pins.

2. The open - circuit or short - circuit test method for between chip pins according to claim 1, characterized in that, The obtaining the level status data corresponding to the test drive data and determining the connection relationship between the chip pins in real time according to the level status data further includes: sequentially traversing the column data in the sixth array and the set of test paths corresponding to the column data; generating chip pin data corresponding to the network points according to the network point information corresponding to the set of test paths; sequentially sending the test drive data according to the chip pin data in combination with the level signals sent by the pins.

3. An open - circuit or short - circuit test system for chip pins, characterized in that, The system is applied to the test method described in any one of claims 1-2. The system includes: a matrix creation unit for creating at least one matrix corresponding to the connection relationship between the network points among the chip pins; a first generation unit for traversing the connection relationships between all network points in the matrix and generating test paths corresponding to the network points; a second generation unit for generating test drive data corresponding to the test paths and used for testing open or short circuits between the chip pins according to the test paths; a first determination unit for obtaining the level status data corresponding to the test drive data and determining the connection relationship between the chip pins in real time according to the level status data; wherein, the connection relationship is an open connection or a short connection between the chip pins.

4. The open - circuit or short - circuit test system for chip pins according to claim 3, characterized in that, The first determination unit further includes: a first traversal module for sequentially traversing the column data in the sixth array and the set of test paths corresponding to the column data; a fourth generation module for generating chip pin data corresponding to the network points according to the network point information corresponding to the set of test paths; a first sending module for sequentially sending the test drive data according to the chip pin data in combination with the level signals sent by the pins.

5. An open - circuit or short - circuit test platform for chip pins, characterized in that, It includes a processor, a memory, and a control program for an open or short circuit test platform between chip pins; wherein, when the processor executes the control program for the open or short circuit test platform between chip pins, the control program for the open or short circuit test platform between chip pins is stored in the memory, and the control program for the open or short circuit test platform between chip pins implements the open or short circuit test method between chip pins as described in any one of claims 1 to 2.

Images