Simulation method, apparatus, device, and storage medium

Abstract

The present disclosure provides simulation methods, devices, equipment and storage media, relates to the technical field of computers, in particular to the technical field of quantum computers, quantum chips and quantum simulation. The specific implementation scheme is as follows: a target correlation relationship corresponding to a first cavity in a packaging box used for packaging a quantum chip is determined; the target correlation relationship is used to represent a mapping relationship between a first candidate cavity characteristic parameter of the first cavity and a first simulation frequency corresponding to the first cavity; the first candidate cavity characteristic parameter can affect the frequency corresponding to the first cavity; a target simulation frequency corresponding to the first cavity is obtained based on the target correlation relationship; in the case that the target simulation frequency meets a first frequency requirement, a first target cavity characteristic parameter of the first cavity is obtained based on the target correlation relationship; the first frequency requirement is obtained based on the frequency of a quantum bit in the quantum chip.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of quantum computers, quantum chips, and quantum simulation technology. Background Technology

[0002] In practice, superconducting quantum chips are highly susceptible to environmental noise interference, which can severely degrade their performance. Therefore, superconducting quantum chips are typically placed in a package (also called a casing) to shield them from environmental noise. However, this casing also creates a resonant cavity within the chip medium and internal space, which possesses a series of inherent resonant frequencies, the lowest of which is called the fundamental frequency. As the number of superconducting qubits integrated onto a superconducting quantum chip increases, the chip's size naturally grows larger; correspondingly, the cavity size within the casing also increases. This significantly reduces the cavity's inherent resonant frequency. If the cavity's resonant frequency approaches the frequency of the components within the superconducting quantum chip, a non-negligible dissipation path is introduced, severely degrading the chip's performance. Therefore, designing a package with a resonant cavity whose fundamental frequency meets the requirements becomes a crucial research topic. Summary of the Invention

[0003] This disclosure provides a simulation method, apparatus, device, and storage medium.

[0004] According to one aspect of this disclosure, a simulation method is provided, comprising:

[0005] A target correlation is determined for the first cavity in the packaging box used to encapsulate the quantum chip; the target correlation is used to characterize the mapping relationship between the first candidate cavity feature parameters of the first cavity and the first simulation frequency corresponding to the first cavity; the first candidate cavity feature parameters can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of the first resonant cavity; the first resonant cavity is composed of the first layer structure in the quantum chip and the internal cavity of the first cavity;

[0006] Based on the target correlation, the target simulation frequency corresponding to the first cavity is obtained;

[0007] If the target simulation frequency meets the first frequency requirement, the first target cavity characteristic parameters of the first cavity are obtained based on the target correlation; the first frequency requirement is obtained based on the frequency of the qubits in the quantum chip.

[0008] According to another aspect of this disclosure, a simulation apparatus is provided, comprising:

[0009] A processing unit is configured to determine a target correlation relationship corresponding to a first cavity in a packaging box used for packaging a quantum chip; the target correlation relationship characterizes the mapping relationship between a first candidate cavity feature parameter of the first cavity and a first simulated frequency corresponding to the first cavity; the first candidate cavity feature parameter can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of a first resonant cavity; the first resonant cavity is composed of a first layer structure in the quantum chip and an internal cavity of the first cavity; the target simulated frequency corresponding to the first cavity is obtained based on the target correlation relationship; if the target simulated frequency meets a first frequency requirement, the first target cavity feature parameter of the first cavity is obtained based on the target correlation relationship; the first frequency requirement is obtained based on the frequency of the qubits in the quantum chip;

[0010] The output unit is used to output the first target cavity characteristic parameters of the first cavity.

[0011] According to another aspect of this disclosure, a computing device is provided, comprising:

[0012] At least one quantum processing unit (QPU);

[0013] A memory, coupled to the at least one QPU and used to store executable instructions,

[0014] The instruction is executed by the at least one QPU to enable the at least one QPU to perform the method described above;

[0015] Or, including:

[0016] At least one processor; and

[0017] A memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described above.

[0019] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above.

[0020] Alternatively, the computer instructions may be used to cause the computer to perform the methods described above.

[0021] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by at least one quantum processing unit, implements the methods described above.

[0022] Alternatively, the computer program may implement the above-described method when executed by a processor.

[0023] In this way, the present invention can obtain the first target cavity characteristic parameters of the first cavity from the target correlation when the target simulation frequency corresponding to the first cavity meets the first frequency requirement (which is based on the frequency of the qubits in the quantum chip). Thus, the first target cavity characteristic parameters of the first cavity are designed automatically, intelligently and efficiently, thereby effectively avoiding the coupling between the components (such as qubits) in the quantum chip and the first cavity, and improving the performance of the quantum chip. Moreover, the present invention is simple to operate and easy to implement, has a low threshold for use, and is also practical.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0025] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0026] Figure 1 This is a schematic diagram of the implementation flow of the simulation method according to the embodiments of this disclosure. Figure 1 ;

[0027] Figures 2(a) and 2(b) are schematic diagrams of the first cavity according to an embodiment of the present disclosure;

[0028] Figure 3 This is a schematic diagram of the implementation process of the simulation method according to the embodiments of this disclosure;

[0029] Figure 4(a) is a front view of the first cavity according to an embodiment of the present disclosure;

[0030] Figure 4(b) is a side view of the first cavity according to an embodiment of the present disclosure;

[0031] Figure 4(c) is a top view of the first cavity according to an embodiment of the present disclosure;

[0032] Figure 5 This is a schematic diagram of the implementation flow of the simulation method according to the embodiments of this disclosure. Figure 3 ;

[0033] Figure 6 This is a schematic diagram of the implementation process of the simulation method according to the embodiments of this disclosure;

[0034] Figure 7(a) is a front view of the second cavity according to an embodiment of the present disclosure;

[0035] Figure 7(b) is a side view of the second cavity according to an embodiment of the present disclosure;

[0036] Figure 7(c) is a top view of the second cavity according to an embodiment of the present disclosure;

[0037] Figure 8(a) is a front view of the package according to an embodiment of the present disclosure;

[0038] Figure 8(b) is a side view of the package according to an embodiment of the present disclosure;

[0039] Figure 9(a) is a perspective view of an example of a package according to an embodiment of the present disclosure;

[0040] Figure 9(b) is a side view of an example of a package according to an embodiment of the present disclosure;

[0041] Figure 10 This is a schematic flowchart of a simulation method according to an embodiment of the present disclosure in one example;

[0042] Figures 11(a) and 11(b) are schematic diagrams illustrating the effect of the simulation method according to an embodiment of the present disclosure in one example;

[0043] Figure 12 This is a schematic diagram of the simulation device according to an embodiment of the present disclosure;

[0044] Figure 13 This is a block diagram of a computing device used to implement the simulation method of the embodiments of this disclosure. Detailed Implementation

[0045] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0046] As a landmark technology of the post-Moore's Law era, quantum computing has become an important development direction for both academia and industry. Compared with traditional computing, quantum computing has unparalleled advantages in solving certain specific problems (such as large number factorization and simulation of complex quantum systems). The development of various high-potential quantum applications has greatly promoted the development of quantum hardware, giving rise to a variety of technical implementation schemes. Among them, superconducting quantum circuits based on Josephson junctions have core advantages such as ease of fabrication, manipulation and readout, and easy scalability, and have become one of the most promising directions among many hardware implementation technology routes. As a physical realization of superconducting quantum systems, the development of superconducting quantum chips integrating multiple superconducting qubits is becoming increasingly important.

[0047] In practice, superconducting quantum chips are highly susceptible to environmental noise interference, which can severely degrade their performance. Therefore, superconducting quantum chips are typically placed in a package (also called a casing) to shield them from environmental noise. However, this casing also creates a resonant cavity within the chip medium and internal space, which possesses a series of inherent resonant frequencies, the lowest of which is called the fundamental frequency. As the number of superconducting qubits integrated onto a superconducting quantum chip increases, the chip's size naturally grows larger; correspondingly, the cavity size within the casing also increases. This significantly reduces the cavity's inherent resonant frequency. If the cavity's resonant frequency approaches the frequency of the components within the superconducting quantum chip, a non-negligible dissipation path is introduced, severely degrading the chip's performance. Therefore, designing a package with a resonant cavity whose fundamental frequency meets the requirements becomes a crucial research topic.

[0048] Based on this, the disclosed solution provides a simulation method that can automatically and efficiently design the key parameters of the packaging box. Specifically, Figure 1 This is a schematic diagram of the implementation flow of the simulation method according to the embodiments of this disclosure. Figure 1 This method can be optionally applied to quantum computing devices that also have classical computing capabilities, or it can be applied to classical computing devices that also have quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any restrictions on this method.

[0049] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 1 As shown, the quantities include:

[0050] Step S101: Determine the target correlation relationship corresponding to the first cavity in the packaging box used to package the quantum chip.

[0051] Here, the target association relationship is used to characterize the mapping relationship between the first candidate cavity feature parameters of the first cavity and the first simulation frequency corresponding to the first cavity.

[0052] Furthermore, the first candidate cavity characteristic parameters can affect the frequency corresponding to the first cavity. The frequency corresponding to the first cavity can affect the chip characteristics of the quantum chip. For example, if the frequency corresponding to the first cavity is close to the frequency of the qubits in the quantum chip, it will affect the chip characteristics of the quantum chip.

[0053] Here, the frequency corresponding to the first cavity is the frequency of the first resonant cavity; the first resonant cavity is composed of the first layer structure in the quantum chip and the internal cavity of the first cavity.

[0054] In a specific example, the frequency corresponding to the first cavity may be the lowest frequency among a series of inherent resonant frequencies of the first resonant cavity, which may also be referred to as the fundamental frequency.

[0055] It should be noted that in this disclosed solution, the fundamental frequency corresponding to the first cavity can be obtained by simulating the first cavity. In this case, the simulation result obtained is the first simulation frequency mentioned above.

[0056] Step S102: Obtain the target simulation frequency corresponding to the first cavity based on the target correlation relationship.

[0057] Step S103: If the target simulation frequency meets the first frequency requirement, the first target cavity characteristic parameters of the first cavity are obtained based on the target correlation relationship.

[0058] Here, the first frequency requirement is derived based on the frequency of the qubits in the quantum chip.

[0059] Here, the first target cavity feature parameters of the first cavity can be used to manufacture the packaging box. Furthermore, the first target cavity feature parameters of the first cavity can be used to manufacture the first cavity in the packaging box. In this way, the packaging box can be manufactured in a targeted manner according to the needs, avoiding blind design of the packaging box due to lack of focus, thereby improving the performance of the quantum chip.

[0060] In this way, the present invention can obtain the first target cavity characteristic parameters of the first cavity from the target correlation when the target simulation frequency corresponding to the first cavity meets the first frequency requirement (which is based on the frequency of the qubits in the quantum chip). Thus, the first target cavity characteristic parameters of the first cavity are designed automatically, intelligently and efficiently, thereby effectively avoiding the coupling between the components (such as qubits) in the quantum chip and the first cavity, and improving the performance of the quantum chip. Moreover, the present invention is simple to operate and easy to implement, has a low threshold for use, and is also practical.

[0061] In a specific example, if it is determined that the target simulation frequency does not meet the first frequency requirement, the candidate cavity characteristic parameters of the first cavity can be adjusted, and the target correlation can be redefined.

[0062] In a specific example, the quantum chip may be a superconducting quantum chip; here, the superconducting quantum chip refers to a quantum chip made of superconducting materials. For example, all components in the superconducting quantum chip (such as qubits, coupling devices, etc.) are made of superconducting materials. This allows the disclosed solution to be applied to superconducting quantum chips, enriching the application scenarios of the disclosed solution.

[0063] Furthermore, in a specific example, the first candidate cavity feature parameters include the support structure parameters of the support portion in the first cavity, and the first geometric feature parameters of the first resonant cavity.

[0064] Here, the support portion is used to support the quantum chip. For example, it supports the first layer structure of the quantum chip. For instance, the support portion is located on both sides of the first cavity, serving as two wings of the cavity, and extends outward from the first cavity so that if the surface of the supported quantum chip extends beyond the opening of the first cavity, the support portion can support the excess portion.

[0065] In one example, as shown in Figure 2(a), the first cavity includes a first base, a cavity located inside the first base, and support portions on both sides of the cavity located inside the first base. In a specific example, the support structure parameters of the support portions may include the width of the support portions. Here, it can be understood that the support structure parameters may specifically include the width of the support portion on one side (e.g., it can be denoted as gap), or include the sum of the widths of the support portions on both sides (e.g., if the widths of the support portions on both sides are the same, then it includes 2gap).

[0066] Furthermore, as shown in Figure 2(b), the support portion is used to support the first layer structure of the quantum chip. At this time, the first layer structure of the quantum chip and the cavity of the first cavity can form a resonant cavity, that is, the first resonant cavity mentioned above.

[0067] Furthermore, the target association relationship includes multiple sub-mapping relationships. The sub-mapping relationships are used to characterize the mapping relationship between the first geometric feature parameter of the first resonant cavity and the first simulation frequency under the current support structure parameters. For example, it can be expressed as "support structure parameter: [first geometric feature parameter, first simulation frequency]". The support structure parameters corresponding to different sub-mapping relationships are different.

[0068] For example, when the support structure parameter is support structure parameter-1, simulations are performed on first cavities with different first cavity feature parameters to obtain sub-mapping relationship-1, which can be denoted as "support structure parameter-1: [first geometric feature parameter-1, first simulation frequency-1]". When the support structure parameter is support structure parameter-2, simulations are performed on first cavities with different first cavity feature parameters to obtain sub-mapping relationship-2, which can be denoted as "support structure parameter-2: [first geometric feature parameter-2, first simulation frequency-2]". The values ​​of support structure parameter-1 and support structure parameter-2 are different.

[0069] In this way, the disclosed solution can quickly determine the first target cavity feature parameters of the first cavity based on the target correlation, thus simplifying the parameter design process, reducing complexity, and laying the foundation for the rapid design of the packaging box in the future.

[0070] Figure 3 This is a schematic diagram of the implementation process of the simulation method according to an embodiment of this disclosure. This method can be optionally applied to quantum computing devices with classical computing capabilities, or to classical computing devices with quantum computing capabilities, or directly to classical computing devices, such as personal computers, servers, server clusters, and other electronic devices with classical computing capabilities, or directly to quantum computers. This disclosure does not impose any limitations on this approach. Figure 1 The methods shown can also be applied to this example, and the related content will not be elaborated further in this example.

[0071] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 3 As shown, it includes:

[0072] Step S301: Determine the target correlation relationship corresponding to the first cavity in the packaging box used to package the quantum chip.

[0073] Here, the target correlation is used to characterize the mapping relationship between the first candidate cavity feature parameters of the first cavity and the first simulation frequency corresponding to the first cavity; the first candidate cavity feature parameters can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of the first resonant cavity; the first resonant cavity is composed of the first layer structure in the quantum chip and the internal cavity of the first cavity.

[0074] Here, the description of the correlation between the first candidate cavity feature parameters and the target can be found in the above explanation, and will not be repeated here.

[0075] Step S302: Obtain the target simulation frequency corresponding to the first cavity based on the target correlation relationship.

[0076] In a specific example, the target simulation frequency can be obtained in the following way, thus laying the foundation for quickly determining whether the first target cavity feature parameter exists in the target correlation; specifically, the above-mentioned method of obtaining the target simulation frequency corresponding to the first cavity based on the target correlation (e.g., step S302) includes:

[0077] The maximum simulation frequency is selected from multiple first simulation frequencies corresponding to the target correlation, wherein the target simulation frequency is the maximum simulation frequency.

[0078] Alternatively, the minimum simulation frequency can be selected from multiple first simulation frequencies corresponding to the target correlation, where the target simulation frequency is the minimum simulation frequency. It should be noted that, in one example, the first simulation frequency can specifically be the fundamental frequency of the simulated first resonant cavity. In this case, the minimum fundamental frequency of the first resonant cavity can be determined from multiple first simulation frequencies (i.e., multiple fundamental frequencies) corresponding to the target correlation. This lays the foundation for efficiently designing the first target cavity characteristic parameters of the first cavity and effectively avoiding coupling between the components (such as qubits) in the quantum chip and the first cavity.

[0079] Step S303: Determine whether the target simulation frequency is greater than or equal to the target frequency; if yes, proceed to step S304; otherwise, that is, if the target simulation frequency is less than the target frequency, proceed to step S305.

[0080] Here, the target frequency is derived from the frequency of the qubits in the quantum chip, for example, equal to the frequency of the qubits, or a minimum security value (i.e., the minimum value that can avoid coupling), which is greater than the frequency of the qubits.

[0081] Step S304: If the target simulation frequency is determined to be greater than or equal to the target frequency, the first target cavity characteristic parameters of the first cavity are obtained based on the following screening rules.

[0082] Here, the filtering rules include at least one of the following:

[0083] Rule 1: The supporting structure parameter is greater than the first value, and the first depth of the first cavity contained in the first geometric feature parameter is greater than the second value.

[0084] Here, both the first value and the second value are empirical values ​​greater than or equal to 0, which can be set according to actual needs. The two values ​​can be the same, such as both being 0, or they can be different. This disclosure does not limit this.

[0085] Rule 2: The first simulation frequency corresponding to the first cavity is the preset frequency that the first cavity is designed to reach.

[0086] Here, the preset frequency is any value greater than or equal to the target frequency, and can be set according to actual needs. This disclosure does not limit this.

[0087] It should be noted that, in Rule 2, the first simulation frequency corresponding to the first cavity is a preset frequency that the first cavity is designed to achieve, which can specifically refer to:

[0088] The difference between the first simulated frequency corresponding to the first cavity and the preset frequency is within a preset error range. This preset error range is an empirical value and can be set according to actual needs. This disclosed solution does not limit this value.

[0089] Rule 3: The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

[0090] Here, the first surface feature parameter is a feature parameter that can affect the connectivity of the quantum chip and the quantum error correction code. The third value is greater than 0, or is an empirical value greater than or equal to 0 and less than or equal to 1, such as a value of 1, which can be set according to actual needs, and this disclosure does not limit it.

[0091] It should be noted that, in one example, as shown in Figure 4(a) (front view of the first cavity), Figure 4(b) (side view of the first cavity), and Figure 4(c) (top view of the first cavity), the first layer structure of the quantum chip supported by the support portion forms a first resonant cavity with the cavity of the first cavity. The support structure parameters include the width of one side (gap in the figure). Further, in one example, the first geometric feature parameter of the first resonant cavity may include a first depth (denoted as d) and a first surface feature parameter; wherein the first surface feature parameter includes the ratio (denoted as k) of the short side (i.e., "width", denoted as a) to the long side (i.e., "length", denoted as b) of the first layer structure in the quantum chip, i.e., k = a / b. Alternatively, the first surface feature parameter may directly include the short side a and the long side b of the first layer structure of the quantum chip; this disclosure does not limit this.

[0092] For example, in one instance, if the target simulation frequency is determined to be greater than or equal to the target frequency, then based on filtering rule 1, at least one first candidate cavity feature parameter is selected from the target association, where the supporting structure parameter is greater than a first value (e.g., 0) and the first depth contained in the first geometric feature parameter is greater than a second value (e.g., 0). Then, the first target cavity feature parameter of the first cavity is determined from the at least one first candidate cavity feature parameter. For example, one of the at least one first candidate cavity feature parameters is selected and directly used as the first target cavity feature parameter of the first cavity.

[0093] Alternatively, in another example, if the target simulation frequency is determined to be greater than or equal to the target frequency, based on filtering rule 2, at least one first candidate cavity feature parameter is selected from the target association relationship if the difference between the first simulation frequency and the preset frequency corresponding to the first cavity is within a preset error range. Then, the first target cavity feature parameter of the first cavity is determined from the at least one first candidate cavity feature parameter. For example, one of the at least one first candidate cavity feature parameters is selected and directly used as the first target cavity feature parameter of the first cavity.

[0094] Alternatively, in another example, if the target simulation frequency is determined to be greater than or equal to the target frequency, based on filtering rule 3, at least one first candidate cavity feature parameter is selected from the target association, and the difference between the first surface feature parameter and the third value (e.g., 1) contained in the first geometric feature parameter is less than a preset threshold (e.g., 0). Then, the first target cavity feature parameter of the first cavity is determined from the at least one first candidate cavity feature parameter obtained. For example, one of the at least one first candidate cavity feature parameters is selected and directly used as the first target cavity feature parameter of the first cavity.

[0095] Alternatively, in another example, if the target simulation frequency is determined to be greater than or equal to the target frequency, firstly, a first screening is performed, based on screening rule 1, to select at least one first candidate cavity feature parameter from the target association relationship where the supporting structure parameter is greater than a first value (e.g., 0) and the first depth in the first geometric feature parameter is greater than a second value (e.g., 0). Secondly, a second screening is performed, based on screening rule 2, to select at least one first candidate cavity feature parameter from the at least first candidate cavity feature parameters obtained in the first screening where the difference between the first simulation frequency corresponding to the first cavity and the preset frequency is within a preset error range. Finally, a third screening is performed, based on screening rule 3, to select at least one first candidate cavity feature parameter from the at least first candidate cavity feature parameters obtained in the second screening where the difference between the first surface feature parameter included in the first geometric feature parameter and the third value (e.g., 1) is less than a preset threshold (e.g., 0). Then, the first target cavity feature parameter of the first cavity is determined from the at least one first candidate cavity feature parameter obtained in the third screening. It can be understood that the screening order in this example is "rule 1 → rule 2 → rule 3". Furthermore, it should be noted that in practical applications, there may be other filtering orders, such as "Rule 2 → Rule 1 → Rule 3", etc. This public scheme does not limit this.

[0096] Step S305: Adjust the candidate cavity feature parameters of the first cavity and return to step S301 to redetermine the target association.

[0097] Thus, the present disclosure provides a specific example of determining the characteristic parameters of the first target cavity. For example, the cavity characteristic parameters of the first cavity can be continuously optimized by using screening rules to finally obtain the characteristic parameters of the first target cavity. In this way, the first target cavity characteristic parameters of the first cavity are designed automatically, intelligently and efficiently, thereby effectively avoiding the coupling between the components (such as qubits) in the quantum chip and the first cavity, and improving the performance of the quantum chip.

[0098] Figure 5 This is a schematic diagram of the implementation flow of the simulation method according to the embodiments of this disclosure. Figure 3 This method can be optionally applied to quantum computing devices that also possess classical computing capabilities, or it can be applied to classical computing devices that also possess quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters, and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any limitations on these applications. Figure 1 and Figure 3 The methods shown can also be applied to this example, and the related content will not be elaborated further in this example.

[0099] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 5 As shown, it includes:

[0100] Step S501: Determine the target correlation relationship corresponding to the first cavity in the packaging box used to package the quantum chip.

[0101] Here, the target correlation is used to characterize the mapping relationship between the first candidate cavity feature parameters of the first cavity and the first simulation frequency corresponding to the first cavity; the first candidate cavity feature parameters can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of the first resonant cavity; the first resonant cavity is composed of the first layer structure in the quantum chip and the internal cavity of the first cavity.

[0102] Here, the description of the correlation between the first candidate cavity feature parameters and the target can be found in the above explanation, and will not be repeated here.

[0103] Step S502: Obtain the target simulation frequency corresponding to the first cavity based on the target correlation relationship.

[0104] The method for determining the target simulation frequency can be referred to the above description, and will not be repeated here.

[0105] Step S503: Determine whether the target simulation frequency is greater than or equal to the target frequency; if yes, proceed to step S504; otherwise, that is, if the target simulation frequency is less than the target frequency, proceed to step S506.

[0106] Here, the target frequency is derived from the frequency of the qubits in the quantum chip, for example, equal to the frequency of the qubits, or a minimum security value (i.e., the minimum value that can avoid coupling), which is greater than the frequency of the qubits.

[0107] Step S504: Select at least one candidate simulation frequency from the multiple first simulation frequencies corresponding to the target correlation. Proceed to step S505.

[0108] Here, the difference between the candidate simulation frequency in the at least one candidate simulation frequency and the preset frequency that the first cavity is required to reach is less than or equal to the preset difference; the preset difference is an empirical value that can be set according to actual needs, and this disclosure does not limit it.

[0109] Step S505: Based on the following filtering rules, select the first target cavity feature parameters of the first cavity from at least one first candidate cavity feature parameters corresponding to the at least one candidate simulation frequency.

[0110] In one example, the first target cavity feature parameters of the first cavity can be selected from the first candidate cavity feature parameters corresponding to each of the at least one candidate simulation frequencies based on the following filtering rules.

[0111] Here, the filtering rules include at least one of the following:

[0112] Rule 1: The supporting structure parameter is greater than the first value, and the first depth contained in the first geometric feature parameter is greater than the second value.

[0113] Rule 3: The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

[0114] For details regarding Rule 1 and Rule 3, please refer to the description above; they will not be repeated here.

[0115] It is understood that the filtering rules used above can be either rule 1 or rule 3, or both rules can be used. This public scheme does not impose any restrictions on this.

[0116] Step S506: Adjust the candidate cavity feature parameters of the first cavity and return to step S501 to redetermine the target association.

[0117] Thus, the present disclosure provides a specific example of determining the characteristic parameters of the first target cavity, which can accurately select the first target cavity characteristic parameters of the first cavity from the target correlation based on the screening rules, and the obtained first cavity can approximate the pre-designed required frequency. In this way, the coupling between the components (such as qubits) in the quantum chip and the first cavity is effectively avoided, thereby improving the performance of the quantum chip.

[0118] Figure 6 This is a schematic diagram illustrating the implementation flow of the simulation method according to an embodiment of this disclosure. This method can be optionally applied to quantum computing devices with classical computing capabilities, or to classical computing devices with quantum computing capabilities, or directly to classical computing devices, such as personal computers, servers, server clusters, and other electronic devices with classical computing capabilities, or directly to quantum computers. This disclosure does not impose any limitations on this approach. Figure 1 , Figure 3 and Figure 5 The methods shown can also be applied to this example, and the related content will not be elaborated further in this example.

[0119] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 6 As shown, it includes:

[0120] Step S601: Determine the target correlation relationship corresponding to the first cavity in the packaging box used to package the quantum chip.

[0121] Here, the target correlation is used to characterize the mapping relationship between the first candidate cavity feature parameters of the first cavity and the first simulation frequency corresponding to the first cavity; the first candidate cavity feature parameters can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of the first resonant cavity; the first resonant cavity is composed of the first layer structure in the quantum chip and the internal cavity of the first cavity.

[0122] Here, the description of the correlation between the first candidate cavity feature parameters and the target can be found in the above explanation, and will not be repeated here.

[0123] Step S602: Obtain the target simulation frequency corresponding to the first cavity based on the target correlation relationship.

[0124] The method for determining the target simulation frequency can be referred to the above description, and will not be repeated here.

[0125] Step S603: Determine whether the target simulation frequency meets the first frequency requirement. If yes, proceed to step S604; otherwise, proceed to step S605.

[0126] Step S604: If the target simulation frequency meets the first frequency requirement, based on the target correlation, obtain the first target cavity characteristic parameters of the first cavity. Then proceed to step S606.

[0127] Here, the first frequency requirement is derived based on the frequency of the qubits in the quantum chip.

[0128] Step S605: Adjust the candidate cavity feature parameters of the first cavity and return to step S601 to redetermine the target association.

[0129] Step S606: Simulate to obtain the second simulated frequency corresponding to the second cavity in the package.

[0130] Here, the second simulation frequency is obtained by simulating a second cavity with second candidate cavity characteristic parameters; the second candidate cavity characteristic parameters can affect the frequency corresponding to the second cavity; the frequency corresponding to the second cavity can affect the chip characteristics of the quantum chip. For example, if the frequency corresponding to the second cavity is close to the frequency of the qubit in the quantum chip, it will affect the chip characteristics of the quantum chip.

[0131] Furthermore, the frequency corresponding to the second cavity is the frequency of the second resonant cavity; the second resonant cavity is composed of the second layer structure in the quantum chip and the internal cavity of the second cavity.

[0132] In a specific example, the frequency corresponding to the second cavity can be the lowest frequency among a series of inherent resonant frequencies of the second resonant cavity, which can also be called the fundamental frequency.

[0133] Furthermore, in a specific example, the second candidate cavity feature parameters are obtained based on the first target cavity feature parameters. For example, the second candidate cavity feature parameters are obtained based on the first geometric feature parameter in the first target cavity feature parameters. In this case, it can be understood that the second candidate cavity feature parameters are initialized based on the first geometric feature parameter in the first target cavity feature parameters; or, the second candidate cavity feature parameters are obtained by adjusting the first target cavity feature parameters (e.g., the first geometric feature parameter in the first target cavity feature parameters). In this way, based on the first target cavity feature parameters obtained through inheritance and optimization, the second target cavity feature parameters of the second cavity can be obtained quickly, improving the optimization efficiency of the cavity feature parameters of the second cavity, and thus improving the processing efficiency of parameter design.

[0134] Furthermore, in a specific example, the second candidate cavity feature parameters include: the second geometric feature parameters of the second resonant cavity.

[0135] It should be noted that, in one example, as shown in Figure 7(a) (front view of the second cavity), Figure 7(b) (side view of the second cavity), and Figure 7(c) (top view of the second cavity), the second cavity includes a second base and a cavity located inside the second base; the second layer structure in the quantum chip and the internal cavity of the second cavity form the second resonant cavity; further, the second geometric feature of the second resonant cavity may include a second depth (which can be denoted as h) and a second surface feature parameter; further, the second surface feature parameter includes the ratio (for example, denoted as l) of the short side (i.e., "width", which can be denoted as n) to the long side (i.e., "length", which can be denoted as m) of the second layer structure in the quantum chip, i.e., l = n / m. Alternatively, the second surface feature parameter may directly include the short side n and the long side m of the second layer structure of the quantum chip, which is not limited in this disclosure.

[0136] Furthermore, in one example, the second surface feature parameter included in the second geometric feature parameter is obtained based on the first surface feature parameter included in the first geometric feature parameter of the first target cavity feature parameter. For example, the ratio l included in the second surface feature parameter is initialized to the optimal parameter value of k included in the first surface feature parameter of the first target cavity feature parameter (which can be denoted as k).* That is, l = k * Alternatively, the second surface feature parameter included in the second geometric feature parameter is obtained by adjusting the first surface feature parameter included in the first geometric feature parameter of the first target cavity feature parameter, for example, l = k * ', where k * 'Indicates the adjusted parameter value of the first surface feature parameter included in the first geometric feature parameter of the first target cavity feature parameter.

[0137] Furthermore, the second depth h included in the second geometric feature parameter can be initialized to a preset depth value. Here, the preset depth value is an empirical value that can be set according to actual needs, and this disclosure does not limit it.

[0138] Alternatively, in another example, the second depth h included in the second geometric feature parameter can also be obtained based on the first depth included in the first geometric feature parameter of the first target cavity feature parameter, for example, h = d. * , where d * The parameter value (i.e., the optimal parameter value) represents the first depth contained in the first geometric feature parameter among the first target cavity feature parameters; or, the second depth h contained in the second geometric feature parameter is obtained after adjusting the first depth contained in the first geometric feature parameter among the first target cavity feature parameters, for example, h = d. * ', where d * ' represents the parameter value (i.e., the optimal parameter value) of the first depth contained in the first geometric feature parameter among the feature parameters of the first target cavity. * Adjusted parameter values.

[0139] In this way, the present invention can automatically and intelligently obtain the second target cavity characteristic parameters of the second cavity after obtaining the first target cavity characteristic parameters of the first cavity. Thus, the core parameters of the packaging box are designed automatically, intelligently and efficiently, thereby effectively avoiding the coupling between the components (such as qubits) in the quantum chip and the first or second cavity, and improving the performance of the quantum chip. Moreover, the present invention is simple to operate and easy to implement, has a low threshold for use, and is also practical.

[0140] In addition, the disclosed solution reduces the complexity of the parameter design process, while also reducing the required computing resources and improving the processing efficiency of parameter design.

[0141] Step S607: Determine whether the second simulation frequency meets the second frequency requirement. If yes, proceed to step S608; otherwise, proceed to step S609.

[0142] Here, the first frequency requirement is derived based on the frequency of the qubits in the quantum chip.

[0143] Step S608: If the second simulation frequency obtained from the simulation meets the second frequency requirement, the second candidate cavity feature parameter corresponding to the second simulation frequency that meets the second frequency requirement is used as the second target cavity feature parameter of the second cavity.

[0144] Here, the second frequency requirement is derived based on the frequency of the qubits in the quantum chip.

[0145] Here, the second target cavity feature parameters of the second cavity can be used to manufacture the packaging box. Furthermore, the second target cavity feature parameters of the second cavity can be used to manufacture the second cavity in the packaging box. In this way, the packaging box can be manufactured in a targeted manner according to the needs, avoiding blind design of the packaging box due to lack of focus, thereby improving the performance of the quantum chip.

[0146] Step S609: Adjust the candidate cavity feature parameters of the second cavity. Then return to step S606.

[0147] It should be noted that the specific steps for obtaining the characteristic parameters of the second target cavity (such as steps S606 to S609) and the specific steps for obtaining the characteristic parameters of the first target cavity (such as steps S601 to S605) can be executed in parallel, for example, by using different simulation systems for parallel simulation, or they can be executed sequentially, for example, by executing steps S601 to S605 first and then steps S606 to S608, or by executing steps S606 to S608 first and then steps S601 to S605. This disclosure does not impose any restrictions on this.

[0148] Furthermore, the adjustment of the candidate cavity feature parameters of the second cavity can refer to: adjusting only the second surface feature parameters, or adjusting both the second surface feature parameters and the second depth. This disclosure does not limit this.

[0149] Here, the first cavity can be designed based on the first target cavity characteristic parameters obtained above, and the second cavity can be designed based on the second target cavity characteristic parameters obtained above. Then, a package containing the first cavity and the second cavity can be designed. In this way, the impact of environmental noise on the quantum chip is effectively reduced, ensuring the high performance of the quantum chip.

[0150] Furthermore, in a specific example, the first cavity is a lower cavity; the second cavity is an upper cavity; the first cavity volume of the lower cavity is larger than the second cavity volume of the upper cavity; furthermore, the second layer structure is located on top of the first layer structure. This effectively reduces the impact of environmental noise on the quantum chip, ensuring its high performance.

[0151] For example, in one example, as shown in Figures 8(a) and 8(b), the support structure parameter in the first target cavity feature parameters can be denoted as gap*, the first depth included in the first geometric feature parameter in the first target cavity feature parameters can be denoted as d*, and the ratio of the short side to the long side included in the first surface feature parameter in the first target cavity feature parameters can be denoted as k*; wherein, based on k* and the area of ​​the first layer structure of the given quantum chip, the length (for example, denoted as b*) and width (for example, a*) of the first layer structure can be obtained, and the first cavity (the lower cavity in the figure) can be designed based on the above parameters; the second depth included in the second geometric feature parameter in the second target cavity feature parameters can be denoted as h*, and the ratio of the short side to the long side included in the second surface feature parameter in the second target cavity feature parameters can be denoted as l*; wherein, based on l* and the area of ​​the second layer structure of the given quantum chip, the length (for example, denoted as m*) and width (for example, n*) of the second layer structure can be designed, and the second cavity (the upper cavity in the figure) can be obtained based on the above parameters. Thus, the packaging box shown in Figure 8(a) and Figure 8(b) is obtained.

[0152] The following detailed explanation of this disclosure, with specific examples, further illustrates the present invention. Specifically, this disclosure proposes a method for systematically and automatically designing the key parameters of a superconducting quantum chip's packaging box based on electromagnetic simulation. Specifically, given the qubit scale of the superconducting quantum chip and the design frequency of the packaging box, this disclosure optimizes the global parameters affecting the packaging box's frequency, making the simulated frequency of the packaging box approach its design frequency, thereby obtaining the key parameters of the packaging box that meet the design requirements. Thus, through this systematic and intelligent method, the packaging box can be designed quickly while effectively ensuring the high performance of the superconducting quantum chip. Compared to existing methods that fail to identify the design focus of the packaging box, leading to blind design, this disclosure improves design efficiency while saving labor and time costs, thereby reducing design costs.

[0153] Before detailing the specific solution disclosed herein, let's first introduce the structure and key parameters of the encapsulation box. Figures 9(a) and 9(b) show the basic structure of the encapsulation box containing the superconducting quantum chip. In this example, the superconducting quantum chip is a 3D flip-chip, comprising a first layer structure (as shown in ⑥) and a second layer structure located above the first layer structure (as shown in ⑤). The encapsulation box is made of copper and includes a first cavity and a second cavity. The first cavity (the lower cavity in Figures 9(a) and 9(b)) includes a first base (as shown in ①). The first base has an internal cavity (as shown in ③), which can be an inverted U-shape, wider at the top and narrower at the bottom, to form a step for supporting the superconducting quantum chip (not shown in the figure, corresponding to the support portion mentioned above). Furthermore, the second cavity (the upper cavity in Figures 9(a) and 9(b)) includes a second base (as shown in ②), and the second base also has an internal cavity (as shown in ④).

[0154] In practical applications, the size (e.g., volume) of the cavity inside the second cavity (the upper cavity in Figures 9(a) and 9(b)) is generally smaller than or equal to the size of the cavity inside the first cavity (the lower cavity in Figures 9(a) and 9(b)). Here, according to the rectangular resonant cavity theory, the larger the size of the rectangular resonant cavity, the smaller its corresponding frequency (e.g., fundamental frequency). When the fundamental frequency of the rectangular resonant cavity decreases to a level close to the frequency of the components (e.g., qubits) in the superconducting quantum chip, it is prone to coupling with the components in the superconducting quantum chip, thus affecting the performance of the superconducting quantum chip. Based on this, in this example, the design of the packaging box can focus only on the fundamental frequency corresponding to the first cavity (e.g., the lower cavity).

[0155] Further, as shown in Figures 4(a), 4(b), and 4(c), the key parameters affecting the fundamental frequency of the first cavity (e.g., the lower cavity) of the packaging box (i.e., the first candidate cavity feature parameters of the first cavity mentioned above) may include: the width of the base step (corresponding to the support structure parameters mentioned above, which can be denoted as gap), the first surface feature parameters included in the first geometric feature parameters of the first resonant cavity, such as the short side (a) and long side (b) of the first layer structure of the superconducting quantum chip, and the depth of the cavity inside the first cavity included in the first geometric feature parameters (corresponding to the first depth mentioned above, which can be denoted as d); here, the first resonant cavity is composed of the first layer structure of the superconducting quantum chip and the cavity inside the first cavity (e.g., the lower cavity).

[0156] Furthermore, as shown in Figures 7(a), 7(b), and 7(c), the key parameters affecting the fundamental frequency of the second cavity (e.g., the upper cavity) of the packaging box (i.e., the second candidate cavity characteristic parameters of the second cavity mentioned above) include: the second surface characteristic parameters included in the second geometric characteristic parameters of the second resonant cavity, such as the short side (which can be denoted as n) and the long side (which can be denoted as m) of the second layer structure of the superconducting quantum chip, and the depth of the cavity inside the second cavity included in the second geometric characteristic parameters (corresponding to the second depth mentioned above, which can be denoted as h); here, the second resonant cavity is composed of the second layer structure of the superconducting quantum chip and the cavity inside the second cavity.

[0157] Furthermore, the content of this disclosure will be specifically introduced and demonstrated from three aspects: the first part introduces the design steps of the key parameters of the packaging box given in this disclosure; the second part briefly explains the theoretical basis of this disclosure; and the third part verifies the effectiveness of this disclosure by combining packaging box design examples.

[0158] Part 1: Design Steps for Key Parameters of the Packaging Box

[0159] Specifically, such as Figure 10 As shown, it specifically includes:

[0160] Step S1001: Determine the target area S of the superconducting quantum chip. For example, based on the scale of the qubits required in the superconducting quantum chip, such as the total number of qubits N and the area A required for each qubit, obtain the area of ​​the first layer structure of the superconducting quantum chip. Let the area of ​​the first layer structure be the target area S, then:

[0161] S = N × A;

[0162] Step S1002: Initialize the dimensions of the superconducting quantum chip contained in the first geometric feature parameters (corresponding to the first surface feature parameters mentioned above). For example, taking the first layer structure of the superconducting quantum chip as a rectangle, the short side (i.e., width, which can be denoted as a) and the long side (i.e., length, which can be denoted as b) of the first layer structure can be initialized. Here, S = a × b.

[0163] Furthermore, we can define k as the ratio of the shorter side a to the longer side b, i.e., k = a / b. Here, in one example, during subsequent optimization, we can start with the shorter side a and the longer side b being of equal length and gradually decrease the lengths of the shorter side a and the longer side b. Therefore, the value of k can be a positive number less than or equal to 1.

[0164] Furthermore, according to the above formula, we have:

[0165]

[0166] At this point, k can be initialized to 1.

[0167] Step S1003: Initialize the support structure parameters in the first cavity and the first depth contained in the first geometric feature parameters. For example, initialize the first depth d to 0mm and the support structure parameter gap to 0mm.

[0168] Step S1004: Model the first cavity and the superconducting quantum chip. Based on the first candidate cavity characteristic parameters obtained in the above steps, namely a, b, d, and gap, model the first cavity and the superconducting quantum chip in electromagnetic simulation software.

[0169] It should be noted that, in one example, in electromagnetic simulation software, the package containing the first cavity and the second cavity can be modeled as a single unit, and then the superconducting quantum chip can be modeled inside the package. At this point, models of the first cavity and the superconducting quantum chip can be obtained.

[0170] Furthermore, during the simulation process, the package containing the superconducting quantum chip can be simulated, and the fundamental frequency corresponding to the first cavity can be obtained. It is understandable that during the optimization of the key parameters of the first cavity, the key parameters of the second cavity can be fixed to avoid interference from the second cavity in the optimization process.

[0171] Step S1005: Optimize the number of parameters included in the first candidate cavity feature parameters. For example, in order to reduce the optimization complexity, the short side a and long side b of the first layer structure in the superconducting quantum chip included in the first surface feature parameters of the first candidate cavity feature parameters are replaced with k. At this time, the first candidate cavity feature parameters of the first cavity specifically include the support structure parameters gap, k and the first depth d.

[0172] Step S1006: Adjust the parameter values ​​of the first candidate cavity feature parameters determined in step S1005, and perform simulation after each adjustment to obtain the target correlation between the first candidate cavity feature parameters (such as k, d and gap) and the fundamental frequency (corresponding to the first simulation frequency mentioned above) of the first cavity.

[0173] Here, the target association relationship includes multiple sub-mapping relationships, each of which is used to characterize the mapping relationship between k and d and the fundamental frequency corresponding to the first cavity when the support part is in the current gap.

[0174] Step S1007: Based on the target correlation, obtain the maximum simulation frequency corresponding to the first cavity.

[0175] For example, in one example, at least one of the following can be used to adjust and optimize the key parameter: decrease k; increase d; increase gap. For example, decrease k while increasing d and gap.

[0176] Step S1008: Determine whether the maximum simulation frequency is greater than or equal to the target frequency; if the maximum simulation frequency is greater than or equal to the target frequency, proceed to step S1010; otherwise, proceed to step S1009.

[0177] Step S1009: The current parameter adjustment scheme fails. Return to step S1006 to readjust the first candidate cavity feature parameters and redetermine the target correlation.

[0178] Here, the target frequency is derived from the frequency of the qubits in the quantum chip, for example, equal to the frequency of the qubits, or a minimum security value (i.e., the minimum value that can avoid coupling), which is greater than the frequency of the qubits.

[0179] Step S1010: Based on the filtering rules, obtain the first target cavity feature parameters from the target association relationship.

[0180] Here, to further determine the cavity characteristic parameters of the first cavity in the package that meets the design requirements, the following filtering rules can be used to filter out the optimal parameter value of the support structure parameter gap (which can be denoted as gap) from the obtained target correlation. * The optimal parameter value for the first depth d (which can be denoted as d) * ), and the optimal parameter value of k (which can be denoted as k). * );

[0181] Furthermore, after obtaining k * Then, according to the formula in step S1002, the optimal parameter value of the short side 'a' of the superconducting quantum chip can be obtained (which can be denoted as 'a'). * ), and the optimal parameter value of the longer side b (which can be denoted as b). * ).

[0182] Here, the filtering rules include at least one of the following:

[0183] Rule 1: The support structure parameters gap and first depth d are both greater than 0;

[0184] Rule 2: The first simulation frequency f corresponding to the first cavity is equal to the preset frequency that the first cavity is designed to achieve (which can be denoted as ω). q That is, f = ω q ;

[0185] Here, the preset frequency is any value greater than or equal to the target frequency, and can be set according to actual needs. This disclosure does not limit this.

[0186] It should be noted that, in rule 2, the first simulation frequency f corresponding to the first cavity is equal to the preset frequency ω that the first cavity is designed to achieve. q Specifically, it can refer to:

[0187] The first simulation frequency f and the preset frequency ω q The difference between them is within a preset error range, which is an empirical value that can be set according to actual needs. This disclosed solution does not limit this range.

[0188] Rule 3: k approaches 1.

[0189] It is understandable that the optimal value obtained is not a single set, but may be multiple sets.

[0190] Step S1011: Initialize the second candidate cavity feature parameters of the second cavity in the encapsulation box, such as initializing the second surface feature parameters included in the second geometric feature parameters of the second candidate cavity feature parameters of the second cavity, and initializing the second depth (which can be denoted as h) included in the second geometric feature parameters.

[0191] Here, similar to the first surface feature parameter, the second surface feature parameter can also include the ratio of the short side to the long side of the second layer structure, which can be denoted as l, i.e., l = the short side (which can be denoted as n) / the long side (which can be denoted as m) of the second layer structure; in this case, initialize l = k * Accordingly, the second depth h = d is initialized. * .

[0192] Step S1012: Simulate the second cavity to obtain the fundamental frequency corresponding to the second cavity (corresponding to the second simulation frequency mentioned above, which can be denoted as e); for example, simulate the package containing the superconducting quantum chip and obtain the fundamental frequency corresponding to the second cavity.

[0193] Step S1013: Determine whether the second simulation frequency e is greater than or equal to the preset frequency ω. q If so, that is, greater than or equal to the preset frequency ω q If the condition is met, proceed to step S1015; otherwise, proceed to step S1014.

[0194] Step S1014: Adjust the cavity characteristic parameters of the second cavity, such as reducing the second surface characteristic parameters, and return to step S1012.

[0195] Step S1015: Output the characteristic parameters of the second target cavity of the second cavity, such as parameters greater than or equal to the preset frequency ω. q The second candidate cavity feature parameters corresponding to the second simulation frequency are used as the second target cavity feature parameters of the second cavity.

[0196] Part Two: Theoretical Basis of this Disclosure

[0197] (I) Parameter Selection

[0198] The package can be approximated as a rectangular resonant cavity. For example, if the first cavity is approximated as a rectangular resonant cavity, then the fundamental frequency expression of the rectangular resonant cavity corresponding to the first cavity is:

[0199]

[0200] Here, f represents the fundamental frequency of the rectangular resonant cavity corresponding to the first cavity, and ε r The first cavity represents the relative permittivity, where a represents the short side of the first layer structure in the quantum chip, b represents the long side of the first layer structure in the quantum chip, and d represents the first depth of the first cavity.

[0201] As shown in the above formula, the fundamental frequency corresponding to the first cavity is determined by the side length and relative permittivity of the rectangular resonant cavity corresponding to the first cavity. Here, due to the presence of the quantum chip's substrate medium within the rectangular resonant cavity corresponding to the first cavity, the relative permittivity is also related to the depth d and the step width gap of the rectangular resonant cavity corresponding to the first cavity. In summary, the fundamental frequency corresponding to the first cavity can be determined by the short side a and long side b, the first depth d, and the step width gap of the first layer structure in the quantum chip. Furthermore, since the dimensions of the first layer structure in the quantum chip can be represented by a scaling factor, it is reasonable for this disclosed scheme to use the ratio k of the short side to the long side of the first layer structure in the quantum chip, the first depth d, and the step width gap as the three parameters for global parameter optimization design of the first cavity packaging box.

[0202] Accordingly, it is reasonable to use the ratio of the short side to the long side of the second layer structure in the quantum chip and the second depth h as the global parameters of the second cavity to optimize the design of the packaging box.

[0203] (II) Screening Rules

[0204] For rule 1, if gap = 0 or d = 0, it means that the first cavity has no step, which is inconsistent with the actual situation.

[0205] For rule 3, the optimal layout of qubits for implementing quantum error-correcting codes is a square, thus making k as close to 1 as possible. This minimizes the adverse effects on quantum error-correcting codes, and the square layout of qubits also improves connectivity between qubits, thereby reducing the complexity of quantum circuits.

[0206] Part Three: Packaging Box Design Examples

[0207] To verify the effectiveness of this disclosure, the following packaging box design example is provided.

[0208] The design steps in this example specifically include:

[0209] Step 1: Determine the target area of ​​the quantum chip. Here, we assume that a quantum chip containing 100 qubits is designed, with an average area of ​​4 mm² per qubit. 2 The resulting quantum chip area is S = 400 mm². 2 ;

[0210] Step 2: Initialize the dimensions of the quantum chip based on its area. Here, let the shorter side of the quantum chip be *a* and the longer side be *b*, and let the scaling factor be *k* = *a / b*. Then the shorter side... Long side Based on the square initialization rule, k is initialized to 1. At this time, both a and b are 20mm after initialization.

[0211] Step 3: Initialize the depth d of the lower cavity in the encapsulation box and the support structure parameter gap. For example, initialize both d and the support structure parameter gap to 0mm;

[0212] Step 4: Model the lower cavity and quantum chip. Based on the initial parameters of the aforementioned package, model the lower cavity and quantum chip using electromagnetic simulation software.

[0213] Step 5: Determine the first candidate cavity feature parameters for the lower cavity in the encapsulation box. Here, the first candidate cavity feature parameters include k, the first depth d, and the support structure parameter gap.

[0214] Furthermore, considering the constraints of wafer size, the wafer diameter R is set to 50mm. In this case, the long side of the quantum chip must not exceed 50mm. Therefore, k is 0.16. Thus, the ratio of the short side to the long side, k, is between 0.16 and 1.

[0215] Step 6: Simulate the lower cavity. Specifically, gradually decrease k to 0.16 while simultaneously increasing d and gap, and simulate the change of the fundamental frequency of the lower cavity with the optimized parameters of the lower cavity.

[0216] In one example, the graph showing the change of fundamental frequency with the optimized parameters of the lower cavity can use different curves to represent different parameters. For example, different colored curves can be used to represent different first depths d and support structure parameters gap. In this case, the curve can be denoted as C. ij =[d i ,gap jIn this diagram, each i corresponds to a color, and the variation of a color with j can be represented by different shades of the curve. Furthermore, the step sizes of d and gap can be set based on actual conditions, for example, both can be 1 mm. At this point, step 6 yields the variation diagram shown in Figure 11(a).

[0217] Step 7: From the graph showing the change of the fundamental frequency (corresponding to the first simulation frequency mentioned above) of the lower cavity with the optimized parameters of the lower cavity (e.g., Figure 11(a)), the maximum simulation frequency can be obtained, which is approximately 16.2 GHz, significantly greater than the target frequency of 12 GHz. Proceed to the next step.

[0218] Step 8: Add filtering rules. For example, based on filtering rules, filter the change graph obtained in Step 6. Here, the filtering rules include:

[0219] Rule 1: Both the first depth d and the support structure parameter gap are greater than 0;

[0220] Rule 2: The first simulated frequency f corresponding to the lower cavity is the preset frequency (i.e., ω). q 12GHz;

[0221] Rule 3: The first surface feature parameter k approximates 1.

[0222] Step 9: Obtain the first target cavity characteristic parameters of the lower cavity. For example, set the preset frequency ω of the encapsulation box. q If the frequency is 12GHz, then the result of step 6 is constrained and optimized according to the screening rules in step 8. For example, the optimized result is shown in Figure 11(b), and the first target cavity feature parameters of the lower cavity are obtained as follows: k = 0.48, d = 13mm, gap = 3mm. At this time, the first simulation frequency corresponding to the lower cavity in the package is 12GHz.

[0223] Step 10: Initialize the second candidate cavity feature parameters of the upper cavity. For example, initialize l to the k value obtained in step 9, i.e., l = 0.48, and initialize the second depth h to the d value obtained in step 9, i.e., h = 13, and perform simulation to obtain the fundamental frequency corresponding to the upper cavity, which is 12.3 GHz, greater than the preset frequency ω. q To meet its design requirements, the final result is:

[0224] First target cavity characteristic parameters: k = 0.48, d = 13 mm, gap = 3 mm;

[0225] Second target cavity characteristic parameters: l = 0.48, h = 13 mm;

[0226] At this point, the design of all key parameters of the packaging box has been completed according to the design requirements.

[0227] This disclosure proposes a method for designing key parameters of a packaging box for encapsulating superconducting quantum chips based on electromagnetic simulation. By combining the electromagnetic simulation of the packaging box with the quantum bit scale and the design frequency of the packaging box, the key parameters of the packaging box can be designed efficiently and on demand. Specifically, this disclosure has the following advantages, including:

[0228] First, it provides a systematic approach that helps to determine the optimal key parameters. It enables the targeted design of key parameters for sample boxes based on specific needs, thereby avoiding blind design due to a lack of focus.

[0229] Secondly, it ensures the high performance of the quantum chip. The base frequency design of the package directly affects the performance of the quantum chip. The scheme disclosed in this paper takes the design frequency of the package as the standard and continuously optimizes the size to make its base frequency meet the design frequency requirements. At the same time, it ensures that the ratio of the short side to the long side of the quantum chip is as close to 1 as possible, thereby maximizing the efficiency of the quantum error correction code and the connectivity between bits, thus ensuring the high performance of the quantum chip.

[0230] Third, it significantly improves design efficiency. The streamlined design process allows for rapid design of packaging boxes, which is of practical value for automating the design of packaging boxes used to encapsulate superconducting quantum chips.

[0231] This disclosure also provides a simulation device, such as Figure 12 As shown, it includes:

[0232] Processing unit 1201 is configured to determine a target correlation relationship corresponding to a first cavity in a packaging box used for packaging a quantum chip; the target correlation relationship is used to characterize the mapping relationship between a first candidate cavity feature parameter of the first cavity and a first simulation frequency corresponding to the first cavity; the first candidate cavity feature parameter can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of a first resonant cavity; the first resonant cavity is composed of a first layer structure in the quantum chip and an internal cavity of the first cavity; the target simulation frequency corresponding to the first cavity is obtained based on the target correlation relationship; if the target simulation frequency meets a first frequency requirement, the first target cavity feature parameter of the first cavity is obtained based on the target correlation relationship; the first frequency requirement is obtained based on the frequency of the qubits in the quantum chip;

[0233] Output unit 1202 is used to output the first target cavity feature parameters of the first cavity.

[0234] In a specific example of the scheme disclosed herein, the first candidate cavity feature parameters include: the support structure parameters of the support portion in the first cavity, and the first geometric feature parameters of the first resonant cavity; the support portion is used to support the quantum chip;

[0235] The target association relationship includes multiple sub-mapping relationships. The sub-mapping relationships are used to characterize the mapping relationship between the first geometric feature parameter of the first resonant cavity and the first simulation frequency under the current support structure parameters of the support part. The support structure parameters corresponding to different sub-mapping relationships are different.

[0236] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0237] The maximum simulation frequency is selected from multiple first simulation frequencies corresponding to the target correlation, wherein the target simulation frequency is the maximum simulation frequency.

[0238] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0239] If the target simulation frequency is determined to be greater than or equal to the target frequency, the first target cavity characteristic parameters of the first cavity are obtained based on the following screening rules; the target frequency is obtained based on the frequency of the qubits in the quantum chip.

[0240] The filtering rules include at least one of the following:

[0241] The supporting structure parameter is greater than the first value, and the first depth contained in the first geometric feature parameter is greater than the second value;

[0242] The first simulation frequency corresponding to the first cavity is the preset frequency that the first cavity is designed to reach.

[0243] The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

[0244] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0245] If the target simulation frequency is determined to be greater than or equal to the target frequency, at least one candidate simulation frequency is selected from multiple first simulation frequencies corresponding to the target correlation, wherein the difference between the candidate simulation frequency in the at least one candidate simulation frequency and the preset frequency required to be reached by the pre-designed first cavity is less than or equal to the preset difference; the target frequency is obtained based on the frequency of the qubits in the quantum chip;

[0246] Based on the following screening rules, the first target cavity feature parameters of the first cavity are selected from at least one first candidate cavity feature parameters corresponding to at least one candidate simulation frequency;

[0247] The filtering rules include at least one of the following:

[0248] The supporting structure parameter is greater than the first value, and the first depth contained in the first geometric feature parameter is greater than the second value;

[0249] The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

[0250] In a specific example of the scheme disclosed herein,

[0251] The processing unit is further configured to simulate and obtain a second simulated frequency corresponding to the second cavity in the package; wherein, the second simulated frequency is obtained by simulating a second cavity with second candidate cavity characteristic parameters; the second candidate cavity characteristic parameters can affect the frequency corresponding to the second cavity; the frequency corresponding to the second cavity is the frequency of the second resonant cavity; the second resonant cavity is composed of the second layer structure in the quantum chip and the internal cavity of the second cavity; when the simulated second frequency meets the second frequency requirement, the second candidate cavity characteristic parameters corresponding to the second simulated frequency that meets the second frequency requirement are used as the second target cavity characteristic parameters of the second cavity; wherein, the second frequency requirement is obtained based on the frequency of the qubits in the quantum chip;

[0252] The output unit is also used to output the second target cavity characteristic parameters of the second cavity.

[0253] In a specific example of the scheme disclosed herein, the second candidate cavity feature parameters are obtained based on the first target cavity feature parameters, or are obtained after adjusting the first target cavity feature parameters.

[0254] In a specific example of the scheme disclosed herein, the second candidate cavity feature parameters include: the second geometric feature parameters of the second resonant cavity;

[0255] The second surface feature parameter included in the second geometric feature parameter is obtained based on the first surface feature parameter included in the first geometric feature parameter in the first target cavity feature parameter; or, the second surface feature parameter included in the second geometric feature parameter is obtained by adjusting the first surface feature parameter included in the first geometric feature parameter in the first target cavity feature parameter.

[0256] In a specific example of the scheme disclosed herein, the first cavity is a lower cavity; the second cavity is an upper cavity; and the first cavity volume of the lower cavity is greater than the second cavity volume of the upper cavity.

[0257] In a specific example of the scheme disclosed herein, the quantum chip is a superconducting quantum chip.

[0258] For a description of the specific functions and examples of each unit of the apparatus in this disclosure embodiment, please refer to the relevant descriptions of the corresponding steps in the above method embodiments, which will not be repeated here.

[0259] This disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above using a quantum computing device.

[0260] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described above for use in classical computing devices.

[0261] Alternatively, the computer program, when executed by at least one quantum processing unit, implements the method applied to a quantum computing device.

[0262] This disclosure also provides a quantum computing device, the quantum computing device comprising:

[0263] At least one quantum processing unit;

[0264] A memory, coupled to the at least one QPU and used to store executable instructions,

[0265] The instructions are executed by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method applied to the quantum computing device.

[0266] It is understood that the quantum processing unit (QPU) used in the present disclosure may also be referred to as a quantum processor or quantum chip, and may involve a physical chip comprising multiple qubits interconnected in a specific manner.

[0267] Furthermore, it is understood that the qubit described in this disclosure can refer to the basic information unit of a quantum computing device. The qubit is contained within the QPU and extends the concept of the classical digital bit.

[0268] According to embodiments of this disclosure, this disclosure also provides a computing device, a readable storage medium, and a computer program product.

[0269] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0270] Figure 13 A schematic block diagram of an example computing device 1300 that can be used to implement embodiments of the present disclosure is shown. The computing device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The computing device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0271] As shown in Figure 8, device 1300 includes a computing unit 1301, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1302 or a computer program loaded from storage unit 1308 into random access memory (RAM) 1303. The RAM 1303 may also store various programs and data required for the operation of device 1300. The computing unit 1301, ROM 1302, and RAM 1303 are interconnected via bus 1304. Input / output (I / O) interface 1305 is also connected to bus 1304.

[0272] Multiple components in device 1300 are connected to I / O interface 1305, including: input unit 1306, such as keyboard, mouse, etc.; output unit 1307, such as various types of monitors, speakers, etc.; storage unit 1308, such as disk, optical disk, etc.; and communication unit 1309, such as network card, modem, wireless transceiver, etc. Communication unit 1309 allows device 1300 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0273] The computing unit 1301 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1301 performs the various methods and processes described above, such as simulation methods. For example, in some embodiments, the simulation method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1308. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1300 via ROM 1302 and / or communication unit 1309. When the computer program is loaded into RAM 1303 and executed by the computing unit 1301, one or more steps of the simulation method described above may be performed. Alternatively, in other embodiments, the computing unit 1301 may be configured to perform simulation methods by any other suitable means (e.g., by means of firmware).

[0274] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0275] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0276] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0277] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0278] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0279] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0280] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0281] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A simulation method, comprising: Determine the target correlation corresponding to the first cavity in the packaging box used to encapsulate the quantum chip; The target association relationship is used to characterize the mapping relationship between the first candidate cavity feature parameters of the first cavity and the first simulation frequency corresponding to the first cavity; the first candidate cavity feature parameters can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of the first resonant cavity; The first resonant cavity is composed of a first layer structure in the quantum chip and an internal cavity of the first cavity body; the first candidate cavity feature parameters include: the support structure parameters of the support portion in the first cavity body, and the first geometric feature parameters of the first resonant cavity; the support portion is used to support the quantum chip; the target correlation relationship includes multiple sub-mapping relationships, and the sub-mapping relationships in the multiple sub-mapping relationships are used to characterize the mapping relationship between the first geometric feature parameters of the first resonant cavity and the first simulation frequency under the current support structure parameters of the support portion; different sub-mapping relationships in the multiple sub-mapping relationships correspond to different support structure parameters; Based on the target correlation, the target simulation frequency corresponding to the first cavity is obtained; If the target simulation frequency meets the first frequency requirement, the first target cavity characteristic parameters of the first cavity are obtained based on the target correlation; the first frequency requirement is obtained based on the frequency of the qubits in the quantum chip.

2. The method according to claim 1, wherein, The step of obtaining the target simulation frequency corresponding to the first cavity based on the target correlation includes: The maximum simulation frequency is selected from multiple first simulation frequencies corresponding to the target correlation, wherein the target simulation frequency is the maximum simulation frequency.

3. The method according to claim 1, wherein, When it is determined that the target simulation frequency meets the first frequency requirement, the first target cavity characteristic parameters of the first cavity are obtained based on the target correlation relationship, including: If the target simulation frequency is determined to be greater than or equal to the target frequency, the first target cavity characteristic parameters of the first cavity are obtained based on the following screening rules; the target frequency is obtained based on the frequency of the qubits in the quantum chip. The filtering rules include at least one of the following: The supporting structure parameter is greater than the first value, and the first depth contained in the first geometric feature parameter is greater than the second value; The first simulation frequency corresponding to the first cavity is the preset frequency that the first cavity is designed to reach. The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

4. The method according to claim 1, wherein, When it is determined that the target simulation frequency meets the first frequency requirement, the first target cavity characteristic parameters of the first cavity are obtained based on the target correlation relationship, including: If the target simulation frequency is determined to be greater than or equal to the target frequency, at least one candidate simulation frequency is selected from multiple first simulation frequencies corresponding to the target correlation, wherein the difference between the candidate simulation frequency in the at least one candidate simulation frequency and the preset frequency required to be reached by the pre-designed first cavity is less than or equal to the preset difference; the target frequency is obtained based on the frequency of the qubits in the quantum chip; Based on the following screening rules, the first target cavity feature parameters of the first cavity are selected from at least one first candidate cavity feature parameters corresponding to at least one candidate simulation frequency; The filtering rules include at least one of the following: The supporting structure parameter is greater than the first value, and the first depth contained in the first geometric feature parameter is greater than the second value; The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

5. The method according to any one of claims 1-4, further comprising: The simulation yields a second simulated frequency corresponding to the second cavity in the package; wherein, the second simulated frequency is obtained by simulating a second cavity with second candidate cavity characteristic parameters; the second candidate cavity characteristic parameters can affect the frequency corresponding to the second cavity; the frequency corresponding to the second cavity is the frequency of the second resonant cavity; the second resonant cavity is composed of the second layer structure in the quantum chip and the internal cavity of the second cavity; If the second simulation frequency obtained from the simulation meets the second frequency requirement, the second candidate cavity feature parameter corresponding to the second simulation frequency that meets the second frequency requirement is used as the second target cavity feature parameter of the second cavity; wherein, the second frequency requirement is obtained based on the frequency of the qubits in the quantum chip.

6. The method according to claim 5, wherein, The second candidate cavity feature parameters are obtained based on the first target cavity feature parameters, or are obtained after adjusting the first target cavity feature parameters.

7. The method according to claim 6, wherein, The second candidate cavity characteristic parameters include: the second geometric characteristic parameters of the second resonant cavity; The second surface feature parameter included in the second geometric feature parameter is obtained based on the first surface feature parameter included in the first geometric feature parameter in the first target cavity feature parameter; or, the second surface feature parameter included in the second geometric feature parameter is obtained by adjusting the first surface feature parameter included in the first geometric feature parameter in the first target cavity feature parameter.

8. The method according to claim 5, wherein, The first cavity is a lower cavity; the second cavity is an upper cavity; the first cavity volume of the lower cavity is greater than the second cavity volume of the upper cavity.

9. The method according to claim 1, wherein, The quantum chip is a superconducting quantum chip.

10. A simulation device, comprising: The processing unit is used to determine the target correlation relationship corresponding to the first cavity in the packaging box used to package the quantum chip; The target association relationship is used to characterize the mapping relationship between the first candidate cavity feature parameters of the first cavity and the first simulation frequency corresponding to the first cavity; the first candidate cavity feature parameters can affect the frequency corresponding to the first cavity; the frequency corresponding to the first cavity is the frequency of the first resonant cavity; The first resonant cavity is composed of a first layer structure in the quantum chip and an internal cavity of the first cavity body; the first candidate cavity feature parameters include: the support structure parameters of the support portion in the first cavity body, and the first geometric feature parameters of the first resonant cavity; the support portion is used to support the quantum chip; the target correlation relationship includes multiple sub-mapping relationships, and the sub-mapping relationships in the multiple sub-mapping relationships are used to characterize the mapping relationship between the first geometric feature parameters of the first resonant cavity and the first simulation frequency under the current support structure parameters of the support portion; different support structure parameters are corresponding to different sub-mapping relationships in the multiple sub-mapping relationships; the target simulation frequency corresponding to the first cavity body is obtained based on the target correlation relationship; when it is determined that the target simulation frequency meets the first frequency requirement, the first target cavity feature parameters of the first cavity body are obtained based on the target correlation relationship; the first frequency requirement is obtained based on the frequency of the qubits in the quantum chip; The output unit is used to output the first target cavity characteristic parameters of the first cavity.

11. The apparatus according to claim 10, wherein, The processing unit is specifically used for: The maximum simulation frequency is selected from multiple first simulation frequencies corresponding to the target correlation, wherein the target simulation frequency is the maximum simulation frequency.

12. The apparatus according to claim 10, wherein, The processing unit is specifically used for: If the target simulation frequency is determined to be greater than or equal to the target frequency, the first target cavity characteristic parameters of the first cavity are obtained based on the following screening rules; the target frequency is obtained based on the frequency of the qubits in the quantum chip. The filtering rules include at least one of the following: The supporting structure parameter is greater than the first value, and the first depth contained in the first geometric feature parameter is greater than the second value; The first simulation frequency corresponding to the first cavity is the preset frequency that the first cavity is designed to reach. The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

13. The apparatus according to claim 10, wherein, The processing unit is specifically used for: If the target simulation frequency is determined to be greater than or equal to the target frequency, at least one candidate simulation frequency is selected from multiple first simulation frequencies corresponding to the target correlation, wherein the difference between the candidate simulation frequency in the at least one candidate simulation frequency and the preset frequency required to be reached by the pre-designed first cavity is less than or equal to the preset difference; the target frequency is obtained based on the frequency of the qubits in the quantum chip; Based on the following screening rules, the first target cavity feature parameters of the first cavity are selected from at least one first candidate cavity feature parameters corresponding to at least one candidate simulation frequency; The filtering rules include at least one of the following: The supporting structure parameter is greater than the first value, and the first depth contained in the first geometric feature parameter is greater than the second value; The difference between the first surface feature parameter included in the first geometric feature parameter and the third value is less than a preset threshold.

14. The apparatus according to any one of claims 11-13, wherein, The processing unit is further configured to simulate and obtain a second simulated frequency corresponding to the second cavity in the package; wherein, the second simulated frequency is obtained by simulating a second cavity with second candidate cavity characteristic parameters; the second candidate cavity characteristic parameters can affect the frequency corresponding to the second cavity; the frequency corresponding to the second cavity is the frequency of the second resonant cavity; the second resonant cavity is composed of the second layer structure in the quantum chip and the internal cavity of the second cavity; when the simulated second frequency meets the second frequency requirement, the second candidate cavity characteristic parameters corresponding to the second simulated frequency that meets the second frequency requirement are used as the second target cavity characteristic parameters of the second cavity; wherein, the second frequency requirement is obtained based on the frequency of the qubits in the quantum chip; The output unit is also used to output the second target cavity characteristic parameters of the second cavity.

15. The apparatus according to claim 14, wherein, The second candidate cavity feature parameters are obtained based on the first target cavity feature parameters, or are obtained after adjusting the first target cavity feature parameters.

16. The apparatus according to claim 15, wherein, The second candidate cavity characteristic parameters include: the second geometric characteristic parameters of the second resonant cavity; The second surface feature parameter included in the second geometric feature parameter is obtained based on the first surface feature parameter included in the first geometric feature parameter in the first target cavity feature parameter; or, the second surface feature parameter included in the second geometric feature parameter is obtained by adjusting the first surface feature parameter included in the first geometric feature parameter in the first target cavity feature parameter.

17. The apparatus according to claim 14, wherein, The first cavity is a lower cavity; the second cavity is an upper cavity; the first cavity volume of the lower cavity is greater than the second cavity volume of the upper cavity.

18. The apparatus according to claim 10, wherein, The quantum chip is a superconducting quantum chip.

19. A computing device, comprising: At least one quantum processing unit (QPU); A memory, coupled to the at least one QPU and used to store executable instructions, The instructions are executed by the at least one QPU to enable the at least one QPU to perform the method of any one of claims 1-9; Or, including: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-9.

20. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, When at least one quantum processing unit is executed, the computer instructions cause the at least one quantum processing unit to perform the method according to any one of claims 1 to 9; Alternatively, the computer instructions are used to cause the computer to perform the method according to any one of claims 1-9.

21. A computer program product comprising a computer program that, when executed by at least one quantum processing unit, implements the method according to any one of claims 1-9; Alternatively, the computer program may, when executed by a processor, implement the method according to any one of claims 1-9.

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