Power device capable of improving avalanche tolerance of super-junction structure and manufacturing method thereof

Abstract

The application relates to a power device capable of improving the avalanche tolerance of a super-junction structure and a preparation method thereof. The device comprises an active region prepared in a central area of a semiconductor substrate and a terminal protection region located at the outer ring of the active region, the terminal protection region surrounds the active region, wherein, in the active region, a front cell unit and a super-junction unit are included, the super-junction unit comprises a plurality of first conductive type columns and second conductive type columns which are alternately distributed in sequence, the conductive type of the first conductive type column is consistent with the conductive type of the semiconductor substrate; for any second conductive type column, a plurality of second conductive type column doped regions which are epitaxially filled in the second conductive type column groove in sequence are included, wherein, according to the sequence of the epitaxial filling in the second conductive type column groove, the doping concentration of the second conductive type column doped region increases in sequence. The application can effectively improve the avalanche energy of the super-junction device and is compatible with the existing process.

Description

Technical Field

[0001] This invention relates to a power device based on a superjunction structure and its fabrication method, and more particularly to a power device and its fabrication method that can improve the avalanche tolerance of a superjunction structure. Background Technology

[0002] In the semiconductor field, chips are divided into multiple parts, which can be categorized into four parts according to product standards: integrated circuits, discrete devices, optoelectronic devices, and sensors; power devices are an important component belonging to discrete devices. Power devices, also known as semiconductor devices that process power, are specifically divided into rectifier devices and switching devices. The development of switching devices has consistently focused on both high frequency and high power. Different devices have inherent limitations in frequency and power due to their structure and materials. Therefore, current efforts often attempt to overcome these limitations by using new materials, new device structures, and / or new operating principles.

[0003] VDMOS and IGBT devices are the leaders in power devices, occupying a large market share. In circuits, these switching devices achieve the control of large current and large voltage with small current or small voltage, providing suitable output for subsequent circuits.

[0004] In a power system, energy consumption occurs partly due to the load and partly due to switching devices. For these switching devices, the goal is to achieve minimal switching energy loss while maintaining high frequency and high power, thereby reducing heat generation in the chip and the system. MOSFETs are unipolar power switching devices characterized by high switching frequencies and are widely used in radar, switching power supplies, automotive electronics, inverters, and other applications.

[0005] Traditional silicon-based VDMOS devices are mostly used below 1000V. This is because there is a natural 2.5-power relationship between their breakdown voltage and specific on-resistance. That is, the higher the breakdown voltage, the faster the specific on-resistance increases, leading to a rapid increase in power consumption. Therefore, the SJ (superjunction)-MOS structure was invented based on the MOSFET structure. The superjunction structure alternates two semiconductor materials with opposite polarities, forming an alternating NPNP structure, also known as a charge-balanced structure. This structure has been theoretically verified.

[0006] The superjunction structure improves the 2.5-power relationship between breakdown voltage and specific on-resistance. Under the same breakdown voltage, a superjunction structure allows for a smaller chip area, meaning more superjunction MOS devices can be fabricated on the same wafer area. However, this is both an advantage and a disadvantage of the superjunction structure. While it can carry a larger current at the same breakdown voltage, the smaller chip area leads to more concentrated heat generation during high voltage and high current switching. This heat can potentially cause failure of the superjunction device during unclamped inductive switching (UIS) under unclamped inductive loads. Therefore, it is crucial to optimize the avalanche withstand capability of superjunction devices to ensure safe operation under various conditions.

[0007] Semiconductor devices are widely used in automotive electronics, aerospace, and many other fields, which inevitably places higher demands on their reliability and stability. Avalanche resistance is one of the most important capabilities. In power devices (UIS), these devices are used in inductive circuits. During circuit switching, the inductive circuit stores some energy due to its inherent properties. This energy is released through the device when the circuit is switched off. The maximum energy that can be safely released is called avalanche tolerance. Avalanche tolerance represents the device's ability to withstand extreme stress under certain extreme operating conditions. Therefore, efforts are being made to optimize device structure, manufacturing processes, and application circuits to improve the avalanche tolerance of devices and enhance their reliability.

[0008] For superjunction MOS devices, avalanche withstand capability is mainly affected by two factors. Firstly, during the uninterrupted switching (UIS) process in the superjunction, the parasitic NPN transistors near the PWELL junction in the MOS structure conduct, leading to uncontrolled avalanche current and potentially causing device failure. Secondly, during the UIS process in the superjunction, excessively concentrated avalanche current prevents heat dissipation, further contributing to device failure. Therefore, effectively improving the avalanche withstand capability of superjunction MOS devices is a pressing technical challenge that needs to be addressed. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a power device and its fabrication method that can improve the avalanche tolerance of superjunction structures. It can effectively improve the avalanche energy of superjunction devices and is compatible with existing processes.

[0010] According to the technical solution provided by this invention, the power device that can improve the avalanche tolerance of a superjunction structure includes an active region fabricated in the central region of a semiconductor substrate and a termination protection zone located on the outer ring of the active region, wherein the termination protection zone surrounds the active region.

[0011] Within the active region, there are front-side cell units and superjunction units. The superjunction unit includes a plurality of alternating first conductivity type pillars and second conductivity type pillars. The conductivity type of the first conductivity type pillar is consistent with the conductivity type of the semiconductor substrate.

[0012] For any second conductivity type pillar, there are several second conductivity type pillar doped regions that are sequentially epitaxially filled in the second conductivity type pillar trench, wherein the doping concentration of the second conductivity type pillar doped regions increases sequentially according to the order of epitaxial filling in the second conductivity type pillar trench.

[0013] The semiconductor substrate includes a substrate of a first conductivity type and a drift region of the first conductivity type located on the substrate, wherein,

[0014] The first conductivity type drift region is adjacent to the substrate;

[0015] The superjunction unit is fabricated in the first conductivity type drift region, and the bottom of the first conductivity type pillar and the bottom of the second conductivity type pillar are located at the junction of the first conductivity type drift region and the substrate;

[0016] A positive cell unit consists of several positive cells arranged in parallel;

[0017] On the cross-section of the power device, for any front cell, there is a first conductivity type base region and a second conductivity type well region symmetrically distributed on both sides of the first conductivity type base region. The first conductivity type base region is located above the first conductivity type pillar and in contact with the first conductivity type pillar. The width of the first conductivity type base region is smaller than the width of the first conductivity type pillar.

[0018] The width of the second conductivity type well region is greater than the width of the second conductivity type pillar, and the second conductivity type well region is in contact with the corresponding first conductivity type pillar and the second conductivity type pillar.

[0019] When the front-side cell adopts a planar cell, a first conductivity type source region and a second conductivity type heavily doped region are set within the second conductivity type well region, wherein...

[0020] The second conductivity type heavily doped region includes a second conductivity type first heavily doped region and a second conductivity type second heavily doped region;

[0021] The first heavily doped region of the second conductivity type covers the bottom of the source region of the first conductivity type.

[0022] The second doped region of the second conductivity type corresponds exactly to the pillar doped region of the second conductivity type filled by the last epitaxial layer, and the width of the second doped region of the second conductivity type is not greater than the width of the pillar doped region of the second conductivity type filled by the last epitaxial layer.

[0023] The source region of the first conductivity type, the first heavily doped region of the second conductivity type, and the second heavily doped region of the second conductivity type are all in ohmic contact with the source metal.

[0024] A gate-conductive polysilicon is disposed above the base region of the first conductivity type, wherein...

[0025] The gate conductive polysilicon includes a horizontal polysilicon body and vertical polysilicon bodies symmetrically distributed at both ends of the horizontal polysilicon body, and the vertical polysilicon bodies and the horizontal polysilicon bodies are connected as one unit.

[0026] The horizontal polycrystalline silicon body corresponds directly to the base region of the first conductivity type, and the horizontal polycrystalline silicon body is insulated from the base region of the first conductivity type.

[0027] A vertical polysilicon body extends into the second conductivity type well region. The vertical polysilicon body is insulated and isolated from the second conductivity type well region, the first conductivity type source region, and the second conductivity type first heavily doped region. The bottom of the vertical polysilicon body is located above the bottom of the first conductivity type source region.

[0028] The vertical and horizontal polycrystalline silicon bodies are insulated from the source metal.

[0029] A heavily doped region of the first conductivity type is formed within the first conductivity type pillar, wherein...

[0030] The heavily doped region of the first conductivity type pillar extends vertically from the top of the first conductivity type pillar to the bottom of the first conductivity type pillar, and the width of the doped region of the first conductivity type pillar is smaller than the width of the first conductivity type pillar.

[0031] The bottom of the heavily doped region of the first conductivity type pillar is located above the bottom of the doped region of the second conductivity type pillar filled by the last epitaxial growth.

[0032] The doped region of the second conductivity type column within the second conductivity type column is columnar in the last filling and U-shaped in the second conductivity type column before the last filling.

[0033] A method for fabricating a power device with improved avalanche tolerance of a superjunction structure, used to fabricate the aforementioned power device, wherein the fabrication method includes:

[0034] A semiconductor substrate of a first conductivity type is provided, the semiconductor substrate comprising a substrate of the first conductivity type and a drift base region of the first conductivity type located on the substrate;

[0035] The first conductivity type drift base region is subjected to trench etching to form a second conductivity type pillar trench after trench etching. The second conductivity type pillar trench extends vertically towards the substrate within the first conductivity type drift base region.

[0036] Epitaxy of a second type of material is performed within the aforementioned second type of conductive type pillar trench to form a second type of conductive type pillar after the epitaxy fills the second type of conductive type pillar trench. After the second type of conductive type pillar is formed, a first type of conductive type pillar is formed based on the first type of conductive type drift base region, which is alternately distributed with the second type of conductive type pillar. The doping concentration of the doped region of the second type of conductive type pillar increases sequentially according to the order of epitaxial filling within and outside the second type of conductive type pillar trench.

[0037] Epitaxy of a first conductivity type material is performed on the aforementioned first conductivity type drift base region to form a first conductivity type epitaxial base layer after epitaxy, and a first conductivity type drift region is formed based on the first conductivity type epitaxial base layer and the first conductivity type drift base region;

[0038] A front cell process is performed in the aforementioned first conductivity type drift region to prepare a front cell unit and a terminal protection zone, the terminal protection zone surrounding the front cell unit.

[0039] The front-side cell process includes:

[0040] Second conductivity type impurity ion implantation is performed above the first conductivity type epitaxial substrate to form a second conductivity type well region and a first conductivity type base region for separating the second conductivity type well region after the second conductivity type impurity ion implantation. The first conductivity type base region is located above the first conductivity type pillar and in contact with the N pillar. The width of the first conductivity type base region is smaller than the width of the N pillar.

[0041] The width of the second conductivity type well region is greater than the width of the second conductivity type pillar, and the second conductivity type well region is in contact with the corresponding first conductivity type pillar and the second conductivity type pillar;

[0042] Based on the first conductivity type base region and the second conductivity type well region described above, the front structure of the front cell is prepared.

[0043] The front-side cell process also includes:

[0044] Second conductivity type impurity ion implantation is performed above the aforementioned second conductivity type well region to form a second conductivity type heavily doped base region within the second conductivity type well region. The second conductivity type heavily doped base region includes a second conductivity type first heavily doped base region and a second conductivity type second heavily doped base region. The second conductivity type first heavily doped base region is adjacent to the junction of the second conductivity type pillar and the first conductivity type pillar. The second conductivity type second heavily doped base region corresponds to the doped region of the last filled second conductivity type pillar.

[0045] First conductivity type impurity ions are implanted above the aforementioned second conductivity type well region to form a first conductivity type source region within the second conductivity type well region. The first conductivity type source region corresponds to the second conductivity type first heavily doped base region. After the first conductivity type source region is formed, a second conductivity type first heavily doped region is formed based on the second conductivity type first heavily doped base region. The second conductivity type first heavily doped region covers the bottom of the first conductivity type source region.

[0046] The front-side cell process also includes:

[0047] A trench is etched on the epitaxial substrate of the first conductivity type to form a polysilicon trench after the trench is etched. The polysilicon trench spans the base region of the first conductivity type and the well region of the second conductivity type. The bottom of the polysilicon trench is located above the bottom of the source region of the first conductivity type. The outer wall of the polysilicon trench of the well region of the second conductivity type is in contact with the source region of the first conductivity type and the first heavily doped region of the second conductivity type.

[0048] A first oxide isolation layer is prepared, which covers the base region of the first conductivity type and the inner wall of the polysilicon trench;

[0049] Polysilicon deposition is performed over the aforementioned first conductivity type base region to obtain gate conductive polysilicon, the gate conductive polysilicon including a horizontal polysilicon body corresponding to the first conductivity type base region and a vertical polysilicon body at least filled in a polysilicon trench, wherein the vertical polysilicon body is in contact with the horizontal polysilicon body.

[0050] A second oxide isolation layer is prepared, which covers the outer surfaces of the horizontal polycrystalline silicon body and the vertical polycrystalline silicon body.

[0051] A source contact hole is prepared, and metal deposition is performed after the source contact hole is prepared to obtain at least a source metal filling the source contact hole. The source metal is in ohmic contact with the source region of the first conductivity type, the first heavily doped region of the second conductivity type, and the second heavily doped region of the second conductivity type.

[0052] Advantages of the present invention: By configuring the second conductivity type pillar in a variable doping form, a peak electric field can be introduced through the second conductivity type pillar. At this time, a portion of the avalanche current will be "shunted" through this path to achieve the purpose of dispersing heat. That is, the variable doping form of the second conductivity type pillar can disperse the avalanche current. Due to the dispersion of the avalanche current, heat can be dispersed, thereby improving the avalanche tolerance of the superjunction power device.

[0053] Furthermore, since the gate conductive polysilicon includes a vertical polysilicon body, the threshold voltage of the power device can be kept largely unaffected when it is turned on. However, when an avalanche occurs, the current has a shorter current path and lower on-resistance when the current passes through the forward parasitic NPN loop. Attached Figure Description

[0054] Figures 1-9 This is a cross-sectional view of an embodiment of the specific fabrication process of the power device of the present invention, wherein,

[0055] Figure 1 This is a cross-sectional view of one embodiment of the present invention after an N-type drift base region is formed on a substrate.

[0056] Figure 2 This is a cross-sectional view of one embodiment of the present invention after etching to obtain P-pillar trenches.

[0057] Figure 3 This is a cross-sectional view of one embodiment of the present invention after the first extensional filling in the P-pillar groove.

[0058] Figure 4 This is a cross-sectional view of one embodiment of the present invention after three extensional fillings in the P-pillar groove.

[0059] Figure 5 This is a cross-sectional view of one embodiment of the N-type epitaxial base layer prepared according to the present invention.

[0060] Figure 6 This is a cross-sectional view of one embodiment of the P+ heavily doped base region prepared according to the present invention.

[0061] Figure 7 This is a cross-sectional view of one embodiment of the present invention after obtaining the N+ source region.

[0062] Figure 8 This is a cross-sectional view of one embodiment of the gate-conductive polycrystalline silicon prepared according to the present invention.

[0063] Figure 9 This is a cross-sectional view of the source metal prepared according to the present invention.

[0064] Explanation of reference numerals in the attached figures: 1-substrate, 2-N-type drift base region, 3-first P-pillar doped region, 4-second P-pillar doped region, 5-third P-pillar doped region, 6-heavily doped N-pillar region, 7-N-type epitaxial base layer, 8-P-type well region, 9-P+ first heavily doped base region, 10-P+ second heavily doped base region, 11-N+ source region, 12-gate conductive polysilicon, 13-second oxide isolation layer, 14-source metal, 15-P-pillar trench, 16-N-pillar, 17-P+ first heavily doped region, 18-first oxide isolation layer, 19-P+ second heavily doped region, 20-N-type base region, 21-horizontal polysilicon body, 22-vertical polysilicon section. Detailed Implementation

[0065] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0066] To effectively improve the avalanche energy of superjunction devices, for power devices that can enhance the avalanche tolerance of superjunction structures, taking N-type as an example, in one embodiment of the present invention, the power device includes an active region fabricated in the central region of a semiconductor substrate and a termination protection zone located around the active region, wherein the termination protection zone surrounds the active region.

[0067] Within the active region, there are frontal cell units and superjunction units, wherein the superjunction unit includes a plurality of N-pillars 16 and P-pillars that are alternately distributed in sequence.

[0068] For any P-pillar, there are several P-pillar doped regions that are sequentially epitaxially filled in the P-pillar trench 15, wherein the doping concentration of the P-pillar doped regions increases sequentially according to the order of epitaxial filling in the P-pillar trench 15.

[0069] Specifically, the semiconductor substrate can be made of commonly used semiconductor materials, such as silicon, and the material of the semiconductor substrate can be selected as needed. A power device generally includes an active region and a termination protection region. The active region is generally located in the central region of the semiconductor substrate, and the termination protection region surrounds the active region. The active region serves as the functional area of ​​the power device, and the termination protection region can be used to improve the voltage withstand capability of the active region.

[0070] For superjunction power devices, the active region of the superjunction power device must include front-side cell units and superjunction units. Superjunction units are used to form the superjunction structure of the superjunction power device, and front-side cell units are used to form the front-side cells of the superjunction power device. When the first conductivity type is N-type, the second conductivity type is P-type. In this case, the superjunction unit generally includes several alternately distributed N-pillars 16 and P-pillars. The arrangement direction of the N-pillars 16 and P-pillars is generally along the active region towards the terminal protection zone. The alternating arrangement of the N-pillars 16 and P-pillars within the superjunction unit is consistent with existing superjunction structures.

[0071] To improve avalanche tolerance, in one embodiment of the present invention, the P-pillars within the superjunction unit are configured with variable doping. To achieve this variable doping, P-pillar trenches 15 are first prepared during P-pillar fabrication. Then, P-type material is epitaxially grown within the P-pillar trenches 15. After multiple epitaxial growths, the P-pillars are obtained. Each epitaxial growth fills a P-pillar doped region, resulting in a P-pillar containing several P-pillar doped regions. Specifically, the doping concentration of the P-pillar doped regions obtained from each epitaxial growth fill is different. Preferably, the doping concentration of the P-pillar doped regions increases sequentially according to the order of epitaxial growth within and outside the P-pillar trenches 15.

[0072] Figure 9 The illustration shows an embodiment of preparing a P-pillar by three epitaxial fillings within a P-pillar trench 15. In this case, the P-pillar includes a first P-pillar doped region 3, a second P-pillar doped region 4, and a third P-pillar doped region 5. The first P-pillar doped region 3, the second P-pillar doped region 4, and the third P-pillar doped region 5 are prepared by epitaxial filling in sequence, thereby obtaining that the doping concentrations of the first P-pillar doped region 3, the second P-pillar doped region 4, and the third P-pillar doped region 5 increase sequentially.

[0073] In specific implementation, the P-pillar doped regions within the P-pillars are columnar after the last filling, and U-shaped before the last filling. That is, the first P-pillar doped region 3 and the second P-pillar doped region 4 are both U-shaped, while the third P-pillar doped region 5 is columnar. When the first P-pillar doped region 3 is formed through epitaxial filling, it covers the sidewalls and bottom wall of the P-pillar trench 15. The second P-pillar doped region 4 covers the first P-pillar doped region 3, and the third P-pillar doped region 5 is enveloped by the second P-pillar doped region 4. Figures 4-9 The diagram only shows the P-pillar trench 15 and a partial form of the P-pillars, that is, only the distribution diagram of the first P-pillar doped region 3, the second P-pillar doped region 4, and the third P-pillar doped region 5 located in the P-pillar trench 15 is shown. For details, please refer to the above description.

[0074] For superjunction power devices, the avalanche withstand capability is mainly affected by two factors. First, during the UIS process of the superjunction, the parasitic NPN transistor near the P-type well region 8 of the MOS structure turns on, causing the avalanche current to become uncontrolled, which may lead to device failure. Second, during the UIS process of the superjunction, the avalanche current is too concentrated, resulting in heat that cannot be dissipated, which may also affect device failure.

[0075] Under the premise of these two influencing factors, when the P-pillar is configured in a variable doping form, a peak electric field can be introduced through the P-pillar when an avalanche occurs. At this time, a portion of the avalanche current will be "shunted" through this path to achieve the purpose of dispersing heat. That is, the variable doping form of the P-pillar can disperse the avalanche current. Due to the dispersion of the avalanche current, heat can be dispersed, thereby improving the avalanche tolerance of the superjunction power device.

[0076] In one embodiment of the present invention, the semiconductor substrate includes an N-type substrate 1 and an N-type drift region located on the substrate, wherein,

[0077] N-type drift region adjacent to substrate 1;

[0078] The superjunction unit is fabricated in the N-type drift region, and the bottom of the N-pillar 16 and the bottom of the P-pillar are located at the junction of the N-type drift region and the substrate 1.

[0079] A positive cell unit consists of several positive cells arranged in parallel;

[0080] On the cross-section of the power device, for any front cell, there is an N-type base region 20 and P-type well regions 8 symmetrically distributed on both sides of the N-type base region 20, wherein the N-type base region 20 is located above an N-pillar 16 and in contact with the N-pillar 16, and the width of the N-type base region 20 is smaller than the width of the N-pillar 16.

[0081] The width of the P-type well region 8 is greater than the width of the P-pillar, and the P-type well region 8 is in contact with the corresponding N-pillar 16 and the P-pillar.

[0082] As explained above, when the conductivity type of the semiconductor substrate is N-type, the conductivity type of substrate 1 is also N-type. The N-type drift region is located on substrate 1 and is adjacent to substrate 1. The doping concentration of the N-type drift region is generally lower than the doping concentration of substrate 1. Generally, the superjunction unit is fabricated within the N-type drift region, and the bottom of the N-pillar 16 and the bottom of the P-pillar are located at the junction of the N-type drift region and substrate 1. The active region typically includes several parallel-distributed active cells. Figure 9 In the middle, the frontal cell includes an N-type base region 20, and P-type well regions 8 are arranged on both sides of the N-type base region 20, with the P-type well regions 8 in contact with the N-type base region 20. Figure 9 The diagram only shows the N-type base region 20 and the P-type well region 8 connected to one end of the N-type base region 20. Since the P-type well regions 8 are symmetrically distributed on both sides, the symmetrical distribution of the P-type well regions 8 on both sides of the N-type base region 20 can be referred to... Figure 9 The illustration.

[0083] Figure 9 In this configuration, an N-type base region 20 corresponds to and contacts an N-pillar 16; the N-type base region 20 is located above the N-pillar 16, and "above" refers to the direction from the substrate 1 towards the N-type drift region. Furthermore, the width of the N-type base region 20 is smaller than the width of the N-pillar 16, and the width of the N-type base region 20 is the direction from the N-type base region 20 towards the P-type well region 8. Figure 9In this process, the width of the P-type well region 8 is greater than the width of the P-pillar. Therefore, when the junction of the P-type well region 8 and the N-type base region 20 is projected into the N-pillar 16, it will fall within the N-pillar 16. Simultaneously, the P-type well region 8 will contact both the N-pillar 16 and the P-pillar. Based on the correspondence between the P-type well region 8, the N-type base region 20, the N-pillar 16, and the P-pillar, frontal cells can be effectively fabricated, improving the stability and reliability of the process.

[0084] In one embodiment of the present invention, when the front-side cell is a planar cell, an N+ source region 11 and a P+ heavily doped region are provided within the P-type well region 8, wherein...

[0085] The P+ heavily doped region includes a first P+ heavily doped region 17 and a second P+ heavily doped region 19.

[0086] The first P+ doped region 17 covers the bottom of the N+ source region 11;

[0087] The P+ second doped region 19 corresponds exactly to the P-pillar doped region filled by the last epitaxial growth, and the width of the P+ second doped region 19 is not greater than the width of the P-pillar doped region filled by the last epitaxial growth.

[0088] The N+ source region 11, the first P+ doped region 17, and the second P+ doped region 19 are all in ohmic contact with the source metal 14.

[0089] Figure 9 In one embodiment, an N+ source region 11, a first heavily doped P+ region 17, and a second heavily doped P+ region 19 are simultaneously disposed within a P-type well region 8. In the figure, the N+ source region 11 extends perpendicularly from the surface of the P-type well region 8 towards the substrate 1. The junction depth of the N+ source region 11 is less than the thickness of the P-type well region 8. The first heavily doped P+ region 17 is located below the N+ source region 11, covering the bottom of the N+ source region 11. The first heavily doped P+ region 17 is adjacent to the N-type base region 8 within the P-type well region 8.

[0090] The parasitic NPN transistor located near the P-type well region 8 of the MOS structure mentioned above specifically refers to the NPN transistor composed of the N-type base region 20, the P-type well region 8, and the N+ source region 11.

[0091] The first P+ doped region 17 covers the bottom of the N+ source region 11. When electrons flow to the N+ source region 11, holes pass through the high-concentration P+ first doped region 17 below. If there were no high-concentration region based on the first P+ doped region 17, the resistivity would increase, causing the on-state voltage drop to rise and the parasitic NPN transistor to turn on. In other words, by using the first P+ doped region 17 in conjunction with the N+ source region 11, the conduction of the parasitic NPN transistor can be effectively suppressed. The second P+ doped region 19 mainly corresponds to the high concentration at the center of the P-pillar. At this time, during avalanche, a spike electric field and a short current path are formed, achieving the purpose of current shunting.

[0092] The P+ second doped region 19 and the P+ first doped region 17 have the same junction depth within the P-type well region 8. The P+ second doped region 19 and the P+ first doped region 17 can generally be prepared by the same process step. The P+ second doped region 19 is separated from the P+ first doped region 17 by the P-type well region 8. The P+ second doped region 19 corresponds to the P-pillar doped region filled by the last epitaxial layer. As explained above, the P-pillar doped region filled by the last epitaxial layer is the third P-pillar doped region 5. At this time, the P+ second doped region 19 corresponds to the third P-pillar doped region 5, but the width of the P+ second doped region 19 is not greater than the width of the third P-pillar doped region 5.

[0093] In order to form the source electrode of the power device, a source metal 14 needs to be fabricated above the N-type drift region. The source metal 14 is in ohmic contact with the N+ source region 11, the first P+ heavily doped region 17 and the second P+ heavily doped region 19. The source electrode of the power device can be formed using the source metal 14.

[0094] In one embodiment of the present invention, a gate conductive polysilicon 12 is disposed above the N-type base region 20, wherein,

[0095] The gate conductive polysilicon 12 includes a horizontal polysilicon body 21 and vertical polysilicon bodies 22 symmetrically distributed at both ends of the horizontal polysilicon body 21. The vertical polysilicon bodies 22 and the horizontal polysilicon body 21 are connected as one unit.

[0096] The horizontal polycrystalline silicon body 21 corresponds to the N-type base region 20, and the horizontal polycrystalline silicon body 21 is insulated from the N-type base region 20.

[0097] The vertical polysilicon body 22 extends into the P-type well region 8. The vertical polysilicon body 22 is insulated from the P-type well region 8, the N+ source region 11, and the P+ first heavily doped region 17. The bottom of the vertical polysilicon body 22 is located above the bottom of the N+ source region 11.

[0098] The vertical polysilicon body 22 and the horizontal polysilicon body 21 are insulated from the source metal 14.

[0099] Figure 8 and Figure 9 The figure shows an embodiment of the gate conductive polysilicon 12. The gate conductive polysilicon 12 includes a horizontal polysilicon body 21 and a vertical polysilicon body 22. The vertical polysilicon body 22 is symmetrically distributed at both ends of the horizontal polysilicon body 21 and is interconnected with the horizontal polysilicon body 21 to form a whole. The horizontal polysilicon body 21 and the vertical polysilicon body 22 can generally be prepared by the same process step. The specific process preparation will be described in the subsequent preparation process.

[0100] The horizontal polycrystalline silicon mass 21 corresponds directly to the N-type base region 20, and the horizontal polycrystalline silicon mass 21 is parallel to the N-type base region 20. Figure 8 and Figure 9 The intermediate-level polycrystalline silicon body 21 is insulated from the N-type base region 20 by a first oxide isolation layer 18. The first oxide isolation layer 18 is generally a silicon dioxide layer, which can be formed by existing commonly used gate oxide processes.

[0101] In order for the vertical polysilicon body 22 to extend into the P-type well region 8, trench etching is generally required within the P-type well region 8 to obtain a polysilicon trench. During the fabrication of the horizontal polysilicon body 21, polysilicon is simultaneously filled into the polysilicon trench, thus forming the vertical polysilicon body 22. Therefore, the bottom of the vertical polysilicon body 22 is located below the horizontal polysilicon body 21, and the top of the vertical polysilicon body 21 is flush with the upper surface of the horizontal polysilicon body 21.

[0102] The first oxide isolation layer 18 also covers the inner wall of the polysilicon trench. The vertical polysilicon body 22 is isolated from the inner wall of the polysilicon trench through the first oxide isolation layer 18. At this time, the vertical polysilicon body 22 can be insulated from the P-type well region 8, the N+ source region 11, and the P+ first heavily doped region 17 through the first oxide isolation layer 18. Figure 8 and Figure 9 In the middle, the bottom of the vertical polysilicon body 22 is located above the bottom of the N+ source region 11, but the N+ source region 11 and the P+ first heavily doped region 17 are in contact with the outer wall of the corresponding adjacent polysilicon trench.

[0103] Figure 8 and Figure 9 In the process of preparing the vertical polycrystalline silicon body 22, an oxidation process is required again to prepare the second oxide isolation layer 13. The second oxide isolation layer 13 can generally be a silicon dioxide layer. The second oxide isolation layer 13 can be used to cover the corresponding outer surfaces of the vertical polycrystalline silicon body 22 and the horizontal polycrystalline silicon body 21.

[0104] In practice, since the gate conductive polysilicon 12 includes a vertical polysilicon body 22, the threshold voltage of the power device when it is turned on can be basically unaffected by the vertical polysilicon body 12. However, when an avalanche occurs, the current has a shorter current path and a lower on-resistance when the current passes through the forward parasitic NPN transistor circuit.

[0105] In one embodiment of the present invention, an N-pillar heavily doped region 6 is provided within the N-pillar 16, wherein,

[0106] The heavily doped N-pillar region 6 extends vertically from the top of the N-pillar 16 to the bottom of the N-pillar 16, and the width of the N-pillar doped region 6 is smaller than the width of the N-pillar 16.

[0107] The bottom of the N-pillar heavily doped region 6 is located above the bottom of the last epitaxially filled P-pillar doped region.

[0108] Figures 5-9 The illustration shows an embodiment in which a heavily doped N-pillar region 6 is prepared within the N-pillar 16. When the heavily doped N-pillar region 6 is provided within the N-pillar 16, the charge balance between the P-pillar and the N-pillar 16 can be achieved by the heavily doped N-pillar region 6, reducing the degradation of the breakdown voltage of the superjunction structure, and partially reducing the resistance during forward conduction. It has a good trade-off characteristic, that is, it can ensure the forward conduction characteristics and breakdown voltage of the power device.

[0109] For a superjunction structure, the ideal situation is a perfect charge balance between the N-pillar 16 and the P-pillar, with equal widths on both sides, opposite conductivity types, and equal charge amounts. After contact, a complete depletion region is formed to achieve a good withstand voltage effect. However, since the present invention increases the doping concentration of the P-pillar, especially at the center of the P-pillar, the charge amount of the P-pillar is relatively high. Therefore, after setting the heavily doped N-pillar region 6 in the N-pillar 16, the doping method in the corresponding region of the N-pillar 16 can be increased to achieve charge balance with the P-pillar that forms a variable doping structure as much as possible.

[0110] The aforementioned superjunction power device can be prepared through the following process steps. Specifically, the preparation method for a power device that can improve the avalanche tolerance of a superjunction structure includes:

[0111] An N-type semiconductor substrate is provided, the semiconductor substrate comprising an N-type substrate 1 and an N-type drift base region 2 located on the substrate 1;

[0112] The above-mentioned N-type drift base region 2 is subjected to trench etching to form P-pillar trench 15 after trench etching. The P-pillar trench 15 extends vertically towards the substrate 1 within the N-type drift base region 2.

[0113] P-type material is epitaxially grown in the above-mentioned P-pillar trench 15 to form a P-pillar after the epitaxial growth fills the P-pillar trench 15. After the P-pillar is formed, N-pillars 16 are formed based on the N-type drift base region 2, which are alternately distributed with the P-pillars. The doping concentration of the P-pillar doped region increases sequentially according to the order of epitaxial growth filling in the P-pillar trench 15.

[0114] An N-type material is epitaxially grown on the aforementioned N-type drift base region 2 to form an N-type epitaxial base layer 7 after epitaxy, and an N-type drift region is formed based on the N-type epitaxial base layer 7 and the N-type drift base region 2.

[0115] The front cell process is performed in the aforementioned N-type drift region to prepare front cell units and terminal protection zones, with the terminal protection zones surrounding the front cell units.

[0116] Figure 1 The image shows an embodiment of a semiconductor substrate. In a specific implementation, the N-type drift base region 2 can be prepared on the substrate 1 by means of epitaxy or other methods. The doping concentration of the N-type drift base region 2 is generally less than the doping concentration of the substrate 1.

[0117] To fabricate the P-pillar of the superjunction unit, trench etching is required in the N-type drift base region 2 to obtain the P-pillar trench 15 after etching. Figure 2 In this design, the depth of the P-pillar trench 15 is consistent with the thickness of the N-type drift base region 2, meaning that the bottom of the P-pillar trench 15 is the substrate 1. The width and distribution of the P-pillar trench 15 can be selected as needed to fabricate the required N-pillar 16 and P-pillar.

[0118] After etching to obtain the P-pillar trench 15, epitaxy of the P-type material is performed. Figure 3 The diagram shows the situation after the first epitaxial filling. At this point, the first P-pillar doped region 3 can be prepared, and the first P-pillar doped region 3 covers the inner wall of the P-pillar trench 15. Figure 4 The image shows the situation after the second and third epitaxial filling. At this point, the second P-pillar doped region 4 and the third P-pillar doped region 5 can be prepared sequentially. As explained above, the doping concentration of the first P-pillar doped region 3, the second P-pillar doped region 4, and the third P-pillar doped region 5 increases sequentially. Of course, in specific implementations, the number of filling cycles can be selected as needed to ensure that the doping concentration increases sequentially and P-pillars are prepared; these will not be listed here. After the P-pillars are formed, N-pillars 16 can be formed using the N-type drift base region 2, as shown... Figure 4 As shown.

[0119] In practice, when it is necessary to prepare an N-pillar heavily doped region 6, N-type impurity ion implantation should be performed after the P-pillar is prepared, with the goal of forming an N-pillar heavily doped region 6 after implantation. Figure 4As shown. After preparing the N-pillar heavily doped region 6, the surface of the N-type drift base region 2 is polished and ground flat, followed by rapid thermal annealing to push the junction to ensure good contact at the PN junction interface and repair lattice surface damage. Generally, the rapid annealing temperature can be 850℃-1150℃, and the rapid annealing temperature and process can be selected according to the actual process.

[0120] Following the above process, N-type material is epitaxially grown on the N-type drift base region 2 to form an N-type epitaxial base layer 7. The N-type epitaxial base layer 7 covers the N-type drift region 2. At this time, the N-type epitaxial base layer 7 is in contact with the top of the N-pillar 16 and the P-pillar, as shown below. Figure 5 As shown, the N-type epitaxial base layer 7 and the N-type drift base region 2 can together form the N-type drift region. After the N-type drift region is formed, a frontal cell process can be performed to prepare the frontal cell unit.

[0121] In one embodiment of the present invention, the frontal cell process includes:

[0122] P-type impurity ion implantation is performed above the N-type epitaxial base layer 7 to form a P-type well region 8 and an N-type base region 20 for separating the P-type well region 8 after the P-type impurity ion implantation. The N-type base region 20 is located above and in contact with an N-pillar 16, and the width of the N-type base region 20 is smaller than the width of the N-pillar 16.

[0123] The width of the P-type well region 8 is greater than the width of the P-pillar, and the P-type well region 8 is in contact with the corresponding N-pillar 16 and the P-pillar.

[0124] Based on the aforementioned N-type base region 20 and P-type well region 8, the frontal structure of the frontal cell is prepared.

[0125] Specifically, after obtaining the N-type epitaxial substrate 7, P-type impurity ion implantation can be performed using techniques commonly used in this field to form a P-type well region 8. The formation of the N-type base region 8, N-type base region 20, and P-type well region 8 using the N-type epitaxial substrate 7 can be found in [reference needed]. Figure 6 And as explained above. Generally, the depth of the P-type well region 8 is consistent with the thickness of the N-type epitaxial base layer 7.

[0126] Furthermore, the frontal cell process also includes:

[0127] P-type impurity ion implantation is performed above the aforementioned P-type well region 8 to form a P+ heavily doped base region within the P-type well region 8. The P+ heavily doped base region includes a first P+ heavily doped base region 9 and a second P+ heavily doped base region 10. The first P+ heavily doped base region 9 is adjacent to the junction of the P-pillar and the N-pillar 16, and the second P+ heavily doped base region 10 corresponds to the last filled P-pillar doped region.

[0128] N-type impurity ions are implanted above the aforementioned P-type well region 8 to form an N+ source region 11 within the P-type well region 8. The N+ source region 11 corresponds to the P+ first heavily doped base region 9. After the N+ source region 11 is formed, a P+ first heavily doped region 17 is formed based on the P+ first heavily doped base region 9. The P+ first heavily doped region 17 covers the bottom of the N+ source region 11.

[0129] After obtaining the P-type well region 8, a second P-type impurity ion implantation can be performed on the P-type well region 8. At this time, a P+ heavily doped base region can be obtained. Figure 6 The illustration shows an embodiment of a P+ heavily doped base region including a first P+ heavily doped base region 9 and a second P+ heavily doped base region 10, wherein the first P+ heavily doped base region 9 and the second P+ heavily doped base region 10 have the same junction depth.

[0130] Subsequently, N-type impurity ion implantation is performed above the P-type well region 8 to prepare the N+ source region 11. Specifically, the implanted region of the N+ source region 11 is the P+ first heavily doped base region 9. After preparing the N+ source region 11, the P+ first heavily doped base region 9 can be used to form the P+ first heavily doped region 17. The P+ first heavily doped region 17 is located below the N+ source region 11 and covers the bottom of the N+ source region 11, as shown below. Figure 7 As shown, the first P+ doped region 17 is formed by the first P+ doped base region 9, which has not formed the N+ source region 11.

[0131] In one embodiment of the present invention, the frontal cell process further includes:

[0132] The N-type epitaxial substrate 7 is etched with trenches to form a polysilicon trench after the trench is etched. The polysilicon trench spans the N-type base region 20 and the P-type well region 8. The bottom of the polysilicon trench is located above the bottom of the N+ source region 11, and the polysilicon trench is located on the outer wall of the P-type well region 8 and contacts the N+ source region 11 and the P+ first heavily doped region 17.

[0133] A first oxide isolation layer 18 is prepared, which covers the N-type base region 20 and the inner wall of the polysilicon trench;

[0134] Polysilicon deposition is performed over the aforementioned N-type base region 20 to obtain gate conductive polysilicon 12, wherein the gate conductive polysilicon 12 includes a horizontal polysilicon body 21 corresponding to the N-type base region 20 and a vertical polysilicon body 22 at least filled in the polysilicon trench, wherein the vertical polysilicon body 22 is in contact with the horizontal polysilicon body 21.

[0135] A second oxide isolation layer 13 is prepared, which covers the outer surfaces of the horizontal polysilicon body 21 and the vertical polysilicon body 22.

[0136] A source contact hole is prepared, and metal deposition is performed after the source contact hole is prepared to obtain at least a source metal 14 filling the source contact hole. The source metal 14 is in ohmic contact with the N+ source region 11, the first P+ doped region 17 and the second P+ doped region 19.

[0137] To fabricate the aforementioned gate-conductive polysilicon 12, trench etching is performed on the N-type epitaxial substrate 7 to form polysilicon trenches. A portion of the formed polysilicon trench is located within the N-type base region 20, and another portion is located within the P-type well region 8 adjacent to the N-type base region 20. The portion of the polysilicon trench within the P-type well region 8 is significantly larger than the portion within the N-type base region 20. The trench opening is located on the surfaces of the N-type base region 20 and the P-type well region 8, and the trench bottom needs to be located above the bottom of the N+ source region 11. The polysilicon trench is located on the outer wall of the P-type well region 8, in contact with the N+ source region 11 and the first heavily doped P+ region 17. At this time, the polysilicon trench is not in contact with the second heavily doped P+ base region 10.

[0138] After etching to obtain the polysilicon trench, a first oxide isolation layer 18 is prepared using a process commonly used in this technical field. The first oxide isolation layer 18 at least covers the N-type base region 20 and the inner wall of the polysilicon trench. The details of the first oxide isolation layer 18 can be found in the above description.

[0139] After the first oxide isolation layer 18 is prepared, polysilicon deposition is performed to prepare gate conductive polysilicon 12. As can be seen from the above description, the gate conductive polysilicon 12 includes a horizontal polysilicon body 21 and a vertical polysilicon body 22. The horizontal polysilicon body 21 corresponds to the N-type base region 20, and the vertical polysilicon body 22 fills the polysilicon trench. The vertical polysilicon body 22 can be insulated and isolated from the N+ source region 11, the P+ first heavily doped base region 17, the P-type well region 8 and the N-type base region 20 through the first oxide isolation layer 18.

[0140] After preparing the gate conductive polysilicon 12, a second oxide isolation layer 13 is prepared. Using the second oxide isolation layer 13, the gate conductive polysilicon 12 can be coated using the first oxide isolation layer 18 and the second oxide isolation layer 13, as shown below. Figure 8 As shown.

[0141] After the second oxide isolation layer 13 is prepared, an insulating dielectric layer is deposited, covering the N-type drift region. Then, contact hole etching is performed to prepare the source contact hole. The source contact hole generally corresponds to the P-type well region 8. The source contact hole extends from the surface of the P-type well region 8 towards the P-pillar direction. The source contact hole etches away part of the N+ source region 11, the first heavily doped P+ region 17, and the second heavily doped P+ base region 19, using the remaining portion of the second heavily doped P+ base region 19 to form the second heavily doped P+ region 19.

[0142] After the source contact hole is prepared, metal deposition can be performed using common techniques in this technical field. At this point, source metal 14 can be prepared. Source metal 14 will cover the insulating dielectric layer and also fill the source contact hole. Using the source metal 14 filled in the source contact hole, ohmic contact can be achieved between source metal 14 and the N+ source region 11, the first heavily doped P+ region 17, and the second heavily doped P+ region 19. Figure 9 As shown.

[0143] In addition, during metal deposition, gate metal can generally be prepared. The gate metal makes a 12-ohm contact with the gate conductive polysilicon to form the gate electrode or gate of a power device. When forming the gate electrode of a power device, the power device is generally a MOSFET type device; when forming the gate of a power device, the power device is generally an IGBT device.

[0144] The above provides one embodiment of the active region fabrication method. The front-side cell units and superjunction units within the active region can also be fabricated using other processes. Of course, the specific details of the terminal protection zone and the back-side structure can be selected and determined according to actual needs. For the steps not specified above, commonly used process conditions and procedures in this technical field can be adopted. The specific implementation of each step should meet the specific fabrication process requirements, and will not be elaborated further here.

Claims

1. A power device that can improve the avalanche tolerance of superjunction structures, characterized in that, The power device includes an active region fabricated in the central region of a semiconductor substrate and a termination protection zone located on the outer ring of the active region, wherein the termination protection zone surrounds the active region. Within the active region, there are front-side cell units and superjunction units. The superjunction unit includes a plurality of alternating first conductivity type pillars and second conductivity type pillars. The conductivity type of the first conductivity type pillar is consistent with the conductivity type of the semiconductor substrate. For any second conductivity type pillar, there are several second conductivity type pillar doped regions that are sequentially epitaxially filled in the second conductivity type pillar trench, wherein the doping concentration of the second conductivity type pillar doped regions increases sequentially according to the order of epitaxial filling in the second conductivity type pillar trench. A heavily doped region of the first conductivity type is formed within the first conductivity type pillar, wherein... The heavily doped region of the first conductivity type pillar extends vertically from the top of the first conductivity type pillar to the bottom of the first conductivity type pillar, and the width of the doped region of the first conductivity type pillar is smaller than the width of the first conductivity type pillar. The bottom of the heavily doped region of the first conductivity type pillar is located above the bottom of the doped region of the second conductivity type pillar filled by the last epitaxial growth.

2. The power device for improving the avalanche tolerance of superjunction structures according to claim 1, characterized in that: The semiconductor substrate includes a substrate of a first conductivity type and a drift region of the first conductivity type located on the substrate, wherein, The first conductivity type drift region is adjacent to the substrate; The superjunction unit is fabricated in the first conductivity type drift region, and the bottom of the first conductivity type pillar and the bottom of the second conductivity type pillar are located at the junction of the first conductivity type drift region and the substrate; A positive cell unit consists of several positive cells arranged in parallel; On the cross-section of the power device, for any front cell, there is a first conductivity type base region and a second conductivity type well region symmetrically distributed on both sides of the first conductivity type base region. The first conductivity type base region is located above the first conductivity type pillar and in contact with the first conductivity type pillar. The width of the first conductivity type base region is smaller than the width of the first conductivity type pillar. The width of the second conductivity type well region is greater than the width of the second conductivity type pillar, and the second conductivity type well region is in contact with the corresponding first conductivity type pillar and the second conductivity type pillar.

3. The power device for improving the avalanche tolerance of superjunction structures according to claim 2, characterized in that, When the front-side cell adopts a planar cell, a first conductivity type source region and a second conductivity type heavily doped region are set within the second conductivity type well region, wherein... The second conductivity type heavily doped region includes a second conductivity type first heavily doped region and a second conductivity type second heavily doped region; The first heavily doped region of the second conductivity type covers the bottom of the source region of the first conductivity type. The second doped region of the second conductivity type corresponds exactly to the pillar doped region of the second conductivity type filled by the last epitaxial layer, and the width of the second doped region of the second conductivity type is not greater than the width of the pillar doped region of the second conductivity type filled by the last epitaxial layer. The source region of the first conductivity type, the first heavily doped region of the second conductivity type, and the second heavily doped region of the second conductivity type are all in ohmic contact with the source metal.

4. The power device for improving avalanche tolerance of superjunction structures according to claim 3, characterized in that, A gate-conducting polysilicon is disposed above the base region of the first conductivity type, wherein, The gate conductive polysilicon includes a horizontal polysilicon body and vertical polysilicon bodies symmetrically distributed at both ends of the horizontal polysilicon body, and the vertical polysilicon bodies and the horizontal polysilicon bodies are connected as one unit. The horizontal polycrystalline silicon body corresponds directly to the base region of the first conductivity type, and the horizontal polycrystalline silicon body is insulated from the base region of the first conductivity type. A vertical polysilicon body extends into the second conductivity type well region. The vertical polysilicon body is insulated and isolated from the second conductivity type well region, the first conductivity type source region, and the second conductivity type first heavily doped region. The bottom of the vertical polysilicon body is located above the bottom of the first conductivity type source region. The vertical and horizontal polycrystalline silicon bodies are insulated from the source metal.

5. The power device for improving the avalanche tolerance of superjunction structures according to any one of claims 1 to 4, characterized in that: The doped region of the second conductivity type column within the second conductivity type column is columnar in the last filling and U-shaped in the second conductivity type column before the last filling.

6. A method for fabricating a power device with improved avalanche tolerance of a superjunction structure, characterized in that, The method for preparing a power device according to any one of claims 1 to 5, wherein the preparation method comprises: A semiconductor substrate of a first conductivity type is provided, the semiconductor substrate comprising a substrate of the first conductivity type and a drift base region of the first conductivity type located on the substrate; The first conductivity type drift base region is subjected to trench etching to form a second conductivity type pillar trench after trench etching. The second conductivity type pillar trench extends vertically towards the substrate within the first conductivity type drift base region. Epitaxy of a second type of material is performed within the aforementioned second type of conductive type pillar trench to form a second type of conductive type pillar after the epitaxy fills the second type of conductive type pillar trench. After the second type of conductive type pillar is formed, a first type of conductive type pillar is formed based on the first type of conductive type drift base region, which is alternately distributed with the second type of conductive type pillar. The doping concentration of the doped region of the second type of conductive type pillar increases sequentially according to the order of epitaxial filling within and outside the second type of conductive type pillar trench. Epitaxy of a first conductivity type material is performed on the aforementioned first conductivity type drift base region to form a first conductivity type epitaxial base layer after epitaxy, and a first conductivity type drift region is formed based on the first conductivity type epitaxial base layer and the first conductivity type drift base region; A front cell process is performed in the aforementioned first conductivity type drift region to prepare a front cell unit and a terminal protection zone, the terminal protection zone surrounding the front cell unit.

7. The method for fabricating a power device with improved avalanche tolerance of a superjunction structure according to claim 6, characterized in that, The front-side cell process includes: Second conductivity type impurity ion implantation is performed above the first conductivity type epitaxial substrate to form a second conductivity type well region and a first conductivity type base region for separating the second conductivity type well region after the second conductivity type impurity ion implantation. The first conductivity type base region is located above the first conductivity type pillar and is in contact with the first conductivity type pillar. The width of the first conductivity type base region is smaller than the width of the first conductivity type pillar. The width of the second conductivity type well region is greater than the width of the second conductivity type pillar, and the second conductivity type well region is in contact with the corresponding first conductivity type pillar and the second conductivity type pillar; Based on the first conductivity type base region and the second conductivity type well region described above, the front structure of the front cell is prepared.

8. The method for fabricating a power device with improved avalanche tolerance of a superjunction structure according to claim 7, characterized in that, The front-side cell process also includes: Second conductivity type impurity ion implantation is performed above the aforementioned second conductivity type well region to form a second conductivity type heavily doped base region within the second conductivity type well region. The second conductivity type heavily doped base region includes a second conductivity type first heavily doped base region and a second conductivity type second heavily doped base region. The second conductivity type first heavily doped base region is adjacent to the junction of the second conductivity type pillar and the first conductivity type pillar. The second conductivity type second heavily doped base region corresponds to the doped region of the last filled second conductivity type pillar. First conductivity type impurity ions are implanted above the aforementioned second conductivity type well region to form a first conductivity type source region within the second conductivity type well region. The first conductivity type source region corresponds to the second conductivity type first heavily doped base region. After the first conductivity type source region is formed, a second conductivity type first heavily doped region is formed based on the second conductivity type first heavily doped base region. The second conductivity type first heavily doped region covers the bottom of the first conductivity type source region.

9. The method for fabricating a power device with improved avalanche tolerance of a superjunction structure according to claim 8, characterized in that, The front-side cell process also includes: A trench is etched on the epitaxial substrate of the first conductivity type to form a polysilicon trench after the trench is etched. The polysilicon trench spans the base region of the first conductivity type and the well region of the second conductivity type. The bottom of the polysilicon trench is located above the bottom of the source region of the first conductivity type. The outer wall of the polysilicon trench of the well region of the second conductivity type is in contact with the source region of the first conductivity type and the first heavily doped region of the second conductivity type. A first oxide isolation layer is prepared, which covers the base region of the first conductivity type and the inner wall of the polysilicon trench; Polysilicon deposition is performed over the aforementioned first conductivity type base region to obtain gate conductive polysilicon, the gate conductive polysilicon including a horizontal polysilicon body corresponding to the first conductivity type base region and a vertical polysilicon body at least filled in a polysilicon trench, wherein the vertical polysilicon body is in contact with the horizontal polysilicon body. A second oxide isolation layer is prepared, which covers the outer surfaces of the horizontal polysilicon body and the vertical polysilicon body. A source contact hole is prepared, and metal deposition is performed after the source contact hole is prepared to obtain at least a source metal filling the source contact hole. The source metal is in ohmic contact with the source region of the first conductivity type, the first heavily doped region of the second conductivity type, and the second heavily doped region of the second conductivity type.

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