Control device and method of operation thereof
By dividing the control device into regions and optimizing the distribution of voltage and clock signals, the problem of increased power consumption of the control device in non-high-speed states is solved, achieving a balance between high speed and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-02
- Publication Date
- 2026-04-10
AI Technical Summary
Existing control devices still provide the operating voltage required by internal components even in non-high-speed states, resulting in increased power consumption and making it difficult to achieve a balance between high speed and low power consumption.
By configuring a first region, a second region, and a third region, and providing corresponding operating voltages and clock signals in different modes, the number of components in the first region is less than that in the second region, and the number of components in the second region is less than that in the third region. The distribution of voltage and clock signals is controlled by a power management controller and a switching unit.
It achieves both high speed and low power consumption in different modes, and effectively saves power consumption through area division and voltage clock signal optimization.
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Figure CN117434858B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a control device, and in particular, to a control device with high speed and low power consumption and an operating method thereof. BACKGROUND
[0002] Generally, a control device (e.g. a microcontroller) is designed with more internal elements and provides operating voltages required by the internal elements, so that the control device has high speed function. However, since the control device is not always in high speed state, and the control device still provides the operating voltages required by the internal elements in non-high speed state, it will increase the power consumption of the control device.
[0003] Therefore, how to effectively design the control device with high speed and low power consumption is an important issue. SUMMARY
[0004] The present invention provides a control device and an operating method thereof, so as to achieve the effect of high speed and low power consumption.
[0005] The present invention provides a control device, comprising a first region, a second region and a third region. The first region comprises a first periphery unit, a first storage unit and a first control unit. The second region comprises a second periphery unit, a first access unit, a second storage unit and a second control unit. The third region comprises an operation unit, a third periphery unit, a second access unit, a third storage unit and a third control unit. In an ultra-low power mode, a first operating voltage and a first clock signal are provided to the first region. In a low power mode, the first operating voltage and the first clock signal are provided to the first region, and the first operating voltage and a second clock signal are provided to the second region. In a high speed mode, the first operating voltage and the first clock signal are provided to the first region, and the first operating voltage and a third clock signal are provided to the third region, or the first operating voltage and the first clock signal are provided to the first region, the first operating voltage and the second clock signal are provided to the second region, and the first operating voltage and the third clock signal are provided to the third region.
[0006] The present application provides an operating method of a control device, comprising the following steps. A first region is provided, comprising a first peripheral unit, a first storage unit and a first control unit. A second region is provided, comprising a second peripheral unit, a first access unit, a second storage unit and a second control unit. A third region is provided, comprising an operation unit, a third peripheral unit, a second access unit, a third storage unit and a third control unit. In an ultra-low power mode, a first working voltage and a first clock signal are provided to the first region. In a low power mode, the first working voltage and the first clock signal are provided to the first region and the first working voltage and a second clock signal are provided to the second region. In a high speed mode, the first working voltage and the first clock signal are provided to the first region and the first working voltage and a third clock signal are provided to the third region, or the first working voltage and the first clock signal are provided to the first region, the first working voltage and the second clock signal are provided to the second region and the first working voltage and the third clock signal are provided to the third region.
[0007] The control device and the operating method thereof disclosed by the present application, by configuring the first region, the second region and the third region, the number of elements of the first region is less than that of the second region, the number of elements of the second region is less than that of the third region, and according to different modes (i.e. the ultra-low power mode, the low power mode and the high speed mode), corresponding working voltage and clock signal are provided to the first region, the second region and / or the third region. In this way, the effect of high speed and low power consumption is achieved. BRIEF DESCRIPTION OF DRAWINGS
[0008] Figure 1 A schematic diagram of a control device according to an embodiment of the present application.
[0009] Figure 2 A detailed schematic diagram of the first region, the second region and the third region of a control device according to an embodiment of the present application.
[0010] Figure 3 A flowchart of an operating method of a control device according to an embodiment of the present application.
[0011] Figure 4 A flowchart of an operating method of a control device according to another embodiment of the present application.
[0012] Figure 5 A flowchart of an operating method of a control device according to another embodiment of the present application.
[0013] REFERENCE NUMERALS
[0014] 100: control device
[0015] 110: first region
[0016] 111: first peripheral unit
[0017] 112: first storage unit
[0018] 113: first control unit
[0019] 120: second area
[0020] 121: second peripheral unit
[0021] 122: first access unit
[0022] 123: second storage unit
[0023] 124: second control unit
[0024] 130: third area
[0025] 131: arithmetic unit
[0026] 132: third peripheral unit
[0027] 133: second access unit
[0028] 134: third storage unit
[0029] 135: third control unit
[0030] 140: power management controller
[0031] 150: first voltage converter
[0032] 160: second voltage converter
[0033] 170: third voltage converter
[0034] 202: low power analog to digital converter
[0035] 204, 236: pulse width modulator
[0036] 206: low power timer
[0037] 208, 220: digital to analog converter
[0038] 210: operational amplifier
[0039] 212, 224: timer
[0040] 214, 226: internal integrated circuit
[0041] 216, 230: universal asynchronous receiver transmitter
[0042] 218, 234: serial peripheral interface
[0043] 222: analog to digital converter
[0044] 228: general-purpose serial bus
[0045] 232: analog comparator
[0046] 238: quadrature encoder interface
[0047] 240: watchdog timer
[0048] 242: USB Type-C connector system software interface
[0049] 244: real-time clock
[0050] 246: internal high-speed oscillator
[0051] 248: internal medium-speed oscillator
[0052] 250: general-purpose input / output port
[0053] 252: system management and controller
[0054] 254: scratchpad
[0055] 256: low-power memory
[0056] 258: first memory
[0057] 260: second memory
[0058] 262: cache memory
[0059] 264: flash memory
[0060] 266, 272, 288: power and clock management controller
[0061] 268, 274, 290: interrupt and wake-up controller
[0062] 270: low-power direct memory access controller
[0063] 276: central processing unit
[0064] 278: first memory controller
[0065] 280: second memory controller
[0066] 282: peripheral direct memory access controller
[0067] 284: cache memory controller
[0068] 286: flash memory controller
[0069] 292: bus
[0070] SW1: first switch unit
[0071] SW2: second switch unit
[0072] SW3: third switch unit
[0073] SW4: fourth switch unit
[0074] SW5: fifth switch unit
[0075] VIN: power supply voltage
[0076] V1: first operating voltage
[0077] V2: second operating voltage
[0078] V3: third operating voltage
[0079] S302-S312, S402-S404, S502-S506: steps DETAILED DESCRIPTION
[0080] In the following enumerated embodiments, the same reference numbers will be used to represent the same or similar elements or components.
[0081] Figure 1 is a schematic diagram of a control device according to an embodiment of the present application. In this embodiment, the control device 100 can be a micro controller unit (MCU), or a microprocessor, or other suitable controller, but embodiments of the present application are not limited thereto. Please refer to Figure 1 , the control device 100 can include a first region 110, a second region 120, and a third region 130.
[0082] The first region 110 can include a first periphery unit 111, a first storage unit 112, and a first control unit 113. The second region 120 can include a second periphery unit 121, a first access unit 122, a second storage unit 123, and a second control unit 124. The third region 130 can include an operation unit 131, a third periphery unit 132, a second access unit 133, a third storage unit 134, and a third control unit 135.
[0083] In this embodiment, the number of elements of the first periphery unit 111 is less than the number of elements of the second periphery unit 121, and the number of elements of the second periphery unit 121 is less than the number of elements of the third periphery unit 132.
[0084] As shown in FIG. 1, the control device 100 can include a first switch unit SW1, a second switch unit SW2, a third switch unit SW3, a fourth switch unit SW4, and a fifth switch unit SW5. Figure 2As shown, in some embodiments, the first peripheral unit 111 may include a low-power analog-to-digital converter (LPADC) 202, a pulse width modulator (PWM) 204, and a low-power timer (LPTimer) 206. Figure 2 As shown, in some embodiments, the second peripheral unit 121 may include a digital-to-analog converter (DAC) 208, an operational amplifier (OPA) 210, a timer 212, an inter-integrated circuit (I2C) 214, a universal asynchronous receiver / transmitter (UART) 216, and a serial peripheral interface (SPI) 218.
[0085] like Figure 2 As shown, in some embodiments, the third peripheral unit 132 may include a digital-to-analog converter (DAC) 220, an analog-to-digital converter (ADC) 222, a timer 224, an internal integrated circuit (I2C) 226, a universal series bus (USB) 228, a universal asynchronous transceiver (UART) 230, an analog comparator (ACMP) 232, a serial peripheral interface (SPI) 234, a pulse width modulator (PWM) 236, a quadrature encoder interface (QEI) 238, a watchdog timer (WDT) 240, a USB Type-C connector system software interface (UCSI) 242, a real-time clock (RTC) 244, an internal high-speed oscillator (HIRC) 246, an internal medium-speed oscillator (MIRC) 248, a general-purpose input / output (GPIO) port 250, and a system management and control unit (global). miscellaneous control register,GMISC)252.
[0086] Furthermore, the size of the first storage unit 112 is, for example, smaller than the size of the second storage unit 123, and the size of the second storage unit 122 is, for example, smaller than the size of the third storage unit 134. Figure 2 As shown, in some embodiments, the first storage unit 112 may include a temporary register 254. For example... Figure 2 As shown, in some embodiments, the second storage unit 123 may include a low-power memory 256, such as low-power static random access memory (LPSRAM). Figure 2 As shown, in some embodiments, the third storage unit 134 may include a first memory 258, a second memory 260, a cache RAM 262, and a flash memory 264. In this embodiment, the first memory 258 and the second memory 260 are, for example, static random access memory (SRAM).
[0087] like Figure 2 As shown, in some embodiments, the first control unit 113 may include a power and clock management controller (PCMC) 266 and a wake-up and interrupt controller (WIC) 268. Figure 2 As shown, in some embodiments, the first access unit 122 may include a low-power direct memory access (LPDMA) controller 270. For example... Figure 2 As shown, in some embodiments, the second control unit 124 may include a power and clock management controller 272 and an interrupt and wake-up controller 274.
[0088] like Figure 2 As shown, in some embodiments, the arithmetic unit 131 may include a central processing unit (CPU) 276. For example... Figure 2As shown, in some embodiments, the second access unit 133 can include a first memory controller 278, a second memory controller 280, a peripheral direct memory access controller (PDMA) 282, a cache controller 284, and a flash memory controller (FMC) 286. In the present embodiment, the first memory controller 278 and the second memory controller 280 are static random access memory controllers (SRAM controllers), for example. In addition, the first memory controller 278 is electrically connected to the first memory 258. The second memory controller 280 is electrically connected to the second memory 260. The cache controller 284 is electrically connected to the cache memory 262 and the central processing unit 276. The flash memory controller 286 is electrically connected to the flash memory 264.
[0089] As shown, in some embodiments, the third control unit 135 can include a power and clock management controller 288 and an interrupt and wake-up controller 290. Figure 2
[0090] In the present embodiment, the low-power analog-to-digital converter 202, the pulse width modulator 204, the low-power timer 206, the digital-to-analog converter 208, the operational amplifier 210, the timer 212, the internal integrated circuit 214, the universal asynchronous receiver-transmitter 216, the serial peripheral interface 218, the digital-to-analog converter 220, the analog-to-digital converter 222, the timer 224, the internal integrated circuit 226, the universal serial bus 228, the universal asynchronous receiver-transmitter 230, the analog comparator 232, the serial peripheral interface 234, the pulse width modulator 236, the quadrature encoder interface 238, the watchdog timer 240, the USB Type-C connector system software interface 242, the real-time clock 244, the general-purpose input-output port 250, the system management and controller 252, the low-power direct memory access controller 270, the central processing unit 276, the first memory controller 278, the second memory controller 280, the peripheral direct memory access controller 282, the cache controller 284, and the flash memory controller 286 are electrically connected to a bus 292 so as to communicate through the bus 292. In the present embodiment, the bus 292 can include an advanced peripheral bus (APB) and an advanced high-performance bus (AHB), but embodiments of the present application are not limited thereto.
[0091] In this embodiment, the control device 100 further comprises a power management controller 140, a first voltage converter 150, a first switch unit SW1, a second switch unit SW2 and a third switch unit SW3.
[0092] The power management controller 140 receives the power supply voltage VIN and generates a first control signal and a second control signal to the first control unit 113. The first voltage converter 150 receives the power supply voltage VIN to generate a first operating voltage VI.
[0093] The first switch unit SW1 is electrically connected to the first voltage converter 150, the power management controller 140 and the first region 110 (i.e. the first peripheral unit 111, the first storage unit 112 and the first control unit 113). The first switch unit SW1 can determine whether to provide the first operating voltage VI to the first region 110 according to the first control signal. For example, when the first switch unit SW1 receives the first control signal such as a high logic level, the first switch unit SW1 is turned on to provide the first operating voltage VI to the first region 110. Further, the first operating voltage VI can be provided to the first peripheral unit 111, the first storage unit 112 and the first control unit 113 of the first region 110 so that the first peripheral unit 111, the first storage unit 112 and the first control unit 113 can operate normally. When the first switch unit SW1 receives the first control signal such as a low logic level, the first switch unit SW1 is not turned on so that the first operating voltage VI is not provided to the first region 110.
[0094] The second switch unit SW2 is electrically connected to the first voltage converter 150, the first control unit 113 and the second control unit 124. In addition, the second switch unit 120 is further electrically connected to the second peripheral unit 121, the first access unit 122 and the second storage unit 123. The second switch unit SW2 can determine whether to provide the first operating voltage VI to the second region 120 according to the control of the first control unit 113 and / or the second control unit 124. For example, when the second switch unit SW2 receives a control signal such as a high logic level provided by the first control unit 113 and / or the second control unit 124, the second switch unit SW2 is turned on to provide the first operating voltage VI to the second region 120. Further, the first operating voltage VI can be provided to the second peripheral unit 121, the first access unit 122, the second storage unit 123 and the second control unit 124 of the second region 120, so that the second peripheral unit 121, the first access unit 122, the second storage unit 123 and the second control unit 124 can operate normally. When the second switch unit SW2 receives a control signal such as a low logic level provided by the first control unit 113 and / or the second control unit 124, the second switch unit SW2 is not turned on, and thus the first operating voltage VI is not provided to the second region 120.
[0095] The third switch unit SW3 is electrically connected to the first voltage converter 150, the second control unit 124 and the third control unit 135. In addition, the third switch unit SW3 is further electrically connected to the operation unit 131, the third peripheral unit 132, the second access unit 133 and the third storage unit 134. The third switch unit SW3 can determine whether to provide the first operating voltage VI to the third region 130 according to the control of the second control unit 124 and / or the third control unit 135. For example, when the third switch unit SW3 receives a control signal such as a high logic level provided by the second control unit 124 and / or the third control unit 135, the third switch unit SW3 is turned on to provide the first operating voltage VI to the third region 130.
[0096] Further, the first operating voltage VI can be provided to the operation unit 131, the third peripheral unit 132, the second access unit 133, the third storage unit 134 and the third control unit 135 of the third region 130, so that the operation unit 131, the third peripheral unit 132, the second access unit 133, the third storage unit 134 and the third control unit 135 can operate normally. When the third switch unit SW3 receives a control signal such as a low logic level provided by the second control unit 124 and / or the third control unit 135, the third switch unit SW3 is not turned on, and thus the first operating voltage VI is not provided to the third region 130.
[0097] In operation of the control device 100, in the ultra-low power mode, the power management controller 140 generates a first control signal of a high logic level to the first switch unit SWl, so that the first switch unit SWl is turned on to provide the first operating voltage Vl to the first region 110. Also, the power management controller 140 provides a second control signal of a high logic level to the first control unit 113 of the first region 110, so that the power and clock management controller 266 of the first control unit 113 can provide a first clock signal to the first region 110 to provide the operating clock required by the first peripheral unit 111.
[0098] In the low power mode, the first control unit 113 (e.g. the power and clock management controller 266) can generate a control signal of a high logic level, for example, to the second switch unit SW2, so that the second switch unit SW2 is turned on to provide the first operating voltage Vl to the second region 120. In addition, the first control unit 113 (e.g. the interrupt and wake-up controller 268) can provide a wake-up signal to the second control unit 124 (e.g. the power and clock management controller 272) to wake up the second region 120. Then, the second control unit 124 (e.g. the power and clock management controller 272) can generate a second clock signal to the second region 120 according to the wake-up signal to provide the operating clock required by the second peripheral unit 121 and the first access unit 122, so that the second region 120 can complete the required task, for example, the first access unit 122 (i.e. the low power direct memory access controller 270) helps to move data to the second storage unit 123 (i.e. the low power memory 256).
[0099] Then, after the second region 120 completes the required task, the first control unit 113 and / or the second control unit 124 can generate a control signal of a low logic level, for example, to the second switch unit SW2, so that the second switch unit SW2 is not turned on to shut down the operation of the second region 120. In this way, the power consumption of the control device 100 can be effectively saved.
[0100] In the high speed mode, the second control unit 124 (e.g., the power and clock management controller 272) can generate a control signal, e.g., a high logic level, to the third switch unit SW3 so that the third switch unit SW3 is turned on to provide the first operating voltage V1 to the third region 130. In addition, the second control unit 124 (e.g., the interrupt and wake-up controller 274) can provide a wake-up signal to the third control unit 135 so as to wake up the third region 130. Then, the third control unit 135 can generate a third clock signal to the third region 130 according to the wake-up signal to provide the operating clock required by the operation unit 131, the third peripheral unit 132 and the second access unit 133 so that the third region 130 can complete the required task, e.g., the operation operation using the operation unit 131 (i.e., the central processing unit 276).
[0101] Then, after the third region 130 completes the required task, the second control unit 124 and / or the third control unit 135 can generate a control signal, e.g., a low logic level, to the third switch unit SW3 so that the third switch unit SW3 is not turned on to shut down the operation of the third region 130. In this way, the power consumption of the control device 100 can be effectively saved.
[0102] In addition, in some embodiments, the control device 100 further comprises a second voltage converter 160, a fourth switch unit SW4, a third voltage converter 170 and a fifth switch unit SW5.
[0103] The second voltage converter 160 is electrically connected to the first voltage converter 150. The second voltage converter 160 can receive the first operating voltage V1 to generate a second operating voltage V2. The fourth switch unit SW4 is electrically connected to the second voltage converter 160, the first control unit 113 and the second control unit 124. In addition, the fourth switch unit SW4 is further electrically connected to the second storage unit 123. The fourth switch unit SW4 can determine whether to provide the second operating voltage V2 to the second storage unit 123 and the second control unit 124 of the second region 120 according to the control of the first control unit 113 and / or the second control unit 124.
[0104] For example, when the fourth switch unit SW4 receives a control signal, such as a high logic level, provided by the first control unit 113 and / or the second control unit 124, the fourth switch unit SW4 is turned on to provide the second operating voltage V2 to the second storage unit 123 and the second control unit 124 of the second region 120, so that the second storage unit 123 and the second control unit 124 operate normally. When the fourth switch unit SW4 receives a control signal, such as a low logic level, provided by the first control unit 113 and / or the second control unit 124, the fourth switch unit SW4 is not turned on, and thus the second operating voltage V2 is not provided to the second storage unit 123 and the second control unit 124 of the second region 120.
[0105] The third voltage converter 170 is electrically connected to the first voltage converter 150. The third voltage converter 170 can receive the first operating voltage VI to generate a third operating voltage V3. The fifth switch unit SW5 is electrically connected to the third voltage converter 170, the second control unit 124 and the third control unit 135. In addition, the fifth switch unit SW5 is further electrically connected to the third storage unit 134. The fifth switch unit SW5 can determine whether to provide the third operating voltage V3 to the third storage unit 134 and the third control unit 135 of the third region 130 according to the control of the second control unit 124 and / or the third control unit 135.
[0106] For example, when the fifth switch unit SW5 receives a control signal, such as a high logic level, provided by the second control unit 124 and / or the third control unit 135, the fifth switch unit SW5 is turned on to provide the third operating voltage V3 to the third storage unit 134 and the third control unit 135 of the third region 130, so that the third storage unit 134 and the third control unit 135 operate normally. When the fifth switch unit SW5 receives a control signal, such as a low logic level, provided by the second control unit 124 and / or the third control unit 135, the fifth switch unit SW5 is not turned on, and thus the third operating voltage V3 is not provided to the third storage unit 134 and the second control unit 135 of the third region 130.
[0107] In the embodiment, the second operating voltage V2 and the third operating voltage V3 are, for example, less than the first operating voltage VI. In addition, the second operating voltage V2 and the third operating voltage V3 can be the same or different. Furthermore, the second voltage converter 160 and the third voltage converter 170 are, for example, low dropout regulators (LDOs).
[0108] In operation of the control device 100, in the ultra-low power mode, the power management controller 140 generates a first control signal of high logic level to the first switch unit SWl, so that the first switch unit SWl is turned on to provide the first operating voltage Vl to the first region 110. Also, the power management controller 140 provides a second control signal of high logic level to the first control unit 113 of the first region 110, so that the power and clock management controller 266 of the first control unit 113 can provide a first clock signal to the first region 110 to provide the operating clock required by the first peripheral unit 111.
[0109] Then, the first control unit 113 (e.g. the power and clock management controller 266) can provide a control signal to the fourth switch unit SW2, so that the fourth switch unit SW2 is turned on to provide the second operating voltage V2 to the second storage unit 123 and the second control unit 124 of the second region 120. In addition, the first control unit 113 (e.g. the interrupt and wake-up controller 268) can provide a wake-up signal to the second control unit 124, so as to wake up the second control unit 124, so that the second region 120 is in the standby state.
[0110] Then, the second control unit 124 (e.g. the power and clock management controller 272) can provide a control signal to the fifth switch unit SW5, so that the fifth switch unit SW5 is turned on to provide the third operating voltage V3 to the third storage unit 134 and the third control unit 135 of the third region 130. In addition, the second control unit 124 (e.g. the interrupt and wake-up controller 274) can provide a wake-up signal to the third control unit 135, so as to wake up the third control unit 135, so that the third region 130 is in the standby state. In this way, the wake-up time of the second region 120 and / or the third region 130 can be effectively saved, and the power consumption of the control device 100 can be saved.
[0111] In the low power mode, the first control unit 113 (e.g., power and clock management controller 266) and / or the second control unit 124 (e.g., power and clock management controller 272) can generate a control signal of, for example, a high logic level to the second switch unit SW2 and a control signal of, for example, a low logic level to the fourth switch unit SW4, so that the second switch unit SW2 is turned on and the fourth switch unit SW4 is turned off to provide the first operating voltage VI to the second region 120. In addition, the first control unit 113 (e.g., interrupt and wake-up controller 268) and / or the second control unit 124 (e.g., interrupt and wake-up controller 274) can provide a wake-up signal to the second control unit 124 (e.g., power and clock management controller 272). Then, the second control unit 124 (e.g., power and clock management controller 272) can generate a second clock signal to the second region 120 according to the wake-up signal to provide the operating clock required by the second peripheral unit 121 and the first access unit 122, so that the second region 120 can complete the required task.
[0112] Then, after the second region 120 completes the required task, the first control unit 113 and / or the second control unit 124 can generate a control signal of, for example, a low logic level to the second switch unit SW2 and a control signal of, for example, a high logic level to the fourth switch unit SW4, so that the second switch unit SW2 is turned off and the fourth switch unit SW4 is turned on to provide the second operating voltage V2 to the second storage unit 123 and the second control unit 124 of the second region 120, thereby maintaining the operation of the second storage unit 123 and the second control unit 124. In this way, the power consumption of the control device 100 can be effectively saved.
[0113] In the high-speed mode, in one embodiment, the second control unit 124 (e.g., the power and clock management controller 272) and / or the third control unit 135 (e.g., the power and clock management controller 288) can generate a control signal of, for example, a high logic level to the third switch unit SW3 and a control signal of, for example, a low logic level to the fifth switch unit SW5, so that the third switch unit SW3 is turned on and the fifth switch unit SW5 is turned off, to provide the first operating voltage VI to the third region 130. In addition, the second control unit 124 (e.g., the interrupt and wake-up controller 274) and / or the third control unit 124 (e.g., the interrupt and wake-up controller 290) can provide a wake-up signal to the third control unit 135 (e.g., the power and clock management controller 290). Then, the third control unit 135 (e.g., the power and clock management controller 290) can generate a third clock signal to the third region 130 according to the wake-up signal, to provide the operating clock required by the operation unit 131, the third peripheral unit 132 and the second access unit 133, so that the third region 130 can complete the required task. At this time, the first region 110, the second region 120 and the third region 130 are all in operation.
[0114] Then, after the third region 130 completes the required task, the second control unit 124 and / or the third control unit 135 can generate a control signal of, for example, a low logic level to the third switch unit SW3 and a control signal of, for example, a high logic level to the fifth switch unit SW5, so that the third switch unit SW3 is turned off and the fifth switch unit SW5 is turned on, to provide the third operating voltage V3 to the third storage unit 134 and the third control unit 135 of the third region 130, to maintain the operation of the third storage unit 134 and the third control unit 135. At this time, the first region 110 and the second region 120 are still in operation. In this way, the power consumption of the control device 100 can be effectively saved.
[0115] In the high-speed mode, in one embodiment, the first control unit 113 can communicate with the second control unit 124, or the first control unit 113 communicates with the third control unit 135 through the second control unit 124, so that the second control unit 124 (e.g., power and clock management controller 272) and / or the third control unit 135 (e.g., power and clock management controller 288) can generate a control signal of, for example, high logic level to the third switch unit SW3 and a control signal of, for example, low logic level to the fifth switch unit SW5, then the third switch unit SW3 is turned on and the fifth switch unit SW5 is turned off, to provide the first operating voltage VI to the third region 130. In addition, the second control unit 124 (e.g., interrupt and wake-up controller 274) and / or the third control unit 124 (e.g., interrupt and wake-up controller 290) can provide a wake-up signal to the third control unit 135 (e.g., power and clock management controller 290). Then, the third control unit 135 (e.g., power and clock management controller 290) can generate a third clock signal to the third region 130 according to the wake-up signal, to provide the operating clock required by the operation unit 131, the third peripheral unit 132 and the second access unit 133, so that the third region 130 can complete the required task. At this time, the first region 110 and the third region 130 are both in operation, but the second region 120 is not in operation.
[0116] Then, after the third region 130 completes the required task, the second control unit 124 and / or the third control unit 135 can generate a control signal of, for example, low logic level to the third switch unit SW3 and a control signal of, for example, high logic level to the fifth switch unit SW5, so that the third switch unit SW3 is turned off and the fifth switch unit SW5 is turned on, to provide the third operating voltage V3 to the third storage unit 134 and the third control unit 135 of the third region 130, thereby maintaining the operation of the third storage unit 134 and the third control unit 135. At this time, the first region 110 still continues to operate. In this way, the power consumption of the control device 100 can be effectively saved.
[0117] In some embodiments, the logic in the third region 130 can be designed with a multi-vth technology, and its operating voltage is between the overdrive voltage and the normal voltage. The logic in the second region 120 can be designed with a high-vth technology, and its operating voltage is between the normal voltage and the low voltage. The logic in the first region 110 can be designed with an extreme high-vth technology, and its operating voltage is between the low voltage and the extreme low voltage.
[0118] In addition, in the present embodiment, the elements in the first region 110 (i.e., the first peripheral elements 111, the first storage unit 112, and the first control unit 113), the elements in the second region 120 (i.e., the second peripheral elements 121, the first access unit 122, the second storage unit 123, and the second control unit 124), and the elements in the third region 130 (i.e., the operation unit 131, the third peripheral elements 132, the second access unit 133, the third storage unit 134, and the third control unit 135) use the same voltage (i.e., the first operating voltage V1), so as to avoid the need for inserting a voltage level converter, and the operating time increase caused by the voltage level converter can be saved.
[0119] Figure 3 A flowchart of an operating method of a control device according to an embodiment of the present application is shown in FIG. 3. In step S302, a first region is provided, including a first peripheral unit, a first storage unit, and a first control unit. In step S304, a second region is provided, including a second peripheral unit, a first access unit, a second storage unit, and a second control unit. In step S306, a third region is provided, including an operation unit, a third peripheral unit, a second access unit, a third storage unit, and a third control unit. In step S308, in an ultra-low power mode, the first operating voltage and the first clock signal are provided to the first region.
[0120] In step S310, in a low power mode, the first operating voltage and the first clock signal are provided to the first region, and the first operating voltage and the second clock signal are provided to the second region. In step S312, in a high speed mode, the first operating voltage and the first clock signal are provided to the first region, and the first operating voltage and the third clock signal are provided to the third region, or the first operating voltage and the first clock signal are provided to the first region, the first operating voltage and the second clock signal are provided to the second region, and the first operating voltage and the third clock signal are provided to the third region. In the present embodiment, the number of elements of the first peripheral unit is less than the number of elements of the second peripheral unit, and the number of elements of the second peripheral unit is less than the number of elements of the third peripheral unit. In addition, the size of the first storage unit is less than the size of the second storage unit, and the size of the second storage unit is less than the size of the third storage unit.
[0121] Figure 4 A flowchart of an operating method of a control device according to another embodiment of the present application is shown in FIG. 4. In the present embodiment, steps S302-S312 are the same as or similar to steps S302-S312 of the embodiment shown in FIG. 3, and can refer to the description of steps S302-S312 of the embodiment shown in FIG. 3. Figure 3 Figure 3 The specific implementation of this embodiment will not be described in detail here. In step S402, the power management controller receives the power supply voltage and generates a first control signal and a second control signal for the first control unit. In step S404, the power supply voltage is received by the first voltage converter to generate a first operating voltage.
[0122] In this embodiment, step S308 further includes, in a low-power mode, providing a first operating voltage to the first region via a first switching unit and providing a first clock signal to the first region via a first control unit, based on the first control signal and the second control signal. Step S310 further includes, in a low-power mode, providing a first operating voltage to the first region via a first switching unit and providing a first clock signal to the first region via a first control unit, based on the first control signal and the second control signal; and, based on the control of the first control unit and / or the second control unit, providing a first operating voltage to the second region via a second switching unit and providing a second clock signal to the second region via a second control unit.
[0123] Step S312 further includes, in high-speed mode, providing a first operating voltage to the first region and providing a first clock signal to the first region through a first switching unit according to a first control signal and a second control signal; providing a first operating voltage to the second region through a second switching unit and providing a second clock signal to the second region according to the control of the first control unit and / or the second control unit; and providing a first operating voltage to the third region through a third switching unit and providing a third clock signal to the third region according to the control of the second control unit and / or the third control unit.
[0124] Figure 5 This is a flowchart of an operation method of a control device according to another embodiment of the present invention. In this embodiment, steps S302-S312, S402-S404 and... Figure 4 Steps S302 to S312 and S402 to S404 are the same or similar, and can be referred to. Figure 4 The specific implementation of this embodiment will not be described in detail here. In step S502, a first operating voltage is received through a second voltage converter to generate a second operating voltage. In step S504, a first operating voltage is received through a third voltage converter to generate a third operating voltage. In step S506, in ultra-low power mode, a second operating voltage is provided to a second storage unit and a second control unit in the second region, and a third operating voltage is provided to a third storage unit and a third control unit in the third region, wherein the second and third operating voltages are lower than the first operating voltage.
[0125] In addition, the step S506 further comprises providing the second operating voltage to the second storage unit and the second control unit in the second region through the fourth switch unit according to the control of the first control unit and / or the second control unit, and providing the third operating voltage to the third storage unit and the third control unit in the third region through the fifth switch unit according to the control of the second control unit and / or the third control unit in the ultra-low power mode. The step S312 further comprises providing the first operating voltage to the first region through the first switch unit and providing the first clock signal to the first region through the first control unit according to the first control signal and the second control signal in the high speed mode, and providing the first operating voltage to the third region through the third switch unit and providing the third clock signal to the third region through the third control unit according to the control of the second control unit and / or the third control unit.
[0126] In summary, the control device and the operating method thereof disclosed in the present application, by configuring the first region, the second region and the third region, the number of elements in the first region is less than the number of elements in the second region, the number of elements in the second region is less than the number of elements in the third region, and according to different modes (i.e. the ultra-low power mode, the low power mode and the high speed mode), corresponding operating voltage and clock signal are provided to the first region, the second region and / or the third region. In this way, the effect of high speed and low power consumption is achieved.
[0127] Although the present application is disclosed with the above-mentioned embodiments, it is not intended to limit the scope of the present application, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be defined by the appended claims.
Claims
1. A control device characterized by comprising: The first region includes a first peripheral unit, a first storage unit and a first control unit; The second region includes a second peripheral unit, a first access unit, a second storage unit and a second control unit; and The third region includes a computing unit, a third peripheral unit, a second access unit, a third storage unit and a third control unit; In an ultra-low power mode, a first operating voltage and a first clock signal are provided to the first region; In a low power mode, the first operating voltage and the first clock signal are provided to the first region, and the first operating voltage and a second clock signal are provided to the second region; In a high speed mode, the first operating voltage and the first clock signal are provided to the first region, and the first operating voltage and a third clock signal are provided to the third region, or the first operating voltage and the first clock signal are provided to the first region, the first operating voltage and the second clock signal are provided to the second region, and the first operating voltage and the third clock signal are provided to the third region. The first peripheral unit includes a low power analog-to-digital converter, a pulse width modulator and a low power timer, the first storage unit includes a register, and the first control unit includes a power and clock management controller and an interrupt and wake-up controller.
2. The control device of claim 1, wherein The second peripheral unit includes a digital-to-analog converter, an operational amplifier, a timer, an internal integrated circuit, a universal asynchronous receiver-transmitter, a serial peripheral interface, the first access unit includes a low power direct memory access controller, the second storage unit includes a low power memory, and the second control unit includes a power and clock management controller and an interrupt and wake-up controller.
3. The control device of claim 1, wherein The computing unit includes a central processing unit, the third peripheral unit includes a digital-to-analog converter, an analog-to-digital converter, a timer, an internal integrated circuit, a universal serial bus, a universal asynchronous receiver-transmitter, an analog comparator, a serial peripheral interface, a pulse width modulator, a quadrature encoder interface, a watchdog timer, a USB Type-C connector system software interface, a real-time clock, an internal high-speed oscillator, an internal medium-speed oscillator, a general purpose input / output port, a system management and controller, the second access unit includes a first memory controller, a second memory controller, a peripheral direct memory access controller, a cache memory controller, a flash memory controller, the third storage unit includes a first memory, a second memory, a cache memory, a flash memory, and the third control unit includes a power and clock management controller and an interrupt and wake-up controller.
4. The control device of claim 1, wherein Further including:
5. The control device of claim 1, wherein A power management controller receives a power voltage, generates a first control signal, and generates a second control signal to the first control unit; A first voltage converter receives the power voltage to generate the first operating voltage; A first switch unit determines whether to provide the first operating voltage to the first region according to the first control signal; A second switching unit, based on the control of the first control unit and / or the second control unit, determines whether to provide the first operating voltage to the second region; as well as A third switching unit, based on the control of the second control unit and / or the third control unit, determines whether to provide the first operating voltage to the third region.
6. The control device of claim 5, wherein In this ultra-low power mode, a second operating voltage is provided to the second storage unit and the second control unit in the second region, and a third operating voltage is provided to the third storage unit and the third control unit in the third region; The second and third operating voltages are both less than the first operating voltage.
7. The control device of claim 6, wherein Including: A second voltage converter receives the first operating voltage to generate the second operating voltage; A fourth switching unit, based on the control of the first control unit and / or the second control unit, determines whether to provide the second operating voltage to the second storage unit and the second control unit in the second region; A third voltage converter receives the first operating voltage to generate the third operating voltage; and A fifth switching unit, based on the control of the second control unit and / or the third control unit, determines whether to provide the third operating voltage to the third region.
8. The control device of claim 1, wherein The size of the first storage unit is smaller than the size of the second storage unit, and the size of the second storage unit is smaller than the size of the third storage unit.
9. A method of operating a control device, characterized by, include: A first area is provided, including a first peripheral unit, a first storage unit and a first control unit; A second area is provided, including a second peripheral unit, a first access unit, a second storage unit and a second control unit; A third area is provided, including a computing unit, a third peripheral unit, a second access unit, a third storage unit and a third control unit; In an ultra-low power mode, a first operating voltage and a first clock signal are provided to the first region; In a low-power mode, the first operating voltage and the first clock signal are provided to the first region, and the first operating voltage and a second clock signal are provided to the second region; as well as In a high-speed mode, the first operating voltage and the first clock signal are provided to the first region and the first operating voltage and the third clock signal are provided to the third region, or the first operating voltage and the first clock signal are provided to the first region, the first operating voltage and the second clock signal are provided to the second region and the first operating voltage and the third clock signal are provided to the third region.
10. The method of operating a control device of claim 9, wherein, The number of components in the first peripheral unit is less than the number of components in the second peripheral unit, and the number of components in the second peripheral unit is less than the number of components in the third peripheral unit.
Citation Information
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