Wide voltage range voltage comparison circuit and wide voltage range voltage processing circuit
By combining the input withstand voltage module, clamp withstand voltage module, and mirror module, and utilizing components such as high-voltage LDMOS transistors and Zener diodes, the BV breakdown problem of the comparator under a wide range of voltage signals is solved, achieving withstand voltage protection and current amplification, expanding the voltage input range, and outputting high and low potentials.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI AWINIC TECH CO LTD
- Filing Date
- 2023-11-27
- Publication Date
- 2026-06-26
AI Technical Summary
Existing comparators struggle to handle wide voltage range signals from 0 to 40V due to the risk of BV breakdown.
It adopts a combined structure of input withstand voltage module, clamp withstand voltage module, mirror module and inverting output module, and uses high voltage P-type and N-type LDMOS transistors and Zener diodes to achieve withstand voltage protection and current mirror amplification, expand the voltage input range and output high and low potentials.
It enables effective comparison of a wide range of voltage signals, improves the circuit's withstand voltage performance, avoids BV breakdown, and has a simple structure with a small chip area.
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Figure CN117434996B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and in particular to a voltage comparison circuit and a voltage processing circuit with a wide voltage range. Background Technology
[0002] A comparator is an integrated circuit that compares the magnitudes of two analog voltages. Comparison involves comparing two or more data items to determine if they are equal, or to determine their relative magnitudes and order of arrangement. A comparator is a circuit that compares an analog voltage signal to a reference voltage.
[0003] Currently, comparators typically include a positive input terminal and a negative input terminal. When the input voltage at the positive input terminal is greater than the input voltage at the negative input terminal, the comparator output level is high; when the input voltage at the positive input terminal is less than the input voltage at the negative input terminal, the comparator output level is low.
[0004] However, if it is necessary to compare two voltage signals with a wide range (e.g., 0-40V), a typical low-voltage comparator cannot handle it because there is a risk of BV breakdown. Summary of the Invention
[0005] In view of this, embodiments of this application provide a voltage comparison circuit and a voltage processing circuit with a wide voltage range to at least partially solve the above-mentioned problems.
[0006] According to a first aspect of the embodiments of this application, a voltage comparison circuit with a wide voltage range is provided, comprising: an input withstand voltage module for receiving a first voltage and a second voltage, and converting the first voltage and the second voltage into a third voltage and a fourth voltage, wherein the first voltage and the second voltage are input voltages; a clamp withstand voltage module for receiving the third voltage and the fourth voltage, and when the third voltage and / or the fourth voltage is in the high voltage domain, obtaining withstand voltage protection by clamping, and outputting a first current corresponding to the first voltage and a second current corresponding to the second voltage; a first mirror module for mirroring the first current to obtain a third current, wherein the third current is N times the first current, and N is a natural number greater than or equal to 1; a second mirror module for mirroring the second current to obtain a fourth current, wherein the fourth current is N times the second current, and N is a natural number greater than or equal to 1; and an inverting output module for outputting a high potential or a low potential according to the magnitude of the third current and the fourth current.
[0007] In one possible implementation, the input withstand voltage module includes: a first high-voltage P-type LDMOS transistor and a second high-voltage P-type LDMOS transistor, wherein the drain of the first high-voltage P-type LDMOS transistor receives the first voltage, the source and gate of the first high-voltage P-type LDMOS transistor output the third voltage, the drain of the second high-voltage P-type LDMOS transistor receives the second voltage, and the source and gate of the second high-voltage P-type LDMOS transistor output the fourth voltage.
[0008] In one possible implementation, the input withstand voltage module further includes: a first resistor and a second resistor, one end of the first resistor being connected to the first voltage and the other end being connected to the drain of the first high-voltage P-type LDMOS transistor, and one end of the second resistor being connected to the second voltage and the other end being connected to the drain of the second high-voltage P-type LDMOS transistor.
[0009] In one possible implementation, the clamping withstand voltage module includes: a first clamping unit, a second clamping unit, a first withstand voltage unit, a second withstand voltage unit, and a current source unit. The first withstand voltage unit receives the third voltage, and the second withstand voltage unit receives the fourth voltage. The first withstand voltage unit and the second withstand voltage unit are respectively connected to the first clamping unit and the second clamping unit, and the first withstand voltage unit and the second withstand voltage unit are connected to the current source unit. If the third voltage is in the high voltage domain, the first clamping unit provides clamping voltage protection for the first withstand voltage unit. If the fourth voltage is in the high voltage domain, the second clamping unit provides clamping voltage protection for the second withstand voltage unit. The current source unit provides low voltage domain current to the first withstand voltage unit and the second withstand voltage unit.
[0010] In one possible implementation, the first voltage-resistant unit is a third high-voltage N-type LDMOS transistor, the second voltage-resistant unit is a fourth high-voltage N-type LDMOS transistor, the gate of the third high-voltage N-type LDMOS transistor is connected to the third voltage, the gate of the fourth high-voltage N-type LDMOS transistor is connected to the fourth voltage, the sources of the third and fourth high-voltage N-type LDMOS transistors are connected to the current source unit, the gate and source of the third high-voltage N-type LDMOS transistor are connected to the first clamping unit, the gate and source of the fourth high-voltage N-type LDMOS transistor are connected to the second clamping unit, the drain of the third high-voltage N-type LDMOS transistor is connected to the first mirror module, and the drain of the fourth high-voltage N-type LDMOS transistor is connected to the second mirror module.
[0011] In one possible implementation, the first clamping unit is a first Zener diode, the second clamping unit is a second Zener diode, the anode of the first Zener diode is connected to the source of the third high-voltage N-type LDMOS transistor, the cathode of the first Zener diode is connected to the gate of the third high-voltage N-type LDMOS transistor, the anode of the second Zener diode is connected to the source of the fourth high-voltage N-type LDMOS transistor, and the cathode of the second Zener diode is connected to the gate of the fourth high-voltage N-type LDMOS transistor.
[0012] In one possible implementation, the current source unit is a first high-voltage N-type LDMOS transistor, the source of which is connected to a low-voltage current source, the gate of which is connected to an internal low-voltage power supply, and the drain of which is connected to the source of the third and fourth high-voltage N-type LDMOS transistors.
[0013] In one possible implementation, the first mirror module includes: a fifth high-voltage P-type LDMOS transistor, a sixth high-voltage P-type LDMOS transistor, and a low-voltage mirror unit; the second mirror module includes: a third high-voltage P-type LDMOS transistor, a fourth high-voltage P-type LDMOS transistor, and a second high-voltage N-type LDMOS transistor. The drain and gate of the fifth high-voltage P-type LDMOS transistor and the gate of the sixth high-voltage P-type LDMOS transistor are all connected to the drain of the third high-voltage N-type LDMOS transistor. The source of the fifth high-voltage P-type LDMOS transistor, the source of the sixth high-voltage P-type LDMOS transistor, and the low-voltage N-type LDMOS transistor are all connected to the drain of the second high-voltage N-type LDMOS transistor. The source of the MOS transistor is connected to the source of the fourth high-voltage P-type LDMOS transistor. The drain of the sixth high-voltage P-type LDMOS transistor is connected to the low-voltage mirror unit. The drain and gate of the third high-voltage P-type LDMOS transistor and the gate of the fourth high-voltage P-type LDMOS transistor are all connected to the drain of the fourth high-voltage N-type LDMOS transistor. The drain of the fourth high-voltage P-type LDMOS transistor is connected to the drain of the second high-voltage N-type LDMOS transistor. The source of the second high-voltage N-type LDMOS transistor is connected to the input terminal of the inverting output module. The gate of the second high-voltage N-type LDMOS transistor is connected to the low-voltage domain current source.
[0014] In one possible implementation, the low-voltage mirror unit includes: a first low-voltage NMOS transistor and a second low-voltage NMOS transistor, wherein the gate and drain of the first low-voltage NMOS transistor and the gate of the second low-voltage NMOS transistor are both connected to the drain of the sixth high-voltage P-type LDMOS transistor, the source of the first low-voltage NMOS transistor and the source of the second low-voltage NMOS transistor are both grounded, and the drain of the second low-voltage NMOS transistor is connected to the input terminal of the inverting output module.
[0015] In one possible implementation, the inverting output module is an inverter logic gate. The input terminals of the inverter logic gate are respectively connected to the source of the second high-voltage N-type LDMOS transistor and the drain of the second low-voltage NMOS transistor. The selectable high potential of the inverter logic gate is the low-voltage domain current source, and the selectable low potential of the inverter logic gate is ground voltage. If the third current is greater than the fourth current, the logic output of the inverter logic gate is a logic low potential; if the third current is less than the fourth current, the logic output of the inverter logic gate is a logic high potential.
[0016] According to a second aspect of the embodiments of this application, a voltage processing circuit with a wide voltage range is provided, including the voltage comparison circuit described in any one of the first aspects of the embodiments, and detecting or operationally amplifying the voltage output by the voltage comparison circuit.
[0017] As can be seen from the above technical solution, in a voltage comparison circuit with a wide voltage range, the input withstand voltage module can improve the circuit's withstand voltage performance, thereby increasing the input range of the first and second voltages, and further expanding the output range of the third and fourth voltages. The first and second mirror modules can amplify the first and second currents and act as mirror current sources to provide appropriate bias current to each amplification stage. Therefore, comparison of voltage signals over a wide range is achieved. The clamping withstand voltage module enables withstand voltage protection when at least one of the third and fourth voltages is in the high-voltage range. The inverting output module can output a high or low potential according to different conditions. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0019] Figure 1 This is a schematic diagram of a voltage comparison circuit with a wide voltage range provided in an embodiment of this application;
[0020] Figure 2 This is a schematic diagram of another wide voltage range voltage comparison circuit provided in an embodiment of this application;
[0021] Figure 3 This is a schematic diagram of a voltage comparison circuit including a first resistor provided in an embodiment of this application;
[0022] Figure 4This is a schematic diagram of a voltage comparison circuit including a first clamping unit provided in an embodiment of this application;
[0023] Figure 5 This is a circuit diagram of a voltage comparison circuit with a wide voltage range provided in an embodiment of this application;
[0024] Figure 6 This is a schematic diagram of another wide voltage range voltage comparison circuit provided in the embodiments of this application;
[0025] Figure 7 This is a schematic diagram of another wide voltage range voltage comparison circuit provided in the embodiments of this application;
[0026] Figure 8 This is a circuit diagram of another wide voltage range voltage comparison circuit provided in an embodiment of this application;
[0027] Figure 9 This is a schematic diagram of a voltage processing circuit with a wide voltage range provided in an embodiment of this application. Detailed Implementation
[0028] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.
[0029] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0030] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0031] Figure 1This is a schematic diagram of a voltage comparison circuit with a wide voltage range provided in an embodiment of this application, as shown below. Figure 1 As shown, the wide voltage range voltage comparison circuit 100 includes: an input withstand voltage module 101, a clamp withstand voltage module 102, a first mirror module 103, a second mirror module 104, and an inverting output module 105. The input withstand voltage module 101 is used to receive a first voltage and a second voltage, which are used as input terminals IN, with the first voltage being a positive voltage and the second voltage being a negative voltage. It also converts the first voltage and the second voltage into a third voltage and a fourth voltage, which are used as input voltages. The clamp withstand voltage module 102 is used to receive the third voltage and the fourth voltage, and when the third voltage and / or the second voltage are both negative, it converts the first voltage and the second voltage into a third voltage and a fourth voltage, which are used as input voltages. When the four voltages are in the high voltage domain, withstand voltage protection is obtained through clamping, and the first current corresponding to the first voltage and the second current corresponding to the second voltage are output; the first mirror module 103 is used to mirror the first current to obtain a third current, the third current being N times the first current, where N is a natural number greater than or equal to 1; the second mirror module 104 is used to mirror the second current to obtain a fourth current, the fourth current being N times the second current, where N is a natural number greater than or equal to 1; the inverting output module 105, as the output terminal OUT, is used to output a high potential or a low potential according to the magnitude of the third current and the fourth current.
[0032] In a voltage comparison circuit with a wide voltage range, the input withstand voltage module 101 improves the circuit's withstand voltage performance, thereby increasing the input range of the first and second voltages, and further expanding the output range of the third and fourth voltages. The first and second mirror modules 103 and 104 amplify the first and second currents and act as mirror current sources to provide appropriate bias current to each amplification stage. Thus, a wide range of voltage signal comparisons is achieved. The clamp withstand voltage module 102 provides withstand voltage protection when at least one of the third and fourth voltages is in the high-voltage range. The inverting output module 105 can output a high or low potential depending on different conditions.
[0033] Figure 2 This is a schematic diagram of another wide voltage range voltage comparison circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, in the voltage comparison circuit 100, the input withstand voltage module 101 may include a first high-voltage P-type LDMOS transistor 1011 and a second high-voltage P-type LDMOS transistor 1012. The drain of the first high-voltage P-type LDMOS transistor 1011 receives a first voltage, and the source and gate of the first high-voltage P-type LDMOS transistor 1011 output a third voltage. The drain of the second high-voltage P-type LDMOS transistor 1012 receives a second voltage, and the source and gate of the second high-voltage P-type LDMOS transistor 1012 output a fourth voltage.
[0034] This application, by using high-voltage P-type LDMOS transistors, can meet the requirements for high voltage resistance and power control. Through the first high-voltage P-type LDMOS transistor 1011 and the second high-voltage P-type LDMOS transistor 1012 included in the input voltage withstand module 101 of this embodiment, the first and second input voltages can be protected from the influence of the reverse voltages, the third and fourth voltages.
[0035] Figure 3 This is a schematic diagram of a voltage comparison circuit including a first resistor provided in an embodiment of this application, as shown below. Figure 3 As shown, in the voltage comparison circuit 100, the input withstand voltage module 101 may also include a first resistor 1013 and a second resistor 1014. One end of the first resistor 1013 is connected to the first voltage and the other end is connected to the drain of the first high-voltage P-type LDMOS transistor 1011. One end of the second resistor 1014 is connected to the second voltage and the other end is connected to the drain of the second high-voltage P-type LDMOS transistor 1012.
[0036] This application provides a certain degree of protection for the first high-voltage P-type LDMOS transistor 1011 and the second high-voltage P-type LDMOS transistor 1012 by setting a first resistor 1013 and a second resistor 1014 in front of the first high-voltage P-type LDMOS transistor 1011 and the second high-voltage P-type LDMOS transistor 1012 through voltage division.
[0037] Figure 4 This is a schematic diagram of a voltage comparison circuit including a first clamping unit provided in an embodiment of this application, as shown below. Figure 4 As shown, in the voltage comparison circuit 100, the clamping withstand voltage module 102 may include: a first clamping unit 1021, a second clamping unit 1022, a first withstand voltage unit 1023, a second withstand voltage unit 1024, and a current source unit 1025. The first withstand voltage unit 1023 receives a third voltage, and the second withstand voltage unit 1024 receives a fourth voltage. The first withstand voltage unit 1023 and the second withstand voltage unit 1024 are respectively connected to the first clamping unit 1021 and the second clamping unit 1022. The first withstand voltage unit 1023 and the second withstand voltage unit 1024 are connected to the current source unit 1025. If the third voltage is in the high voltage domain, the first clamping unit 1021 provides clamping voltage protection for the first withstand voltage unit 1023. If the fourth voltage is in the high voltage domain, the second clamping unit 1022 provides clamping voltage protection for the second withstand voltage unit 1024. The current source unit 1025 provides low voltage domain current to the first withstand voltage unit 1023 and the second withstand voltage unit 1024.
[0038] This application provides clamping voltage protection for the first withstand voltage unit 1023 and the second withstand voltage unit 1024 through the first clamping unit 1021 and the second clamping unit 1022 in the clamping withstand voltage module 102, respectively, and can protect the corresponding components from being broken down when the corresponding voltage is in the high voltage domain.
[0039] Figure 5 This is a circuit diagram of a wide voltage range voltage comparison circuit provided in an embodiment of this application. In some embodiments, such as... Figure 5 As shown, the first withstand voltage unit 1023 in the voltage comparison circuit 100 can be a third high-voltage N-type LDMOS transistor 1026, and the second withstand voltage unit 1024 can be a fourth high-voltage N-type LDMOS transistor 1027. The gate of the third high-voltage N-type LDMOS transistor 1026 is connected to a third voltage, and the gate of the fourth high-voltage N-type LDMOS transistor 1027 is connected to a fourth voltage. The sources of the third high-voltage N-type LDMOS transistor 1026 and the fourth high-voltage N-type LDMOS transistor 1027 are connected to and connected to the current source unit 1025. The gate and source of the third high-voltage N-type LDMOS transistor 1026 are connected to the first clamping unit 1021, and the gate and source of the fourth high-voltage N-type LDMOS transistor 1026 are connected to the second clamping unit 1022. The drain of the third high-voltage N-type LDMOS transistor 1026 is connected to the first mirror module 103, and the drain of the fourth high-voltage N-type LDMOS transistor 1027 is connected to the second mirror module 104.
[0040] This application uses a high-voltage N-type LDMOS transistor to meet the requirements for high voltage resistance and power control.
[0041] like Figure 5 As shown, the current source unit 1025 in the voltage comparison circuit 100 can be a first high-voltage N-type LDMOS transistor 1028. The source of the first high-voltage N-type LDMOS transistor 1028 is connected to the low-voltage domain current source 106. The gate of the first high-voltage N-type LDMOS transistor 1028 is connected to the internal low-voltage power supply. The drain of the first high-voltage N-type LDMOS transistor 1028 is connected to the source of the third high-voltage N-type LDMOS transistor 1026 and the fourth high-voltage N-type LDMOS transistor 1027.
[0042] This application, by setting the current source unit 1025 as the first high-voltage N-type LDMOS transistor 1028, can withstand a VSWR three times higher than that of a commonly used bipolar transistor, and can operate at higher reflected power without damaging the LDMOS device. At the same time, because the LDMOS transistor has high instantaneous peak power, it can better withstand over-excitation of the input signal and is suitable for transmitting radio frequency signals.
[0043] Figure 6 This is a schematic diagram of another wide voltage range voltage comparison circuit provided in the embodiments of this application, as shown below. Figure 6 As shown, the first mirror module 103 in the voltage comparison circuit 100 may include: a fifth high-voltage P-type LDMOS transistor 1031, a sixth high-voltage P-type LDMOS transistor 1032, and a low-voltage mirror unit 1033. The second mirror module 104 may include: a third high-voltage P-type LDMOS transistor 1041, a fourth high-voltage P-type LDMOS transistor 1042, and a second high-voltage N-type LDMOS transistor 1043.
[0044] The drain and gate of the fifth high-voltage P-type LDMOS transistor 1031, and the gate of the sixth high-voltage P-type LDMOS transistor 1032 are all connected to the drain of the third high-voltage N-type LDMOS transistor 1026. The sources of the fifth high-voltage P-type LDMOS transistor 1031, the sixth high-voltage P-type LDMOS transistor 1032, the third high-voltage P-type LDMOS transistor 1041, and the fourth high-voltage P-type LDMOS transistor 1042 are connected. The drain of the sixth high-voltage P-type LDMOS transistor 1032 is connected to the low-voltage mirror unit 10. 33. The drain and gate of the third high-voltage P-type LDMOS transistor 1041 and the gate of the fourth high-voltage P-type LDMOS transistor 1042 are all connected to the drain of the fourth high-voltage N-type LDMOS transistor 1027. The drain of the fourth high-voltage P-type LDMOS transistor 1042 is connected to the drain of the second high-voltage N-type LDMOS transistor 1043. The source of the second high-voltage N-type LDMOS transistor 1043 is connected to the input terminal of the inverting output module 105. The gate of the second high-voltage N-type LDMOS transistor 1043 is connected to the low-voltage domain current source 106.
[0045] This application uses the fifth high-voltage P-type LDMOS transistor 1031, the sixth high-voltage P-type LDMOS transistor 1032, and the low-voltage mirror unit 1033 in the first mirror module 103, and the third high-voltage P-type LDMOS transistor 1041, the fourth high-voltage P-type LDMOS transistor 1042, and the second high-voltage N-type LDMOS transistor 1043 in the second mirror module 104 to amplify the two input currents for subsequent comparison.
[0046] Figure 7 This is a circuit diagram of another wide-voltage-range voltage comparison circuit provided in the embodiments of this application, such as... Figure 7 As shown, the low-voltage mirror unit 1033 in the voltage comparator circuit 100 may include: a first low-voltage NMOS transistor 10331 and a second low-voltage NMOS transistor 10332. The gate and drain of the first low-voltage NMOS transistor 10331 and the gate of the second low-voltage NMOS transistor 10332 are all connected to the drain of the sixth high-voltage P-type LDMOS transistor 1032. The source of the first low-voltage NMOS transistor 10331 and the source of the second low-voltage NMOS transistor 10332 are both grounded. The drain of the second low-voltage NMOS transistor 10332 is connected to the input terminal of the inverting output module 105.
[0047] This application utilizes a low-voltage NMOS transistor in the low-voltage mirror unit 1033, which can conduct when Vgs is greater than a certain value, making it suitable for low-side driving when the source is grounded.
[0048] like Figure 5 As shown, in the voltage comparator circuit 100, the first high-voltage P-type LDMOS transistor 1011, the second high-voltage P-type LDMOS transistor 1012, the third high-voltage P-type LDMOS transistor 1041, the fourth high-voltage P-type LDMOS transistor 1042, the fifth high-voltage P-type LDMOS transistor 1031, and the sixth high-voltage P-type LDMOS transistor 1032 can all be high-voltage P-type LDMOS transistors that can withstand high voltage at VDS but not at VGS. The current source unit 1025, the first withstand voltage unit 1023, and the second withstand voltage unit 1024 can all be high-voltage N-type LDMOS transistors. Specifically, the current source unit 1025 can be the first high-voltage N-type LDMOS transistor 1028, the first withstand voltage unit 1023 can be the third high-voltage N-type LDMOS transistor 1026, and the second withstand voltage unit 1024 can be the fourth high-voltage N-type LDMOS transistor 1027. The first high-voltage N-type LDMOS transistor 1028, the second high-voltage N-type LDMOS transistor 1043, the third high-voltage N-type LDMOS transistor 1026, and the fourth high-voltage N-type LDMOS transistor 1027 are all high-voltage N-type LDMOS transistors that can withstand high voltage at VDS but not at VGS. The first low-voltage NMOS transistor 10331 and the second low-voltage NMOS transistor 10332 are both ordinary low-voltage NMOS transistors that cannot withstand high voltage at ground (G / D / S) and cannot withstand high voltage between themselves. The first resistor 1013 is a port protection resistor, and the resistance value of the first resistor 1031 is equal to the resistance value of the second resistor 1014. The first clamping unit 1021 and the second clamping unit 1022 can be Zener diodes. L1 is an external low-voltage current source, and the low-voltage current source 106 is an internal low-voltage power supply. V+ and V- are the input voltages. The inverting output module 105 may include an inverter logic gate.
[0049] When both V+ and V- are in the low-voltage region, and V+ > V-, the third voltage > the fourth voltage. Therefore, the third voltage minus the fifth voltage > the fourth voltage minus the fifth voltage. Thus, the VGS of the first withstand voltage unit 1023 > the VGS of the second withstand voltage unit 1024. According to the current formula for a MOSFET in the saturation region, I = K * (VGS - VTH). 2, the current of the first voltage withstand unit 1023 > the current of the second voltage withstand unit 1024. At the same time, the mirror ratios of the first mirror module 103 and the second mirror module 104 are both at least one time. Therefore, the current of the first voltage withstand unit 1023 = the current of the fifth high-voltage P-type LDMOS transistor 1031 = the current of the sixth high-voltage P-type LDMOS transistor 1032 = the current of the first low-voltage NMOS transistor 10331 = the current of the second low-voltage NMOS transistor 10332 > the current of the second high-voltage N-type LDMOS transistor 1043 = the current of the third high-voltage P-type LDMOS transistor 1041 = the current of the fourth high-voltage P-type LDMOS transistor 1042 = the current of the second voltage withstand unit 1024. That is, the discharge current at the input end of the inverting output module 105 is greater than the charging current. Therefore, the input end of the inverting output module 105 is at a low potential. After passing through the inverter logic gate included in the inverting output module 105, the output OUT is at a logic high potential, and the high potential is the internal low-voltage power supply. When V+ < V-, according to the same derivation as above, it can be obtained that the output OUT is at a logic low potential, and the low potential is the ground.
[0050] When both V+ and V- belong to the high-voltage domain and V+ > V-, the third voltage > the fourth voltage and both are in the high-voltage domain. At this time, the voltage provided by the current source unit 1025 is initially low, and the first clamping unit 1021 and the second clamping unit 1022 will break down. The clamped voltages after breakdown will respectively protect the VGS of the first voltage withstand unit 1023 and the VGS of the second voltage withstand unit 1024. After the first clamping unit 1021 and the second clamping unit 1022 break down, the voltage provided by the current source unit 1025 is also in the high-voltage domain. Since the VDS of the current source unit 1025, that is, the first high-voltage N-type LDMOS transistor 1028, can withstand high voltage, and the VGS of the first voltage withstand unit 1023 and the second voltage withstand unit 1024 are both relatively large at this time, the voltage provided by the current source unit 1025 will continue to charge until the current of the first voltage withstand unit 1023 + the current of the second voltage withstand unit 1024 = the current of the external low-voltage domain current source. At this time, the VGS of the first clamping unit 1021 and the second clamping unit 1022 will be respectively less than the clamped voltage values of the first clamping unit 1021 and the second clamping unit 1022, that is, the first clamping unit 1021 and the second clamping unit 1022 are no longer in the clamping state. At this time, it still satisfies that the third voltage - the fifth voltage > the fourth voltage - the fifth voltage, that is, the VGS of the first voltage withstand unit 1023 > the VGS of the second voltage withstand unit 1024. According to the same analysis as the example where both V+ and V- belong to the low-voltage domain above, the output OUT is at a logic high potential, and the high potential is the internal low-voltage power supply.
[0051] It should be noted that when the third voltage, the fourth voltage, and the fifth voltage are all in the high-voltage domain, there is no withstand voltage problem for the first withstand voltage unit 1023 and the second withstand voltage unit 1024. Since the fifth high-voltage P-type LDMOS transistor 1031, the sixth high-voltage P-type LDMOS transistor 1032, the third high-voltage P-type LDMOS transistor 1041, the fourth high-voltage P-type LDMOS transistor 1042, and the second high-voltage N-type LDMOS transistor 1043 are high-voltage LDMOS transistors, there is no withstand voltage problem. At the same time, the voltage at the input end of the low-voltage mirror unit 1033 is clamped at the VGS of the first high-voltage N-type LDMOS transistor 1028 at most, and there is also no withstand voltage problem. Since the voltage at the input end of the inverting output module 105 < the voltage of the internal low-voltage power supply - the VGS of the second high-voltage N-type LDMOS transistor 1043, the voltage of the internal low-voltage power supply is in the low-voltage domain and there is no withstand voltage problem. When V+ < V-, it can be deduced by the same reasoning as above that the output OUT is at a logic low level, and the low level is ground, and there is also no withstand voltage problem.
[0052] When V+ is in the high-voltage domain and V- is in the low-voltage domain, the third voltage is in the high-voltage domain, and the first clamping unit 1021 will be broken down. The voltage provided by the current source unit 1025 is in the high-voltage domain. At this time, the fourth voltage will not be in the low-voltage domain because V- is in the low-voltage domain. There is no discharge path at the output end of the second high-voltage P-type LDMOS transistor 1012. Therefore, the fourth voltage = the voltage provided by the current source unit 1025. No current flows through the second withstand voltage unit 1024, and the current value of the second high-voltage N-type LDMOS transistor 1043 = 0. However, since the VGS of the first withstand voltage unit 1023 is stabilized at the clamping voltage by the first clamping unit 1021 and is turned on, the voltage provided by the current source unit 1025 continues to rise until the current of the first withstand voltage unit 1023 = the current of the external low-voltage domain current source. At this time, the current of the second low-voltage NMOS transistor 10332 = the current of the external low-voltage domain current source > 0 = the current of the second high-voltage N-type LDMOS transistor 1043. The input end of the inverting output module 105 is at a low level, so the output OUT is at a logic high level; similarly, when V+ is in the low-voltage domain and V- is in the high-voltage domain, the output OUT is at a logic low level.
[0053] In summary, through the circuit structure of the present application, the withstand voltage problem in the circuit can be well solved, and the structure is relatively simple, occupying a small area in the chip.
[0054] Figure 8 It is the circuit diagram of another voltage comparison circuit with a wide voltage range provided by the embodiment of the present application, as Figure 8As shown, the voltage comparator circuit 100 may further include parasitic diodes D1 and D2, which are the parasitic diodes of the first high-voltage P-type LDMOS transistor 1011 and the second high-voltage P-type LDMOS transistor 1012, respectively. When VGS = 0 for the first high-voltage P-type LDMOS transistor 1011 and the second high-voltage P-type LDMOS transistor 1012, their channels are closed.
[0055] When V+ is in the high-voltage domain and V- is in the low-voltage domain, the third voltage is in the high-voltage domain, and the first clamping unit 1021 will break down. The voltage provided by the current source unit 1025 is in the high-voltage domain. At this time, the fourth voltage will not be in the low-voltage domain because V- is in the low-voltage domain. Because there is a forward-biased Zener diode between the voltage provided by the current source unit 1025 and the fourth voltage, namely the second clamping unit 1022, the fourth voltage is in the high-voltage domain. The second high-voltage P-type LDMOS transistor 1012 is a high-voltage LDMOS transistor in the off state. Since the output terminal of the second high-voltage P-type LDMOS transistor 1012 is equipped with a parasitic body diode D2 that is reverse-biased to the input terminal of the second high-voltage P-type LDMOS transistor 1012 and can withstand high voltage, the second voltage and V- will not be affected by the fourth voltage, and there is no voltage withstand problem. Similarly, when V+ is in the low-voltage domain and V- is in the high-voltage domain, the voltage withstand problem can be solved by the parasitic body diode D1.
[0056] This application, by incorporating parasitic diodes D1 and D2, ensures that the parasitic diodes reverse-break down before damaging the LDMOS transistor under overvoltage conditions, directly diverting a large current to ground. This prevents the LDMOS transistor from burning out under overvoltage conditions. Furthermore, it provides a path for the reverse induced voltage in the circuit, preventing it from breaking down the LDMOS transistor.
[0057] Figure 9 This is a schematic diagram of a voltage processing circuit with a wide voltage range provided in an embodiment of this application, as shown below. Figure 9 As shown, this application provides a voltage processing circuit 200 with a wide voltage range. The circuit includes a voltage comparison circuit 100 of any of the aforementioned wide voltage range voltage comparison circuit embodiments, and detects or amplifies the voltage output by the voltage comparison circuit 100.
[0058] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.
[0059] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.
[0060] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A voltage comparator circuit with a wide voltage range, characterized in that, include: An input withstand voltage module is used to receive a first voltage and a second voltage, and convert the first voltage and the second voltage into a third voltage and a fourth voltage, wherein the first voltage and the second voltage are the input voltages; The clamping withstand voltage module is used to receive the third voltage and the fourth voltage, and when the third voltage and / or the fourth voltage is in the high voltage domain, it obtains withstand voltage protection by clamping, and outputs a first current corresponding to the first voltage and a second current corresponding to the second voltage. The first mirror module is used to mirror the first current to obtain a third current, wherein the third current is N times the first current, and N is a natural number greater than or equal to 1. The second mirror module is used to mirror the second current to obtain a fourth current, wherein the fourth current is N times the second current, and N is a natural number greater than or equal to 1. An inverting output module is used to output a high or low potential based on the magnitudes of the third current and the fourth current. The input withstand voltage module includes: a first high-voltage P-type LDMOS transistor and a second high-voltage P-type LDMOS transistor. The drain of the first high-voltage P-type LDMOS transistor receives the first voltage, and the source and gate of the first high-voltage P-type LDMOS transistor output the third voltage. The drain of the second high-voltage P-type LDMOS transistor receives the second voltage, and the source and gate of the second high-voltage P-type LDMOS transistor output the fourth voltage. The input withstand voltage module further includes: a first resistor and a second resistor, one end of the first resistor is connected to the first voltage and the other end is connected to the drain of the first high-voltage P-type LDMOS transistor, and one end of the second resistor is connected to the second voltage and the other end is connected to the drain of the second high-voltage P-type LDMOS transistor. The clamping withstand voltage module includes: a first clamping unit, a second clamping unit, a first withstand voltage unit, a second withstand voltage unit, and a current source unit. The first withstand voltage unit receives the third voltage, and the second withstand voltage unit receives the fourth voltage. The first withstand voltage unit and the second withstand voltage unit are respectively connected to the first clamping unit and the second clamping unit, and the first withstand voltage unit and the second withstand voltage unit are connected to the current source unit. If the third voltage is in the high voltage range, the first clamping unit provides clamping voltage protection for the first withstand voltage unit. If the fourth voltage is in the high voltage range, the second clamping unit provides clamping voltage protection for the second withstand voltage unit. The current source unit provides low voltage range current to the first withstand voltage unit and the second withstand voltage unit.
2. The circuit as described in claim 1, characterized in that, The first voltage withstand unit is a third high-voltage N-type LDMOS transistor, and the second voltage withstand unit is a fourth high-voltage N-type LDMOS transistor. The gate of the third high-voltage N-type LDMOS transistor is connected to the third voltage, and the gate of the fourth high-voltage N-type LDMOS transistor is connected to the fourth voltage. The sources of the third and fourth high-voltage N-type LDMOS transistors are connected to the current source unit. The first clamping unit is connected between the gate and source of the third high-voltage N-type LDMOS transistor, and the second clamping unit is connected between the gate and source of the fourth high-voltage N-type LDMOS transistor. The drain of the third high-voltage N-type LDMOS transistor is connected to the first mirror module, and the drain of the fourth high-voltage N-type LDMOS transistor is connected to the second mirror module.
3. The circuit as described in claim 2, characterized in that, The first clamping unit is a first Zener diode, the second clamping unit is a second Zener diode, the anode of the first Zener diode is connected to the source of the third high-voltage N-type LDMOS transistor, the cathode of the first Zener diode is connected to the gate of the third high-voltage N-type LDMOS transistor, the anode of the second Zener diode is connected to the source of the fourth high-voltage N-type LDMOS transistor, and the cathode of the second Zener diode is connected to the gate of the fourth high-voltage N-type LDMOS transistor.
4. The circuit as described in claim 3, characterized in that, The current source unit is a first high-voltage N-type LDMOS transistor. The source of the first high-voltage N-type LDMOS transistor is connected to a low-voltage current source. The gate of the first high-voltage N-type LDMOS transistor is connected to an internal low-voltage power supply. The drain of the first high-voltage N-type LDMOS transistor is connected to the source of the third high-voltage N-type LDMOS transistor and the fourth high-voltage N-type LDMOS transistor.
5. The circuit as described in claim 4, characterized in that, The first mirror module includes: a fifth high-voltage P-type LDMOS transistor, a sixth high-voltage P-type LDMOS transistor, and a low-voltage mirror unit. The second mirror module includes: a third high-voltage P-type LDMOS transistor, a fourth high-voltage P-type LDMOS transistor, and a second high-voltage N-type LDMOS transistor. The drain and gate of the fifth high-voltage P-type LDMOS transistor and the gate of the sixth high-voltage P-type LDMOS transistor are all connected to the drain of the third high-voltage N-type LDMOS transistor. The source of the fifth high-voltage P-type LDMOS transistor, the source of the sixth high-voltage P-type LDMOS transistor, and the source of the third high-voltage P-type LDMOS transistor are all connected to the drain of the second high-voltage N-type LDMOS transistor. The source of the fourth high-voltage P-type LDMOS transistor is connected to the source of the fifth high-voltage P-type LDMOS transistor. The drain of the sixth high-voltage P-type LDMOS transistor is connected to the low-voltage mirror unit. The drain and gate of the third high-voltage P-type LDMOS transistor and the gate of the fourth high-voltage P-type LDMOS transistor are all connected to the drain of the fourth high-voltage N-type LDMOS transistor. The drain of the fourth high-voltage P-type LDMOS transistor is connected to the drain of the second high-voltage N-type LDMOS transistor. The source of the second high-voltage N-type LDMOS transistor is connected to the input terminal of the inverting output module. The gate of the second high-voltage N-type LDMOS transistor is connected to the low-voltage domain current source.
6. The circuit as described in claim 5, characterized in that, The low-voltage mirror unit includes a first low-voltage NMOS transistor and a second low-voltage NMOS transistor. The gate and drain of the first low-voltage NMOS transistor and the gate of the second low-voltage NMOS transistor are all connected to the drain of the sixth high-voltage P-type LDMOS transistor. The source of the first low-voltage NMOS transistor and the source of the second low-voltage NMOS transistor are both grounded. The drain of the second low-voltage NMOS transistor is connected to the input terminal of the inverting output module.
7. The circuit as described in claim 6, characterized in that, The inverting output module is an inverter logic gate. The input terminals of the inverter logic gate are respectively connected to the source of the second high-voltage N-type LDMOS transistor and the drain of the second low-voltage NMOS transistor. The selectable high potential of the inverter logic gate is the low-voltage domain current source, and the selectable low potential of the inverter logic gate is ground voltage. If the third current is greater than the fourth current, the logic output of the inverter logic gate is logic low. If the third current is less than the fourth current, the logic output of the inverter logic gate is logic high.
8. A voltage processing circuit with a wide voltage range, characterized in that, It includes the voltage comparison circuit according to any one of claims 1-7, and detects or amplifies the voltage output by the voltage comparison circuit.