Spaceborne computer system with memory space single event upset detection capability
By introducing a detection module into the onboard computer system to perform autonomous memory space single-event flip detection, the problems of resource consumption and error accumulation in traditional detection methods are solved, adaptive detection and correction are achieved, and the system's radiation resistance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INST OF CONTROL ENG
- Filing Date
- 2023-11-17
- Publication Date
- 2026-05-26
AI Technical Summary
Traditional spaceborne computer systems consume processor resources and are prone to accumulating single-event upset errors when performing memory space single-event upset detection at fixed detection cycles, exceeding the error correction capabilities of the error correction and detection module, and thus failing to effectively correct dual-memory bit errors and multi-memory bit errors.
A detection module is introduced to perform single-event flip detection in autonomous memory space. By adjusting the detection cycle length, the detection and correction are performed using the bus, memory interface controller, and error correction module, avoiding processor resource occupation. The detection cycle is dynamically adjusted according to the number of single memory bit errors.
It achieves adaptive adjustment of the detection cycle without consuming processor resources, avoids error accumulation, ensures error correction capability, effectively corrects single memory bit errors, reduces bus usage, and prevents error propagation.
Smart Images
Figure CN117437970B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radiation-hardened integrated circuit technology, and in particular to a spaceborne computer system with single-event upset detection capability for memory space. Background Technology
[0002] In the space radiation environment, as the size of integrated circuit processes continues to shrink, memory cells such as SRAM and SDRAM are becoming increasingly sensitive to single-event upsets (SOME). Memory resistance to SOME is a necessary function for spaceborne electronic equipment.
[0003] Traditional spaceborne computer systems rely on the processor to perform single-event fault detection (SET) on memory during idle periods. When a single-bit error is detected in a memory word due to an SET, the error correction module corrects it. This method requires a fixed detection cycle and consumes valuable processor computing and memory access resources. Furthermore, the error correction module can only correct single-bit errors within a memory word, not double-bit or multi-bit errors. If the fixed detection cycle is too long, prolonged periods without detection and correction can easily lead to the accumulation of SET errors, causing single-bit errors to evolve into double-bit or multi-bit errors, exceeding the error correction capability of the checksum in the error correction module.
[0004] Therefore, there is an urgent need for a new spaceborne computer system with memory space single-event flip detection capability. Summary of the Invention
[0005] To address the problem that traditional spaceborne computer systems utilize processors to perform single-event upset (SWE) detection in memory space at fixed detection cycles, which not only consumes processor computing resources but also easily leads to the accumulation of SWE errors exceeding the error correction capabilities of the error correction and detection module, this invention provides a spaceborne computer system with memory space SWE detection capabilities.
[0006] In a first aspect, embodiments of the present invention provide a spaceborne computer system with memory space single-event flip detection capability, the system comprising: a processor, a bus, a memory, a memory interface controller, an error correction and detection module, and a detection module;
[0007] The memory contains several storage words, and each storage word contains several storage bits and several parity bits;
[0008] The detection module is used to adjust the duration of the next detection cycle based on the number of memory words that have single-bit faults in the current detection cycle, and to perform space single-event flip detection and correction on the memory in each detection cycle through the bus, the memory interface controller and the error correction and detection module.
[0009] The error correction and detection module is connected to the memory through the memory interface controller, and the error correction and detection module is used to correct single-bit faults in each memory word.
[0010] Secondly, embodiments of the present invention also provide a memory space single-event flip detection method based on the system described in any embodiment of this specification, the method comprising:
[0011] Step 200: Obtain the preset default period value as the current detection period;
[0012] Step 202: After the current detection cycle has elapsed, the memory is subjected to space single-event upset detection and correction via the bus, memory interface controller, and error correction and detection module.
[0013] Step 204: Adjust the duration of the next detection cycle based on the number of memory words that have experienced single-bit errors in the current detection cycle.
[0014] Step 206: Use the duration of the next detection cycle as the new current detection cycle, and proceed to step 202.
[0015] This invention provides a spaceborne computer system with memory space single-event upset (SET) detection capability. Firstly, a detection module is added for SET detection. Compared to traditional methods using the processor, this solution does not occupy processor resources and autonomously completes the memory detection task. Secondly, the detection module can adaptively adjust the interval of the next detection cycle based on the number of memory words with single-bit faults in the current detection cycle. This avoids the accumulation of SET errors due to excessively long detection cycles, ensuring that the error correction capability of the error detection module is not exceeded, while also preventing excessively short detection cycles from frequently occupying the bus. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1This is a schematic diagram of the composition of a spaceborne computer system with memory space single-event flip detection capability provided in an embodiment of the present invention;
[0018] Figure 2 This is a flowchart of a single-event upset detection method for memory space provided in an embodiment of the present invention. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0020] The following describes the specific implementation of the above concept.
[0021] Please refer to Figure 1 This invention provides a spaceborne computer system with memory space single-event flip detection capability. The system includes: a processor, a bus, a memory, a memory interface controller, an error correction and detection module, and a detection module.
[0022] The memory contains several memory words, and each memory word contains several memory bits and several parity bits;
[0023] The detection module is used to adjust the duration of the next detection cycle based on the number of memory words that have experienced single-bit faults in the current detection cycle, and to perform space single-event flip detection and correction on the memory in each detection cycle through the bus, memory interface controller and error correction and detection module.
[0024] The error correction and detection module is connected to the memory through the memory interface controller. The error correction and detection module is used to detect and correct single-bit errors in each memory word.
[0025] In this embodiment of the invention, firstly, a detection module is added to perform spatial single-event flip detection. Compared with the traditional method of using the processor for detection, this solution does not occupy the processor's computing resources and autonomously completes the memory detection task. Secondly, the detection module can adaptively adjust the interval of the next detection cycle according to the number of memory words that have single-bit faults in the current detection cycle. This can avoid the accumulation of single-event flip errors due to excessively long detection cycles, ensuring that the error correction capability of the error correction and detection module is not exceeded, and also avoid the frequent occupation of the bus due to excessively short detection cycles.
[0026] It should be noted that single particles generated in the space radiation environment may not affect the memory, or they may cause an abnormal flip of a bit in each memory word. Therefore, it is necessary to periodically detect and correct single-event flips in the memory space.
[0027] It is understood that the detection process is executed by the detection module and does not occupy processor resources. During the detection, the processor can execute other computational programs except for memory access; after the detection process is completed, the processor can access memory normally. Compared with existing technologies, this solution solves the problem that traditional memory detection using processor access operations requires pausing the normal execution of processor tasks, resulting in a large amount of processor computing resources being occupied.
[0028] Furthermore, a storage word can contain 32 storage bits plus 8 parity bits, or it can contain 8 storage bits plus 5 parity bits, or other combinations. There is no limitation on the number of storage bits and parity bits in a storage word. The parity bit in each storage word is used to store the target checksum.
[0029] In some implementations, the detection module adjusts the duration of the next detection cycle based on the number of memory words experiencing single-bit faults in the current detection cycle, and initiates space single-event flip detection and correction of the memory in each detection cycle by activating the bus, memory interface controller, and error correction / detection module, including:
[0030] Step S1: Obtain the preset default period value as the current detection period;
[0031] Step S2: After the current detection cycle has elapsed, each memory word in the memory is read through the bus to perform spatial single-event flip detection and correction on the memory, and to count the number of memory words that have undergone single-memory faults in the current detection cycle.
[0032] Step S3: Calculate the duration of the next detection cycle based on the number of storage words that have experienced single-bit errors in the current detection cycle, the current detection cycle, and the preset judgment threshold.
[0033] Step S4: Use the duration of the next detection cycle as the new current detection cycle, and proceed to step S2.
[0034] In this embodiment, since the error correction and detection module can only correct storage words with single-bit errors, a judgment threshold can be set, which is the threshold for the number of storage words with single-bit errors in one cycle. When the number of storage words with single-bit errors in the current detection cycle exceeds the judgment threshold, the duration of the next detection cycle is reduced. When the number of storage words with single-bit errors in the current detection cycle is less than the judgment threshold, the duration of the next detection cycle is appropriately increased. In this way, the detection cycle is dynamically adjusted adaptively to avoid problems caused by detection cycles that are too long or too short.
[0035] In some implementations, the duration of the next detection cycle is calculated using the following formula:
[0036]
[0037] In the formula, T n+1 T represents the duration of the next detection cycle. n For the current detection cycle, F t To determine the threshold, F b For positive bias, F n This represents the number of memory words that have experienced single-bit faults during the current detection cycle.
[0038] For example, the default period T0 is set to 100ms, and the judgment threshold F is... t Set to 1, positive bias F b Set to 1; if the number of memory words with single-bit errors, F0, is 0 in the 0th detection cycle, then the next detection cycle... If the number of memory words with single-bit errors, F1, is 1 in the first detection cycle, then in the next detection cycle... If the number of memory words with single-bit errors, F2, is 2 in the second detection cycle, then in the next detection cycle... And so on.
[0039] It should be noted that the forward bias can be set to 1 or 2 to avoid the occurrence of single-bit error errors in the number F of memory words during the current detection cycle. n When the value is 0, the duration T of the next detection cycle n+1 The calculation returned infinity, causing the program to malfunction.
[0040] In some implementations, each memory word in the memory is read via a bus to perform space single-event flip detection and correction on the memory, including:
[0041] The memory interface controller is used to read each word in the memory to calculate the check value of each word.
[0042] The target check code stored in the check bit of each storage word in the memory is compared with the check bit to detect whether a single-event flip occurs in each storage word in the current detection cycle, so as to determine whether a single storage bit error or a double storage bit error occurs in each storage word.
[0043] The error correction and detection module is used to correct memory words that have experienced single-bit errors.
[0044] In this embodiment, by comparing the target check code with the newly calculated check value of each storage word in the current detection cycle, it is possible to detect whether a single-bit or double-bit error has occurred in each storage word. However, the error correction and detection module can only correct single-bit errors. Therefore, this solution only counts the number of storage words with single-bit errors to adjust the detection cycle. When a double-bit error occurs, other methods must be used for error correction, and the error correction method for double-bit errors is not considered in this solution. Moreover, by using the adaptive memory space single-event flip detection method of this solution from the beginning, the occurrence of double or multiple bit errors caused by error accumulation can be greatly avoided.
[0045] like Figure 2 As shown, embodiments of the present invention also provide a memory space single-event flip detection method based on any embodiment of the system described herein, comprising:
[0046] Step 200: Obtain the preset default period value as the current detection period;
[0047] Step 202: After the current detection cycle has elapsed, the memory is subjected to space single-event upset detection and correction via the bus, memory interface controller, and error correction and detection module.
[0048] Step 204: Adjust the duration of the next detection cycle based on the number of memory words that have experienced single-bit errors in the current detection cycle.
[0049] Step 206: Use the duration of the next detection cycle as the new current detection cycle, and proceed to step 202.
[0050] In some implementations, the duration of the next detection cycle in step 204 is calculated using the following formula:
[0051]
[0052] In the formula, T n+1 T represents the duration of the next detection cycle. n For the current detection cycle, F t To determine the threshold, F b For positive bias, F nThis represents the number of memory words that have experienced single-bit faults during the current detection cycle.
[0053] In some implementations, step 202, which involves performing space single-event upset detection and correction on the memory via a bus, memory interface controller, and error correction / detection module, may include:
[0054] The memory interface controller is used to read each word in the memory to calculate the check value of each word.
[0055] The target check code stored in the check bit of each storage word in the memory is compared with the check bit to detect whether a single-event flip occurs in each storage word in the current detection cycle, so as to determine whether a single storage bit error or a double storage bit error occurs in each storage word.
[0056] The error correction and detection module is used to correct memory words that have experienced single-bit errors.
[0057] Since the above method is based on the same concept as the system embodiment of the present invention, the specific details can be found in the description of the system embodiment of the present invention, and will not be repeated here.
[0058] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0059] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as FLASH, SRAM, and DRAM.
[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A spaceborne computer system with memory space single-event flip detection capability, characterized in that, include: Processor, bus, memory, memory interface controller, error correction and detection module, and detection module; The memory contains several storage words, and each storage word contains several storage bits and several parity bits; The detection module is used to adjust the duration of the next detection cycle based on the number of memory words that have single-bit faults in the current detection cycle, and to perform space single-event flip detection and correction on the memory in each detection cycle through the bus, the memory interface controller and the error correction and detection module. The error correction and detection module is connected to the memory through the memory interface controller, and the error correction and detection module is used to correct single-bit faults in each memory word; The detection module adjusts the duration of the next detection cycle based on the number of memory words experiencing single-bit faults in the current detection cycle, and activates the bus, the memory interface controller, and the error correction and detection module in each detection cycle to perform space single-event flip detection and correction on the memory, including: Step S1: Obtain the preset default period value as the current detection period; Step S2: After the current detection cycle duration, each storage word in the memory is read through the bus to perform space single-event flip detection and correction on the memory, and to count the number of storage words that have undergone single-bit faults in the current detection cycle. Step S3: Calculate the duration of the next detection cycle based on the number of storage words that have experienced single-bit errors in the current detection cycle, the current detection cycle, and the preset judgment threshold. Step S4: Take the duration of the next detection cycle as the new current detection cycle, and proceed to step S2. The duration of the next testing cycle is calculated using the following formula: In the formula, The duration of the next testing cycle, For the current testing cycle, The threshold value is the one used for determining the threshold. For positive bias, This represents the number of memory words that have experienced single-bit faults during the current detection cycle.
2. The system according to claim 1, characterized in that, The step of reading each memory word in the memory via the bus to perform space single-event flip detection and correction on the memory includes: The memory interface controller is used to read each storage word in the memory to calculate the check value of each storage word. The target check code stored in the check bit of each storage word in the memory is compared with the target check code stored in the check bit of each storage word in the current detection period to detect whether a single-event flip has occurred in each storage word, so as to determine whether a single storage bit error or a double storage bit error has occurred in each storage word. The error correction and detection module is used to correct storage words in the memory that have experienced single-bit faults.
3. A method for detecting single-event upsets in memory space based on the system described in any one of claims 1-2, characterized in that, include: Step 200: Obtain the preset default period value as the current detection period; Step 202: After the current detection cycle has elapsed, the memory is subjected to space single-event upset detection and correction via the bus, memory interface controller, and error correction and detection module. Step 204: Adjust the duration of the next detection cycle based on the number of memory words that have experienced single-bit errors in the current detection cycle. Step 206: Use the duration of the next detection cycle as the new current detection cycle, and proceed to step 202.
4. The method according to claim 3, characterized in that, The duration of the next testing cycle is calculated using the following formula: In the formula, The duration of the next testing cycle, For the current testing cycle, The threshold value is the one used for determining the threshold. For positive bias, This represents the number of memory words that have experienced single-bit faults during the current detection cycle.
5. The method according to claim 4, characterized in that, The process of detecting and correcting space single-event upsets in the memory via a bus, memory interface controller, and error correction module includes: The memory interface controller is used to read each storage word in the memory to calculate the check value of each storage word. The target check code stored in the check bit of each storage word in the memory is compared with the target check code stored in the check bit of each storage word in the current detection period to detect whether a single-event flip has occurred in each storage word, so as to determine whether a single storage bit error or a double storage bit error has occurred in each storage word. The error correction and detection module is used to correct the memory words that have experienced single-bit faults in the memory.