Display substrate

Abstract

A display substrate has a display area and a peripheral area, and comprises a plurality of sub-pixels, a first power signal line, a second power signal line, a first power signal bus and a second power signal bus. The plurality of sub-pixels are located in the display area. The first power signal line and the second power signal line are at least partially located in the display area. The first power signal line is configured to transmit a first power signal to at least part of the sub-pixels. The second power signal line is configured to transmit a second power signal to at least part of the sub-pixels. The first power signal bus and the second power signal bus are located in the peripheral area. The first power signal line is electrically connected to the first power signal bus. The second power signal line is electrically connected to the second power signal bus. The second power signal bus comprises a first part arranged on a side of the first power signal bus close to the display area and a second part arranged on a side of the first power signal bus away from the display area. The display substrate has better display effect.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a display substrate. BACKGROUND

[0002] In the field of display, an organic light emitting diode (OLED) display panel has a broad development prospect due to its self-luminous, high contrast, low energy consumption, wide viewing angle, fast response speed, flexible panel, wide temperature range, simple manufacturing, and the like. SUMMARY

[0003] At least one embodiment of the present disclosure provides a display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising a substrate, a plurality of sub-pixels, a first power signal line, a second power signal line, a first power signal bus and a second power signal bus, the plurality of sub-pixels are disposed on the substrate and located in the display area, the first power signal line and the second power signal line are disposed on the substrate and at least partially located in the display area, wherein the first power signal line is configured to transmit a first power signal to at least part of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least part of the plurality of sub-pixels; the first power signal bus and the second power signal bus are disposed on the substrate and located in the peripheral area, wherein the first power signal line is electrically connected to the first power signal bus, the second power signal line is electrically connected to the second power signal bus, and the second power signal bus comprises a first part disposed on a side of the first power signal bus close to the display area and a second part disposed on a side of the first power signal bus away from the display area, so as to at least partially surround the first power signal bus.

[0004] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises: a light shielding layer disposed on the substrate, wherein each of the plurality of sub-pixels comprises a light emitting device and a pixel driving circuit for driving the light emitting device, the pixel driving circuit is disposed on a side of the light shielding layer away from the substrate, and the first power signal bus is disposed in the same layer as the light shielding layer.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel driving circuit comprises a thin film transistor, the thin film transistor comprises a gate electrode disposed on a side of the light shielding layer away from the substrate and a source / drain electrode located on a side of the gate electrode away from the substrate, and the first part is disposed in the same layer as the source / drain electrode.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second part is disposed in the same layer as the gate electrode.

[0007] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the second power signal bus further comprises a third part and a fourth part electrically connecting the first part and the second part, the third part and the fourth part are located on opposite sides of the first power signal bus, and the first part, the second part, the third part and the fourth part together surround the first power signal bus.

[0008] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the third part and the fourth part are arranged in the same layer as the first part and are integrally connected with the first part.

[0009] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the third part and the fourth part are symmetrically structured.

[0010] For example, the display substrate provided by at least one of the embodiments of the present disclosure further comprises a first power connection line arranged in the same layer as the first power signal bus and electrically connecting the first power signal bus and the first power signal line.

[0011] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first power signal line is arranged in the same layer as the source-drain electrode and is electrically connected with the first power connection line through a relay via hole.

[0012] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the second power signal line is arranged in the same layer as the source-drain electrode.

[0013] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the second power signal line extends from the display area to the peripheral area and is electrically connected with the first part.

[0014] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the potential of the first power signal is higher than the potential of the second power signal.

[0015] For example, the display substrate provided by at least one of the embodiments of the present disclosure further comprises a planarization layer and a first electrode layer; the planarization layer is arranged on a side of the source-drain electrode away from the substrate, and comprises a first via hole arranged in the peripheral area and exposing the first part and a second via hole arranged in the display area and exposing the source-drain electrode, the first electrode layer is arranged on a side of the planarization layer away from the substrate, and comprises a first electrode arranged in the display area and a connection electrode arranged in the peripheral area, the first electrode is electrically connected with the source-drain electrode through the second via hole, and the connection electrode is electrically connected with the first part through the first via hole.

[0016] For example, the display substrate provided by at least one of the embodiments of the present disclosure further includes a pixel definition layer disposed on a side of the first electrode layer away from the substrate substrate, and including a connection opening disposed on the peripheral region and a sub-pixel opening disposed on the display region, the connection opening exposing the connection electrode, and the sub-pixel opening exposing the first electrode.

[0017] For example, the display substrate provided by at least one of the embodiments of the present disclosure further includes a light-emitting material layer and a second electrode layer; the light-emitting material layer is at least partially disposed in the sub-pixel opening, and the second electrode layer is disposed on a side of the light-emitting material layer away from the substrate substrate and extends from the display region to the peripheral region and is electrically connected to the connection electrode through the connection opening.

[0018] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the second electrode layer terminates on a side of the first power signal bus close to the display region, and has a spacing from the first power signal bus.

[0019] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, in a direction perpendicular to the substrate substrate, the first portion at least partially overlaps the first power connection line, and the first portion includes a first hollow portion that overlaps the first power connection line in the direction perpendicular to the substrate substrate.

[0020] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first portion further includes a second hollow portion that does not overlap the first power connection line in the direction perpendicular to the substrate substrate.

[0021] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, in a direction perpendicular to the substrate substrate, at least one of the third portion and the fourth portion at least partially overlaps the first power connection line, and at least one of the third portion and the fourth portion includes a third hollow portion that overlaps the first power connection line in the direction perpendicular to the substrate substrate.

[0022] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first power connection line includes a first wiring portion extending in a first direction and a second wiring portion extending in a second direction, the first direction being different from the second direction, in a direction perpendicular to the substrate substrate, the first wiring portion at least partially overlaps the first portion and overlaps the first hollow portion, and the second wiring portion overlaps at least one of the third portion and the fourth portion and overlaps the third hollow portion. BRIEF DESCRIPTION OF DRAWINGS

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figure 1 A pixel circuit diagram of a display substrate provided in at least one embodiment of this disclosure;

[0025] Figures 2A-2C A signal timing diagram of a driving method for a pixel circuit provided in at least one embodiment of this disclosure;

[0026] Figure 3 This is a plan view of a display substrate provided in at least one embodiment of the present disclosure;

[0027] Figure 4 for Figure 3 A partial planar schematic diagram of the display substrate within the dashed frame area;

[0028] Figure 5 for Figure 4 A partial enlarged planar schematic diagram of the display substrate in the area within the dashed frame;

[0029] Figure 6 A partial cross-sectional schematic diagram of a sub-pixel of a display substrate provided in at least one embodiment of this disclosure; and

[0030] Figures 7-13B This is a partial planar schematic diagram of each functional layer of a display substrate provided in at least one embodiment of the present disclosure, and a partial planar schematic diagram of each functional layer stacked sequentially. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning commonly understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms are used herein to distinguish one element from another, and are not necessarily used in a sequence or to denote importance or quantity. The terms "comprise", "comprising", "include", "including", and the like are used herein to mean including but not limited to. The terms "connected", "coupled", and the like are used herein to mean either a direct connection or an indirect connection through one or more intervening elements, whether mechanical, electrical, or otherwise. The terms "upper", "lower", "left", "right", and the like are used herein only to represent relative positions, and may change accordingly when the absolute positions of the described objects change.

[0033] The display substrate generally includes a display area and a peripheral area surrounding the display area, the display area having a plurality of sub-pixels for display. At least some of the plurality of sub-pixels include a light emitting device and a pixel driving circuit for driving the light emitting device to emit light. The peripheral area includes a control circuit for providing a control signal to the pixel driving circuit, and a power bus and the like structure.

[0034] With the development trend of large screen and narrow frame of display devices, the arrangement space of the above-mentioned control circuit and the power bus and the like structure of the peripheral area of the display substrate needs to be as small as possible. At this time, the circuit arrangement is too compact, which is prone to signal crosstalk and the like problems. Therefore, how to reasonably utilize the limited arrangement space to layout the above-mentioned circuit structure is an important direction for optimizing the structure of the display substrate.

[0035] In the plurality of sub-pixels of the display substrate, the pixel driving circuit is generally implemented as a 3T1C (three thin film transistors and one storage capacitor), 7T1C (seven thin film transistors and one storage capacitor), 8T1C (eight thin film transistors and one storage capacitor), or 8T2C (eight thin film transistors and two storage capacitors) structure, to achieve the effect of driving the light emitting device. For example, the pixel driving circuit with a 3T1C structure is taken as an example for introduction below, but the embodiments of the present disclosure do not limit the specific structure of the pixel driving circuit.

[0036] For example, the pixel driving circuit with a 3T1C structure includes a driving sub-circuit for driving the light emitting device to emit light, and a detection sub-circuit for detecting the electrical characteristics of the sub-pixel to achieve external compensation. For example, Figure 1 A schematic diagram of a 3T1C pixel driving circuit provided by at least one embodiment of the present disclosure is shown.

[0037] Reference is made to Figure 1The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. The first transistor T1 is, for example, a driving transistor, and the second transistor T2 is, for example, a data writing transistor. The first source-drain electrode of the second transistor T2 is electrically connected to the first capacitor electrode Ca of the storage capacitor Cst and the gate of the first transistor T1. The second source-drain electrode of the second transistor T2 is configured to receive a data signal DT. The second transistor T2 is configured to write the data signal DT to the gate of the first transistor T1 and the storage capacitor Cst in response to a first control signal G1. The first source-drain electrode of the first transistor T1 is electrically connected to the second capacitor electrode Cb of the storage capacitor Cst and is configured to be electrically connected to the first electrode of the light-emitting device EM. The second source-drain electrode of the first transistor T1 is configured to receive a first power supply voltage V1 (e.g., receiving a high power supply voltage via the power signal line VDD). In the first transistor T1, the voltage at its gate controls the current used to drive the light-emitting device. The first source / drain electrode of the third transistor T3 is electrically connected to the first source / drain electrode of the first transistor T1 and the second capacitor electrode Cb of the storage capacitor Cst. The second source / drain electrode of the third transistor T3 is connected to the detection line SEN to connect to an external detection circuit. The third transistor T3 is configured to detect the electrical characteristics of its sub-pixel in response to a second control signal G2 to achieve external compensation. These electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and drive current of the light-emitting device EM. The external detection circuit is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), which will not be described in detail in the embodiments of this disclosure.

[0038] For example, Figure 1 The storage capacitor Cst shown also includes a third capacitor electrode Cc, which is located on the side of the first capacitor electrode Ca away from the second capacitor electrode Cb and is electrically connected to the second capacitor electrode Cb to form a parallel capacitor structure, thereby increasing the capacitance value of the storage capacitor Cst. For example, the second electrode of the light-emitting device EM is electrically connected to the power signal line VSS to receive a low power supply voltage.

[0039] The transistors used in the embodiments of this disclosure can all be thin-film transistors or other switching devices with the same characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is directly described as the first source-drain electrode, and the other as the second source-drain electrode. Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage). It should be noted that in the following description, the following terms are used interchangeably. Figure 1 The transistors described herein are exemplified by N-type transistors; however, this description is not intended to limit the scope of this disclosure.

[0040] The following is combined Figures 2A-2C The signal timing diagram shown is for Figure 1 The working principle of the pixel driving circuit shown is explained, in which... Figure 2A The following is a signal timing diagram of the pixel driving circuit during the display process. Figure 2B and Figure 2C The signal timing diagram of the pixel driving circuit during the detection process is shown.

[0041] For example, such as Figure 2A As shown, the display process of each frame of the image includes a data writing and reset phase 1 and a light emission phase 2. Figure 2A The timing waveforms of each signal in each stage are shown. One operation of the 3T1C pixel driving circuit includes: In the data writing and reset stage 1, the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, the first switch K1 is turned off, the analog-to-digital converter writes a reset signal to the first electrode (e.g., anode) of the light-emitting device EM through the detection line SEN and the third transistor T3, the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting device to the working voltage; In the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 operates in saturation and the current remains unchanged, and drives the light-emitting device to emit light.

[0042] For example, Figure 2BThe signal timing diagram of the pixel driving circuit when detecting the threshold voltage is shown. One working process of the 3T1C pixel driving circuit includes: the first control signal G1 and the second control signal G2 are both open signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light emitting device EM through the detection line SEN and the third transistor T3, the first transistor T1 is turned on and charges the node S until the first transistor T1 is turned off, and the voltage on the detection line SEN is sampled by the digital-to-analog converter to obtain the threshold voltage of the first transistor T1. This process can be performed when the display device is powered off, for example.

[0043] For example, Figure 2C The signal timing diagram of the pixel driving circuit when detecting the threshold voltage is shown. One working process of the 3T1C pixel driving circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both open signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light emitting device EM through the detection line SEN and the third transistor T3; in the second stage, the first control signal G1 is a closed signal, the second control signal G1 is an open signal, the second transistor T2 is turned off, the third transistor T3 is turned on, and the detection line SEN is floating; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 works in the saturation state and the current remains unchanged and drives the light emitting device to emit light, and then the voltage on the detection line SEN is sampled by the digital-to-analog converter, and the carrier mobility in the first transistor T1 can be calculated in combination with the size and duration of the light emitting current. For example, this process can be performed in the blanking stage between display stages.

[0044] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained and the corresponding compensation algorithm can be implemented.

[0045] For example, the peripheral region of the display substrate includes a power bus for providing a power signal for the power signal line VDD and the power signal line VSS respectively. Since the power signal line VDD is used to transmit a high-level signal, the high-level signal is prone to crosstalk with other signals transmitted on the display substrate, and therefore the arrangement of the power bus needs to be optimized.

[0046] The display substrate provided in the embodiments of the present disclosure has a display area and a peripheral area surrounding the display area at least partially, and comprises a substrate, a plurality of sub-pixels, a first power signal line, a second power signal line, a first power signal bus and a second power signal bus; the plurality of sub-pixels are arranged on the substrate and located in the display area, the first power signal line and the second power signal line are arranged on the substrate and located in the display area at least partially, the first power signal line is configured to transmit a first power signal to at least part of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least part of the plurality of sub-pixels; the first power signal bus and the second power signal bus are arranged on the substrate and located in the peripheral area, the first power signal line is electrically connected to the first power signal bus, the second power signal line is electrically connected to the second power signal bus, and the second power signal bus comprises a first part arranged on a side of the first power signal bus close to the display area and a second part arranged on a side of the first power signal bus away from the display area, so as to surround the first power signal bus at least partially.

[0047] In the display substrate provided in the embodiments of the present disclosure, in the peripheral area, the second power signal bus surrounds the first power signal bus at least partially, so that the first power signal bus can be shielded from electromagnetic interference, the signal transmission of the first power signal bus is more accurate, and the display effect of the display substrate is improved.

[0048] In the following, the display substrate provided in the embodiments of the present disclosure will be described in detail through several specific embodiments.

[0049] The display substrate provided in the embodiments of the present disclosure has a display area and a peripheral area surrounding the display area at least partially, and comprises a substrate, a plurality of sub-pixels, a first power signal line, a second power signal line, a first power signal bus and a second power signal bus; the plurality of sub-pixels are arranged on the substrate and located in the display area, the first power signal line and the second power signal line are arranged on the substrate and located in the display area at least partially, the first power signal line is configured to transmit a first power signal to at least part of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least part of the plurality of sub-pixels; the first power signal bus and the second power signal bus are arranged on the substrate and located in the peripheral area, the first power signal line is electrically connected to the first power signal bus, the second power signal line is electrically connected to the second power signal bus, and the second power signal bus comprises a first part arranged on a side of the first power signal bus close to the display area and a second part arranged on a side of the first power signal bus away from the display area, so as to surround the first power signal bus at least partially. Figure 3 A schematic plan view of the display substrate is shown, Figure 4 An enlarged schematic view of the display substrate in the area enclosed by the dashed line in Figure 3 An enlarged schematic view of the display substrate in the area enclosed by the dashed line in Figure 5 An enlarged schematic view of the display substrate in the area enclosed by the dashed line in Figure 4 An enlarged schematic view of the display substrate in the area enclosed by the dashed line in Figure 6 A partial cross-sectional schematic view of the sub-pixel of the display substrate is shown.

[0050] As shown in Figure 3 , the display substrate has a display area AA and a peripheral area NA surrounding the display area AA at least partially. In combination with Figures 3-6 , the display substrate further comprises a substrate 101, a plurality of sub-pixels SP, a first power signal line VDD, a second power signal line VSS, a first power signal bus VDB and a second power signal bus VSB.

[0051] A plurality of sub-pixels SP are disposed on the substrate 101 and located in the display region AA, for realizing display effect. The first power signal line VDD and the second power signal line VSS are disposed on the substrate 101 and at least partially located in the display region AA. The first power signal line VDD is configured to transmit a first power signal to at least part of the plurality of sub-pixels SP, and the second power signal line VSS is configured to transmit a second power signal different from the first power signal to at least part of the plurality of sub-pixels SP.

[0052] For example, in some embodiments, the potential of the first power signal is higher than the potential of the second power signal, that is, the first power signal line VDD is used to transmit a high power voltage, and the second power signal line VSS is used to transmit a low power voltage. For example, in some embodiments, the second power signal bus VSB can be grounded.

[0053] The first power signal bus VDB and the second power signal bus VSB are disposed on the substrate 101 and located in the peripheral region NA. The first power signal line VDD is electrically connected to the first power signal bus VDB to obtain the first power signal from the first power signal bus VDB. For example, in some embodiments, the first power signal line VDD can extend from the display region AA to the peripheral region NA to be electrically connected to the first power signal bus VDB. The second power signal line VSS is electrically connected to the second power signal bus VSB to obtain the second power signal from the second power signal bus VSB. For example, in some embodiments, the second power signal line VSS can extend from the display region AA to the peripheral region NA to be electrically connected to the second power signal bus VSB.

[0054] For example, as shown in Figure 4 and Figure 5 The second power signal bus VSB includes a first part VSB1 disposed on the side (lower side in the figure) of the first power signal bus VDB close to the display region AA and a second part VSB2 disposed on the side (upper side in the figure) of the first power signal bus VDB away from the display region AA, so that the second power signal bus VSB at least partially surrounds the first power signal bus VDB. In this way, the second power signal bus VSB can at least achieve the effect of shielding electromagnetic interference for the first power signal bus VDB on the opposite sides (upper and lower sides in the figure) of the first power signal bus VDB, so that the signal transmission of the first power signal bus VDB is more accurate, and the display effect of the display substrate is improved.

[0055] For example, in some embodiments, as shown in Figure 6As shown, the display substrate also includes a light-shielding layer SH, which is disposed on the substrate 101. For example, each of the plurality of sub-pixels includes a light-emitting device EM and a pixel driving circuit for driving the light-emitting device. The pixel driving circuit is disposed on the side of the light-shielding layer SH away from the substrate 101. For example, the pixel driving circuit includes a thin-film transistor (TFT). Figure 6 The thin-film transistor includes a driving transistor and a storage capacitor, among other structures. The thin-film transistor includes an active layer Ta disposed on the side of the light-shielding layer SH away from the substrate 101, a gate Tg disposed on the side of the active layer Ta away from the substrate 101, and source and drain electrodes Td and Ts disposed on the side of the gate Tg away from the substrate 101. The source and drain electrodes Td and Ts are electrically connected to the active layer Ta through vias.

[0056] For example, in the direction perpendicular to the substrate 101, that is Figure 6 In the vertical direction, the light-shielding layer SH overlaps at least partially with the active layer Ta, thereby achieving the effect of shielding the active layer Ta from light and preventing external light from shining on the active layer Ta and affecting the normal operation of the thin film transistor.

[0057] For example, such as Figure 6 As shown, the storage capacitor includes a first capacitor electrode Ca, a second capacitor electrode Cb, and a third capacitor electrode Cc. In a direction perpendicular to the substrate 101, the first capacitor electrode Ca and the second capacitor electrode Cb overlap to form a first capacitor C1, and the first capacitor electrode Ca and the third capacitor electrode Cc overlap to form a first capacitor C2. The first capacitor C1 and the first capacitor C2 are connected in parallel, thereby increasing the capacitance of the storage capacitor.

[0058] For example, such as Figure 6 As shown, the first capacitor electrode Ca is disposed in the same layer as the active layer Ta, the second capacitor electrode Cb is disposed in the same layer as the source and drain electrodes Td and Ts, and the third capacitor electrode Cc is disposed in the same layer as the light-shielding layer SH. This simplifies the fabrication process of the display substrate and avoids increasing the thickness of the display substrate by having too many functional layers, thereby facilitating the thinner design of the display substrate.

[0059] It should be noted that in the embodiments of this disclosure, "same-layer setting" means that two or more functional layers or structural layers are formed on the same layer and with the same material in the layer structure of the display substrate. That is, in the manufacturing process, the two functional layers or structural layers can be formed from the same material layer and can be formed with the same patterning process to form the required pattern and structure, thereby simplifying the manufacturing process of the display substrate.

[0060] For example, in some embodiments, the first power signal bus VDB is arranged in the same layer as the light shielding layer SH. For example, the first part VSB1 of the second power signal bus VSB is arranged in the same layer as the source / drain electrodes Td and Ts. For example, the second part VSB2 of the second power signal bus VSB is arranged in the same layer as the gate electrode Tg, so as to further simplify the manufacturing process of the display substrate, avoid the display substrate having too many structure layers, and make the display substrate thin. In addition, the first power signal bus VDB, the first part VSB1 and the second part VSB2 of the second power signal bus VSB are respectively made of different metal layers, so as to increase the distance between the first power signal bus VDB and the second power signal bus VSB, and thus avoid the short circuit and other adverse phenomena caused by the too close signal lines.

[0061] For example, in some embodiments, as shown in Figure 4 , the second power signal bus VSB further includes a third part VSB3 and a fourth part VSB4 electrically connecting the first part VSB1 and the second part VSB3, the third part VSB3 and the fourth part VSB4 are located on opposite sides of the first power signal bus VDB, for example Figure 4 , left and right sides, at this time, the first part VSB1, the second part VSB, the third part VSB3 and the fourth part VSB4 together surround the first power signal bus VDB. For example, as shown in Figure 4 , the first part VSB1, the second part VSB, the third part VSB3 and the fourth part VSB4 completely surround the first power signal bus VDB, so as to fully realize the anti-crosstalk effect of the first power signal bus VDB.

[0062] For example, in some embodiments, as shown in Figure 4 , the third part VSB3 and the fourth part VSB4 can be arranged in the same layer as the first part VSB1 and integrally connected with the first part VSB1, and the third part VSB3 and the fourth part VSB4 are electrically connected with the second part VSB2 through the via hole, so that the first part VSB1, the second part VSB, the third part VSB3 and the fourth part VSB4 of the second power signal bus VSB form an integral whole for transmitting the same low power signal, and the voltage drop of the second power signal bus VSB can be reduced.

[0063] For example, in some embodiments, as shown in Figure 4 , the third part VSB3 and the fourth part VSB4 are symmetrical in structure, that is, have substantially the same shape, size and layout, so as to keep the signal transmission performance of the left and right sides of the display substrate substantially the same, and improve the display uniformity of the display substrate.

[0064] For example, in some embodiments, as shown in Figure 5As shown, the display substrate further comprises a first power connection line DL, which can be arranged in the same layer as the first power signal bus VDB, i.e., in the same layer as the light shielding layer SH. The first power connection line DL is used to electrically connect the first power signal bus VDB and the first power signal line VDD.

[0065] For example, in some embodiments, the first power connection line DL can be arranged in the same layer as the first power signal bus VDB and integrally connected therewith.

[0066] For example, in some embodiments, as shown in Figure 5 As shown, the first power signal line VDD can be arranged in the same layer as the source and drain electrodes Td and Ts and electrically connected to the first power connection line DL through the adapter via V. For example, in some embodiments, the second power signal line VSS is arranged in the same layer as the source and drain electrodes Td and Ts and integrally connected to the first part VSB1 of the second power signal bus VSB.

[0067] For example, as shown in Figure 5 As shown, the second power signal line VSS extends from the display area AA to the peripheral area NA and is electrically connected to, e.g., integrally connected to, the first part VSB1 of the second power signal bus VSB.

[0068] For example, in some embodiments, as shown in Figure 5 As shown, in the direction perpendicular to the substrate 101, the first part VSB1 of the second power signal bus VSB at least partially overlaps the first power connection line DL, and the first part VSB1 comprises a first hollow part H1 overlapping the first power connection line DL in the direction perpendicular to the substrate 101. In this way, the overlapping area of the first power connection line DL and the first part VSB1 can be reduced, and the formation of a parasitic capacitance structure between the first power connection line DL and the first part VSB1 can be avoided, so as to avoid affecting the normal transmission of electrical signals.

[0069] For example, in some embodiments, as shown in Figure 5 As shown, the first part VSB1 of the second power signal bus VSB further comprises a second hollow part H2 that does not overlap the first power connection line DL in the direction perpendicular to the substrate 101. The second hollow part H2 can increase the area transparency and reduce the etching difference of the large-area first part VSB1 in different areas, thereby improving the etching uniformity of the large-area first part VSB1.

[0070] For example, in some embodiments, as shown in Figure 4 and Figure 5As shown, in the direction perpendicular to the substrate 101, at least one of the third portion VSB3 and the fourth portion VSB4 (for example, both the third portion VSB3 and the fourth portion VSB4) of the second power signal bus VSB at least partially overlaps with the first power connection line DL, and at least one of the third portion VSB3 and the fourth portion VSB4 (for example, both the third portion VSB3 and the fourth portion VSB4) includes a third hollow portion H3 overlapping with the first power connection line DL in the direction perpendicular to the substrate 101, so that the overlapping area of the first power connection line DL and the third portion VSB3 and the fourth portion VSB4 can be reduced.

[0071] For example, in other embodiments, the third portion VSB3 and the fourth portion VSB4 can also include a hollow portion (not shown in the figure) that does not overlap with the first power connection line DL in the direction perpendicular to the substrate 101, so as to improve the etching uniformity of the third portion VSB3 and the fourth portion VSB4.

[0072] For example, in some embodiments, as shown in Figure 5 As shown, the first power connection line DL can include a first wire portion DL1 extending in a first direction (vertical direction in the figure) and a second wire portion DL2 extending in a second direction (horizontal direction in the figure), the first direction being different from the second direction, for example, the first direction being perpendicular to the second direction. For example, in combination with Figure 4 and Figure 5 The first wire portion DL1 includes a plurality of first wires parallel to each other, and the second wire portion DL2 includes two second wires oppositely arranged and arranged on the same straight line. For example, part of the first wires are directly connected with the first power signal bus VDB, part of the first wires are connected with the second wires, and are electrically connected with the first power signal bus VDB through the second wires.

[0073] For example, in the direction perpendicular to the substrate 101, the first wire portion DL1 at least partially overlaps with the first portion VSB1 of the second power signal bus VSB and overlaps with the first hollow portion H1, and the second wire portion DL2 overlaps with at least one of the third portion VSB3 and the fourth portion VSB4 (for example, both the third portion VSB3 and the fourth portion VSB4) of the second power signal bus VSB and overlaps with the third hollow portion H3.

[0074] For example, in some embodiments, as shown in Figure 6 As shown, the display substrate further includes a planarization layer PLN and a first electrode layer. The planarization layer PLN is arranged on the side of the source and drain electrodes Td and Ts away from the substrate 101, so as to planarize the pixel driving circuit and provide a flat surface for the arrangement of the first electrode layer. In combination with Figure 4 andFigure 6 The planarization layer PLN includes a first via V1 of the first part of the exposed second power signal bus VSB, which is disposed in the peripheral area NA, and a second via V2 of the exposed source and drain electrodes Ts, which is disposed in the display area AA.

[0075] For example, such as Figure 6 As shown, the first electrode layer is disposed on the side of the planarization layer PLN away from the substrate 101, combined with... Figure 5 and Figure 6 The first electrode layer includes a first electrode E1 disposed in the display area AA and a connection electrode EL disposed in the peripheral area NA. The first electrode E1 is electrically connected to the source / drain electrode Ts through a second via V2, and the connection electrode EL is electrically connected to the first part VSB1 of the second power signal bus VSB through a first via V1. For example, the first electrode E1 can serve as the anode of the light-emitting device EM.

[0076] For example, in some embodiments, such as Figure 6 As shown, the display substrate also includes a pixel defining layer (PDL), which is disposed on the side of the first electrode layer away from the substrate 101, in conjunction with... Figure 5 and Figure 6 The pixel delimiting layer (PDL) includes a connection opening (PDL1) disposed in the peripheral area NA and a sub-pixel opening (PDL2) disposed in the display area AA. The connection opening (PDL1) exposes the connection electrode EL, and the sub-pixel opening (PDL2) exposes the first electrode E1, thereby defining the effective light-emitting area of ​​the light-emitting device EM.

[0077] For example, in some embodiments, such as Figure 6 As shown, the display substrate also includes a light-emitting material layer E2 and a second electrode layer E3. The light-emitting material layer E2 is at least partially disposed in the sub-pixel opening PDL2, and can be driven to emit light by the first electrode E1 exposed by the sub-pixel opening PDL2. The second electrode layer E3 is disposed on the side of the light-emitting material layer E2 away from the substrate 101. For example, the second electrode layer E3 can serve as the cathode of the light-emitting device EM. For example, in some embodiments, the second electrode layer E3 can be an electrode layer formed over the entire surface, that is, continuously formed in a sheet shape on the substrate and extending from the display area AA to the peripheral area NA, and electrically connected to the connection electrode EL through the connection opening PLN1, so that the second electrode layer E3 can be electrically connected to the first part VSB1 of the second power signal bus VSB to receive a low power signal.

[0078] For example, in some embodiments, such as Figure 5As shown, the second electrode layer E3 ends at a side of the first power signal bus VDB close to the display area AA, for example, the end boundary line of the second electrode layer E3 is E3D, so that the second electrode layer E3 has a spacing with the first power signal bus VDB, that is, the boundary line E3D has a spacing with the first power signal bus VDB, for example, the spacing distance is greater than 1.0 microns, for example, 1.20 microns, 1.30 microns, 1.35 microns, 1.40 microns, 1.45 microns or 1.50 microns, etc. In this way, the risk of short circuit between the second electrode layer E3 and the first power signal bus VDB can be reduced, and the yield of the display substrate can be improved.

[0079] For example, in some embodiments, the display substrate can further include structures such as a barrier layer and a buffer layer (not shown in the figure) disposed on the substrate 101 to prevent impurities from entering into the functional layers on the substrate 101. For example, as shown in FIG. 1, the display substrate can further include a barrier layer 101B and a buffer layer 101C disposed on the substrate 101. Figure 6 As shown, the display substrate can further include structures such as an insulating layer 102 disposed on the light shielding layer SH, a gate insulating layer GI disposed on the active layer Ta, an interlayer insulating layer IDL disposed on the gate Tg, a passivation layer PVX disposed on the source / drain electrodes Td and Ts, and an encapsulation layer disposed on the second electrode layer (not shown in the figure).

[0080] For example, the passivation layer PVX has a via PVX1 penetrating the second via V2 of the planarization layer PLN, so that the first electrode E1 is electrically connected to the source / drain electrode Ts through the second via V2 and the via PVX1. For example, the passivation layer PVX further includes a via PVX2 penetrating the first via V1 (see FIG. 2B), so that the connecting electrode EL is electrically connected to the first part VSB1 of the second power signal bus VSB through the first via V1 and the via PVX2. Figure 11A

[0081] For example, the encapsulation layer can be a composite encapsulation layer including a stack of multiple inorganic encapsulation layers and organic encapsulation layers, for example, a three-layer stack structure of inorganic encapsulation layer / organic encapsulation layer / inorganic encapsulation layer, to have a better encapsulation effect. For example, the display substrate can further include a cover plate (for example, a glass transparent cover plate) disposed on the encapsulation layer, and other structures on the display substrate are not specifically limited in the embodiments of the present disclosure.

[0082] ​For example, in embodiments of the present disclosure, the substrate 101 can be a rigid substrate such as glass, quartz, etc. or a flexible substrate such as polyimide (PI), etc. The materials of the active layer Ta and the first capacitor electrode Ca include, but are not limited to, silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathienyl, polythiophene, etc.). During the manufacturing process, the semiconductor material of the first capacitor electrode Ca is made conductive to have good electrical conductivity. The light shielding layer SH, the third capacitor electrode Cc, and the first power signal bus VDD can be made of metal materials such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc. or alloy materials. For example, the gate Tg and the second part VSB2 of the second power signal bus VSB can be made of metal materials such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc. or alloy materials. For example, the gate Tg and the second part VSB2 of the second power signal bus VSB can be a single-layer or multi-layer structure, such as a stacked structure of molybdenum-titanium alloy and copper, etc. For example, the source-drain electrodes Td and Ts, the second capacitor electrode Cb, and the first part VSB1, the third part VSB3, and the fourth part VSB4 of the second power signal bus VSB can be made of metal materials such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc. or alloy materials, and can also be formed as a single-layer or multi-layer structure, such as a stacked structure of molybdenum-titanium alloy and copper, etc.

[0083] For example, the insulating layer 102, the gate insulating layer GI, the interlayer insulating layer IDL, the passivation layer PVX, and the inorganic encapsulation layer can be inorganic insulating layers made of inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNy), or silicon oxynitride (SiOxNy), etc. For example, the planarization layer PLN, the pixel definition layer PDL, and the organic encapsulation layer can be organic insulating layers made of organic insulating materials such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc.

[0084] For example, the first electrode E1 and the connecting electrode EL can adopt a material with a high work function, such as a transparent metal oxide, for example, ITO, IZO, or the like. For example, the first electrode E1 can further include a metal layer of Ag or the like, so as to form a multi-layer structure of the transparent metal oxide / metal layer. For example, the light-emitting material layer E2 can include an organic light-emitting material, so that the light-emitting device EM is formed as an organic light-emitting device (OLED); or in other embodiments, the light-emitting material layer E2 can also include a quantum dot light-emitting material, so that the light-emitting device EM is formed as a quantum dot device (QLED). For example, the second electrode layer E3 can adopt a metal material or an alloy material, such as magnesium (Mg), lithium (Li), aluminum (Al), silver (Ag), or the like. Embodiments of the present disclosure do not limit the materials of the various functional layers.

[0085] For example, Figures 7-13B The partial planar schematic diagrams of the various functional layers of the display substrate and the partial planar schematic diagram of the various functional layers being sequentially stacked are shown. Hereinafter, the relative positional relationship of the various functional layers of the display substrate is introduced with reference to the structure shown. Figures 7-13B The structure shown is taken as an example to introduce the various functional layers of the display substrate and the relative positional relationship thereof.

[0086] For example, Figure 7 The partial planar schematic diagram of the first conductive layer where the light-blocking layer SH is located is shown. As shown in Figure 7 The first conductive layer includes the light-blocking layer SH, the first power signal bus VDB, the first power signal connecting line DL, and the like.

[0087] For example, in the preparation process, a sputtering process can be adopted to form the material of the first conductive layer on the substrate 101, and a photolithography process is performed to pattern the material of the first conductive layer, so as to obtain the patterns of the light-blocking layer SH, the first power signal bus VDB, the first power signal connecting line DL, and the like.

[0088] For example, the photolithography process can include the processes of coating, exposure, development, and etching of photoresist, and specific details can be referred to related technologies, which are not described herein again.

[0089] For example, referring to Figure 6 The insulating layer 102 can be formed on the first conductive layer. In the preparation process, a deposition process can be adopted to form the material of the insulating layer 102, which can include one or more of SiNx, SiOx, or SiOxNy, and the thickness can be 150 nm-500 nm, for example, 200 nm, 300 nm, or 400 nm, or the like.

[0090] For example, in the preparation process, a sputtering process can be used to form a semiconductor oxide, such as IGZO, ZnON, ITZO, etc. amorphous oxide, on the insulating layer 102 to form a semiconductor material layer, and a photolithography process is used to pattern the semiconductor material layer to form the pattern of the active layer Ta and the first capacitor electrode Ca. For example, subsequent conductorization treatment, such as doping treatment, can be performed on the pattern of the first capacitor electrode Ca and part of the pattern of the active layer Ta to have good conductivity.

[0091] For example, in the preparation process, a deposition process can be used to form the material of the gate insulating layer GI, and a sputtering process is used to form the material of the second conductive layer on the material of the gate insulating layer GI. The deposition thickness of the material of the second conductive layer can be 200-1000 nm, such as 400 nm, 600 nm, or 800 nm, etc. and a photolithography process is used to form the gate Tg and the second part VSB2 of the second power signal bus VSB, as shown in Figure 8A For example, the photoresist pattern used in the above photolithography process can not be stripped. The photoresist pattern can be used as a mask to etch the material of the gate insulating layer GI to form the pattern of the gate insulating layer GI by using a dry etching process, and the exposed semiconductor material layer is treated by using NH 3 , N 2 or H 2 gas to make the treated semiconductor material layer have good conductivity.

[0092] For example, Figure 8B shows a partial plan view of the second conductive layer and the first conductive layer, as shown in Figure 8B , the second part VSB2 of the second power signal bus VSB is located on the side of the first power signal bus VDB away from the display area AA.

[0093] For example, Figure 9A shows a partial plan view of the interlayer insulating layer IDL, as shown in FIG. 9, the interlayer insulating layer IDL includes a via VS1 for electrically connecting the third part VSB3 (and the fourth part VSB4) and the second part VSB2 of the second power signal bus VSB, and a via VS2 for electrically connecting the source / drain electrode Ts / Td and the active layer Ta.

[0094] For example, in the preparation process, a deposition process can be used to deposit the material of the interlayer insulating layer IDL on the second conductive layer, and a dry etching process is used to obtain the via VS1 and the via VS2. For example, the material of the interlayer insulating layer IDL can be a single layer or a multi-layer structure formed by SiNx or SiOx.

[0095] For example, Figure 9BA partial plan view of the interlayer dielectric layer IDL and the second conductive layer, the first conductive layer is shown in FIG. 2A, for example. The via VS1 exposes the second portion VSB2 of the second power signal bus VSB, and the via VS2 exposes the active layer Ta. Figure 9B As shown in FIG. 2B, for example, the via VS1 exposes the second portion VSB2 of the second power signal bus VSB, and the via VS2 exposes the active layer Ta.

[0096] For example, in the preparation process, a sputtering process can be used to form the material of the third conductive layer on the interlayer dielectric layer IDL, and the deposition thickness of the material of the third conductive layer can be 200nm-1000nm. The source / drain electrodes Ts / Td and the first power signal line VDD, the second power signal line VSS, the first portion VSB1, the third portion VSB3 (and the fourth portion VSB4) of the second power signal bus VSB are formed by a photolithography process, as shown in FIG. 3A, for example. For example, the first portion VSB1 has a first hollow portion H1 and a second hollow portion H2, and the third portion VSB3 (and the fourth portion VSB4) has a third hollow portion H3. Figure 10A

[0097] For example, as shown in FIG. 3B, for example, the third conductive layer and the interlayer dielectric layer IDL, the second conductive layer, the first conductive layer are stacked in a partial plan view. Figure 10B As shown in FIG. 3B, for example, the third portion VSB3 (and the fourth portion VSB4) of the second power signal bus VSB is electrically connected to the second portion VSB2 through the via VS1, and the source / drain electrodes Ts / Td are electrically connected to the active layer Ta through the via VS2, which is not specifically shown in the figure, and can be referred to FIG. 2B. Figure 10B Figure 6

[0098] For example, as shown in FIG. 4A, for example, the third conductive layer and the interlayer dielectric layer IDL, the second conductive layer, the first conductive layer are stacked in a partial plan view. Figure 11A As shown in FIG. 4B, for example, the third portion VSB3 (and the fourth portion VSB4) of the second power signal bus VSB is electrically connected to the second portion VSB2 through the via VS1, and the source / drain electrodes Ts / Td are electrically connected to the active layer Ta through the via VS2, which is not specifically shown in the figure, and can be referred to FIG. 2B.

[0099] For example, the material of the passivation layer PVX, such as SiO2, can be formed on the third conductive layer by a deposition process, and the pattern of the passivation layer PVX is formed by a photolithography process. The passivation layer PVX includes a via PVX1 exposing the source / drain electrode Ts in the display area AA and a via PXV2 exposing the first portion VSB1 in the non-display area NA.

[0100] For example, as shown in FIG. 5A, for example, the third conductive layer and the interlayer dielectric layer IDL, the second conductive layer, the first conductive layer are stacked in a partial plan view. Figure 11B ​​​A partial plan view of the passivation layer PVX and the planarization layer PLN and the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer is shown in FIG. 6A. As shown in FIG. 6A, the first via V1 and the via PXV2 expose the first portion VSB1 in the peripheral region NA. In the display region AA, the second via V2 and the via PVX1 expose the source / drain electrode Ts, Figure 11B As shown in FIG. 6B, the first via V1 and the via PXV2 expose the first portion VSB1 in the peripheral region NA. In the display region AA, the second via V2 and the via PVX1 expose the source / drain electrode Ts, Figure 11B As shown in FIG. 6B, the first via V1 and the via PXV2 expose the first portion VSB1 in the peripheral region NA. In the display region AA, the second via V2 and the via PVX1 expose the source / drain electrode Ts, Figure 6 .

[0101] For example, a partial plan view of the first electrode layer is shown in FIG. 5A. As shown in FIG. 5A, the first electrode layer includes the first electrode E1 in the display region AA and the connection electrode EL in the peripheral region NA. In the manufacturing process, a sputtering process can be used to form a material of the first electrode layer on the planarization layer PLN, and the thickness of the material is about 100 nm-600 nm, for example, 200 nm, 300 nm, 400 nm, or 500 nm, etc., and a photolithography process is used to obtain the pattern of the first electrode E1 and the connection electrode EL. Figure 12A Figure 12A For example, a partial plan view of the first electrode layer is shown in FIG. 5A. As shown in FIG. 5A, the first electrode layer includes the first electrode E1 in the display region AA and the connection electrode EL in the peripheral region NA. In the manufacturing process, a sputtering process can be used to form a material of the first electrode layer on the planarization layer PLN, and the thickness of the material is about 100 nm-600 nm, for example, 200 nm, 300 nm, 400 nm, or 500 nm, etc., and a photolithography process is used to obtain the pattern of the first electrode E1 and the connection electrode EL.

[0102] For example, a partial plan view of the first electrode layer is shown in FIG. 5A. As shown in FIG. 5A, the first electrode layer includes the first electrode E1 in the display region AA and the connection electrode EL in the peripheral region NA. In the manufacturing process, a sputtering process can be used to form a material of the first electrode layer on the planarization layer PLN, and the thickness of the material is about 100 nm-600 nm, for example, 200 nm, 300 nm, 400 nm, or 500 nm, etc., and a photolithography process is used to obtain the pattern of the first electrode E1 and the connection electrode EL. Figure 12B For example, a partial plan view of the first electrode layer is shown in FIG. 5A. As shown in FIG. 5A, the first electrode layer includes the first electrode E1 in the display region AA and the connection electrode EL in the peripheral region NA. In the manufacturing process, a sputtering process can be used to form a material of the first electrode layer on the planarization layer PLN, and the thickness of the material is about 100 nm-600 nm, for example, 200 nm, 300 nm, 400 nm, or 500 nm, etc., and a photolithography process is used to obtain the pattern of the first electrode E1 and the connection electrode EL. Figure 12B As shown in FIG. 6B, the first via V1 and the via PXV2 expose the first portion VSB1 in the peripheral region NA. In the display region AA, the second via V2 and the via PVX1 expose the source / drain electrode Ts, Figure 12B As shown in FIG. 6B, the first via V1 and the via PXV2 expose the first portion VSB1 in the peripheral region NA. In the display region AA, the second via V2 and the via PVX1 expose the source / drain electrode Ts, Figure 6 .

[0103] For example, a partial plan view of the first electrode layer is shown in FIG. 5A. As shown in FIG. 5A, the first electrode layer includes the first electrode E1 in the display region AA and the connection electrode EL in the peripheral region NA. In the manufacturing process, a sputtering process can be used to form a material of the first electrode layer on the planarization layer PLN, and the thickness of the material is about 100 nm-600 nm, for example, 200 nm, 300 nm, 400 nm, or 500 nm, etc., and a photolithography process is used to obtain the pattern of the first electrode E1 and the connection electrode EL. Figure 13A For example, a partial plan view of the first electrode layer is shown in FIG. 5A. As shown in FIG. 5A, the first electrode layer includes the first electrode E1 in the display region AA and the connection electrode EL in the peripheral region NA. In the manufacturing process, a sputtering process can be used to form a material of the first electrode layer on the planarization layer PLN, and the thickness of the material is about 100 nm-600 nm, for example, 200 nm, 300 nm, 400 nm, or 500 nm, etc., and a photolithography process is used to obtain the pattern of the first electrode E1 and the connection electrode EL. Figure 6 For example, a partial plan view of the first electrode layer is shown in FIG. 5A. As shown in FIG. 5A, the first electrode layer includes the first electrode E1 in the display region AA and the connection electrode EL in the peripheral region NA. In the manufacturing process, a sputtering process can be used to form a material of the first electrode layer on the planarization layer PLN, and the thickness of the material is about 100 nm-600 nm, for example, 200 nm, 300 nm, 400 nm, or 500 nm, etc., and a photolithography process is used to obtain the pattern of the first electrode E1 and the connection electrode EL.

[0104] ​For example, in the preparation process, the material of the pixel definition layer PLN can be formed by a coating process. After pre-baking, exposure, development and other processes, the pattern of the pixel definition layer PLN, such as the connection opening PDL1 and the sub-pixel opening PDL2, is formed. Then, the pixel definition layer PLN is removed by post-baking at 230 degrees to remove water and organic solvents in the pixel definition layer PLN. Finally, the pixel definition layer PLN with a thickness of 1.8-2.0 μm is formed.

[0105] For example, Figure 13B A partial plan view of the pixel definition layer PLN and the first electrode layer, the passivation layer PVX, the planarization layer PLN, the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer is shown as follows. Figure 13B As shown, the connection opening PDL1 exposes the connection electrode EL, so that the second electrode layer E2 formed subsequently is electrically connected to the connection electrode EL through the connection opening PDL1.

[0106] For example, the display substrate further has a light-emitting material layer E2 (formed by, for example, inkjet printing), a second electrode layer E3 (formed by, for example, sputtering), an encapsulation layer and other structures. The formation method and specific structure of the structures can refer to the description of related technologies and Figure 6 and will not be described here.

[0107] In the embodiments of the present disclosure, the second power signal line VSS and the first power signal line VDD in the display area AA are both arranged in the same layer as the source-drain electrodes Ts and Td, the first power signal line VDD is connected to the first power signal bus VDB through a via, the first power signal bus VDB is arranged in the same layer as the light shielding layer SH, and different parts of the second power signal bus VSB are arranged in the same layer as the gate electrode Tg and the source-drain electrodes Ts / Td respectively, so that the distance between the high and low power signal lines can be increased, and meanwhile, the first power signal bus VDB is away from the second electrode layer E3, so that the first power signal bus VDB can be prevented from being short-circuited with the second electrode layer E3, and the yield of the display substrate is improved; different parts of the second power signal bus VSB are arranged on the side close to the display area AA and the side away from the display area AA respectively, so as to at least partially surround the first power signal bus VDB, and the first power signal bus VDB can be provided with an electromagnetic shielding effect; the second electrode layer E3 is electrically connected with the second power signal bus VSB through a connection opening in the pixel definition layer PDL and a connection electrode EL arranged in the same layer as the first electrode E1, which is conducive to the lapping of the second electrode layer E3 and the second power signal bus VSB; in addition, the first power connection line DL electrically connected with the first power signal bus VDB is designed with a groove at the overlapping position with the second power signal bus VSB, that is, the second power signal bus VSB has a first hollow part and a third hollow part, so that the parasitic capacitance can be avoided; the second power signal bus VSB arranged in a large area further has a second hollow part, so that the transparent area can be increased and the etching difference can be reduced, thereby ensuring the yield of the display substrate and improving the display effect.

[0108] In summary, the display substrate provided by the embodiments of the present disclosure can achieve narrow frame and large screen while having better display effect and production yield.

[0109] The following points need to be explained:

[0110] (1) The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0111] (2) For the sake of clarity, the thickness of a layer or region is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure, that is, the drawings are not drawn according to the actual proportion. It can be understood that when an element such as a layer, a film, a region or a substrate is referred to as being located “on” or “under” another element, the element can be “directly” located on or under another element or there can be an intermediate element.

[0112] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0113] The above merely describes a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising: Substrate Multiple sub-pixels are disposed on the substrate and located in the display area. A first power signal line and a second power signal line are disposed on the substrate and at least partially located in the display area, wherein the first power signal line is configured to transmit a first power signal to at least a portion of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least a portion of the plurality of sub-pixels. A first power signal bus and a second power signal bus are disposed on the substrate and located in the peripheral region, wherein the first power signal line is electrically connected to the first power signal bus, and the second power signal line is electrically connected to the second power signal bus. The second power signal bus includes a first portion disposed on the side of the first power signal bus closer to the display area and a second portion disposed on the side of the first power signal bus farther from the display area, so as to at least partially surround the first power signal bus.

2. The display substrate according to claim 1, further comprising: A light-shielding layer is disposed on the substrate. Each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device, wherein the pixel driving circuit is disposed on the side of the light-shielding layer away from the substrate. The first power signal bus is disposed on the same layer as the light-shielding layer.

3. The display substrate according to claim 2, wherein, The pixel driving circuit includes a thin-film transistor, the thin-film transistor including a gate disposed on the side of the light-shielding layer away from the substrate and source / drain electrodes located on the side of the gate away from the substrate. The first part is disposed in the same layer as the source and drain electrodes.

4. The display substrate according to claim 3, wherein, The second part is disposed on the same layer as the gate.

5. The display substrate according to any one of claims 1-4, wherein, The second power signal bus further includes a third part and a fourth part electrically connected to the first part and the second part, the third part and the fourth part being located on opposite sides of the first power signal bus. The first part, the second part, the third part, and the fourth part together surround the first power signal bus.

6. The display substrate according to claim 5, wherein, The third and fourth parts are disposed on the same layer as the first part and are integrally connected to the first part.

7. The display substrate according to claim 5, wherein, The third and fourth parts are structurally symmetrical.

8. The display substrate according to claim 3, further comprising: The first power connection line is disposed on the same layer as the first power signal bus and is electrically connected to the first power signal bus and the first power signal line.

9. The display substrate according to claim 8, wherein, The first power signal line is disposed on the same layer as the source and drain electrodes, and is electrically connected to the first power connection line through an adapter via.

10. The display substrate according to claim 3, wherein, The second power signal line is disposed on the same layer as the source and drain electrodes.

11. The display substrate according to claim 10, wherein, The second power signal line extends from the display area to the surrounding area and is electrically connected to the first part.

12. The display substrate according to any one of claims 1-4, wherein, The potential of the first power signal is higher than the potential of the second power signal.

13. The display substrate according to claim 3, further comprising: A planarization layer is disposed on the side of the source / drain electrodes away from the substrate, including a first via disposed in the peripheral region exposing the first portion and a second via disposed in the display area exposing the source / drain electrodes. A first electrode layer is disposed on the side of the planarization layer away from the substrate, including a first electrode disposed in the display area and a connection electrode disposed in the peripheral area. The first electrode is electrically connected to the source / drain electrode through a second via, and the connection electrode is electrically connected to the first portion through the first via.

14. The display substrate according to claim 13, further comprising: A pixel defining layer is disposed on the side of the first electrode layer away from the substrate, including a connection opening disposed in the peripheral region and a sub-pixel opening disposed in the display region, wherein the connection opening exposes the connection electrode and the sub-pixel opening exposes the first electrode.

15. The display substrate according to claim 14, further comprising: A light-emitting material layer is at least partially disposed within the sub-pixel opening. The second electrode layer is disposed on the side of the light-emitting material layer away from the substrate, extends from the display area to the peripheral area, and is electrically connected to the connection electrode through the connection opening.

16. The display substrate according to claim 15, wherein, The second electrode layer terminates on the side of the first power signal bus closest to the display area and is spaced apart from the first power signal bus.

17. The display substrate according to claim 8, wherein, In a direction perpendicular to the substrate, the first portion at least partially overlaps with the first power connection line, and the first portion includes a first cutout portion that overlaps with the first power connection line in a direction perpendicular to the substrate.

18. The display substrate according to claim 17, wherein, The first part further includes a second cutout portion that does not overlap with the first power connection line in a direction perpendicular to the substrate.

19. The display substrate according to claim 17, wherein, The second power signal bus further includes a third part and a fourth part electrically connecting the first part and the second part. In a direction perpendicular to the substrate, at least one of the third part and the fourth part at least partially overlaps with the first power connection line, and at least one of the third part and the fourth part includes a third cutout portion that overlaps with the first power connection line in a direction perpendicular to the substrate.

20. The display substrate according to claim 19, wherein, The first power connection cable includes a first trace portion extending along a first direction and a second trace portion extending along a second direction, wherein the first direction is different from the second direction. In a direction perpendicular to the substrate, the first trace portion overlaps at least partially with the first portion and with the first cutout portion, and the second trace portion overlaps with at least one of the third portion and the fourth portion, and with the third cutout portion.

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