Pixel circuit, pixel driving method and display device

Abstract

A pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a first light-emitting control circuit (11), a driving circuit (12), a second light-emitting control circuit (13), a reset control circuit (20) and a light-emitting element (10); the reset control circuit (20) is electrically connected with a reset control line (R0), a connection node and a first initial voltage terminal (I1) for providing a first initial voltage (Vi1) respectively, and is configured to provide the first initial voltage (Vi1) to the connection node under the control of a reset control signal provided by the reset control line (R0); the connection node is a first node (N1), a third node (N3) or a fourth node (N4).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] When the relevant pixel circuit is working, during the non-light-emitting stage, the parasitic capacitance of the first node (which can be a node electrically connected to the first end of the driving circuit) will retain the charge from the previous light-emitting stage. At the same time, due to the leakage of the transistor included in the first light-emitting control circuit, when the first voltage terminal re-enters the light-emitting stage, the first node will have a certain amount of charge accumulation, causing the brightness to increase within the same display cycle, thus forming a flicker. Summary of the Invention

[0003] The main objective of this invention is to provide a pixel circuit, a pixel driving method, and a display device to solve the problem of brightness increasing within the same display cycle in related technologies, which causes flickering.

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a first light-emitting control circuit, a driving circuit, a second light-emitting control circuit, a reset control circuit, and a light-emitting element;

[0005] The first light-emitting control circuit is electrically connected to the light-emitting control line, the first voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the first node under the control of the light-emitting control signal provided by the light-emitting control line.

[0006] The control terminal of the driving circuit is electrically connected to the second node, the first terminal of the driving circuit is electrically connected to the first node, and the second terminal of the driving circuit is electrically connected to the third node; the driving circuit is used to control the generation of a driving current to drive the light-emitting element under the control of the potential of its control terminal.

[0007] The second light-emitting control circuit is electrically connected to the light-emitting control line, the third node, and the fourth node respectively, and is used to control the connection or disconnection between the third node and the fourth node under the control of the light-emitting control signal;

[0008] The first electrode of the light-emitting element is electrically connected to the fourth node, and the second electrode of the light-emitting element is electrically connected to the second voltage terminal;

[0009] The reset control circuit is electrically connected to the reset control line, the connection node, and the first initial voltage terminal for providing the first initial voltage, and is used to provide the first initial voltage to the connection node under the control of the reset control signal provided by the reset control line.

[0010] The connection node is the first node, the third node, or the fourth node.

[0011] Optionally, the reset control circuit is also electrically connected to the fifth node, and is used to control the connection or disconnection between the first initial voltage terminal and the fifth node under the control of the reset control signal, and to control the disconnection or connection between the fifth node and the connection node, and to maintain the potential of the fifth node.

[0012] Optionally, the reset control circuit includes a first control circuit, a second control circuit, and a first energy storage circuit;

[0013] The first control circuit is electrically connected to the reset control line, the connection node, and the fifth node, respectively, and is used to control the connection node and the fifth node to be connected or disconnected under the control of the reset control signal;

[0014] The second control circuit is electrically connected to the reset control line, the fifth node, and the first initial voltage terminal, respectively, and is used to control the writing of the first initial voltage provided by the first initial voltage terminal into the fifth node under the control of the reset control signal;

[0015] The first energy storage circuit is electrically connected to the fifth node and is used to store electrical energy.

[0016] Optionally, the reset control line is the light emission control line; or, the reset control signal provided by the reset control line is the same as the light emission control signal provided by the light emission control line.

[0017] Optionally, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0018] The control electrode of the first transistor is electrically connected to the reset control line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the third node.

[0019] The control electrode of the second transistor is electrically connected to the reset control line, the first electrode of the second transistor is electrically connected to the first initial voltage terminal, and the second electrode of the second transistor is electrically connected to the fifth node.

[0020] Optionally, the first transistor is an oxide thin-film transistor, and the second transistor is a low-temperature polycrystalline silicon thin-film transistor.

[0021] Optionally, the first energy storage circuit includes a first capacitor;

[0022] The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal.

[0023] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit, and a second initialization circuit.

[0024] The data writing circuit is electrically connected to the write control line, the data line and the first node respectively, and is used to write the data voltage provided by the data line to the first node under the control of the write control signal provided by the write control line.

[0025] The compensation control circuit is electrically connected to the compensation control line, the control terminal of the drive circuit, and the second terminal of the drive circuit, respectively, and is used to control the connection or disconnection between the control terminal of the drive circuit and the second terminal of the drive circuit under the control of the compensation control signal provided by the compensation control line;

[0026] The first initialization circuit is electrically connected to the initialization control line, the second initial voltage terminal, and the control terminal of the drive circuit, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the control terminal of the drive circuit under the control of the initialization control signal provided by the initialization control line.

[0027] The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy;

[0028] The second initialization circuit is electrically connected to the write control line, the third initial voltage terminal and the fourth node respectively, and is used to write the third initial voltage provided by the third initial voltage terminal to the fourth node under the control of the write control signal.

[0029] Optionally, the first light-emitting control circuit includes a third transistor, the second light-emitting control circuit includes a fourth transistor, and the driving circuit includes a driving transistor;

[0030] The control electrode of the third transistor is electrically connected to the light-emitting control line, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first node.

[0031] The control electrode of the fourth transistor is electrically connected to the light-emitting control line, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0032] The control electrode of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the third node.

[0033] Optionally, the data writing circuit includes a fifth transistor, the compensation control circuit includes a sixth transistor, the first initialization circuit includes a seventh transistor, the second initialization circuit includes an eighth transistor, and the second energy storage circuit includes a second capacitor.

[0034] The control electrode of the fifth transistor is electrically connected to the write control line, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the first terminal of the drive circuit.

[0035] The control electrode of the sixth transistor is electrically connected to the compensation control line, the first electrode of the sixth transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the second terminal of the driving circuit.

[0036] The control electrode of the seventh transistor is electrically connected to the initialization control line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the control terminal of the driving circuit.

[0037] The control electrode of the eighth transistor is electrically connected to the write control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node mentioned above.

[0038] The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the first voltage terminal.

[0039] In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, wherein the display cycle includes a non-emissive phase and an emissive phase; the pixel driving method includes:

[0040] During the non-light-emitting phase, the reset control circuit, under the control of the reset control signal, provides the first initial voltage to the connection node.

[0041] Optionally, the reset control circuit includes a first control circuit, a second control circuit, and a first energy storage circuit; the pixel driving method includes:

[0042] During the light-emitting stage, the second control circuit, under the control of the reset control signal, writes the first initial voltage into the fifth node, and the first energy storage circuit stores the first initial voltage in the fifth node.

[0043] During the non-light-emitting phase, the first control circuit, under the control of the reset control signal, controls the connection between the fifth node and the connection node to write the first initial voltage into the connection node.

[0044] Optionally, the pixel circuit further includes a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit, and a second initialization circuit; the display cycle includes a first display stage comprising a sequentially set initialization stage, a compensation stage, and a light emission stage, the compensation stage including a data writing stage; the pixel driving method includes:

[0045] During the initialization phase, the first initialization circuit, under the control of the reset control signal, writes the second initial voltage into the control terminal of the drive circuit, so that at the start of the compensation phase, the drive circuit can control the connection between the first node and the third node under the control of the potential of its control terminal.

[0046] During the data writing phase, the data line provides a data voltage Vdata, and the data writing circuit writes the data voltage Vdata into the first node under the control of the write control signal.

[0047] During the compensation phase, the compensation control circuit controls the connection between the second node and the third node under the control of the compensation control signal.

[0048] During the light-emitting stage, the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal, the second light-emitting control circuit controls the connection between the third node and the fourth node under the control of the light-emitting control signal, and the driving circuit generates a driving current to drive the light-emitting element.

[0049] Optionally, the pixel circuit further includes a data writing circuit; the non-light-emitting phase includes a data writing phase; the display frame includes a refresh sub-display frame and at least one hold sub-display frame; the refresh sub-display frame includes the display period, and the hold sub-display frame includes the display period; the pixel driving method further includes:

[0050] In the holding sub-display frame, the data line provides a first voltage signal;

[0051] During the data writing phase of the holding sub-display frame, the data writing circuit writes the first voltage signal to the first node under the control of the write control signal.

[0052] Optionally, the pixel circuit further includes a compensation control circuit; the display cycle further includes a compensation phase; and the pixel driving method further includes:

[0053] During the data writing phase of the refresh sub-display frame, the data line provides a data voltage, and the data writing circuit writes the data voltage to the first node under the control of the write control signal.

[0054] During the compensation phase of the refresh sub-display frame, the compensation control circuit, under the control of the compensation control signal, controls the connection between the control terminal of the drive circuit and the second terminal of the drive circuit.

[0055] During the light-emitting phase in the refresh sub-display frame and the light-emitting phase in the hold sub-display frame, the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal, the second light-emitting control circuit controls the connection between the third node and the fourth node under the control of the light-emitting control signal, and the driving circuit generates the driving current to drive the light-emitting element.

[0056] During the holding sub-display frame, the compensation control circuit, under the control of the compensation control signal, controls the disconnection between the control terminal of the drive circuit and the second terminal of the drive circuit.

[0057] Optionally, in the display frame, the frequency of the write control signal is less than the frequency of the light emission control signal.

[0058] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above.

[0059] The pixel circuit, pixel driving method, and display device described in the embodiments of the present invention can suppress the phenomenon of increasing brightness within the same display cycle, thereby improving the flicker phenomenon. Attached Figure Description

[0060] Figure 1 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0061] Figure 2 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 3 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0063] Figure 4 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0064] Figure 5 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0065] Figure 6 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0066] Figure 7 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0067] Figure 8This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0068] Figure 9 This is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0069] Figure 10 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] Figure 11 This is a public announcement. Figure 10 The timing diagram of at least one embodiment of the pixel circuit shown;

[0071] Figure 12 This is a public announcement Figure 10 The timing diagram of at least one embodiment of the pixel circuit shown;

[0072] Figure 13 This is a public announcement. Figure 10 The timing diagram of at least one embodiment of the pixel circuit shown;

[0073] Figure 14 This is a public announcement Figure 10 A schematic diagram of brightness differences when switching frequencies in at least one embodiment of the pixel circuit shown;

[0074] Figure 15 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] Figure 16 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] Figure 17 This is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Detailed Implementation

[0077] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0078] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0079] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0080] The pixel circuit described in this embodiment includes a first light-emitting control circuit, a driving circuit, a second light-emitting control circuit, a reset control circuit, and a light-emitting element;

[0081] The first light-emitting control circuit is electrically connected to the light-emitting control line, the first voltage terminal, and the first node, respectively, and is used to control the connection or disconnection between the first voltage terminal and the first node under the control of the light-emitting control signal provided by the light-emitting control line.

[0082] The control terminal of the driving circuit is electrically connected to the second node, the first terminal of the driving circuit is electrically connected to the first node, and the second terminal of the driving circuit is electrically connected to the third node; the driving circuit is used to control the generation of a driving current to drive the light-emitting element under the control of the potential of its control terminal.

[0083] The second light-emitting control circuit is electrically connected to the light-emitting control line, the third node, and the fourth node respectively, and is used to control the connection or disconnection between the third node and the fourth node under the control of the light-emitting control signal;

[0084] The first electrode of the light-emitting element is electrically connected to the fourth node, and the second electrode of the light-emitting element is electrically connected to the second voltage terminal;

[0085] The reset control circuit is electrically connected to the reset control line, the connection node, and the first initial voltage terminal for providing the first initial voltage, and is used to provide the first initial voltage to the connection node under the control of the reset control signal provided by the reset control line.

[0086] The connection node is the first node, the third node, or the fourth node.

[0087] When the pixel circuit described in the embodiments of this disclosure is working, the display cycle may include a non-light-emitting phase and a light-emitting phase;

[0088] During the non-light-emitting phase, the reset control circuit, under the control of the reset control signal, provides the first initial voltage to the connection node. This allows the excess charge accumulated by the first node to be canceled by the first initial voltage provided to the connection node when entering the light-emitting phase. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time, but is not limited to this) is suppressed, and the flicker phenomenon is improved.

[0089] In at least one embodiment of this disclosure, the first voltage terminal may be a high voltage terminal and the second voltage terminal may be a low voltage terminal, but this is not a limitation.

[0090] Optionally, the light-emitting element may be an organic light-emitting diode, but is not limited thereto.

[0091] In at least one embodiment of this disclosure, the non-light-emitting phase may include, but is not limited to, the time period included in the display cycle other than the light-emitting phase.

[0092] In at least one embodiment of this disclosure, the reset control line is the light emission control line; or, the reset control signal provided by the reset control line is the same as the light emission control signal provided by the light emission control line; but this is not a limitation.

[0093] In at least one embodiment of this disclosure, the reset control circuit is also electrically connected to the fifth node, and is used to control the connection or disconnection between the first initial voltage terminal and the fifth node under the control of the reset control signal, and to control the disconnection or connection between the fifth node and the connection node, and to maintain the potential of the fifth node.

[0094] Optionally, the voltage value of the first initial voltage may be greater than or equal to -3V and less than or equal to -2.3V. For example, the voltage value of the first initial voltage may be -3V, -2.3V, -2.4V, -2.5V or -2.8V, but is not limited thereto.

[0095] like Figure 1 As shown, the pixel circuit described in at least one embodiment of this disclosure includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit 20, and a light-emitting element 10;

[0096] The first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first voltage terminal V1 and the first node N1 under the control of the light-emitting control signal provided by the light-emitting control line E1; the first voltage terminal V1 is used to provide a first voltage signal.

[0097] The control terminal of the driving circuit 12 is electrically connected to the second node N2, the first terminal of the driving circuit 12 is electrically connected to the first node N1, and the second terminal of the driving circuit 12 is electrically connected to the third node N3; the driving circuit is used to control the generation of driving current to drive the light-emitting element 10 under the control of the potential of its control terminal.

[0098] The second light-emitting control circuit 13 is electrically connected to the light-emitting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the connection between the third node N3 and the fourth node N4 under the control of the light-emitting control signal;

[0099] The first electrode of the light-emitting element 10 is electrically connected to the fourth node N4, and the second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2;

[0100] The reset control circuit 20 is electrically connected to the reset control line R0, the third node N3, and the first initial voltage terminal I1 for providing the first initial voltage Vi1, and is used to provide the first initial voltage Vi1 to the third node N3 under the control of the reset control signal provided by the reset control line R0.

[0101] exist Figure 1 In at least one embodiment of the pixel circuit shown, the connection node is a third node N3.

[0102] exist Figure 1 In at least one embodiment of the pixel circuit shown, the reset control line may be the light emission control line, or the reset control signal provided by the reset control line and the light emission control signal provided by the light emission control line may be the same control signal, but this is not a limitation.

[0103] This disclosure is as follows Figure 1 In at least one embodiment of the pixel circuit shown, the display cycle includes a light-emitting phase and a non-light-emitting phase during operation;

[0104] During the non-light-emitting phase, the reset control circuit 20, under the control of the reset control signal, provides the first initial voltage Vi1 to the third node N3 to reset the potential of the third node N3. This allows the excess charge accumulated in the first node N1 to be canceled out by the reset low potential when it flows through the third node N3 again during the light-emitting phase. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, improving the flicker problem.

[0105] like Figure 2 As shown, the pixel circuit described in at least one embodiment of this disclosure includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit 20, and a light-emitting element 10;

[0106] The first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first voltage terminal V1 and the first node N1 under the control of the light-emitting control signal provided by the light-emitting control line E1; the first voltage terminal V1 is used to provide a first voltage signal.

[0107] The control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current to drive the light-emitting element 10 under the control of the potential of its control terminal.

[0108] The second light-emitting control circuit 13 is electrically connected to the light-emitting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the connection between the third node N3 and the fourth node N4 under the control of the light-emitting control signal;

[0109] The first electrode of the light-emitting element 10 is electrically connected to the fourth node N4, and the second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2;

[0110] The reset control circuit 20 is electrically connected to the reset control line R0, the first node N1, and the first initial voltage terminal I1 for providing the first initial voltage Vi1, and is used to provide the first initial voltage Vi1 to the first node N1 under the control of the reset control signal provided by the reset control line R0.

[0111] exist Figure 2 In at least one embodiment of the pixel circuit shown, the connection node is a first node N1.

[0112] exist Figure 2 In at least one embodiment of the pixel circuit shown, the reset control line may be the light emission control line, or the reset control signal provided by the reset control line and the light emission control signal provided by the light emission control line may be the same control signal, but this is not a limitation.

[0113] This disclosure is as follows Figure 2 In at least one embodiment of the pixel circuit shown, the display cycle includes a light-emitting phase and a non-light-emitting phase during operation;

[0114] During the non-light-emitting phase, the reset control circuit 20, under the control of the reset control signal, provides the first initial voltage Vi1 to the first node N1, so that when the light-emitting phase is entered again, the excess charge accumulated by the first node N1 is canceled by the low potential of the reset, thereby suppressing the phenomenon of increasing brightness within the same display cycle (the display cycle can be one frame display time) and improving the flicker problem.

[0115] like Figure 3 As shown, the pixel circuit described in at least one embodiment of this disclosure includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit 20, and a light-emitting element 10;

[0116] The first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first voltage terminal V1 and the first node N1 under the control of the light-emitting control signal provided by the light-emitting control line E1; the first voltage terminal V1 is used to provide a first voltage signal.

[0117] The control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current to drive the light-emitting element 10 under the control of the potential of its control terminal.

[0118] The second light-emitting control circuit 13 is electrically connected to the light-emitting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the connection between the third node N3 and the fourth node N4 under the control of the light-emitting control signal;

[0119] The first electrode of the light-emitting element 10 is electrically connected to the fourth node N4, and the second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2;

[0120] The reset control circuit 20 is electrically connected to the reset control line R0, the fourth node N4, and the first initial voltage terminal I1 for providing the first initial voltage Vi1, and is used to provide the first initial voltage Vi1 to the fourth node N4 under the control of the reset control signal provided by the reset control line R0.

[0121] exist Figure 3 In at least one embodiment of the pixel circuit shown, the connection node is the fourth node N4.

[0122] exist Figure 3 In at least one embodiment of the pixel circuit shown, the reset control line may be the light emission control line, or the reset control signal provided by the reset control line and the light emission control signal provided by the light emission control line may be the same control signal, but this is not a limitation.

[0123] This disclosure is as follows Figure 3 In at least one embodiment of the pixel circuit shown, the display cycle includes a light-emitting phase and a non-light-emitting phase during operation;

[0124] During the non-light-emitting phase, the reset control circuit 20, under the control of the reset control signal, provides the first initial voltage Vi1 to the fourth node N4. This ensures that when the light-emitting phase is entered again, the excess charge accumulated in the first node N1 is canceled out by the reset low potential when flowing through the fourth node N4. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame display time) is suppressed, thus improving the flicker problem.

[0125] Optionally, the reset control circuit may include a first control circuit, a second control circuit, and a first energy storage circuit;

[0126] The first control circuit is electrically connected to the reset control line, the connection node, and the fifth node, respectively, and is used to control the connection node and the fifth node to be connected or disconnected under the control of the reset control signal;

[0127] The second control circuit is electrically connected to the reset control line, the fifth node, and the first initial voltage terminal, respectively, and is used to control the writing of the first initial voltage provided by the first initial voltage terminal into the fifth node under the control of the reset control signal;

[0128] The first energy storage circuit is electrically connected to the fifth node and is used to store electrical energy.

[0129] In at least one embodiment of this disclosure, the reset control circuit may include a first control circuit, a second control circuit, and a first energy storage circuit;

[0130] During the light-emitting stage, the second control circuit, under the control of the reset control signal, writes the first initial voltage into the fifth node, and the first energy storage circuit stores the first initial voltage in the fifth node N5.

[0131] During the non-light-emitting phase, the first control circuit, under the control of the reset control signal, controls the connection between the fifth node and the third node to write the first initial voltage into the connection node.

[0132] like Figure 4 As shown, the pixel circuit described in this embodiment includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit, and a light-emitting element 10; the reset circuit includes a first control circuit 14, a second control circuit 15, and a first energy storage circuit 16.

[0133] The first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first voltage terminal V1 and the first node N1 under the control of the light-emitting control signal provided by the light-emitting control line E1; the first voltage terminal V1 is used to provide a first voltage signal.

[0134] The control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current to drive the light-emitting element 10 under the control of the potential of its control terminal.

[0135] The second light-emitting control circuit 13 is electrically connected to the light-emitting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the connection between the third node N3 and the fourth node N4 under the control of the light-emitting control signal;

[0136] The first electrode of the light-emitting element 10 is electrically connected to the fourth node N4, and the second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2;

[0137] The first control circuit 14 is electrically connected to the light-emitting control line E1, the third node N3 and the fifth node N5 respectively, and is used to control the connection between the third node N3 and the fifth node N5 under the control of the light-emitting control signal;

[0138] The second control circuit 15 is electrically connected to the light-emitting control line E1, the fifth node N5 and the first initial voltage terminal I1 respectively, and is used to control the first initial voltage Vi1 provided by the first initial voltage terminal I1 to be written into the fifth node N5 under the control of the light-emitting control signal.

[0139] The first energy storage circuit 16 is electrically connected to the fifth node N5 and is used to store electrical energy.

[0140] exist Figure 4 In at least one embodiment shown, the connection node is a third node N3, and the reset control line is a light emission control line E1.

[0141] This disclosure is as follows Figure 4 At least one embodiment of the pixel circuit shown, when in operation,

[0142] During the light emission stage, the second control circuit 15 writes the first initial voltage Vi1 into the fifth node N5 under the control of the light emission control signal, and the first energy storage circuit 16 stores the first initial voltage Vi1 in the fifth node N5.

[0143] During the non-light-emitting phase, Vi1 stored in the fifth node N5 resets the potential of the third node N3 through the first control circuit 14. This allows the excess charge accumulated in the first node N1 to be offset by the reset low potential when it flows through the third node N3 again during the light-emitting phase. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, thus improving the flicker problem.

[0144] like Figure 5 As shown, the pixel circuit described in this embodiment includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit, and a light-emitting element 10; the reset control circuit includes a first control circuit 14, a second control circuit 15, and a first energy storage circuit 16.

[0145] The first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first voltage terminal V1 and the first node N1 under the control of the light-emitting control signal provided by the light-emitting control line E1; the first voltage terminal V1 is used to provide a first voltage signal.

[0146] The control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current to drive the light-emitting element 10 under the control of the potential of its control terminal.

[0147] The second light-emitting control circuit 13 is electrically connected to the light-emitting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the connection between the third node N3 and the fourth node N4 under the control of the light-emitting control signal;

[0148] The first electrode of the light-emitting element 10 is electrically connected to the fourth node N4, and the second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2;

[0149] The first control circuit 14 is electrically connected to the light-emitting control line E1, the first node N1 and the fifth node N5 respectively, and is used to control the connection between the first node N1 and the fifth node N5 under the control of the light-emitting control signal;

[0150] The second control circuit 15 is electrically connected to the light-emitting control line E1, the fifth node N5 and the first initial voltage terminal I1 respectively, and is used to control the first initial voltage Vi1 provided by the first initial voltage terminal I1 to be written into the fifth node N5 under the control of the light-emitting control signal.

[0151] The first energy storage circuit 16 is electrically connected to the fifth node N5 and is used to store electrical energy.

[0152] exist Figure 5 In at least one embodiment shown, the connection node is a first node N1, and the reset control line is a light emission control line E1.

[0153] This disclosure is as follows Figure 5 In at least one embodiment of the pixel circuit shown, the display cycle includes a non-light-emitting phase and a light-emitting phase during operation;

[0154] During the light emission stage, the second control circuit 15 writes the first initial voltage Vi1 into the fifth node N5 under the control of the light emission control signal, and the first energy storage circuit 16 stores the first initial voltage Vi1 in the fifth node N5.

[0155] During the non-light-emitting phase, Vi1 stored in the fifth node N5 resets the potential of the first node N1 through the first control circuit 14. This allows the excess charge accumulated in the first node N1 to be offset by the reset low potential when the light-emitting phase is entered again. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, thus improving the flicker problem.

[0156] like Figure 6 As shown, the pixel circuit described in this embodiment includes a first light-emitting control circuit 11, a driving circuit 12, a second light-emitting control circuit 13, a reset control circuit, and a light-emitting element 10; the reset control circuit includes a first control circuit 14, a second control circuit 15, and a first energy storage circuit 16.

[0157] The first light-emitting control circuit 11 is electrically connected to the light-emitting control line E1, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first voltage terminal V1 and the first node N1 under the control of the light-emitting control signal provided by the light-emitting control line E1; the first voltage terminal V1 is used to provide a first voltage signal.

[0158] The control terminal of the driving circuit 12 is electrically connected to the second node N2; the driving circuit is used to control the generation of a driving current to drive the light-emitting element 10 under the control of the potential of its control terminal.

[0159] The second light-emitting control circuit 13 is electrically connected to the light-emitting control line E1, the third node N3 and the fourth node N4 respectively, and is used to control the connection between the third node N3 and the fourth node N4 under the control of the light-emitting control signal;

[0160] The first electrode of the light-emitting element 10 is electrically connected to the fourth node N4, and the second electrode of the light-emitting element 10 is electrically connected to the second voltage terminal V2;

[0161] The first control circuit 14 is electrically connected to the light-emitting control line E1, the fourth node N4 and the fifth node N5 respectively, and is used to control the connection between the fourth node N4 and the fifth node N5 under the control of the light-emitting control signal;

[0162] The second control circuit 15 is electrically connected to the light-emitting control line E1, the fifth node N5 and the first initial voltage terminal I1 respectively, and is used to control the first initial voltage Vi1 provided by the first initial voltage terminal I1 to be written into the fifth node N5 under the control of the light-emitting control signal.

[0163] The first energy storage circuit 16 is electrically connected to the fifth node N5 and is used to store electrical energy.

[0164] exist Figure 6 In at least one embodiment shown, the connection node is the fourth node N4, and the reset control line is the light emission control line E1.

[0165] This disclosure is as follows Figure 6 In at least one embodiment of the pixel circuit shown, the display cycle includes a non-light-emitting phase and a light-emitting phase during operation;

[0166] During the light emission stage, the second control circuit 15 writes the first initial voltage Vi1 into the fifth node N5 under the control of the light emission control signal, and the first energy storage circuit 16 stores the first initial voltage Vi1 in the fifth node N5.

[0167] During the non-light-emitting phase, Vi1 stored in the fifth node N5 resets the potential of the fourth node N4 through the first control circuit 14. This allows the excess charge accumulated in the first node N1 to be offset by the reset low potential when it flows through the fourth node N4 when the light-emitting phase is entered again. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, thus improving the flicker problem.

[0168] Optionally, the first control circuit includes a first transistor, and the second control circuit includes a second transistor;

[0169] The control electrode of the first transistor is electrically connected to the reset control line, the first electrode of the first transistor is electrically connected to the fifth node, and the second electrode of the first transistor is electrically connected to the third node.

[0170] The control electrode of the second transistor is electrically connected to the reset control line, the first electrode of the second transistor is electrically connected to the first initial voltage terminal, and the second electrode of the second transistor is electrically connected to the fifth node.

[0171] Optionally, the first transistor is an oxide thin-film transistor, and the second transistor is a low-temperature polycrystalline silicon thin-film transistor.

[0172] In at least one embodiment of this disclosure, the first energy storage circuit includes a first capacitor;

[0173] The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal.

[0174] The pixel circuit described in at least one embodiment of this disclosure may further include a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit, and a second initialization circuit.

[0175] The data writing circuit is electrically connected to the write control line, the data line and the first node respectively, and is used to write the data voltage provided by the data line to the first node under the control of the write control signal provided by the write control line.

[0176] The compensation control circuit is electrically connected to the compensation control line, the control terminal of the drive circuit, and the second terminal of the drive circuit, respectively, and is used to control the connection between the control terminal of the drive circuit and the second terminal of the drive circuit under the control of the compensation control signal provided by the compensation control line;

[0177] The first initialization circuit is electrically connected to the initialization control line, the second initial voltage terminal, and the control terminal of the driving circuit, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the control terminal of the driving circuit under the control of the initialization control signal provided by the initialization control line, so that at the beginning of the compensation phase, the driving circuit can control the first terminal of the driving circuit and the second terminal of the driving circuit to be connected under the control of the potential of its control terminal.

[0178] The second energy storage circuit is electrically connected to the control terminal of the drive circuit and is used to store electrical energy;

[0179] The second initialization circuit is electrically connected to the write control line, the third initial voltage terminal and the fourth node respectively, and is used to write the third initial voltage provided by the third initial voltage terminal to the fourth node under the control of the write control signal, so as to control the light-emitting element to not emit light.

[0180] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit 41, a compensation control circuit, a first initialization circuit, a second energy storage circuit, and a second initialization circuit. The data writing circuit is used to control data voltage writing, and the compensation control circuit is used to control threshold voltage compensation. The first initialization circuit is used to reset the potential of the control terminal of the driving circuit so that, at the beginning of the compensation phase, the driving circuit can control the connection between the first terminal and the second terminal of the driving circuit under the control of the potential of its control terminal. The second energy storage circuit is used to maintain the potential of the control terminal of the driving circuit, and the second initialization circuit is used to reset the potential of the first electrode of the light-emitting element so as to control the light-emitting element not to emit light.

[0181] When the pixel circuit described in at least one embodiment of this disclosure is in operation, during low-frequency display, the display frame may include a refresh sub-display frame and at least one hold sub-display frame;

[0182] In the holding sub-display frame, the data line can provide a first voltage signal;

[0183] During the data writing phase of the holding sub-display frame, the data writing circuit writes the first voltage signal to the first node under the control of the write control signal.

[0184] In the holding sub-display frame, even if the transistors in the data writing circuit leak current, the potential of the first node will remain at the first voltage value (the first voltage value is the voltage value of the first voltage signal), so that the potential of the first node remains at the same level when displayed at different frequencies, reducing brightness differences.

[0185] In at least one embodiment of this disclosure, the first voltage signal can be a high voltage signal, and the first voltage value can be greater than or equal to 2.5V and less than or equal to 7V; for example, the first voltage value can be 2.5V, 3V, 4V, 4.6V, 5V, 5.8V, 6.4V or 7V, but is not limited thereto.

[0186] In related technologies, when the pixel circuit performs low-frequency display, the display frame may include a refresh sub-display frame and at least one hold sub-display frame. In the refresh sub-display frame, data voltage is written to the pixel circuit and light is emitted accordingly. The hold sub-display frame at least serves to lengthen the light emission time to achieve the purpose of low frequency. In the hold sub-display frame, the data line provides a DC voltage signal, for example, the voltage value of the DC voltage signal can be 6.4V. In the hold sub-display frame, the DC voltage signal leaks to the first node through the transistor included in the data writing circuit, causing the potential of the first node to rise. When entering the light emission stage again, it will increase the driving current of the transistor included in the driving circuit, thereby increasing the brightness. Based on this, at least one embodiment of this disclosure controls the data line to provide a first voltage signal in the hold sub-display frame to improve the problem of large brightness differences when displaying at different frequencies.

[0187] In at least one embodiment of this disclosure, when the pixel circuit performs low-frequency display, the data line can be controlled to provide a first voltage signal during a time period other than the data writing phase in the refresh sub-display frame;

[0188] When the pixel circuit is performing normal display (i.e., when the display frequency of the pixel circuit is high), the data line can be controlled to provide a first voltage signal during the time period included in the display frame, excluding the data writing phase.

[0189] like Figure 7 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit 41, a compensation control circuit 42, a first initialization circuit 43, a second energy storage circuit 44, and a second initialization circuit 45.

[0190] The data writing circuit 41 is electrically connected to the write control line GP, the data line D1 and the first node N1 respectively, and is used to write the data voltage provided by the data line D1 into the first node N1 under the control of the write control signal provided by the write control line GP.

[0191] The compensation control circuit 42 is electrically connected to the compensation control line GN, the control terminal of the drive circuit 12 and the second terminal of the drive circuit 12, respectively, and is used to control the connection between the control terminal of the drive circuit 12 and the second terminal of the drive circuit 12 under the control of the compensation control signal provided by the compensation control line GN.

[0192] The first initialization circuit 43 is electrically connected to the initialization control line R1, the second initial voltage terminal I2 and the control terminal of the driving circuit 12, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 12 under the control of the initialization control signal provided by the initialization control line R1.

[0193] The second energy storage circuit 44 is electrically connected to the control terminal of the drive circuit 12 and is used to store electrical energy;

[0194] The second initialization circuit 45 is electrically connected to the write control line GP, the third initial voltage terminal I3 and the fourth node N4 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the fourth node N4 under the control of the write control signal.

[0195] Optionally, the second initial voltage Vi2 may be greater than or equal to -5V and less than or equal to -3V, but is not limited thereto.

[0196] In at least one embodiment of this disclosure, the third initial voltage terminal I3 may be the same initial voltage terminal as the first initial voltage terminal I1, but this is not a limitation. In actual operation, the third initial voltage terminal I3 may be a different initial voltage terminal from the first initial voltage terminal I1.

[0197] like Figure 8 As shown, in Figure 5 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit 41, a compensation control circuit 42, a first initialization circuit 43, a second energy storage circuit 44, and a second initialization circuit 45.

[0198] The data writing circuit 41 is electrically connected to the write control line GP, the data line D1 and the first node N1 respectively, and is used to write the data voltage provided by the data line D1 into the first node N1 under the control of the write control signal provided by the write control line GP.

[0199] The compensation control circuit 42 is electrically connected to the compensation control line GN, the control terminal of the drive circuit 12 and the second terminal of the drive circuit 12, respectively, and is used to control the connection between the control terminal of the drive circuit 12 and the second terminal of the drive circuit 12 under the control of the compensation control signal provided by the compensation control line GN.

[0200] The first initialization circuit 43 is electrically connected to the initialization control line R1, the second initial voltage terminal I2 and the control terminal of the driving circuit 12, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 12 under the control of the initialization control signal provided by the initialization control line R1.

[0201] The second energy storage circuit 44 is electrically connected to the control terminal of the drive circuit 12 and is used to store electrical energy;

[0202] The second initialization circuit 45 is electrically connected to the write control line GP, the third initial voltage terminal I3 and the fourth node N4 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the fourth node N4 under the control of the write control signal.

[0203] like Figure 9 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit 41, a compensation control circuit 42, a first initialization circuit 43, a second energy storage circuit 44, and a second initialization circuit 45.

[0204] The data writing circuit 41 is electrically connected to the write control line GP, the data line D1 and the first node N1 respectively, and is used to write the data voltage provided by the data line D1 into the first node N1 under the control of the write control signal provided by the write control line GP.

[0205] The compensation control circuit 42 is electrically connected to the compensation control line GN, the control terminal of the drive circuit 12 and the second terminal of the drive circuit 12, respectively, and is used to control the connection between the control terminal of the drive circuit 12 and the second terminal of the drive circuit 12 under the control of the compensation control signal provided by the compensation control line GN.

[0206] The first initialization circuit 43 is electrically connected to the initialization control line R1, the second initial voltage terminal I2 and the control terminal of the driving circuit 12, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the control terminal of the driving circuit 12 under the control of the initialization control signal provided by the initialization control line R1.

[0207] The second energy storage circuit 44 is electrically connected to the control terminal of the drive circuit 12 and is used to store electrical energy;

[0208] The second initialization circuit 45 is electrically connected to the write control line GP, the third initial voltage terminal I3 and the fourth node N4 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the fourth node N4 under the control of the write control signal.

[0209] Optionally, the first light-emitting control circuit includes a third transistor, the second light-emitting control circuit includes a fourth transistor, and the driving circuit includes a driving transistor;

[0210] The control electrode of the third transistor is electrically connected to the light-emitting control line, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first node.

[0211] The control electrode of the fourth transistor is electrically connected to the light-emitting control line, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0212] The control electrode of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the third node.

[0213] Optionally, the data writing circuit includes a fifth transistor, the compensation control circuit includes a sixth transistor, the first initialization circuit includes a seventh transistor, the second initialization circuit includes an eighth transistor, and the second energy storage circuit includes a second capacitor.

[0214] The control electrode of the fifth transistor is electrically connected to the write control line, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the first terminal of the drive circuit.

[0215] The control electrode of the sixth transistor is electrically connected to the compensation control line, the first electrode of the sixth transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the second terminal of the driving circuit.

[0216] The control electrode of the seventh transistor is electrically connected to the initialization control line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the control terminal of the driving circuit.

[0217] The control electrode of the eighth transistor is electrically connected to the write control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the fourth node mentioned above.

[0218] The first end of the second capacitor is electrically connected to the second node, and the second end of the second capacitor is electrically connected to the first voltage terminal.

[0219] like Figure 10 As shown, in Figure 7 Based on at least one embodiment of the pixel circuit shown, the light-emitting element is an organic light-emitting diode O1; the first control circuit 14 includes a first transistor T1, and the second control circuit 15 includes a second transistor T2;

[0220] The gate of the first transistor T1 is electrically connected to the light-emitting control line E1, the source of the first transistor T1 is electrically connected to the fifth node N5, and the drain of the first transistor T1 is electrically connected to the third node N3.

[0221] The gate of the second transistor T2 is electrically connected to the light-emitting control line E1, the source of the second transistor T2 is electrically connected to the first initial voltage terminal I1, and the drain of the second transistor T2 is electrically connected to the fifth node N5; the first initial voltage terminal I1 is used to provide the first initial voltage Vi1;

[0222] The first energy storage circuit 16 includes a first capacitor C1;

[0223] The first terminal of the first capacitor C1 is electrically connected to the fifth node N5, and the second terminal of the first capacitor C1 is electrically connected to the high voltage terminal VDD.

[0224] The first light-emitting control circuit 11 includes a third transistor T3, the second light-emitting control circuit 13 includes a fourth transistor T4, and the driving circuit 12 includes a driving transistor T0.

[0225] The gate of the third transistor T3 is electrically connected to the light-emitting control line E1, the source of the third transistor T3 is electrically connected to the high voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the first node N1.

[0226] The gate of the fourth transistor T4 is electrically connected to the light-emitting control line E1, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4; the anode of the organic light-emitting diode O1 is electrically connected to the fourth node N4, and the cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0227] The gate of the driving transistor T0 is electrically connected to the second node N2, the source of the driving transistor T0 is electrically connected to the first node N1, and the drain of the driving transistor T2 is electrically connected to the third node N3.

[0228] The data writing circuit 41 includes a fifth transistor T5, the compensation control circuit 42 includes a sixth transistor T6, the first initialization circuit 43 includes a seventh transistor T7, the second initialization circuit 45 includes an eighth transistor T8, and the second energy storage circuit 44 includes a second capacitor C2.

[0229] The gate of the fifth transistor T5 is electrically connected to the write control line GP, the source of the fifth transistor T5 is electrically connected to the data line D1, and the drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T0.

[0230] The gate of the sixth transistor T6 is electrically connected to the compensation control line GN, the source of the sixth transistor T6 is electrically connected to the gate of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0.

[0231] The gate of the seventh transistor T7 is electrically connected to the initialization control line R1, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the gate of the driving transistor T0; the second initial voltage terminal I2 is used to provide the second initial voltage Vi2.

[0232] The gate of the eighth transistor T8 is electrically connected to the write control line GP, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected to the fourth node N4 mentioned above.

[0233] The first end of the second capacitor C2 is electrically connected to the second node N2, and the second end of the second capacitor C2 is electrically connected to the high voltage terminal VDD.

[0234] exist Figure 10 In the figure, C0 represents the parasitic capacitance between the first node N1 and the high-voltage terminal VDD.

[0235] exist Figure 10 In at least one embodiment of the pixel circuit shown, the first initial voltage terminal and the third initial voltage terminal are the same voltage terminal, the first voltage terminal is a high voltage terminal VDD, and the second voltage terminal is a low voltage terminal VSS, but this is not a limitation.

[0236] exist Figure 10 In at least one embodiment of the pixel circuit shown, the reset control line is the light emission control line E1.

[0237] exist Figure 10In at least one embodiment of the pixel circuit shown, T1, T6 and T7 are oxide thin-film transistors, and T0, T2, T3, T4, T5 and T8 are low-temperature polycrystalline silicon thin-film transistors, but are not limited thereto.

[0238] like Figure 11 As shown, this disclosure is as follows Figure 10 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase S1, a compensation phase S2, a data writing phase, and a light emission phase S3; the data writing phase is included in the compensation phase S2; the initialization phase S1, the compensation phase S2, and the light emission phase S3 are arranged sequentially.

[0239] During the initialization phase S1, R1 provides a high voltage signal, and T7 is turned on to provide the second initial voltage Vi2 provided by the second initial voltage terminal I2 to the second node N2, so that the driving transistor T0 can be turned on at the beginning of the compensation phase.

[0240] During the initialization phase S1, GN provides a low voltage signal, GP provides a high voltage signal, E1 provides a high voltage signal, T1 is turned on, and T2, T3, T4, T5, T6, and T0 are all turned off. During the data writing phase, data line D1 provides a data voltage Vdata, GP provides a low voltage signal, T5 is turned on to write the data voltage Vdata to the first node N1, and T8 is turned on to write the first initial voltage Vi1 to the anode of O1 so that O1 does not emit light.

[0241] During the compensation phase S2, GN provides a high voltage signal, E1 provides a high voltage signal, R1 provides a low voltage signal, T7 is turned off, T1 is turned on; T6 is turned on to connect the second node N2 and the third node N3.

[0242] At the start of the compensation phase S2, T0 is turned on, and Vdata charges C2 through T5, T0 and T6 to increase the potential of the second node N2 until T0 is turned off. At this time, the potential of the second node N2 is Vdata + Vth, where Vth is the threshold voltage of T0 and Vth is a negative value.

[0243] During the light emission phase S3, E1 provides a low voltage signal, R1 provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, T3 and T4 are both turned on, and T0 drives O1 to emit light; T2 is turned on to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the fifth node N5.

[0244] exist Figure 11 and Figure 12 In the diagram, L0 represents the luminous intensity of O1.

[0245] exist Figure 11 In the working sequence shown, the data writing stage is included in the compensation stage S2, but is not limited thereto; in actual operation, the data writing stage may also be in the same time period as the compensation stage S2.

[0246] exist Figure 11 In the diagram, GP_2 is the next row write control line adjacent to GP, and the waveform corresponding to GP_2 is the waveform of the next row write control signal provided by the next row write control line.

[0247] like Figure 11 As shown, during the first half of the compensation phase S2, GP provides a low voltage signal, and during the second half of the compensation phase S2, GP_2 provides a low voltage signal to control the adjacent row pixel circuits to access the corresponding data voltage in a time-division manner.

[0248] This disclosure is as follows Figure 10 In at least one embodiment of the pixel circuit shown, during operation, the light-emitting phase S3 and T2 are turned on to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the fifth node N5, and the first capacitor C1 stores the first initial voltage Vi1 in the fifth node N5.

[0249] During the non-light-emitting phase (which can be the time period excluding the light-emitting phase included in the display cycle), T1 is turned on to control the connection between the fifth node N5 and the third node N3, so that the first initial voltage Vi1 is written into the third node N3. This allows the excess charge accumulated by the first node N1 to be canceled by the reset low potential when it flows through the third node N3 upon entering the light-emitting phase again. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, improving the flicker problem.

[0250] like Figure 12 As shown, this disclosure is as follows Figure 10 When at least one embodiment of the pixel circuit shown is in operation, the display cycle in the refresh sub-display frame may include an initialization stage S1, a compensation stage S2, a data writing stage, a first light emission stage S31, a second light emission stage S32, a third light emission stage S33, and a fourth light emission stage S34, which are set sequentially; the data writing stage is included in the compensation stage S2.

[0251] The initialization stage S1, the compensation stage S2, the first light emission stage S31, the second light emission stage S32, the third light emission stage S33, and the fourth light emission stage S34 are set sequentially;

[0252] A first interval stage S01 is provided between the first light-emitting stage S31 and the second light-emitting stage S32, a second interval stage S02 is provided between the second light-emitting stage S32 and the third light-emitting stage S33, and a third interval stage S03 is provided between the third light-emitting stage S33 and the fourth light-emitting stage S34.

[0253] During the initialization phase S1, R1 provides a high voltage signal, and T7 is turned on to provide the second initial voltage Vi2 provided by the second initial voltage terminal I2 to the second node N2, so that the driving transistor T0 can be turned on at the beginning of the compensation phase.

[0254] During the initialization phase S1, GN provides a low voltage signal, GP provides a high voltage signal, E1 provides a high voltage signal, T1 is turned on, and T2, T3, T4, T5, T6 and T0 are all turned off.

[0255] During the data writing phase, data line D1 provides data voltage Vdata, GP provides a low voltage signal, T5 is turned on to write data voltage Vdata into the first node N1; T8 is turned on to write the first initial voltage Vi1 into the anode of O1 so that O1 does not emit light.

[0256] During the compensation phase S2, GN provides a high voltage signal, E1 provides a high voltage signal, R1 provides a low voltage signal, T7 is turned off, T1 is turned on; T6 is turned on to connect the second node N2 and the third node N3.

[0257] At the start of the compensation phase S2, T0 is turned on, and Vdata charges C2 through T5, T0, and T6 to increase the potential of the second node N2 until T0 is turned off. At this time, the potential of the second node N2 is Vdata + Vth, where Vth is the threshold voltage of T0 and is negative. In the first light emission phase S31, the second light emission phase S32, the third light emission phase S33, and the fourth light emission phase S34, E1 provides a low voltage signal, R1 provides a low voltage signal, GN provides a low voltage signal, and GP provides a high voltage signal. T3 and T4 are both turned on, and T0 drives O1 to emit light. T2 is turned on to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the fifth node N5.

[0258] In the first interval stage S01, the second interval stage S02, and the third interval stage S03, E1 provides a high voltage signal, R1 provides a low voltage signal, GN provides a low voltage signal, GP provides a high voltage signal, and T1 is turned on to write the first initial voltage Vi1 stored in the fifth node N5 to the third node N3.

[0259] like Figure 12As shown, in at least one embodiment of the pixel circuit described in this disclosure, when operating in a low-frequency display mode, the frequency of the write control signal provided by the write control line GP is lower than the frequency of the light emission control signal provided by the light emission control line E1. The light emission control signal is a high-frequency signal, while the write control signal, the initialization control signal provided by the initialization control line R1, and the compensation control signal provided by the compensation control line GN are all low-frequency signals to reduce power consumption.

[0260] like Figure 13 As shown, this disclosure is as follows Figure 10 In at least one embodiment of the pixel circuit shown, during operation, in low-frequency display, the display frame may include a refresh sub-display frame F1 and at least one hold sub-display frame;

[0261] In the holding sub-display frame, data line D1 provides a high voltage signal; the voltage value of the high voltage signal provided by data line D1 is equal to the voltage value of the high voltage signal provided by the high voltage terminal VDD, for example, the voltage value of the high voltage signal can be 4.6V;

[0262] During the data writing phase in the holding sub-display frame, GP provides a low voltage, and T5 is turned on to write the high voltage signal to the first node N1;

[0263] In the holding sub-display frame, when E1 provides a low voltage signal, T1 and T2 are turned on, and T0 drives O1 to emit light.

[0264] Since the voltage value of the high voltage signal provided by the data line D1 is equal to the voltage value of the high voltage signal provided by the high voltage terminal VDD when maintaining the sub-display frame, even if T5 leaks current, the potential of N1 will remain at 4.6V, so that the potential of the first node N1 remains at the same level when displayed at different frequencies, thus improving the brightness difference caused by this.

[0265] exist Figure 12 and Figure 13 In the diagram, frame F21 is the first holding sub-display frame, and frame F2N is the Nth holding sub-display frame, where N is an integer greater than 1.

[0266] The data writing stage included in the first holding sub-display frame F21 is labeled S41, and the data writing stage included in the Nth holding sub-display frame F2N is labeled S4N.

[0267] exist Figure 13 In the diagram, GP_2 is the next row write control line adjacent to GP, and the waveform corresponding to GP_2 is the waveform of the next row write control signal provided by the next row write control line.

[0268] Depend on Figure 14It can be seen that when the data line D1 provides a high voltage signal in the holding sub-display frame, and the voltage value of the high voltage signal is equal to the voltage value of the high voltage signal provided by the high voltage terminal VDD, the brightness changes by 2.8% when the refresh rate changes from 120Hz to 1Hz, and the brightness difference is significantly improved when switching frequencies.

[0269] This disclosure Figure 15 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 10 The difference in at least one embodiment of the pixel circuit shown is that the drain of T1 is electrically connected to the first node N1.

[0270] This disclosure is as follows Figure 15 At least one embodiment of the pixel circuit shown, when in operation,

[0271] During the light emission phase, E1 provides a low voltage signal, T1 is turned off, T2 is turned on, the first initial voltage Vi1 is written to the fifth node N5, and C1 stores the first initial voltage Vi1 in the fifth node N5.

[0272] During the non-light-emitting phase, E1 provides a high-voltage signal, T1 is turned on, and Vi1 stored in the fifth node N5 resets the potential of the first node N1 through T1. This allows the excess charge accumulated in the first node N1 to be canceled by the reset low potential when the light-emitting phase is entered again. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, thus improving the flicker problem.

[0273] This disclosure is as follows Figure 15 In at least one embodiment of the pixel circuit shown, when in low-frequency display mode, the frequency of the write control signal provided by GP is lower than the frequency of the light emission control signal provided by E1, so as to reduce power consumption.

[0274] This disclosure Figure 16 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 10 The difference in at least one embodiment of the pixel circuit shown is that the drain of T1 is electrically connected to the fourth node N4. This disclosure is as follows: Figure 16 At least one embodiment of the pixel circuit shown, when in operation,

[0275] During the light emission phase, E1 provides a low voltage signal, T1 is turned off, T2 is turned on, the first initial voltage Vi1 is written to the fifth node N5, and C1' stores the first initial voltage Vi1 in the fifth node N5;

[0276] During the non-light-emitting phase, E1 provides a high-voltage signal, T2 is turned off, and T1 is turned on. Vi1 stored in the fifth node N5 resets the potential of the fourth node N4 through T1. This allows the excess charge accumulated in the first node N1 to be canceled out by the reset low potential when it flows through the fourth node N4 when the light-emitting phase is entered again. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, improving the flicker problem.

[0277] This disclosure is as follows Figure 16 In at least one embodiment of the pixel circuit shown, when in low-frequency display mode, the frequency of the write control signal provided by GP is lower than the frequency of the light emission control signal provided by E1, so as to reduce power consumption.

[0278] This disclosure Figure 17 At least one embodiment of the pixel circuit shown is consistent with this disclosure. Figure 16 The difference between at least one embodiment of the pixel circuit shown in this disclosure is that: Figure 17 At least one embodiment of the pixel circuit shown does not include an eighth transistor T8.

[0279] This disclosure is as follows Figure 17 At least one embodiment of the pixel circuit shown, when in operation,

[0280] During the light emission phase, E1 provides a low voltage signal, T1 is turned off, T2 is turned on, the first initial voltage Vi1 is written to the fifth node N5, and C1' stores the first initial voltage Vi1 in the fifth node N5;

[0281] During the non-light-emitting phase, E1 provides a high-voltage signal, T2 is turned off, and T1 is turned on. Vi1 stored in the fifth node N5 resets the potential of the fourth node N4 through T1. This allows the excess charge accumulated in the first node N1 to be canceled out by the reset low potential when it flows through the fourth node N4 when the light-emitting phase is entered again. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame of display time) is suppressed, improving the flicker problem.

[0282] This disclosure is as follows Figure 17 In at least one embodiment of the pixel circuit shown, when in low-frequency display mode, the frequency of the write control signal provided by GP is lower than the frequency of the light emission control signal provided by E1, so as to reduce power consumption.

[0283] The pixel driving method described in this embodiment is applied to the pixel circuit described above, and the display cycle includes a non-light-emitting phase and a light-emitting phase; the pixel driving method includes:

[0284] During the non-light-emitting phase, the reset control circuit, under the control of the reset control signal, provides a first initial voltage to the connection node. This allows the excess charge accumulated by the first node to be canceled out by the first initial voltage provided to the connection node when entering the light-emitting phase. As a result, the phenomenon of increasing brightness within the same display cycle (which can be one frame display time) is suppressed, thus improving the flicker problem.

[0285] Optionally, the reset control circuit includes a first control circuit, a second control circuit, and a first energy storage circuit; the pixel driving method described in at least one embodiment of this disclosure includes:

[0286] During the light-emitting stage, the second control circuit, under the control of the reset control signal, writes the first initial voltage into the fifth node, and the first energy storage circuit stores the first initial voltage in the fifth node.

[0287] During the non-light-emitting phase, the first control circuit, under the control of the reset control signal, controls the connection between the fifth node and the connection node to write the first initial voltage into the connection node.

[0288] In a specific implementation, the reset control circuit may include a first control circuit, a second control circuit, and a first energy storage circuit; during the light-emitting stage, the second control circuit and the first energy storage circuit control the writing and storage of the first initial voltage in the fifth stage; during the non-light-emitting stage, the first control circuit writes the first initial voltage into the connection node.

[0289] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit, and a second initialization circuit; the display cycle includes a first display stage comprising an initialization stage, a compensation stage, and a light emission stage set sequentially, the compensation stage including a data writing stage; the pixel driving method includes:

[0290] During the initialization phase, the first initialization circuit, under the control of the reset control signal, writes the second initial voltage into the control terminal of the drive circuit, so that at the start of the compensation phase, the drive circuit can control the connection between the first node and the third node under the control of the potential of its control terminal.

[0291] During the data writing phase, the data line provides a data voltage Vdata, and the data writing circuit writes the data voltage Vdata into the first node under the control of the write control signal.

[0292] During the compensation phase, the compensation control circuit controls the connection between the second node and the third node under the control of the compensation control signal.

[0293] During the light-emitting stage, the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal, the second light-emitting control circuit controls the connection between the third node and the fourth node under the control of the light-emitting control signal, and the driving circuit generates a driving current to drive the light-emitting element.

[0294] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit; the non-light-emitting phase includes a data writing phase; the display frame includes a refresh sub-display frame and at least one hold sub-display frame; the refresh sub-display frame includes the display period, and the hold sub-display frame includes the display period; the pixel driving method further includes:

[0295] In the holding sub-display frame, the data line provides a first voltage signal;

[0296] During the data writing phase of the holding sub-display frame, the data writing circuit writes the first voltage signal to the first node under the control of the write control signal.

[0297] In the holding sub-display frame, even if the transistors in the data writing circuit leak current, the potential of the first node will remain at the first voltage value (the first voltage value is the voltage value of the first voltage signal), so that the potential of the first node remains at the same level when displayed at different frequencies, reducing brightness differences.

[0298] Optionally, the pixel circuit further includes a compensation control circuit; the display cycle further includes a compensation phase; the pixel driving method described in at least one embodiment of this disclosure further includes:

[0299] During the data writing phase of the refresh sub-display frame, the data line provides a data voltage, and the data writing circuit writes the data voltage to the first node under the control of the write control signal.

[0300] During the compensation phase of the refresh sub-display frame, the compensation control circuit, under the control of the compensation control signal, controls the connection between the control terminal of the drive circuit and the second terminal of the drive circuit.

[0301] During the light-emitting phase in the refresh sub-display frame and the light-emitting phase in the hold sub-display frame, the first light-emitting control circuit controls the connection between the first voltage terminal and the first node under the control of the light-emitting control signal, the second light-emitting control circuit controls the connection between the third node and the fourth node under the control of the light-emitting control signal, and the driving circuit generates the driving current to drive the light-emitting element.

[0302] During the holding sub-display frame, the compensation control circuit, under the control of the compensation control signal, controls the disconnection between the control terminal of the drive circuit and the second terminal of the drive circuit.

[0303] In the pixel driving method described in at least one embodiment of this disclosure, during the light emission phase in the refresh sub-display frame and the light emission phase in the hold sub-display frame, the driving circuit drives the light-emitting element to emit light. During the hold sub-display frame, the compensation control circuit controls the control terminal of the driving circuit to disconnect from the second terminal of the driving circuit. Therefore, even if the transistors included in the data writing circuit are turned on during a specific time period in the hold sub-display frame, the potential of the control terminal of the driving circuit will not be turned on, and the display brightness will not be affected.

[0304] Optionally, in the display frame, the frequency of the write control signal is less than the frequency of the light emission control signal.

[0305] In at least one embodiment of this disclosure, when the pixel circuit operates in a low-frequency display mode, the display frame includes a refresh sub-display frame and at least one hold sub-display frame, wherein the frequency of the write control signal is less than the frequency of the light emission control signal in the display frame, so as to reduce power consumption.

[0306] The display device described in this disclosure includes the pixel circuit described above.

[0307] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0308] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, characterized by comprising: The first light-emitting control circuit, a driving circuit, a second light-emitting control circuit, a reset control circuit and a light-emitting element are included. The first light-emitting control circuit is electrically connected with a light-emitting control line, a first voltage terminal and a first node respectively, and is used for controlling the connection or disconnection between the first voltage terminal and the first node under the control of a light-emitting control signal provided by the light-emitting control line. The control end of the driving circuit is electrically connected with a second node, the first end of the driving circuit is electrically connected with the first node, and the second end of the driving circuit is electrically connected with a third node; the driving circuit is used for controlling the generation of a driving current for driving the light-emitting element under the control of the potential of the control end. The second light-emitting control circuit is electrically connected with the light-emitting control line, the third node and a fourth node respectively, and is used for controlling the connection or disconnection between the third node and the fourth node under the control of the light-emitting control signal. The first pole of the light-emitting element is electrically connected with the fourth node, and the second pole of the light-emitting element is electrically connected with a second voltage terminal. The reset control circuit is electrically connected with a reset control line, a connection node and a first initial voltage terminal for providing a first initial voltage respectively, and is used for providing the first initial voltage to the connection node under the control of a reset control signal provided by the reset control line. The connection node is the first node, the third node or the fourth node. The reset control circuit is also electrically connected with a fifth node, and is used for controlling the connection or disconnection between the first initial voltage terminal and the fifth node, and controlling the disconnection or connection between the fifth node and the connection node under the control of the reset control signal, and is used for maintaining the potential of the fifth node. The reset control circuit includes a first control circuit, a second control circuit and a first energy storage circuit. The first control circuit is electrically connected with the reset control line, the connection node and the fifth node respectively, and is used for controlling the connection or disconnection between the connection node and the fifth node under the control of the reset control signal. The second control circuit is electrically connected with the reset control line, the fifth node and the first initial voltage terminal respectively, and is used for writing the first initial voltage provided by the first initial voltage terminal into the fifth node under the control of the reset control signal. The first energy storage circuit is electrically connected with the fifth node, and is used for storing energy.

2. The pixel circuit of claim 1, wherein, The reset control line is the light-emitting control line; or the reset control signal provided by the reset control line is the same as the light-emitting control signal provided by the light-emitting control line.

3. The pixel circuit of claim 1, wherein, The first control circuit includes a first transistor, and the second control circuit includes a second transistor. The control pole of the first transistor is electrically connected with the reset control line, the first pole of the first transistor is electrically connected with the fifth node, and the second pole of the first transistor is electrically connected with the third node. The control pole of the second transistor is electrically connected with the reset control line, the first pole of the second transistor is electrically connected with the first initial voltage terminal, and the second pole of the second transistor is electrically connected with the fifth node.

4. The pixel circuit of claim 3, wherein, The first transistor is an oxide thin film transistor, and the second transistor is a low-temperature polysilicon thin film transistor.

5. The pixel circuit of claim 1, wherein, The first energy storage circuit comprises a first capacitor; The first end of the first capacitor is electrically connected with the fifth node, and the second end of the first capacitor is electrically connected with the first voltage terminal.

6. The pixel circuit of claim 1, wherein, Further comprising a data writing circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit and a second initialization circuit; The data writing circuit is electrically connected with a writing control line, a data line and a first node respectively, and is used for writing a data voltage provided by the data line into the first node under the control of a writing control signal provided by the writing control line; The compensation control circuit is electrically connected with a compensation control line, a control terminal of the driving circuit and a second terminal of the driving circuit respectively, and is used for controlling the control terminal of the driving circuit and the second terminal of the driving circuit to be in communication or disconnected under the control of a compensation control signal provided by the compensation control line; The first initialization circuit is electrically connected with an initialization control line, a second initial voltage terminal and the control terminal of the driving circuit respectively, and is used for writing a second initial voltage provided by the second initial voltage terminal into the control terminal of the driving circuit under the control of an initialization control signal provided by the initialization control line; The second energy storage circuit is electrically connected with the control terminal of the driving circuit, and is used for storing electric energy; The second initialization circuit is electrically connected with the writing control line, a third initial voltage terminal and the fourth node respectively, and is used for writing a third initial voltage provided by the third initial voltage terminal into the fourth node under the control of the writing control signal.

7. The pixel circuit of claim 1, wherein, The first light emitting control circuit comprises a third transistor, the second light emitting control circuit comprises a fourth transistor, and the driving circuit comprises a driving transistor; The control electrode of the third transistor is electrically connected with the light emitting control line, the first electrode of the third transistor is electrically connected with the first voltage terminal, and the second electrode of the third transistor is electrically connected with the first node; The control electrode of the fourth transistor is electrically connected with the light emitting control line, the first electrode of the fourth transistor is electrically connected with the third node, and the second electrode of the fourth transistor is electrically connected with the fourth node; The control electrode of the driving transistor is electrically connected with the second node, the first electrode of the driving transistor is electrically connected with the first node, and the second electrode of the driving transistor is electrically connected with the third node.

8. The pixel circuit of claim 6, wherein, The data writing circuit comprises a fifth transistor, the compensation control circuit comprises a sixth transistor, the first initialization circuit comprises a seventh transistor, the second initialization circuit comprises an eighth transistor, and the second energy storage circuit comprises a second capacitor; The control electrode of the fifth transistor is electrically connected with the writing control line, the first electrode of the fifth transistor is electrically connected with the data line, and the second electrode of the fifth transistor is electrically connected with the first terminal of the driving circuit; The control electrode of the sixth transistor is electrically connected with the compensation control line, the first electrode of the sixth transistor is electrically connected with the control terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected with the second terminal of the driving circuit; The control electrode of the seventh transistor is electrically connected with the initialization control line, the first electrode of the seventh transistor is electrically connected with the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected with the control terminal of the driving circuit; The control electrode of the eighth transistor is electrically connected with the write control line, the first electrode of the eighth transistor is electrically connected with the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected with the fourth node; The first terminal of the second capacitor is electrically connected with the second node, and the second terminal of the second capacitor is electrically connected with the first voltage terminal.

9. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 8, characterized in that, The display period comprises a non-emitting phase and an emitting phase; the pixel driving method comprises: In the non-emitting phase, the reset control circuit provides the first initial voltage to the connection node under the control of the reset control signal; The reset control circuit comprises a first control circuit, a second control circuit and a first energy storage circuit; the pixel driving method comprises: In the emitting phase, the second control circuit writes the first initial voltage to the fifth node under the control of the reset control signal, and the first energy storage circuit stores the first initial voltage in the fifth node; In the non-emitting phase, the first control circuit controls the communication between the fifth node and the connection node to write the first initial voltage to the connection node under the control of the reset control signal.

10. The pixel driving method according to claim 9, wherein The pixel circuit further comprises a data write circuit, a compensation control circuit, a first initialization circuit, a second energy storage circuit and a second initialization circuit; the display period comprises a first display phase, which comprises an initialization phase, a compensation phase and an emitting phase arranged in sequence, and the compensation phase comprises a data write phase; the pixel driving method comprises: In the initialization phase, the first initialization circuit writes the second initial voltage to the control terminal of the driving circuit under the control of the reset control signal, so that the driving circuit can control the communication between the first node and the third node under the control of the potential of the control terminal at the beginning of the compensation phase; In the data write phase, the data line provides a data voltage Vdata, and the data write circuit writes the data voltage Vdata to the first node under the control of a write control signal; In the compensation phase, the compensation control circuit controls the communication between the second node and the third node under the control of a compensation control signal; In the emitting phase, the first emitting control circuit controls the communication between the first voltage terminal and the first node under the control of an emitting control signal, the second emitting control circuit controls the communication between the third node and the fourth node under the control of the emitting control signal, and the driving circuit generates a driving current for driving the light emitting element.

11. The pixel driving method according to claim 9, wherein The pixel circuit further comprises a data write circuit; the non-emitting phase comprises a data write phase; a display frame comprises a refresh sub-display frame and at least one holding sub-display frame; the refresh sub-display frame comprises the display period, and the holding sub-display frame comprises the display period; the pixel driving method further comprises: In the holding sub-display frame, the data line provides a first voltage signal; In the data writing stage in the refresh sub-display frame, the data line provides a data voltage, and the data writing circuit writes the data voltage into the first node under the control of the writing control signal.

12. The pixel driving method according to claim 11, wherein The pixel circuit further comprises a compensation control circuit; the display period further comprises a compensation stage; and the pixel driving method further comprises: In the data writing stage in the refresh sub-display frame, the data line provides a data voltage, and the data writing circuit writes the data voltage into the first node under the control of the writing control signal; In the compensation stage in the refresh sub-display frame, the compensation control circuit controls the communication between the control end of the driving circuit and the second end of the driving circuit under the control of a compensation control signal; In the light emitting stage in the refresh sub-display frame and the light emitting stage in the holding sub-display frame, the first light emitting control circuit controls the communication between the first voltage end and the first node under the control of a light emitting control signal, the second light emitting control circuit controls the communication between the third node and the fourth node under the control of the light emitting control signal, and the driving circuit generates a driving current for driving the light emitting element; In the holding sub-display frame, the compensation control circuit controls the disconnection between the control end of the driving circuit and the second end of the driving circuit under the control of a compensation control signal.

13. The pixel driving method according to claim 12, wherein In the display frame, the frequency of the writing control signal is less than the frequency of the light emitting control signal.

14. A display device comprising: A display panel comprising the pixel circuit as claimed in any one of claims 1 to 8.

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