Array substrate and display panel

Abstract

This application provides an array substrate and a display panel. The array substrate includes: a substrate; scan lines disposed on the substrate; common lines disposed on the substrate; data lines disposed on the substrate, with the data lines intersecting the scan lines; a first insulating layer disposed on the substrate, covering the scan lines and the common lines; a common electrode disposed on the first insulating layer, electrically connected to the common lines, the common electrode being made of transparent metal; a second insulating layer disposed on the first insulating layer, covering the common electrode; a thin-film transistor, the gate of which is electrically connected to the scan lines, and the source of which is electrically connected to the data lines; a color resist layer disposed on the second insulating layer; a planarization layer disposed on the color resist layer; and a pixel electrode disposed on the planarization layer, the pixel electrode and the common electrode partially overlapping in a direction perpendicular to the plane of the substrate. The array substrate and display panel of this application can avoid the occurrence of dark spots.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] In traditional liquid crystal display panels using COA (Color-filter On Array) technology, the common electrode is placed on the color resist layer, the planarization layer is placed on the color resist layer, and the pixel electrode is placed on the planarization layer.

[0003] The aforementioned liquid crystal display panel generates an image by applying different driving voltages to the pixel electrodes and the common electrode to control the deflection of the liquid crystal molecules in the liquid crystal layer, thereby allowing the light from the backlight module to pass through.

[0004] In practice, the inventors discovered that the pixel units of the aforementioned traditional liquid crystal display panels are prone to dark spots, that is, the pixel units are not transparent.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] This application provides an array substrate and a display panel that can avoid the occurrence of dark spots.

[0007] This application provides an array substrate, comprising: a substrate; scan lines disposed on the substrate; a common line disposed on the substrate; a data line disposed on the substrate, the data line intersecting the scan lines; a first insulating layer disposed on the substrate, the first insulating layer covering the scan lines and the common line; a common electrode disposed on the first insulating layer, the common electrode being electrically connected to the common line, the common electrode being made of a transparent metal; a second insulating layer disposed on the first insulating layer, the second insulating layer covering the common electrode; a thin-film transistor, the gate of the thin-film transistor being electrically connected to the scan lines, and the source of the thin-film transistor being electrically connected to the data lines; a color resist layer disposed on the second insulating layer; a planarization layer disposed on the color resist layer; and a pixel electrode disposed on the planarization layer, the pixel electrode and the common electrode partially overlapping in a direction perpendicular to the plane of the substrate, a portion of the pixel electrode being electrically connected to the drain of the thin-film transistor through a first via penetrating the planarization layer and the color resist layer.

[0008] In the array substrate described above, the gate includes a first gate and a second gate. The first gate is disposed between the substrate and the first insulating layer and is electrically connected to the scan line. The second gate is disposed between the first insulating layer and the second insulating layer and is electrically connected to the scan line. The material of the second gate is a transparent metal.

[0009] In the above-mentioned array substrate, a portion of the second gate is electrically connected to the scan line through a second via penetrating the first insulating layer; or a first bridging portion is further provided on the planarization layer, the material of the first bridging portion being transparent metal, the second gate being electrically connected to one end of the first bridging portion through a third via penetrating the second insulating layer and the planarization layer, and the scan line being electrically connected to the other end of the first bridging portion through a fourth via penetrating the first insulating layer, the second insulating layer, and the planarization layer.

[0010] In the above-mentioned array substrate, a portion of the common electrode is electrically connected to the common line through a fifth via penetrating the first insulating layer; or a second bridging portion is further provided on the planarization layer, the material of the second bridging portion being transparent metal, the common electrode being electrically connected to one end of the second bridging portion through a sixth via penetrating the second insulating layer and the planarization layer, and the common line being electrically connected to the other end of the second bridging portion through a seventh via penetrating the first insulating layer, the second insulating layer, and the planarization layer.

[0011] In the array substrate described above, the data line is broken into at least two data line segments at the position where it intersects with the scan line, and the scan line is disposed between two adjacent data line segments; the array substrate also includes a first bridging wire, the two ends of the first bridging wire being electrically connected to two adjacent data line segments disposed on both sides of the scan line through an eighth via and a ninth via that at least penetrate the first insulating layer, respectively, and the material of the first bridging wire is transparent metal.

[0012] In the aforementioned array substrate, the first bridging wire is disposed between the first insulating layer and the second insulating layer. Both the eighth via and the ninth via penetrate the first insulating layer. A segment of a data line is electrically connected to one end of the first bridging wire through the eighth via, and an adjacent segment of the data line is electrically connected to the other end of the first bridging wire through the ninth via. Alternatively, the first bridging wire is disposed on the second insulating layer, with the eighth via penetrating both the first and second insulating layers, and the ninth via penetrating both the first and second insulating layers. A segment of a data line is electrically connected to one end of the first bridging wire through the eighth via, and an adjacent segment of the data line is electrically connected to the other end of the first bridging wire through the ninth via. Alternatively, the first bridging wire is disposed on the planarization layer, with the eighth via penetrating the first insulating layer, the second insulating layer, and the planarization layer, and the ninth via penetrating the first insulating layer, the second insulating layer, and the planarization layer. A segment of a data line is electrically connected to one end of the first bridging wire through the eighth via, and an adjacent segment of the data line is electrically connected to the other end of the first bridging wire through the ninth via.

[0013] In the array substrate described above, the scan line is broken into at least two scan line segments at the position where it intersects with the data line, and the data line is disposed between two adjacent scan line segments; the array substrate also includes a second bridging wire, the two ends of the second bridging wire being electrically connected to two adjacent scan line segments disposed on both sides of the data line through at least a tenth via and an eleventh via penetrating the first insulating layer, and the material of the second bridging wire is transparent metal.

[0014] In the aforementioned array substrate, the second bridging wire is disposed between the first insulating layer and the second insulating layer. Both the tenth via and the eleventh via penetrate the first insulating layer. A scan line is segmented and electrically connected to one end of the second bridging wire through the tenth via, and an adjacent scan line is segmented and electrically connected to the other end of the second bridging wire through the eleventh via. Alternatively, the second bridging wire is disposed on the second insulating layer, with the tenth via penetrating both the first and second insulating layers, and the eleventh via penetrating both the first and second insulating layers. A scan line is segmented and electrically connected to one end of the second bridging wire through the tenth via, and an adjacent scan line is segmented and electrically connected to the other end of the second bridging wire through the eleventh via. One end of the second bridge wire is electrically connected through the tenth via, and the other adjacent scan line is electrically connected to the other end of the second bridge wire through the eleventh via; or the second bridge wire is disposed on the planarization layer, the tenth via penetrates the first insulating layer, the second insulating layer and the planarization layer, the eleventh via penetrates the first insulating layer, the second insulating layer and the planarization layer, one scan line is electrically connected to the other end of the second bridge wire through the tenth via, and the other adjacent scan line is electrically connected to the other end of the second bridge wire through the eleventh via.

[0015] In the above-mentioned array substrate, both the source and the drain are disposed on the second insulating layer, and the source is electrically connected to the data line through a twelfth via penetrating the first insulating layer and the second insulating layer; or both the source and the drain are disposed on the second insulating layer, and the array substrate further includes a third bridge wire, one end of which is connected to the source through a thirteenth via penetrating the color resist layer and the planarization layer, and the other end of which is electrically connected to the data line through a fourteenth via penetrating the planarization layer, the color resist layer, the second insulating layer and the first insulating layer, and the material of the third bridge wire is transparent metal.

[0016] This application also provides a display panel, the display panel including an opposing substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0017] In this application, since the common electrode is disposed below the color resist layer, that is, the color resist layer is disposed between the common electrode and the pixel electrode, and a second insulating layer is also disposed between the color resist layer and the common electrode, the needle-like crystals formed by the color resist layer after being heated will not cause the common electrode to contact (electrically connect) with the pixel electrode. Therefore, the technical solution of this application can effectively prevent the charge of the pixel electrode from flowing into the common electrode, thereby preventing the dark spot phenomenon of the display panel. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the cross-sectional structure of a traditional array substrate;

[0019] Figure 2 yes Figure 1 A schematic diagram of a cross-section of the portion of the array substrate in which needle-like crystals are formed;

[0020] Figure 3 yes Figure 1 Scanning electron microscope image of the surface of the array substrate in which needle-like crystals are formed;

[0021] Figure 4 This is a schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the planar structure of the array substrate provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0024] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0025] A traditional display panel includes an array substrate, an opposing substrate, and a liquid crystal layer, wherein the liquid crystal layer is disposed between the array substrate and the opposing substrate, such as... Figure 1 , Figure 2 and Figure 3As shown, a conventional array substrate includes a substrate 101, a thin-film transistor 102, a signal line layer 103, a gate insulating layer 104, a passivation layer, a color resist layer 105, a common electrode 106, a planarization layer 107, and a pixel electrode 108. The passivation layer is disposed on the gate insulating layer 104 and covers at least a portion of the thin-film transistor 102. The color resist layer 105 is disposed on the passivation layer. The common electrode 106 is disposed on the color resist layer 105 and is electrically connected to the common line of the signal line layer 103 through a via. The planarization layer 107 is disposed on the common electrode 106. The pixel electrode 108 is disposed on the planarization layer 107 and is electrically connected to the drain of the thin-film transistor 102. However, under EUV (Extreme Ultraviolet) lithography, the red resist dispersion system in the resist layer 105 is easily destroyed, and its connection with the surrounding dispersion system is weakened. Under the high temperature of the oven, the red resist easily forms needle-like crystals 1051, which pierce the common electrode 106 and the planarization layer 107 located between the common electrode 106 and the pixel electrode 108. This causes the common electrode 106 to come into direct contact with the pixel electrode 108, and the potential on the pixel electrode 108 is pulled away by the common electrode 106. Therefore, the display panel cannot be turned on normally, forming dark spots.

[0026] An embodiment of this application provides a display panel, which includes an array substrate, a counter substrate, and a liquid crystal layer. The liquid crystal layer is disposed between the array substrate and the counter substrate. A common electrode and a black matrix are disposed on the counter substrate, and the common electrode covers the black matrix.

[0027] like Figure 4 and Figure 5 As shown, the array substrate 200 provided in this application embodiment adopts COA technology. The array substrate 200 includes a substrate 201, a metal wiring layer 202, an insulating layer, a thin film transistor 206, a first transparent metal layer 204, a color resist layer 207, a planarization layer 208, and a second transparent metal layer 209.

[0028] The metal trace layer 202 includes data lines 2023, common lines 2022, and scan lines 2021 disposed on the substrate 201. The data lines 2023, common lines 2022, and scan lines 2021 are made of the same metal layer. The scan lines 2021 and common lines 2022 are parallel and insulated from each other, while the scan lines 2021 and data lines 2023 are perpendicular and insulated from each other. The data lines intersect with the scan lines, and the data lines 2023 are interrupted at their intersection with the scan lines 2021. The material of the metal trace layer includes, but is not limited to, one or more combinations of aluminum, chromium, molybdenum, and copper.

[0029] The insulating layer includes a first insulating layer 203 disposed on the substrate 201 and a second insulating layer 205 stacked on the first insulating layer 203. The first insulating layer 203 covers the scan line 2021, the common line 2022 and the data line 2023, that is, the data line 2023, the common line 2022 and the scan line 2021 are disposed between the substrate 201 and the first insulating layer 203.

[0030] The first transparent metal layer 204 is disposed between the first insulating layer 203 and the second insulating layer 205. The first transparent metal layer 204 includes a common electrode 2042, which is disposed on the first insulating layer 203. A portion of the common electrode 2042 is electrically connected to the common line 2022 through a fifth via penetrating the first insulating layer 203. The material of the common electrode 2042 is a transparent metal, such as indium tin oxide (ITO). The common electrode 2042 is sheet-shaped and spans multiple pixel units along the length of the scan line 2021. The common electrode 2042 shields a portion of the data line 2023, that is, the common electrode 2042 and a portion of the data line 2023 overlap in a direction perpendicular to the plane of the substrate 201. The common electrode 2042 extends along the row direction (the length direction of the scan line 2021), and the common electrode 2042 is used to shield the electric field of the data line 2023 from the electric field of the pixel electrode.

[0031] The array substrate further includes a first bridging wire. Specifically, the first transparent metal layer 204 also includes a first bridging wire, that is, the material of the first bridging wire is transparent metal. The first bridging wire is separated (insulated) from the common electrode 2042. The length direction of the elongated first bridging wire is perpendicular to the direction of the scan line 2021. The width of the first bridging wire is equal to the width of the data line 2023 (equal here includes the case where the difference in width between the two is within 5%). The first bridging wire is disposed between the first insulating layer 203 and the second insulating layer 205. One data line 2023 is broken into at least two data line segments at the position where it intersects with the scan line. One data line segment is disposed between two adjacent scan lines 2021, and one scan line 2021 is disposed between two adjacent data line segments. The two ends of the first bridging wire are electrically connected to two adjacent data line segments disposed on both sides of the scan line 2021 through at least an eighth via and a ninth via penetrating the first insulating layer 203, respectively. The adjacent data line segments are electrically connected by the first bridging wire, and the length of the first bridging wire is greater than the distance between the ends of the adjacent data line segments located on both sides of the scan line 2021 (the spacing of the data lines 2023 at the break). The first bridging wire is disposed between the first insulating layer and the second insulating layer. Both the eighth via and the ninth via penetrate the first insulating layer. A segment of one data line is electrically connected to one end of the first bridging wire through the eighth via, and a segment of an adjacent data line is electrically connected to the other end of the first bridging wire through the ninth via. Alternatively, the first bridging wire is disposed on the second insulating layer. The eighth via penetrates both the first and second insulating layers, and the ninth via penetrates both the first and second insulating layers. A segment of one data line is electrically connected to one end of the first bridging wire through the eighth via, and a segment of an adjacent data line is electrically connected to the other end of the first bridging wire through the ninth via. Alternatively, the first bridging wire is disposed on the planarization layer. The eighth via penetrates the first insulating layer, the second insulating layer, and the planarization layer, and the ninth via penetrates the first insulating layer, the second insulating layer, and the planarization layer. A segment of one data line is electrically connected to one end of the first bridging wire through the eighth via, and a segment of an adjacent data line is electrically connected to the other end of the first bridging wire through the ninth via.

[0032] As an alternative, the scan line is broken into at least two scan line segments at the position where it intersects with the data line. The data line is disposed between two adjacent scan line segments. The array substrate also includes a second bridging wire. The two ends of the second bridging wire are electrically connected to two adjacent scan line segments disposed on both sides of the data line through at least two tenth vias and eleventh vias penetrating the first insulating layer. The material of the second bridging wire is transparent metal.

[0033] The second bridging wire is disposed between the first insulating layer and the second insulating layer. Both the tenth via and the eleventh via penetrate the first insulating layer. A segment of a scan line is electrically connected to one end of the second bridging wire through the tenth via, and a segment of an adjacent scan line is electrically connected to the other end of the second bridging wire through the eleventh via. Alternatively, the second bridging wire is disposed on the second insulating layer. The tenth via penetrates both the first and second insulating layers, and the eleventh via penetrates both the first and second insulating layers. A segment of a scan line is electrically connected to one end of the second bridging wire through the tenth via, and a segment of an adjacent scan line is electrically connected to the other end of the second bridging wire through the eleventh via. Alternatively, the second bridging wire is disposed on the planarization layer. The tenth via penetrates the first insulating layer, the second insulating layer, and the planarization layer, and the eleventh via penetrates both the first and second insulating layers. A segment of a scan line is electrically connected to one end of the second bridging wire through the tenth via, and a segment of an adjacent scan line is electrically connected to the other end of the second bridging wire through the eleventh via.

[0034] The diameter of the maximum inscribed circle of the eighth and ninth vias is greater than the width of the data line 2023 or the first bridge wire. A portion of the first bridge wire fills the eighth and ninth vias, thus ensuring good contact between the data line 2023 and the first bridge wire.

[0035] The second insulating layer 205 is disposed on the first insulating layer 203, and the second insulating layer 205 covers the common electrode 2042. The thickness of the second insulating layer 205 is less than the thickness of the first insulating layer 203.

[0036] The source and drain of the thin-film transistor 206 are both disposed on the second insulating layer 205. The source of the thin-film transistor 206 is electrically connected to the data line 2023. The gate of the thin-film transistor 206 includes a first gate and a second gate 2041. The first gate is disposed between the substrate 201 and the first insulating layer 203, and is electrically connected to the scan line 2021. The material of the first gate is the same as the material of the scan line 2021. That is, the first gate, the data line 2023, the scan line 2021, and the common line 2022 are disposed on the same layer. The second gate 2041 is disposed on the data line 2023. Between the first insulating layer 203 and the second insulating layer 205, the material of the second gate 2041 is transparent metal, and a portion of the second gate 2041 is electrically connected to the scan line 2021 through a second via penetrating the first insulating layer 203; or, a first bridging portion is further provided on the planarization layer, the material of the first bridging portion is transparent metal, the second gate is electrically connected to one end of the first bridging portion through a third via penetrating the second insulating layer and the planarization layer, and the scan line is electrically connected to the other end of the first bridging portion through a fourth via penetrating the first insulating layer, the second insulating layer and the planarization layer.

[0037] As an alternative, a second bridging portion is also provided on the planarization layer. The material of the second bridging portion is transparent metal. The common electrode is electrically connected to one end of the second bridging portion through a sixth via penetrating the second insulating layer and the planarization layer. The common line is electrically connected to the other end of the second bridging portion through a seventh via penetrating the first insulating layer, the second insulating layer, and the planarization layer.

[0038] The source electrode is electrically connected to the data line 2023 through a twelfth via penetrating the first insulating layer and the second insulating layer 205. Alternatively, the source electrode can be electrically connected to the first bridge wire or the data line 2023 through a metal layer disposed on the second insulating layer 205. In this application, by adding a second gate 2041 electrically connected to the first gate, the distance between the gate and the semiconductor layer can be reduced, ensuring that the gate has greater controllability.

[0039] As an alternative, both the source and the drain are disposed on the second insulating layer. The array substrate further includes a third bridge wire. One end of the third bridge wire is connected to the source through a thirteenth via penetrating the color resist layer and the planarization layer. The other end of the third bridge wire is electrically connected to the data line through a fourteenth via penetrating the planarization layer, the color resist layer, the second insulating layer, and the first insulating layer. The material of the third bridge wire is transparent metal.

[0040] The color resist layer 207 is disposed on the second insulating layer 205. Of course, a passivation layer (not shown in the figure) may also be disposed between the color resist layer 207 and the second insulating layer 205. The passivation layer also covers at least a portion of the thin film transistor 206. The color resist layer 207 includes multiple color resists of different colors, and the portions of two adjacent color resists of different colors overlap.

[0041] The planarization layer 208 is disposed on the color resist layer 207 and covers the color resist layer 207.

[0042] The second transparent metal layer is disposed on the planarization layer 208. The second transparent metal layer includes the pixel electrode 209. The pixel electrode 209 is made of transparent metal. The pixel electrode 209 is connected to the drain of the thin film transistor 206. That is, the pixel electrode 209 is disposed on the planarization layer 208. A portion of the pixel electrode 209 is electrically connected to the drain of the thin film transistor 206 through a first via penetrating the planarization layer 208 and the color resist layer 207. The pixel electrode 209 and the common electrode 2042 partially overlap in a direction perpendicular to the plane of the substrate 201. The pixel electrode 209 and the common electrode 2042 constitute a storage capacitor.

[0043] The first bridging wire can also be disposed on the planarization layer 208 or the second insulating layer 205. Two adjacent data lines are electrically connected to the first bridging wire disposed on the planarization layer 208 or the second insulating layer 205 through the eighth via and the ninth via. The eighth via and the ninth via penetrate the first insulating layer 203 and the second insulating layer 205, or the eighth via and the ninth via penetrate the first insulating layer 203, the second insulating layer 205 and the planarization layer 208.

[0044] To ensure that the common electrode 2042 functions properly as a transparent storage capacity and shielding layer (TSS), the data line 2023 is disposed between the substrate 201 and the first insulating layer 203 (the data line 2023 is disposed on the same layer as the scan line 2021). Therefore, a portion of the common electrode 2042 can cover the data line 2023, thereby shielding the electric field of the data line 2023 and effectively reducing light leakage caused by the electric field of the data line 2023.

[0045] As an improvement, the length of the common electrode 2042 covering the data line 2023 (the data line segment) in the column direction (the length direction of the data line 2023) is greater than or equal to the length of the pixel electrode 209 in the column direction.

[0046] As an improvement, to further prevent needle-like crystals generated by the red resist in the color resist layer 207 from piercing the pixel electrode 209, the array substrate further includes a protective layer. The protective layer is disposed between the color resist layer 207 and the planarization layer 208, or between the planarization layer 208 and the pixel electrode 209. The protective layer is a single film layer or a combination of one or more of silicon dioxide, silicon nitride, and aluminum oxide. Since silicon dioxide, silicon nitride, and aluminum oxide have the characteristics of being transparent, hard, and insulating, the protective layer made of one or more of silicon dioxide, silicon nitride, and aluminum oxide on the color resist layer 207 can effectively prevent the needle-like crystals generated by the color resist layer 207 from extending to the pixel electrode 209, thereby damaging (piercing) the pixel electrode 209, and will not have a significant impact on the light transmittance of the display panel, nor will it cause the pixel electrode 209 to short-circuit or lose charge.

[0047] As an improvement, when the protective layer is disposed between the color resist layer and the planarization layer, the thickness of the protective layer is greater than the thickness of the color resist layer. This makes the length of the needle-like crystals generated in the red color resist less than the thickness of the protective layer, thereby effectively preventing the needle-like crystals from touching the pixel electrode.

[0048] As an improvement, to prevent needle-like crystal formation in the red resist layer 207, the red resist layer 207 comprises at least a first red resist stack, a spacer layer, and a second red resist stack. The first red resist stack is disposed on the second insulating layer 205 or the passivation layer, the spacer layer is disposed on the first red resist stack, and the second red resist stack is disposed on the spacer layer. That is, the conventional red resist is divided into multiple different red sub-resistors in a direction perpendicular to the plane of the substrate 201 by the transparent spacer layer. The thickness of any one of the first red resist stack, the spacer layer, and the second red resist stack is less than the thickness of the green and blue resists in the resist layer 207. The spacer layer is made of one or more of silicon dioxide, silicon nitride, and aluminum oxide (stacked). By using the spacer layer to divide the red color resist into at least two thinner red sub-color resists, the length of the needle-like crystals generated by the red color resist can be effectively reduced. That is, even if the needle-like crystals are generated in one of the red sub-color resists, the length of the needle-like crystals is small and difficult to reach the pixel electrode 209, let alone pierce the pixel electrode 209. Even if the needle-like crystals are generated in at least two red sub-color resists, the probability that the needle-like crystals generated by the two red sub-color resists are generated in the same position and connected together is small, making it difficult to form long needle-like crystals, and therefore difficult to reach and pierce the pixel electrode 209.

[0049] In this application, since the common electrode 2042 is disposed below the color resist layer 207, that is, the color resist layer 207 is disposed between the common electrode 2042 and the pixel electrode 209, and the second insulating layer 205 is also disposed between the color resist layer 207 and the common electrode 2042, the needle-like crystals formed by the color resist layer 207 after being heated will not cause the common electrode 2042 to contact (electrically connect) with the pixel electrode 209. Therefore, the technical solution of this application can effectively prevent the charge of the pixel electrode 209 from flowing into the common electrode 2042, thereby preventing the dark spot phenomenon of the display panel.

[0050] Because the common electrode 2042 and the pixel electrode 209 are separated by the second insulating layer 205 and the planarization layer 208, the distance between the common electrode 2042 and the pixel electrode 209 is increased. Even if the needle-like crystals formed after the color resist layer 207 is heated pierce the planarization layer 208, the common electrode 2042 will not come into contact with the pixel electrode 209. In this case, the planarization layer 208 and the second insulating layer 205 can be thinned, thereby reducing the driving voltage (since the distance between the pixel electrode 209 and the common electrode 2042 is smaller, the same display effect (driving effect) can be achieved by reducing the voltage of the data signal input to the pixel electrode 209). Furthermore, the material of the planarization layer 208 can be replaced from organic to inorganic materials, which is beneficial for improving production efficiency.

[0051] The above provides a detailed description of an array substrate and display panel provided by the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the core idea of ​​this application, and the above description should not be construed as a limitation on the scope of protection of this application.

Claims

1. An array substrate, characterized in that, include: substrate; Scan lines are disposed on the substrate; A common line is disposed on the substrate; A data line is disposed on the substrate, and the data line is arranged to intersect with the scan line. A first insulating layer is disposed on the substrate, and the first insulating layer covers the scan line and the common line; A common electrode is disposed on the first insulating layer, and the common electrode is electrically connected to the common line. The material of the common electrode is a transparent metal. A second insulating layer is disposed on the first insulating layer, and the second insulating layer covers the common electrode; A thin-film transistor, wherein the gate of the thin-film transistor is electrically connected to the scan line, and the source of the thin-film transistor is electrically connected to the data line; A color resist layer is disposed on the second insulating layer; A planarization layer is disposed on the color resist layer; as well as Pixel electrodes are disposed on the planarization layer. A protective layer is disposed between the color resist layer and the planarization layer, or between the planarization layer and the pixel electrode. The protective layer is a single film layer or a combination of one or more of silicon dioxide, silicon nitride, and aluminum oxide. The pixel electrode and the common electrode partially overlap in a direction perpendicular to the plane of the substrate. A portion of the pixel electrode is electrically connected to the drain of the thin-film transistor through a first via penetrating the planarization layer and the color resist layer.

2. The array substrate according to claim 1, characterized in that, The gate includes a first gate and a second gate. The first gate is disposed between the substrate and the first insulating layer and is electrically connected to the scan line. The second gate is disposed between the first insulating layer and the second insulating layer and is electrically connected to the scan line. The material of the second gate is a transparent metal.

3. The array substrate according to claim 2, characterized in that, A portion of the second gate is electrically connected to the scan line through a second via penetrating the first insulating layer; or The planarization layer is further provided with a first bridging portion, the first bridging portion being made of transparent metal. The second gate is electrically connected to one end of the first bridging portion through a third via penetrating the second insulating layer and the planarization layer. The scan line is electrically connected to the other end of the first bridging portion through a fourth via penetrating the first insulating layer, the second insulating layer, and the planarization layer.

4. The array substrate according to claim 1, characterized in that, A portion of the common electrode is electrically connected to the common line through a fifth via penetrating the first insulating layer; or The planarization layer is further provided with a second bridging portion, which is made of transparent metal. The common electrode is electrically connected to one end of the second bridging portion through a sixth via penetrating the second insulating layer and the planarization layer. The common line is electrically connected to the other end of the second bridging portion through a seventh via penetrating the first insulating layer, the second insulating layer, and the planarization layer.

5. The array substrate according to claim 1, characterized in that, The data line is broken into at least two data line segments at the position where it intersects with the scan line, and the scan line is disposed between two adjacent data line segments; The array substrate further includes a first bridging wire, the two ends of which are respectively electrically connected to two adjacent data lines disposed on both sides of the scan line through an eighth via and a ninth via that penetrate at least the first insulating layer. The material of the first bridging wire is transparent metal.

6. The array substrate according to claim 5, characterized in that, The first bridging wire is disposed between the first insulating layer and the second insulating layer. Both the eighth via and the ninth via penetrate the first insulating layer. One data line is segmented and electrically connected to one end of the first bridging wire through the eighth via, and the adjacent data line is segmented and electrically connected to the other end of the first bridging wire through the ninth via; or The first bridging wire is disposed on the second insulating layer. The eighth via penetrates both the first and second insulating layers. The ninth via penetrates both the first and second insulating layers. One data line is segmented and electrically connected to one end of the first bridging wire through the eighth via. An adjacent data line is segmented and electrically connected to the other end of the first bridging wire through the ninth via. The first bridging wire is disposed on the planarization layer. The eighth via penetrates the first insulating layer, the second insulating layer, and the planarization layer. The ninth via penetrates the first insulating layer, the second insulating layer, and the planarization layer. One data line is electrically connected to one end of the first bridging wire through the eighth via, and the other adjacent data line is electrically connected to the other end of the first bridging wire through the ninth via.

7. The array substrate according to claim 1, characterized in that, The scan line is broken into at least two scan line segments at the position where it intersects with the data line, and the data line is disposed between two adjacent scan line segments; The array substrate further includes a second bridging wire, the two ends of which are respectively electrically connected to two adjacent scan lines disposed on both sides of the data line through a tenth via and an eleventh via that penetrate at least the first insulating layer. The material of the second bridging wire is transparent metal.

8. The array substrate according to claim 7, characterized in that, The second bridging wire is disposed between the first insulating layer and the second insulating layer. The tenth via and the eleventh via both penetrate the first insulating layer. One scan line is electrically connected to one end of the second bridging wire in segments through the tenth via, and the other adjacent scan line is electrically connected to the other end of the second bridging wire in segments through the eleventh via. or The second bridging wire is disposed on the second insulating layer. The tenth via penetrates the first insulating layer and the second insulating layer. The eleventh via penetrates the first insulating layer and the second insulating layer. One scan line is electrically connected to one end of the second bridging wire through the tenth via. The other adjacent scan line is electrically connected to the other end of the second bridging wire through the eleventh via. or The second bridging wire is disposed on the planarization layer. The tenth via penetrates the first insulating layer, the second insulating layer, and the planarization layer. The eleventh via penetrates the first insulating layer, the second insulating layer, and the planarization layer. One scan line segment is electrically connected to one end of the second bridging wire through the tenth via. The adjacent scan line segment is electrically connected to the other end of the second bridging wire through the eleventh via.

9. The array substrate according to claim 1, characterized in that, Both the source and the drain are disposed on the second insulating layer, and the source is electrically connected to the data line through a twelfth via penetrating the first and second insulating layers; or Both the source and the drain are disposed on the second insulating layer. The array substrate further includes a third bridge wire. One end of the third bridge wire is connected to the source through a thirteenth via penetrating the color resist layer and the planarization layer. The other end of the third bridge wire is electrically connected to the data line through a fourteenth via penetrating the planarization layer, the color resist layer, the second insulating layer and the first insulating layer. The material of the third bridge wire is transparent metal.

10. A display panel, characterized in that, The display panel includes an opposing substrate, a liquid crystal layer, and an array substrate as described in any one of claims 1 to 9, wherein the liquid crystal layer is disposed between the array substrate and the opposing substrate.

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