Gate driving circuit and display panel

Abstract

The application provides a gate drive circuit and a display panel. The gate drive circuit comprises N GOA units in cascade. An nth-stage GOA unit comprises a pull-up control module, a pull-up module, a pull-down module and a pull-down maintenance module. The pull-up module receives a first clock signal to output a first gate drive signal to a gate signal terminal of the nth-stage, and receives a second clock signal to output a second gate drive signal to a gate signal terminal of an (n+1)th-stage. The application sets the gate signal terminal of the nth-stage and the gate signal terminal of the (n+1)th-stage in one GOA unit, so that one GOA unit outputs two-stage gate drive signals to scan two rows of sub-pixels in the display panel. The number of GOA units in the gate drive circuit is reduced, the space occupied by the gate drive circuit in the frame of the display panel is reduced, and a narrow frame design is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and particularly relates to a gate drive circuit and a display panel. BACKGROUND

[0002] Gate Drive On Array (GOA) technology is to integrate a scan line drive circuit on an array substrate of a liquid crystal panel, thereby reducing product cost in terms of material cost and manufacturing process.

[0003] With the development of display industry technology, users have higher and higher requirements on the appearance design of display panels, such as the design of a narrow frame. A gate drive circuit is arranged in a frame area of a display panel, the gate drive circuit includes n-stage GOA units, and each stage of GOA unit is provided with a plurality of thin film transistors, so that the frame area cannot be further reduced.

[0004] At present, a gate drive circuit is urgently needed to solve the above technical problems. SUMMARY

[0005] The present application provides a gate drive circuit and a display panel to solve the technical problem of a large frame of an existing display panel.

[0006] To solve the above problems, the technical scheme provided by the present application is as follows:

[0007] The present application provides a gate drive circuit, the gate drive circuit includes N GOA units in cascade, the nth GOA unit is any one of the N GOA units, the nth GOA unit includes a pull-up control module, a pull-up module, a pull-down module and a pull-down maintenance module, the pull-up control module and the pull-up module are connected to a first control node, the pull-down module is electrically connected to the first control node and a first potential line, and the pull-down maintenance module is electrically connected to the first control node and a second potential line.

[0008] The pull-up control module receives a first-stage transmission signal in a first stage, and pulls up the first control node to a first high potential;

[0009] The pull-up module receives a first clock signal and outputs a first gate drive signal to a gate signal end of the nth stage according to the potential of the first control node, and the pull-up module receives a second clock signal and outputs a second gate drive signal to a gate signal end of the nth+1 stage according to the potential of the first control node;

[0010] The pull-down module receives a second-stage transmission signal in a third stage, and pulls down the potential of the first control node to a first low potential;

[0011] The pull-down maintaining module receives a third clock signal in the third stage, and pulls down the potential of the gate signal end of the nth stage to a second direct current low level and pulls down the potential of the gate signal end of the nth+1 stage to the first low potential.

[0012] In the gate drive circuit, the pull-up control module is connected with the stage transmission signal end of the nth-X stage, the first control node, the first high potential line and the pull-down maintaining module, and the stage transmission signal end of the nth-X stage is used for outputting the first stage transmission signal.

[0013] The pull-up control module comprises a pull-up control transistor, a gate of the pull-up control transistor is connected with the first stage transmission signal end, a source of the pull-up control transistor is connected with the first high potential line, and a drain of the pull-up control transistor is connected with the first control node and the pull-down maintaining module.

[0014] In the gate drive circuit, the pull-up module comprises a first pull-up unit and a second pull-up unit, the first pull-up unit is connected with the first control node, the clock signal line of the nth stage and the gate signal end of the nth stage, and the second pull-up unit is connected with the first control node, the clock signal line of the nth+1 stage and the gate signal end of the nth+1 stage.

[0015] The clock signal line of the nth stage is used for providing the first clock signal, and the clock signal line of the nth+1 stage is used for providing the second clock signal.

[0016] In the gate drive circuit, the first pull-up unit comprises a first pull-up transistor, a gate of the first pull-up transistor is connected with the first control node, a source of the first pull-up transistor is connected with the clock signal line of the nth stage, and a drain of the first pull-up transistor is connected with the gate signal end of the nth stage.

[0017] The second pull-up unit comprises a second pull-up transistor, a gate of the second pull-up transistor is connected with the first control node, a source of the second pull-up transistor is connected with the clock signal line of the nth+1 stage, and a drain of the second pull-up transistor is connected with the gate signal end of the nth+1 stage.

[0018] In the gate drive circuit, the pull-up module further comprises a stage transmission unit, and the stage transmission unit comprises a stage transmission transistor.

[0019] A gate of the stage transmission transistor is connected with the first control node, a source of the stage transmission transistor is connected with the first clock signal line, and a drain of the stage transmission transistor is connected with the stage transmission signal end of the nth stage.

[0020] In the gate drive circuit of the present application, the pull-down module comprises a pull-down transistor, a gate of the pull-down transistor is connected to a stage transmission signal terminal of an n+Yth stage, a source of the pull-down transistor is connected to the first control node, and a drain of the pull-down transistor is connected to the first low potential line, and the stage transmission signal terminal of the n+Yth stage is used to provide the second stage transmission signal.

[0021] In the gate drive circuit of the present application, the pull-down maintaining module comprises an inverter and a voltage adjusting unit, the voltage adjusting unit and the inverter are connected to the second control node, and the inverter is used to control the potential of the second control node.

[0022] The voltage adjusting unit comprises a first adjusting transistor, a second adjusting transistor, a third adjusting transistor, a fourth adjusting transistor and a fifth adjusting transistor.

[0023] A gate of the first adjusting transistor is connected to the second control node, a source of the first adjusting transistor is connected to a gate signal terminal of an nth stage, and a drain of the first adjusting transistor is connected to the second low potential line.

[0024] A gate of the second adjusting transistor is connected to the second control node, a source of the second adjusting transistor is connected to a gate signal terminal of an n+1th stage, and a drain of the second adjusting transistor is connected to the first low potential line.

[0025] A gate of the third adjusting transistor is connected to the second control node, a source of the third adjusting transistor is connected to the first control node, and a drain of the third adjusting transistor is connected to the first low potential line.

[0026] A gate of the fourth adjusting transistor and a gate of the fifth adjusting transistor are connected to the second control node, a source of the fourth adjusting transistor is connected to the first control node, a drain of the fourth adjusting transistor and a source of the fifth adjusting transistor are connected to a stage transmission signal terminal of the nth stage, and a drain of the fifth adjusting transistor is connected to the first low potential line.

[0027] In the gate drive circuit of the present application, the inverter comprises a first inverting transistor, a second inverting transistor, a third inverting transistor, a fourth inverting transistor, a fifth inverting transistor and a sixth inverting transistor.

[0028] A gate of the first inverting transistor is connected to a clock signal line of an n+Yth stage, a source of the first inverting transistor and a source of the third inverting transistor are connected to a second high potential line, a drain of the first inverting transistor and a gate of the third inverting transistor are connected to a third control node, and a drain of the third inverting transistor is connected to the second control node.

[0029] The gate of the second inverter transistor and the gate of the fourth inverter transistor are connected to the first control node, the source of the second inverter transistor is connected to the third control node, the source of the fourth inverter transistor and the source of the fifth inverter transistor are connected to the second control node, and the drain of the second inverter transistor, the drain of the fourth inverter transistor and the drain of the fifth inverter transistor are connected to the first low potential line;

[0030] The gate of the sixth inverter transistor and the gate of the fifth inverter transistor are connected to the clock signal line of the n+Y-Xth stage, the source of the sixth inverter transistor is connected to the third control node, and the drain of the sixth inverter transistor is connected to the first low potential line.

[0031] Among them, the clock signal line of the n+Yth stage is used to output a third clock signal, the clock signal line of the n+Y-Xth stage is used to output a fourth clock signal, and the third clock signal and the fourth clock signal are mutually coupled signals.

[0032] In the gate drive circuit of the present application, the inverter further comprises a reset transistor, the gate of the reset transistor is connected to a reset signal line, the source of the reset transistor is connected to the second high potential line, and the drain of the reset transistor is connected to the second control node.

[0033] In the gate drive circuit of the present application, the gate drive circuit comprises m clock signal lines, X is greater than or equal to (m / 2)-1 and less than or equal to (m / 2)+1.

[0034] In the gate drive circuit of the present application, the first plate of the bootstrap capacitor is connected to the first control node and the pull-up module, and the second plate of the bootstrap capacitor is connected to the gate signal end of the n th stage and the pull-down maintenance module.

[0035] The present application also proposes a display panel comprising the above-mentioned gate drive circuit.

[0036] Beneficial effects: By arranging the gate signal end of the n th stage and the gate signal end of the n+1 th stage in one GOA unit, the present application enables one GOA unit to output two-stage gate drive signals to scan two rows of sub-pixels in the display panel, reduces the number of GOA units in the gate drive circuit, reduces the space occupied by the gate drive circuit in the frame of the display panel, and realizes narrow frame design. BRIEF DESCRIPTION OF DRAWINGS

[0037] The technical solutions and other beneficial effects of the present application will become apparent through the following detailed description of specific embodiments of the present application in conjunction with the accompanying drawings.

[0038] Figure 1 A structure diagram of a GOA unit in a gate driving circuit of the present application;

[0039] Figure 2 A timing control diagram in the gate driving circuit of the present application;

[0040] Figure 3 A state diagram of the GOA unit in the reset stage; Figure 2

[0041] Figure 4 A state diagram of the GOA unit in the first stage; Figure 2

[0042] Figure 5 A state diagram of the GOA unit in the second stage; Figure 2

[0043] Figure 6 A state diagram of the GOA unit in the third stage; Figure 2

[0044] Figure 7 A state diagram of the GOA unit in the fourth stage; Figure 2

[0045] A structure diagram of a display panel of the present application. Figure 8 DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0047] With the development of display industry technology, users have higher and higher requirements on the appearance design of display panels, such as the design of narrow frame. The frame area of the display panel is provided with a gate driving circuit, which includes n-stage GOA units, and each stage of GOA unit is provided with a plurality of thin film transistors, so that the frame area cannot be further reduced. The present application proposes the following technical solutions based on the above technical problems:

[0048] Please refer to Figures 1 to 7 The present application proposes a gate driving circuit, which includes N GOA units 100 connected in cascade, and the nth-stage GOA unit 100 is any one of the N GOA units 100.

[0049] ​​​​​In the embodiment, the nth GOA unit 100 can include a pull-up control module 10, a bootstrap capacitor Cbt, a pull-up module 20, a pull-down module 30, and a pull-down maintenance module 40, the pull-up control module 10 and the pull-up module 20 are connected to the first control node Q, the pull-down module 30 is electrically connected to the first control node Q and the first potential line VSSQ, and the pull-down maintenance module 40 is electrically connected to the first control node VSSQ and the second potential line VSSG.

[0050] In the embodiment, the pull-up control module 10 receives the first stage transmission signal at the first stage, pulls up the first control node Q to the first high potential, and charges the bootstrap capacitor Cbt; the bootstrap capacitor Cbt maintains the potential of the first control node Q at the second stage; the pull-up module 20 receives the first clock signal and outputs the first gate drive signal to the gate signal end G(n) of the nth stage according to the potential of the first control node Q, and the pull-up module 20 receives the second clock signal and outputs the second gate drive signal to the gate signal end G(n+1) of the nth+1 stage according to the potential of the first control node Q; the pull-down module 30 receives the second stage transmission signal at the third stage, and pulls down the potential of the first control node Q to the first low potential; the pull-down maintenance module 40 receives the third clock signal at the third stage, pulls down the potential of the gate signal end G(n) of the nth stage to the second direct-current low level, and pulls down the potential of the gate signal end G(n+1) of the nth+1 stage to the first low potential.

[0051] The application sets the gate signal end G(n) of the nth stage and the gate signal end G(n+1) of the nth+1 stage in one GOA unit 100, so that one GOA unit 100 outputs two-stage gate drive signals to scan two rows of sub-pixels in the display panel, reduces the number of GOA units 100 in the gate drive circuit, that is, reduces the space occupied by the gate drive circuit in the display panel frame, and realizes narrow-frame design; for example, the display panel of the application has K rows of sub-pixels, and the number of GOA units 100 required is only K / 2, and the number of thin film transistors is reduced by nearly half, so that the arrangement of transistors in the GOA unit 100 can be redesigned to realize narrow-frame design of the display panel.

[0052] Please refer to Figure 1 The pull-up control module 10 is connected to the stage transmission signal end ST(n-X) of the nth-X stage, the first control node Q, the first high potential line Vgh, and the pull-down maintenance module 40, and the stage transmission signal end ST(n-X) of the nth-X stage is used to output the first stage transmission signal; the pull-up control module 10 includes a pull-up control transistor T11, the gate of the pull-up control transistor T11 is connected to the stage transmission signal end ST(n-X) of the nth-X stage, the source of the pull-up control transistor T11 is connected to the first high potential line Vgh, and the drain of the pull-up control transistor T11 is connected to the first control node Q and the pull-down maintenance module 40.

[0053] In this embodiment, the gate drive circuit can include m clock signal lines, X is greater than or equal to (m / 2)-1 and less than or equal to (m / 2)+1. For example, when the gate drive circuit includes 4 clock signal lines, X can be one of 1, 2, 3; when the gate drive circuit includes 8 clock signal lines, X can be one of 3, 4, 5.

[0054] In this embodiment, the value of X is usually half of the clock signal lines in the gate drive circuit.

[0055] Referring to Figure 1 The pull-up module 20 includes a first pull-up unit 210 and a second pull-up unit 220, the first pull-up unit 210 is connected with the first control node Q, the clock signal line CK(n) of the n-th stage, and the gate signal end G(n) of the n-th stage, the second pull-up unit 220 is connected with the first control node Q, the clock signal line CK(n+1) of the n+1-th stage, and the gate signal end G(n+1) of the n+1-th stage; the clock signal line CK(n) of the n-th stage is used to provide a first clock signal, and the clock signal line CK(n+1) of the n+1-th stage is used to provide a second clock signal.

[0056] Referring to Figure 1 The first pull-up unit 210 includes a first pull-up transistor T21, the gate of the first pull-up transistor T21 is connected with the first control node Q, the source of the first pull-up transistor T21 is connected with the clock signal line CK(n) of the n-th stage, and the drain of the first pull-up transistor T21 is connected with the gate signal end G(n) of the n-th stage.

[0057] In this embodiment, the second pull-up unit 220 includes a second pull-up transistor T211, the gate of the second pull-up transistor T211 is connected with the first control node Q, the source of the second pull-up transistor T211 is connected with the clock signal line CK(n+1) of the n+1-th stage, and the drain of the second pull-up transistor T211 is connected with the gate signal end G(n+1) of the n+1-th stage.

[0058] Referring to Figure 1 The pull-up module 20 further includes a stage transmission unit 230, the stage transmission unit 230 includes a stage transmission transistor T22; the gate of the stage transmission transistor T22 is connected with the first control node Q, the source of the stage transmission transistor T22 is connected with the first clock signal line, and the drain of the stage transmission transistor T22 is connected with the stage transmission signal end ST(n) of the n-th stage.

[0059] Referring to Figure 1The pull-down module 30 comprises a pull-down transistor T41, a gate of the pull-down transistor T41 is connected with the stage transmission signal terminal ST(n+Y) of the n+Yth stage, a source of the pull-down transistor T41 is connected with the first control node Q, and a drain of the pull-down transistor T41 is connected with the first low potential line VSSQ. The stage transmission signal terminal ST(n+Y) of the n+Yth stage is used for providing a second stage transmission signal, and Y is an integer.

[0060] Referring to Figure 1 The pull-down maintaining module 40 comprises an inverter 410 and a voltage adjusting unit 420. The voltage adjusting unit 420 and the inverter 410 are connected with the second control node P. The inverter 410 is used for controlling the potential of the second control node P.

[0061] In the embodiment, the voltage adjusting unit 420 comprises a first adjusting transistor T32, a second adjusting transistor T321, a third adjusting transistor T42, a fourth adjusting transistor T412 and a fifth adjusting transistor T72.

[0062] A gate of the first adjusting transistor T32 is connected with the second control node P, a source of the first adjusting transistor T32 is connected with the gate signal terminal G(n) of the nth stage, and a drain of the first adjusting transistor T32 is connected with the second low potential line VSSG.

[0063] A gate of the second adjusting transistor T321 is connected with the second control node P, a source of the second adjusting transistor T321 is connected with the gate signal terminal G(n+1) of the n+1th stage, and a drain of the second adjusting transistor T321 is connected with the first low potential line VSSQ.

[0064] A gate of the third adjusting transistor T42 is connected with the second control node P, a source of the third adjusting transistor T42 is connected with the first control node Q, and a drain of the third adjusting transistor T42 is connected with the first low potential line VSSQ.

[0065] A gate of the fourth adjusting transistor T412 and a gate of the fifth adjusting transistor T72 are connected with the second control node P, a source of the fourth adjusting transistor T412 is connected with the first control node Q, a drain of the fourth adjusting transistor T412 and a source of the fifth adjusting transistor T72 are connected with the stage transmission signal terminal ST(n) of the nth stage, and a drain of the fifth adjusting transistor T72 is connected with the first low potential line VSSQ.

[0066] Referring to Figure 1The inverter 410 comprises a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53, a fourth inverting transistor T54, a fifth inverting transistor T55 and a sixth inverting transistor T511; a gate of the first inverting transistor T51 is connected to the clock signal line CK(n+Y) of the nth+Y stage, a source of the first inverting transistor T51 and a source of the third inverting transistor T53 are connected to the second high potential line VDD, a drain of the first inverting transistor T51 and a gate of the third inverting transistor T53 are connected to the third control node S, and a drain of the third inverting transistor T53 is connected to the second control node P; a gate of the second inverting transistor T52 and a gate of the fourth inverting transistor T54 are connected to the first control node, a source of the second inverting transistor T52 is connected to the third control node S, a source of the fourth inverting transistor T54 and a source of the fifth inverting transistor T55 are connected to the second control node P, a drain of the second inverting transistor T52, a drain of the fourth inverting transistor T54 and a drain of the fifth inverting transistor T55 are connected to the first low potential line VSSQ; a gate of the sixth inverting transistor T511 and a gate of the fifth inverting transistor T55 are connected to the clock signal line CK(n+Y-X) of the nth+Y-X stage, a source of the sixth inverting transistor T511 is connected to the third control node S, and a drain of the sixth inverting transistor T511 is connected to the first low potential line VSSQ.

[0067] In the embodiment, the clock signal line CK(n+Y) of the nth+Y stage is used to output a third clock signal, and the clock signal line CK(n+Y-X) of the nth+Y-X stage is used to output a fourth clock signal, the third clock signal and the fourth clock signal are mutually coupled signals.

[0068] Please refer to Figure 1 The inverter 410 further comprises a reset transistor, a gate of the reset transistor is connected to the reset signal line Rest, a source of the reset transistor is connected to the second high potential line VDD, and a drain of the reset transistor is connected to the second control node P.

[0069] Please refer to Figure 1 A first plate of the bootstrap capacitor Cbt is connected to the first control node Q and the pull-up module 20, and a second plate of the bootstrap capacitor Cbt is connected to the gate signal end G(n) of the nth stage and the pull-down maintaining module 40.

[0070] The gate drive circuit of the present application will be described in detail below in combination with the timing control diagram in Figure 2 .

[0071] In the reset stage t0, please refer to Figure 3, the reset signal line Rest outputs high level to the gate of the reset transistor, the second high potential line VDD outputs high level to the second control node P through the source and the drain of the reset transistor, so as to pull up the potential of the second control node P to high potential, since the second control node P is connected with the gates of the first adjusting transistor T32, the second adjusting transistor T321, the third adjusting transistor T42, the fourth adjusting transistor T412 and the fifth adjusting transistor T72, the first adjusting transistor T32, the second adjusting transistor T321, the third adjusting transistor T42, the fourth adjusting transistor T412 and the fifth adjusting transistor T72 are opened, so that the first control node Q is connected with the first low potential line VSSQ, the gate signal end G(n) of the nth stage is connected with the second low potential line VSSG, and the gate signal end G(n+1) of the n+1th stage is connected with the first low potential line VSSQ, so as to reset the potentials of the first control node Q, the gate signal end G(n) of the nth stage, the gate signal end G(n+1) of the n+1th stage and the stage transmission signal end ST(n) of the nth stage.

[0072] In the first stage t1, referring to Figure 4 , the stage transmission signal end ST(n-X) of the n-Xth stage outputs high level to the gate of the pull-up control transistor T11, the pull-up control transistor T11 is opened, the first high potential line Vgh outputs high level to the first control node Q through the source and the drain of the pull-up control transistor T11, so as to pull up the potential of the first control node Q to the first high potential, and the first pull-up transistor T21, the second pull-up transistor T211 and the stage transmission transistor T22 are opened, at the same time, the bootstrap capacitor Cbt starts to charge.

[0073] Secondly, since the gate of the second inverting transistor T52 and the gate of the fourth inverting transistor T54 are both connected with the first control node Q, the second inverting transistor T52 and the fourth inverting transistor T54 are opened, the second control node P and the third control node S are both connected with the first low potential line VSSQ, and the potentials of the second control node P and the third control node S are both pulled down to the first low potential, so as to close the first adjusting transistor T32, the second adjusting transistor T321, the third adjusting transistor T42, the fourth adjusting transistor T412 and the fifth adjusting transistor T72.

[0074] In the second stage t2, referring to Figure 5, the stage transfer signal end ST(n-X) of the n-Xth stage outputs low level to the gate of the pull-up control transistor T11, the pull-up control transistor T11 is closed, the first high level of the first control node Q maintains the first pull-up transistor T21, the second pull-up transistor T211 and the stage transfer transistor T22 to be opened, the clock signal line CK(n) of the n-th stage transmits the first gate drive signal to the gate signal end G(n) of the n-th stage through the source and the drain of the first pull-up transistor T21, the clock signal line CK(n+1) of the n+1-th stage transmits the second gate drive signal to the gate signal end G(n+1) of the n+1-th stage through the source and the drain of the second pull-up transistor T211, and the clock signal line CK(n) of the n-th stage transmits the stage transfer signal to the stage transfer signal end ST(n) of the n-th stage through the source and the drain of the stage transfer transistor T22.

[0075] Meanwhile, the clock signal line CK(n) of the n-th stage outputs high level, and the potential of the first control node Q will continue to be pulled up, so that the potential of the first control node Q is pulled up from the first high level to the second high level.

[0076] Meanwhile, the high level of the first control node Q continues to open the second inverter transistor T52 and the fourth inverter transistor T54, and the second control node P and the third control node S are continuously connected with the first low potential line VSSQ.

[0077] In the third stage t3, please refer to Figure 6 , the stage transfer signal end ST(n+Y) of the n+Yth stage outputs high level to the gate of the pull-down transistor T41 to open the pull-down transistor T41, and the first control node Q is connected with the first low potential line VSSQ through the source and the drain of the pull-down transistor T41 to pull down the potential of the first control node Q to the first low level, so that the first pull-up transistor T21, the second pull-up transistor T211 and the stage transfer transistor T22 are closed.

[0078] Meanwhile, the clock signal line CK(n+Y) of the n+Yth stage outputs high level to the gate of the first inverter transistor T51 to open the first inverter transistor T51, and the second high potential line VDD pulls up the third control node S to high level through the source and the drain of the first inverter transistor T51; and the high level of the third control node S is transmitted to the gate of the third inverter transistor T53 to open the third inverter transistor T53, and the high level of the second high potential line VDD pulls up the second control node P to high level through the source and the drain of the third inverter transistor T53.

[0079] In the embodiment, since the potential of the second control node P is high, the first adjusting transistor T32, the second adjusting transistor T321, the third adjusting transistor T42, the fourth adjusting transistor T412 and the fifth adjusting transistor T72 can be opened, the first control node Q is connected with the first low potential line VSSQ through the source and the drain of the third inverter transistor T53, and the first control node Q is also connected with the first low potential line VSSQ through the source and the drain of the fourth inverter transistor T54 and the source and the drain of the fifth inverter transistor T55, the source and the drain of the first inverter transistor T51 of the gate signal terminal G(n) of the nth stage is connected with the second low potential line VSSG, the source and the drain of the second inverter transistor T52 of the gate signal terminal G(n+1) of the (n+1)th stage is connected with the first low potential line VSSQ, and the source and the drain of the fourth inverter transistor T54 of the stage transfer signal terminal ST(n) of the nth stage is connected with the first low potential line VSSQ, so as to pull down the potentials of the first control node Q, the stage transfer signal terminal ST(n) of the nth stage and the gate signal terminal G(n+1) of the (n+1)th stage to the first low potential, and pull down the potential of the gate signal terminal G(n) of the nth stage to the second low potential.

[0080] In the fourth stage t4, please refer to Figure 7 , the stage transfer signal terminal ST(n+Y) of the (n+Y)th stage outputs low level to the gate of the pull-down transistor T41, so as to close the pull-down transistor T41; the clock signal line CK(n+Y) of the (n+Y)th stage outputs low level to the gate of the first inverter transistor T51, so as to close the first inverter transistor T51; the clock signal line CK(n+Y-X) of the (n+Y-X)th stage outputs high level to the gate of the sixth inverter transistor T511, so as to open the sixth inverter transistor T511, the third control node S is connected with the first low potential line VSSQ through the source and the drain of the sixth inverter transistor T511, and the potential of the third control node S is pulled down to the low potential, so as to close the third inverter transistor T53; meanwhile, the clock signal line CK(n+Y-X) of the (n+Y-X)th stage outputs high level to the gate of the fifth inverter transistor T55, so as to open the fifth inverter transistor T55, the second control node P is connected with the first low potential line VSSQ through the source and the drain of the fifth inverter transistor T55, and the potential of the second control node P is pulled down to the low potential.

[0081] It should be noted that Figure 2 the timing control diagram in the above embodiment is taken as an example in which all the transistors in the gate driving circuit are N-type transistors, and the transistors in the gate driving circuit of the present application can also be P-type transistors, or a mixture of P-type transistors and N-type transistors, and different timing control diagrams correspond to different types of transistors.

[0082] Please refer to Figure 8The application further provides a display panel 200, which comprises the display part 300 and the above-mentioned gate drive circuit 100 arranged on one side of the display part. The display panel 200 can be a liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel or the like.

[0083] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0084] The above describes in detail the gate drive circuit and the display panel provided by the embodiments of the application. The principles and implementation manners of the application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the application and the core ideas thereof. Those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A gate driving circuit comprising N GOA units cascaded, characterized in that, The nth-stage GOA unit is any one of the N GOA units, and the nth-stage GOA unit comprises a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintenance module, the pull-up control module and the pull-up module are connected to a first control node, the pull-down module is electrically connected to the first control node and a first potential line, and the pull-down maintenance module is electrically connected to the first control node and a second potential line; The pull-up control module receives a first-stage transmission signal in a first stage, and pulls up the first control node to a first high potential; The pull-up module receives a first clock signal and outputs a first gate drive signal to a gate signal end of the nth stage according to the potential of the first control node, and the pull-up module receives a second clock signal and outputs a second gate drive signal to a gate signal end of the nth+1 stage according to the potential of the first control node; The pull-down module receives a second-stage transmission signal in a third stage, and pulls down the potential of the first control node to a first low potential; The pull-down maintenance module receives a third clock signal in the third stage, and pulls down the potential of the gate signal end of the nth stage to a second direct-current low level and the potential of the gate signal end of the nth+1 stage to the first low potential; The pull-down maintenance module comprises an inverter and a voltage adjustment unit, the voltage adjustment unit and the inverter are connected to a second control node, and the inverter is used to control the potential of the second control node; The voltage adjustment unit comprises a first adjustment transistor, a second adjustment transistor, a third adjustment transistor, a fourth adjustment transistor, and a fifth adjustment transistor; The gate of the first adjustment transistor is connected to the second control node, the source of the first adjustment transistor is connected to the gate signal end of the nth stage, and the drain of the first adjustment transistor is connected to a second low potential line; The gate of the second adjustment transistor is connected to the second control node, the source of the second adjustment transistor is connected to the gate signal end of the nth+1 stage, and the drain of the second adjustment transistor is connected to a first low potential line; The gate of the third adjustment transistor is connected to the second control node, the source of the third adjustment transistor is connected to the first control node, and the drain of the third adjustment transistor is connected to the first low potential line; The gate of the fourth adjustment transistor and the gate of the fifth adjustment transistor are connected to the second control node, the source of the fourth adjustment transistor is connected to the first control node, the drain of the fourth adjustment transistor and the source of the fifth adjustment transistor are connected to a stage transmission signal end of the nth stage, and the drain of the fifth adjustment transistor is connected to the first low potential line.

2. The gate drive circuit according to claim 1, characterized by The pull-up control module is connected to a stage transmission signal end of the nth-X stage, the first control node, a first high potential line, and the pull-down maintenance module, and the stage transmission signal end of the nth-X stage is used to output the first-stage transmission signal. The pull-up control module comprises a pull-up control transistor, a gate of the pull-up control transistor is connected to the first stage transmission signal terminal, a source of the pull-up control transistor is connected to the first high potential line, and a drain of the pull-up control transistor is connected to the first control node and the pull-down maintenance module.

3. The gate drive circuit according to claim 1, characterized by The pull-up module comprises a first pull-up unit and a second pull-up unit, the first pull-up unit is connected to the first control node, the nth stage clock signal line and the nth stage gate signal terminal, and the second pull-up unit is connected to the first control node, the nth+1 stage clock signal line and the nth+1 stage gate signal terminal. The nth stage clock signal line is used for providing the first clock signal, and the nth+1 stage clock signal line is used for providing the second clock signal.

4. The gate drive circuit according to claim 3, characterized by The first pull-up unit comprises a first pull-up transistor, a gate of the first pull-up transistor is connected to the first control node, a source of the first pull-up transistor is connected to the nth stage clock signal line, and a drain of the first pull-up transistor is connected to the nth stage gate signal terminal. The second pull-up unit comprises a second pull-up transistor, a gate of the second pull-up transistor is connected to the first control node, a source of the second pull-up transistor is connected to the nth+1 stage clock signal line, and a drain of the second pull-up transistor is connected to the nth+1 stage gate signal terminal.

5. The gate drive circuit according to claim 4, characterized in that The pull-up module further comprises a stage transmission unit, and the stage transmission unit comprises a stage transmission transistor. A gate of the stage transmission transistor is connected to the first control node, a source of the stage transmission transistor is connected to the first clock signal line, and a drain of the stage transmission transistor is connected to the nth stage stage transmission signal terminal.

6. The gate drive circuit according to claim 3, characterized by The pull-down module comprises a pull-down transistor, a gate of the pull-down transistor is connected to the nth+Y stage stage transmission signal terminal, a source of the pull-down transistor is connected to the first control node, and a drain of the pull-down transistor is connected to the first low potential line.

7. The gate drive circuit according to claim 3, characterized by The inverter comprises a first inverting transistor, a second inverting transistor, a third inverting transistor, a fourth inverting transistor, a fifth inverting transistor and a sixth inverting transistor. A gate of the first inverting transistor is connected to the nth+Y stage clock signal line, a source of the first inverting transistor and a source of the third inverting transistor are connected to the second high potential line, a drain of the first inverting transistor and a gate of the third inverting transistor are connected to the third control node, and a drain of the third inverting transistor is connected to the second control node. A gate of the second inverting transistor and a gate of the fourth inverting transistor are connected to the first control node, a source of the second inverting transistor is connected to the third control node, a source of the fourth inverting transistor and a source of the fifth inverting transistor are connected to the second control node, and a drain of the second inverting transistor, a drain of the fourth inverting transistor and a drain of the fifth inverting transistor are connected to the first low potential line. A gate of the sixth inverter transistor and a gate of the fifth inverter transistor are connected to a clock signal line of an (n+Y-X)th stage, a source of the sixth inverter transistor is connected to the third control node, and a drain of the sixth inverter transistor is connected to the first low potential line. The clock signal line of the (n+Y)th stage is configured to output a third clock signal, and the clock signal line of the (n+Y-X)th stage is configured to output a fourth clock signal, the third clock signal and the fourth clock signal being mutually coupled signals.

8. The gate drive circuit according to claim 7, characterized by The inverter further comprises a reset transistor, a gate of the reset transistor being connected to a reset signal line, a source of the reset transistor being connected to the second high potential line, and a drain of the reset transistor being connected to the second control node.

9. The gate drive circuit according to claim 3, characterized by The gate driving circuit comprises m clock signal lines, X is greater than or equal to (m / 2)-1 and less than or equal to (m / 2)+1.

10. The gate drive circuit according to claim 1, characterized by The nth GOA unit further comprises a bootstrap capacitor, a first plate of the bootstrap capacitor being connected to the first control node and the pull-up module, and a second plate of the bootstrap capacitor being connected to a gate signal terminal of the nth stage and the pull-down maintaining module.

11. A display panel, characterized by, The display panel comprises the gate driving circuit according to any one of claims 1 to 10.

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