A display panel

Abstract

The present application relates to a display panel. The present application integrates at least one pixel circuit module on each driving circuit module, so that the frame position where the driving circuit layer in the prior art is located has display function to form a frame display area, which is beneficial to realize the frameless effect of the display panel. In the main display area, the pixel circuit layer is electrically connected to the first signal transfer pad, and the first signal transfer pad is electrically connected to the signal line. In the frame display area, the pixel circuit layer is electrically connected to the first signal transfer pad, the first signal transfer pad is electrically connected to the second signal transfer pad, the second signal transfer pad is electrically connected to the third signal transfer pad, and the third signal transfer pad is electrically connected to the signal line. Therefore, the signal line can be prepared by thick metal process, the thickness of the signal line is improved, the square resistance of the signal line is reduced, the pressure drop is further reduced, the display brightness of the display panel is improved, and the display uniformity of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] At present, mainstream mini light-emitting diode (Mini LED) backlight products, Mini LED direct display products and micro light-emitting diode (Micro LED) direct display products are basically based on low temperature poly-silicon (English full name: Low Temperature Poly-Silicon, LTPS for short) or indium gallium zinc oxide (English full name: Indium Gallium Zinc Oxide, IGZO for short) thin film transistor (English full name: Thin Film Transistor, TFT for short) backplane. After the backplane process is completed, the anode and cathode in the pixel circuit layer for driving the light-emitting diode (English full name: light-emitting diode, LED for short) to emit light are exposed on the surface of the backplane, and then the anode and cathode of the Mini LED or Micro LED are electrically connected to the anode and cathode in the pixel circuit layer through the process of piece welding or through massive transfer and metal bonding or other bonding processes, so as to finally realize that the Mini LED or Micro LED can be actively matrix driven (English full name: Active Matrix, AM for short) through the pixel circuit layer in the backplane.

[0003] In the current backplane process, the signal line material is generally copper, molybdenum / aluminum / molybdenum or titanium / aluminum / titanium. On the one hand, the signal line made by the film forming, exposure, development and etching process through the physical vapor deposition (English full name: Physical Vapor Deposition, PVD for short) sputtering process has a very limited thickness, and the maximum thickness is about 1 um, which leads to a large square resistance of the signal line. On the other hand, in the case of a large-size display panel, or in the case of a display panel with high transparency requirement, the width of the signal line on the display panel is compressed as much as possible to improve the transmittance, and the resistance of the signal line will be large. The large resistance of the signal line will lead to an increase in the voltage drop in the display panel, resulting in a decrease in the display brightness of the display panel, and ultimately leading to uneven display brightness of the display panel. SUMMARY

[0004] The purpose of the present application is to provide a display panel which can solve the problem of uneven display brightness of the display panel caused by the large resistance of the signal line in the existing display panel.

[0005] To solve the above problems, the application provides a display panel, which comprises a main display area and a frame display area; the display panel comprises: a substrate; a metal layer arranged on the substrate, wherein the metal layer comprises a plurality of signal lines; a plurality of driving circuit modules arranged on a side of the metal layer away from the substrate and located in the frame display area and arranged at intervals; and a plurality of pixel circuit modules arranged on a side of the driving circuit modules in the frame display area away from the substrate and arranged at intervals; each of the pixel circuit modules comprises: a first substrate, a pixel circuit layer arranged on the first substrate, a light-emitting unit arranged on a side of the pixel circuit layer away from the first substrate, and a first signal transfer pad arranged on a side of the first substrate away from the pixel circuit layer; each of the driving circuit modules comprises: a second substrate, a driving circuit layer arranged on the second substrate, a second signal transfer pad arranged on a side of the driving circuit layer away from the second substrate, and a third signal transfer pad arranged on a side of the second substrate away from the driving circuit layer; in the frame display area, the pixel circuit layer is electrically connected to the first signal transfer pad, the first signal transfer pad is electrically connected to the second signal transfer pad, the second signal transfer pad is electrically connected to the third signal transfer pad, and the third signal transfer pad is electrically connected to the signal line.

[0006] Further, the first signal transfer pad comprises one or more of a first scan signal transfer pad, a first data signal transfer pad, a first high-voltage power supply signal transfer pad and a first low-voltage power supply signal transfer pad which are respectively electrically connected to a first scan line, a first data line, a first high-voltage power supply line and a first low-voltage power supply line of the pixel circuit layer; and the second signal transfer pad is arranged in one-to-one correspondence with the first signal transfer pad.

[0007] Further, the main display area is also provided with a plurality of pixel circuit modules arranged at intervals on a side of the metal layer in the main display area away from the substrate; in the main display area, the pixel circuit layer is electrically connected to the first signal transfer pad, and the first signal transfer pad is electrically connected to the signal line in the main display area; the metal layer in the main display area comprises: third data lines arranged in a first direction, fourth scan lines arranged in parallel with each other in a second direction intersecting the first direction, a third high-voltage power supply line and a third low-voltage power supply line; and the first scan signal transfer pad, the first data signal transfer pad, the first high-voltage power supply signal transfer pad and the first low-voltage power supply signal transfer pad are respectively electrically connected to the fourth scan lines, the third data lines, the third high-voltage power supply line and the third low-voltage power supply line.

[0008] Further, the third signal conversion pad comprises one or more of a first clock signal conversion pad, a first positive power input signal conversion pad, a first negative power input signal conversion pad, a second scan signal conversion pad, a third scan signal conversion pad, a second data signal conversion pad, a second high-voltage power signal conversion pad, and a second low-voltage power signal conversion pad, which are electrically connected to the first clock signal line, the first positive power input line, the first negative power input line, the second scan line, the third scan line, the second data line, the second high-voltage power line, and the second low-voltage power line of the driving circuit layer, respectively; the metal layer of the frame display area comprises: second clock signal lines, second positive power input lines, second negative power input lines, fourth data lines, fourth high-voltage power lines, and fourth low-voltage power lines arranged in parallel along a first direction, and fifth scan lines and sixth scan lines arranged in parallel along a second direction intersecting the first direction; the first clock signal conversion pad, the first positive power input signal conversion pad, the first negative power input signal conversion pad, the second scan signal conversion pad, the third scan signal conversion pad, the second data signal conversion pad, the second high-voltage power signal conversion pad, and the second low-voltage power signal conversion pad are electrically connected to the second clock signal lines, the second positive power input lines, the second negative power input lines, the fifth scan lines, the sixth scan lines, the fourth data lines, the fourth high-voltage power lines, and the fourth low-voltage power lines, respectively.

[0009] Further, the first scan signal conversion pad, the first data signal conversion pad, the first high-voltage power signal conversion pad, and the first low-voltage power signal conversion pad are respectively correspondingly electrically connected to the third scan signal conversion pad, the second data signal conversion pad, the second high-voltage power signal conversion pad, and the second low-voltage power signal conversion pad.

[0010] Further, the first substrate comprises a first buffer layer, a first flexible layer, a first barrier layer, a second flexible layer, a second barrier layer, a first conductive unit, and a second buffer layer arranged in sequence; the pixel circuit layer comprises a first gate insulating layer, a second gate insulating layer, a first interlayer insulating layer, a second conductive unit, a first planar layer, a third conductive unit, and a second planar layer; the first low-voltage power line is electrically connected to the third conductive unit through the second planar layer, the third conductive unit is electrically connected to the second conductive unit through the first planar layer, the second conductive unit is electrically connected to the first conductive unit through the first interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and the second buffer layer, and the first conductive unit is electrically connected to the first signal conversion pad through the second barrier layer, the second flexible layer, the first barrier layer, the first flexible layer, and the first buffer layer.

[0011] Further, the second substrate comprises a third buffer layer, a third flexible layer, a third barrier layer, a fourth flexible layer, a fourth barrier layer, a fourth conductive unit and a fourth buffer layer arranged in sequence; the driving circuit layer comprises a third gate insulating layer, a fourth gate insulating layer, a second interlayer insulating layer, a fifth conductive unit, a third planar layer, a sixth conductive unit and a fourth planar layer; the second signal transfer pad is electrically connected to the sixth conductive unit through the fourth planar layer, the sixth conductive unit is electrically connected to the fifth conductive unit through the third planar layer, the fifth conductive unit is electrically connected to the fourth conductive unit through the second interlayer insulating layer, the fourth gate insulating layer, the third gate insulating layer and the fourth buffer layer, and the fourth conductive unit is electrically connected to the third signal transfer pad through the fourth barrier layer, the fourth flexible layer, the third barrier layer, the third flexible layer and the third buffer layer.

[0012] Further, the interval between the two pixel circuit modules located in the main display area is equal to the interval between the pixel circuit modules located in the frame display area.

[0013] Further, the display panel further comprises a first encapsulation body located in the main display area; the first encapsulation body covers a side of the light emitting unit away from the first substrate and extends to cover the pixel circuit layer and the first substrate; and the bottom surface of the first encapsulation body is flush with the bottom surface of the first substrate.

[0014] Further, the display panel further comprises a second encapsulation body located in the frame display area; the second encapsulation body covers a side of the light emitting unit away from the first substrate and extends to cover the pixel circuit layer, the first substrate, the first signal transfer pad, the second signal transfer pad, the driving circuit layer and the second substrate; and the bottom surface of the second encapsulation body is flush with the bottom surface of the second substrate.

[0015] Further, the thickness of the signal line of the metal layer is greater than 10 microns.

[0016] Further, the light emitting unit is a light emitting diode, the anode of the light emitting diode is electrically connected to the anode of the pixel circuit layer, and the cathode of the light emitting diode is electrically connected to the cathode of the pixel circuit layer; or the light emitting unit is an organic light emitting diode, the anode of the organic light emitting diode is electrically connected to the anode of the pixel circuit layer, and the cathode of the organic light emitting diode is electrically connected to the cathode of the pixel circuit layer.

[0017] The display panel of the present application has the advantages that: the present application integrates at least one pixel circuit module on each driving circuit module, so that the bezel position where the driving circuit layer in the prior art is located has display function to form a bezel display area, which is beneficial to realize the bezel-free effect of the display panel.

[0018] In the main display area, the pixel circuit layer is electrically connected to the first signal transfer pad, the first signal transfer pad is electrically connected to the signal line; in the bezel display area, the pixel circuit layer is electrically connected to the first signal transfer pad, the first signal transfer pad is electrically connected to the second signal transfer pad, the second signal transfer pad is electrically connected to the third signal transfer pad, and the third signal transfer pad is electrically connected to the signal line, so that the signal line can be prepared by thick metal process, the thickness of the signal line is improved, the square resistance of the signal line is reduced, and then the pressure drop is reduced, the display brightness of the display panel is improved, and the display uniformity of the display panel is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 is a plane schematic diagram of the display panel of the present application;

[0021] Figure 2 is a plane schematic diagram of the substrate and the metal layer of the present application;

[0022] Figure 3 is a structural diagram of the display panel of the main display area of the present application;

[0023] Figure 4 is a structural diagram of the pixel circuit module of the present application;

[0024] Figure 5 is a circuit diagram of the pixel circuit module of the present application;

[0025] Figure 6 is a schematic diagram of the first signal transfer pad of the present application;

[0026] Figure 7 is a structural diagram of the display panel of the bezel display area of the present application; Figure 1 ;

[0027] Figure 8 is a structural diagram of the display panel of the bezel display area of the present application; Figure 2 ;

[0028] Figure 9 is a structural schematic diagram of a driving circuit module and a pixel circuit module of a frame display area of the present application;

[0029] Figure 10 is a schematic diagram of a third signal transfer pad of the present application;

[0030] Figure 11 is a connection schematic diagram of a first signal transfer pad and a signal line of a main display area of the present application;

[0031] Figure 12 is a connection schematic diagram of a third signal transfer pad and a signal line of a frame display area of the present application.

[0032] Explanation of reference signs:

[0033] 100, display panel; 101, main display area;

[0034] 102, frame display area;

[0035] 1, substrate; 2, metal layer;

[0036] 3, pixel circuit module; 4, driving circuit module;

[0037] 5, first package; 6, second package;

[0038] 21, signal line;

[0039] 31, first substrate; 32, pixel circuit layer;

[0040] 33, light emitting unit; 34, first signal transfer pad;

[0041] 3101, first buffer layer; 3102, first flexible layer;

[0042] 3103, first barrier layer; 3104, second flexible layer;

[0043] 3105, second barrier layer; 3106, first conductive unit;

[0044] 3107, second buffer layer;

[0045] 3201, active layer; 3202, first gate insulating layer;

[0046] 3203, first electrode; 3204, second gate insulating layer;

[0047] 3205, second electrode; 3206, first interlayer insulating layer;

[0048] 3207, third electrode; 3208, fourth electrode;

[0049] 3209, second conductive unit; 3210, first flat layer;

[0050] 3211, fifth electrode; 3212, third conductive unit;

[0051] 3213, second flat layer; 3214, anode;

[0052] 3215, first low-voltage power supply line; 3216, pixel definition layer;

[0053] 41, second substrate; 42, driving circuit layer;

[0054] 43, second signal transfer pad; 44, third signal transfer pad;

[0055] 4101, third buffer layer; 4102, third flexible layer;

[0056] 4103, third barrier layer; 4104, fourth flexible layer;

[0057] 4105, fourth barrier layer; 4106, fourth conductive unit;

[0058] 4107, fourth buffer layer;

[0059] 4201, third gate insulating layer; 4202, fourth gate insulating layer;

[0060] 4203, second interlayer insulating layer; 4204, fifth conductive unit;

[0061] 4205, third flat layer; 4206, sixth conductive unit;

[0062] 4207, fourth flat layer. DETAILED DESCRIPTION

[0063] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings, in order to give a complete understanding of the technical contents of the present application to the person skilled in the art, to exemplify that the present application can be implemented, to make the technical contents disclosed by the present application more clear, and to make it easier for the person skilled in the art to understand how to implement the present application. However, the present application can be embodied in many different forms of embodiments, and the protection scope of the present application is not limited to the embodiments mentioned herein, and the description of the embodiments below is not used to limit the scope of the present application.

[0064] The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc., are only the directions in the drawings, and the directional terms used herein are used to explain and describe the present application, and are not used to limit the protection scope of the present application.

[0065] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component.

[0066] Example 1

[0067] like Figure 1 As shown, this embodiment provides a display panel 100. The display panel 100 includes a main display area 101 and a border display area 102. In this embodiment, the border display area 102 is located at both ends of the main display area 101. In other embodiments, the border display area 102 may be located at only one end of the main display area 101, or it may be located at all four ends of the main display area 101.

[0068] The display panel 100 includes: a substrate 1, a metal layer 2, multiple driving circuit modules 4, and multiple pixel circuit modules 3.

[0069] The substrate 1 is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, which gives the substrate 1 good impact resistance and can effectively protect the display panel 100.

[0070] like Figure 1 and Figure 2 As shown, a metal layer 2 is disposed on the substrate 1. The metal layer 2 includes a plurality of signal lines 21.

[0071] The signal lines 21 of the metal layer 2 can be formed on the surface of the substrate 1 using thick metal fabrication processes such as electroplating, chemical plating, and printing. Therefore, the thickness of the signal lines 21 in the metal layer 2 is greater than 10 micrometers. Increasing the thickness of the signal lines 21 reduces their sheet resistance, thereby reducing voltage drop, increasing the display brightness of the display panel 100, and improving the display uniformity of the display panel 100.

[0072] like Figure 1 and Figure 3 As shown, multiple pixel circuit modules 3 are disposed on the side of the metal layer 2 of the main display area 101 away from the substrate 1, and are spaced apart from each other.

[0073] The pixel circuit module 3 can be soldered or bonded to the corresponding position using surface mount technology (SMT) and other processes to achieve electrical connection with the corresponding signal line 21.

[0074] likeFigure 3 As shown, each pixel circuit module 3 includes: a first substrate 31, a pixel circuit layer 32, a light-emitting unit 33, and a first signal transition pad 34.

[0075] like Figure 4 As shown, the first substrate 31 includes: a first buffer layer 3101, a first flexible layer 3102, a first barrier layer 3103, a second flexible layer 3104, a second barrier layer 3105, a first conductive unit 3106, and a second buffer layer 3107.

[0076] The first buffer layer 3101 mainly serves a buffering function, and its material can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc.

[0077] The first flexible layer 3102 is disposed on the first buffer layer 3101. In this embodiment, the first flexible layer 3102 is made of polyimide (PI). In other embodiments, the first flexible layer 3102 may also be made of flexible materials such as polyethylene dicarboxylate (PET), thereby increasing the flexibility of the first substrate 31.

[0078] The first barrier layer 3103 is disposed on the side of the first flexible layer 3102 away from the first buffer layer 3101. The first barrier layer 3103 can be used to prevent water and oxygen from penetrating through the first flexible layer 3102 to the structure above the first barrier layer 3103, thereby preventing damage to the display panel 100.

[0079] The second flexible layer 3104 is disposed on the side of the first barrier layer 3103 away from the first buffer layer 3101. In this embodiment, the second flexible layer 3104 is made of polyimide (PI). In other embodiments, the second flexible layer 3104 may also be made of flexible materials such as polyethylene dicarboxylate (PET), thereby increasing the flexibility of the first substrate 31.

[0080] The second barrier layer 3105 is disposed on the side of the second flexible layer 3104 away from the first buffer layer 3101. The second barrier layer 3105 can be used to prevent water and oxygen from penetrating through the second flexible layer 3104 to the structure above the second barrier layer 3105, thereby preventing damage to the display panel 100.

[0081] The first conductive unit 3106 is disposed on the side of the second barrier layer 3105 away from the first buffer layer 3101 and is electrically connected to the first signal transition pad 34.

[0082] The second buffer layer 3107 is disposed on the side of the first conductive unit 3106 away from the first buffer layer 3101. The second buffer layer 3107 mainly serves as a buffer, and can be made of SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx.

[0083] The pixel circuit layer 32 is disposed on the first substrate 31 and electrically connected to the corresponding signal line 21.

[0084] The pixel circuit layer 32 includes an active layer 3201, a first gate insulating layer 3202, a first electrode 3203, a second gate insulating layer 3204, a second electrode 3205, a first interlayer insulating layer 3206, a third electrode 3207, a fourth electrode 3208, a second conductive unit 3209, a first planarization layer 3210, a fifth electrode 3211, a third conductive unit 3212, a second planarization layer 3213, an anode 3214, a first low-voltage power supply line 3215, and a pixel definition layer 3216.

[0085] The active layer 3201 is disposed on the first substrate 31. Specifically, the active layer 3201 is disposed on the side of the second buffer layer 3107 away from the first buffer layer 3101. The active layer 3201 includes a channel portion 32011 and two conductive portions 32012 respectively located at both ends of the channel portion 32011.

[0086] The first gate insulating layer 3202 is disposed on the side of the active layer 3201 away from the first substrate 31 and extends to cover the second buffer layer 3107. The first gate insulating layer 3202 mainly serves to prevent short circuiting between the active layer 3201 and the first electrode 3203. The first gate insulating layer 3202 can be made of SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, a combination of SiOx, SiNx, and SiOx, or the like.

[0087] The first electrode 3203 is disposed on the side of the first gate insulating layer 3202 away from the first substrate 31. The first electrode 3203 is disposed in correspondence with the channel portion 32011 of the active layer 3201. The first electrode 3203 can be made of Mo, a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu, and IZO, a combination of IZO, Cu, and IZO, a combination of Mo, Cu, and ITO, a combination of Ni, Cu, and Ni, a combination of MoTiNi, Cu, and MoTiNi, a combination of NiCr, Cu, and NiCr, CuNb, or the like.

[0088] The second gate insulating layer 3204 is disposed on the side of the first electrode 3203 away from the first substrate 31 and extends to cover the first gate insulating layer 3202. The second gate insulating layer 3204 is mainly used to prevent the first electrode 3203 and the second electrode 3205 from short circuiting. The material of the second gate insulating layer 3204 can be SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, a combination of SiOx, SiNx and SiOx, or the like.

[0089] The second electrode 3205 is disposed on the side of the second gate insulating layer 3204 away from the first substrate 31. The second electrode 3205 is used to couple with the first electrode 3203 to form a storage capacitor Cst. The material of the second electrode 3205 can be Mo, a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu and IZO, a combination of IZO, Cu and IZO, a combination of Mo, Cu and ITO, a combination of Ni, Cu and Ni, a combination of MoTiNi, Cu and MoTiNi, a combination of NiCr, Cu and NiCr, CuNb, or the like.

[0090] The first interlayer insulating layer 3206 is disposed on the side of the second electrode 3205 away from the first substrate 31 and extends to cover the second gate insulating layer 3204. The material of the interlayer insulating layer 3206 can be SiOx, SiNx, SiNOx, or the like.

[0091] The third electrode 3207 and the fourth electrode 3208 are disposed on the side of the interlayer insulating layer 3206 away from the first substrate 31 and are respectively electrically connected to the two conductive parts 32012 of the active layer 3201. In this embodiment, the third electrode 3207 is a source electrode and the fourth electrode 3208 is a drain electrode.

[0092] The second conductive unit 3209 is disposed in the same layer as the third electrode 3207 and the fourth electrode 3208.

[0093] The first planar layer 3210 covers the side of the third electrode 3207 and the fourth electrode 3208 away from the first substrate 31 and extends to cover the first interlayer insulating layer 3206. The material of the first planar layer 3210 can be SiOx, SiNx, SiNOx, a combination of SiNx and SiOx, or the like.

[0094] The fifth electrode 3211 is disposed on the side of the first planar layer 3210 away from the first substrate 31. The fifth electrode 3211 is mainly used to electrically connect the anode 3214 and the fourth electrode 3208.

[0095] The third conductive unit 3212 is disposed in the same layer as the fifth electrode 3211.

[0096] The second planarization layer 3213 covers the side of the fifth electrode 3211 and the third conductive unit 3212 away from the first substrate 31, and extends to cover the first planarization layer 3210. The material of the second planarization layer 3213 may be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc.

[0097] The anode 3214 is disposed on the side of the second planarization layer 3213 away from the first substrate 31. The anode 3214 can be made of metal. In this embodiment, the anode 3214 is made of silver (Ag). Therefore, the anode 3214 has good electrical conductivity.

[0098] In this embodiment, the first low-voltage power line 3215 is disposed in the same layer as the anode 3214. In this embodiment, the first low-voltage power line 3215 is made of the same material as the anode 3214, thus allowing the low-voltage power line 3215 and the anode 3214 to be formed in a single process. In this embodiment, the first low-voltage power line 3215 is reused as the cathode of the pixel circuit layer 32.

[0099] The pixel definition layer 3216 is disposed on the side of the first low-voltage power line 3215 and the anode 3214 away from the first substrate 31, and extends to cover the second planarization layer 3213.

[0100] The active layer 3201, the first gate insulating layer 3202, the first electrode 3203, the second gate insulating layer 3204, the second electrode 3205, the first interlayer insulating layer 3206, the third electrode 3207, and the fourth electrode 3208 constitute the first thin film transistor T1.

[0101] like Figure 5 As shown, in this embodiment, the source of T1 is electrically connected to the first high-voltage power supply line VDD, the drain of T1 is electrically connected to the positive electrode 3302 of the light-emitting unit 33, and the gate of T1 is electrically connected to the first plate of the storage capacitor Cst. The second plate of the storage capacitor Cst is electrically connected to the first high-voltage power supply line VDD. The source of T2 is electrically connected to the first data line Data, the drain of T2 is electrically connected to the gate of T1, and the gate of T2 is electrically connected to the first scan line Scan. In this embodiment, the negative electrode 3303 of the light-emitting unit 33 is electrically connected to the first low-voltage power supply line VSS.

[0102] The light-emitting unit 33 is electrically connected to the side of the pixel circuit layer 32 away from the first substrate 31.

[0103] In this embodiment, the light-emitting unit 33 is a light-emitting diode (LED). Specifically, the light-emitting diode can be a Mini LED or a Micro LED. The light-emitting unit 33 includes a light-emitting functional layer 3301, a positive electrode 3302, and a negative electrode 3303.

[0104] In this embodiment, the positive electrode 3302 of the light-emitting unit 33 is electrically connected to the anode 3214 of the pixel circuit layer 32, and the negative electrode 3303 of the light-emitting unit 33 is electrically connected to the first low-voltage power supply line (cathode) 3215 of the pixel circuit layer 32.

[0105] In other embodiments, the light-emitting unit 33 can also be an organic light-emitting diode (OLED). The anode of the organic light-emitting diode is electrically connected to the anode 3214 of the pixel circuit layer 32, and the cathode of the organic light-emitting diode is electrically connected to the first low-voltage power supply line 3215 of the pixel circuit layer 32.

[0106] The first signal transfer pad 34 is disposed on the side of the first substrate 31 away from the pixel circuit layer 32. The first signal transfer pad 34 can be obtained by performing a metal patterning process on the surface of the side of the first substrate 31 away from the pixel circuit layer 32.

[0107] As shown in FIG. 1, the first signal transfer pad 34 includes one or more of a first scan signal transfer pad 3401 electrically connected to the first scan line Scan of the pixel circuit layer 32, a first data signal transfer pad 3402 electrically connected to the first data line Data of the pixel circuit layer 32, a first high-voltage power supply signal transfer pad 3403 electrically connected to the first high-voltage power supply line VDD of the pixel circuit layer 32, and a first low-voltage power supply signal transfer pad 3404 electrically connected to the first low-voltage power supply line VSS of the pixel circuit layer 32. Figure 6

[0108] As shown in FIG. 1, the first signal transfer pad 34 includes one or more of a first scan signal transfer pad 3401 electrically connected to the first scan line Scan of the pixel circuit layer 32, a first data signal transfer pad 3402 electrically connected to the first data line Data of the pixel circuit layer 32, a first high-voltage power supply signal transfer pad 3403 electrically connected to the first high-voltage power supply line VDD of the pixel circuit layer 32, and a first low-voltage power supply signal transfer pad 3404 electrically connected to the first low-voltage power supply line VSS of the pixel circuit layer 32. Figure 11 ​As shown, the metal layer 2 of the main display area 101 comprises: third data lines 2102 arranged along a first direction M, fourth scan lines 2101 arranged parallel to each other along a second direction N intersecting the first direction M, a third high-voltage power supply line 2103, and a third low-voltage power supply line 2104; the first scan signal transfer pad 3401, the first data signal transfer pad 3402, the first high-voltage power supply signal transfer pad 3403, and the first low-voltage power supply signal transfer pad 3404 are electrically connected to the fourth scan line 2101, the third data line 2102, the third high-voltage power supply line 2103, and the third low-voltage power supply line 2104, respectively. In fact, the metal layer 2 is provided with a fourth scan signal transfer pad (not shown in the figure), a third data signal transfer pad, a third high-voltage power supply signal transfer pad (not shown in the figure), and a third low-voltage power supply signal transfer pad (not shown in the figure) corresponding to the fourth scan line 2101, the third data line 2102, the third high-voltage power supply line 2103, and the third low-voltage power supply line 2104, respectively, and then the first scan signal transfer pad 3401, the first data signal transfer pad 3402, the first high-voltage power supply signal transfer pad 3403, and the first low-voltage power supply signal transfer pad 3404 are electrically connected to the fourth scan signal transfer pad (not shown in the figure), the third data signal transfer pad, the third high-voltage power supply signal transfer pad (not shown in the figure), and the third low-voltage power supply signal transfer pad (not shown in the figure), respectively.

[0109] As shown, Figure 4 In the present embodiment, the first low-voltage power supply line 3215 is electrically connected to the third conductive unit 3212 through the second flat layer 3213, the third conductive unit 3212 is electrically connected to the second conductive unit 3209 through the first flat layer 3210, the second conductive unit 3209 is electrically connected to the first conductive unit 3106 through the first interlayer insulating layer 3206, the second gate insulating layer 3204, the first gate insulating layer 3202, and the second buffer layer 3107, and the first conductive unit 3106 is electrically connected to the first signal transfer pad 34 through the second barrier layer 3105, the second flexible layer 3104, the first barrier layer 3103, the first flexible layer 3102, and the first buffer layer 3101.

[0110] In the present embodiment, the first signal transfer pad 34 is electrically connected to the pixel circuit layer 32 in the main display area 101, and the first signal transfer pad 34 is electrically connected to the signal line 21, so that the signal line 21 can be prepared by a thick metal process, the thickness of the signal line 21 is increased, the sheet resistance of the signal line 21 is reduced, the pressure drop is further reduced, the display brightness of the display panel 100 is improved, and the display uniformity of the display panel 100 is improved.

[0111] As shown, Figure 3As shown in FIG. 1, the display panel 100 further comprises a first encapsulation body 5. The first encapsulation body 5 is located in the main display area 101. Specifically, the first encapsulation body 5 covers the side of the light emitting unit 33 away from the first substrate 31, and extends to cover the pixel circuit layer 32 and the first substrate 31; the bottom surface of the first encapsulation body 5 is flush with the bottom surface of the first substrate 31. The first encapsulation body 5 is mainly used to prevent water and oxygen from invading the light emitting unit 33, the pixel circuit layer 32 and the first substrate 31.

[0112] As shown in FIG. 1, the display panel 100 further comprises a first encapsulation body 5. The first encapsulation body 5 is located in the main display area 101. Specifically, the first encapsulation body 5 covers the side of the light emitting unit 33 away from the first substrate 31, and extends to cover the pixel circuit layer 32 and the first substrate 31; the bottom surface of the first encapsulation body 5 is flush with the bottom surface of the first substrate 31. The first encapsulation body 5 is mainly used to prevent water and oxygen from invading the light emitting unit 33, the pixel circuit layer 32 and the first substrate 31. Figure 1 、 Figure 7 and Figure 8 As shown in FIG. 1, a plurality of driving circuit modules 4 are arranged on the side of the metal layer 2 away from the substrate 1 and located in the frame display area 102, and are arranged at intervals. The driving circuit module 4 can be welded or bonded to the corresponding position by surface mounting technology (Surface Mounted Technology, SMT for short) process, and is electrically connected with the corresponding signal line 21.

[0113] As shown in FIG. 1, a plurality of pixel circuit modules 3 are also arranged on the side of the driving circuit module 4 away from the substrate 1 in the frame display area 102, and are arranged at intervals. The interval between the pixel circuit modules 3 located in the main display area 101 is equal to the interval between the pixel circuit modules 3 located in the frame display area 102, so that the display uniformity of the display panel 100 can be improved. In this embodiment, the pixel circuit modules 3 located in the main display area 101 and the pixel circuit modules 3 located in the frame display area 102 have the same structure. In other embodiments, the pixel circuit modules 3 located in the main display area 101 and the pixel circuit modules 3 located in the frame display area 102 can also have different structures. Figure 1 、 Figure 7 and Figure 8 As shown in FIG. 1, a plurality of pixel circuit modules 3 are also arranged on the side of the driving circuit module 4 away from the substrate 1 in the frame display area 102, and are arranged at intervals. The interval between the pixel circuit modules 3 located in the main display area 101 is equal to the interval between the pixel circuit modules 3 located in the frame display area 102, so that the display uniformity of the display panel 100 can be improved. In this embodiment, the pixel circuit modules 3 located in the main display area 101 and the pixel circuit modules 3 located in the frame display area 102 have the same structure. In other embodiments, the pixel circuit modules 3 located in the main display area 101 and the pixel circuit modules 3 located in the frame display area 102 can also have different structures.

[0114] As shown in FIG. 1, each of the driving circuit modules 4 is arranged corresponding to at least one of the pixel circuit modules 3. In this embodiment, each of the driving circuit modules 4 is arranged corresponding to three of the pixel circuit modules 3. Figure 8 In this embodiment, at least one pixel circuit module 3 is integrated on each driving circuit module 4, so that the frame position where the driving circuit layer is located in the prior art has display function to form the frame display area 102, which is conducive to realizing the frameless effect of the display panel 100.

[0115] As shown in FIG. 1, each of the driving circuit modules 4 is arranged corresponding to at least one of the pixel circuit modules 3. In this embodiment, each of the driving circuit modules 4 is arranged corresponding to three of the pixel circuit modules 3.

[0116] Figure 9 ​As shown, each of the drive circuit modules 4 comprises a second substrate 41, a drive circuit layer 42, a second signal transfer pad 43, and a third signal transfer pad 44.

[0117] The second substrate 41 comprises a third buffer layer 4101, a third flexible layer 4102, a third barrier layer 4103, a fourth flexible layer 4104, a fourth barrier layer 4105, a fourth conductive unit 4106, and a fourth buffer layer 4107.

[0118] The third buffer layer 4101 mainly serves as a buffer and can be made of SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx.

[0119] The third flexible layer 4102 is disposed on the third buffer layer 4101. In this embodiment, the third flexible layer 4102 is made of polyimide (PI). In other embodiments, the third flexible layer 4102 can also be made of a flexible material such as polyethylene terephthalate (PET), thereby increasing the flexibility of the second substrate 41.

[0120] The third barrier layer 4103 is disposed on the side of the third flexible layer 4102 away from the first buffer layer 3101. The third barrier layer 4103 can prevent water and oxygen from penetrating through the third flexible layer 4102 to the structure above the third barrier layer 4103, thereby preventing damage to the display panel 100.

[0121] The fourth flexible layer 4104 is disposed on the side of the third barrier layer 4103 away from the third buffer layer 4101. In this embodiment, the fourth flexible layer 4104 is made of polyimide (PI). In other embodiments, the fourth flexible layer 4104 can also be made of a flexible material such as polyethylene terephthalate (PET), thereby increasing the flexibility of the second substrate 41.

[0122] The fourth barrier layer 4105 is disposed on the side of the fourth flexible layer 4104 away from the third buffer layer 4101. The fourth barrier layer 4105 can prevent water and oxygen from penetrating through the fourth flexible layer 4104 to the structure above the fourth barrier layer 4105, thereby preventing damage to the display panel 100.

[0123] The fourth conductive unit 4106 is disposed on the side of the second barrier layer 3105 away from the third buffer layer 4101.

[0124] The fourth buffer layer 4107 is disposed on the side of the fourth conductive unit 4106 away from the third buffer layer 4101. The fourth buffer layer 4107 mainly serves as a buffer and can be made of SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx.

[0125] The driving circuit layer 42 is disposed on the second substrate 41 and is electrically connected to the corresponding signal line 21.

[0126] The driving circuit layer 42 comprises a third gate insulating layer 4201, a fourth gate insulating layer 4202, a second interlayer insulating layer 4203, a fifth conductive unit 4204, a third planar layer 4205, a sixth conductive unit 4206, and a fourth planar layer 4207. The driving circuit layer 42 has the same structure as the first thin film transistor T1 of the pixel circuit layer 32, and thus will not be described again here.

[0127] The second signal transfer pad 43 is disposed on the side of the driving circuit layer 42 close to the second substrate 41. The third signal transfer pad 44 is disposed on the side of the second substrate 41 away from the driving circuit layer 42. The second signal transfer pad 43 is disposed in one-to-one correspondence with the first signal transfer pad 34.

[0128] As shown in FIG. 4, the third signal transfer pad 44 comprises one or more of a first clock signal transfer pad 4401, a first positive power input signal transfer pad 4402, a first negative power input signal transfer pad 4403, a second scan signal transfer pad 4404, a third scan signal transfer pad 4405, a second data signal transfer pad 4406, a second high-voltage power signal transfer pad 4407, and a second low-voltage power signal transfer pad 4408 electrically connected to the first clock signal line (not shown), the first positive power input line (not shown), the first negative power input line (not shown), the second scan line (Scan(n-1)), the third scan line (Scan(n)), the second data line, the second high-voltage power line, and the second low-voltage power line of the driving circuit layer 42, respectively. Figure 10

[0129] Specifically, the first scan signal transfer pad 3401, the first data signal transfer pad 3402, the first high-voltage power signal transfer pad 3403, and the first low-voltage power signal transfer pad 3404 are respectively electrically connected to the third scan signal transfer pad 4405, the second data signal transfer pad 4406, the second high-voltage power signal transfer pad 4407, and the second low-voltage power signal transfer pad 4408.

[0130] As shown in FIG. 4, the third signal transfer pad 44 comprises one or more of a first clock signal transfer pad 4401, a first positive power input signal transfer pad 4402, a first negative power input signal transfer pad 4403, a second scan signal transfer pad 4404, a third scan signal transfer pad 4405, a second data signal transfer pad 4406, a second high-voltage power signal transfer pad 4407, and a second low-voltage power signal transfer pad 4408 electrically connected to the first clock signal line (not shown), the first positive power input line (not shown), the first negative power input line (not shown), the second scan line (Scan(n-1)), the third scan line (Scan(n)), the second data line, the second high-voltage power line, and the second low-voltage power line of the driving circuit layer 42, respectively. Figure 12 ​As shown, the metal layer 2 of the frame display area 102 comprises: the second clock signal lines 2105, the second positive power input lines 2106, the second negative power input lines 2107, the fourth data lines 2110, the fourth high-voltage power lines 2111 and the fourth low-voltage power lines 2112 arranged along the first direction M and parallel to each other; and the fifth scan lines 2108 and the sixth scan lines 2109 arranged along the second direction N crossing the first direction M and parallel to each other; the first clock signal transfer pad 4401, the first positive power input signal transfer pad 4402, the first negative power input signal transfer pad 4403, the second scan signal transfer pad 4404, the third scan signal transfer pad 4405, the second data signal transfer pad 4406, the second high-voltage power signal transfer pad 4407 and the second low-voltage power signal transfer pad 4408 are respectively electrically connected to the second clock signal lines 2105, the second positive power input lines 2106, the second negative power input lines 2107, the fifth scan lines 2108, the sixth scan lines 2109, the fourth data lines 2110, the fourth high-voltage power lines 2111 and the fourth low-voltage power lines 2112. In other embodiments, the fifth scan lines 2108 and the sixth scan lines 2109 can also be arranged along the first direction M.

[0131] Similarly, the metal layer 2 is provided with the second clock signal transfer pad (not shown), the second positive power input signal transfer pad (not shown), the second negative power input signal transfer pad (not shown), the fifth scan signal transfer pad (not shown), the sixth scan signal transfer pad (not shown), the fourth data signal transfer pad (not shown), the fourth high-voltage power signal transfer pad (not shown) and the fourth low-voltage power signal transfer pad (not shown) corresponding to the second clock signal lines 2105, the second positive power input lines 2106, the second negative power input lines 2107, the fifth scan lines 2108, the sixth scan lines 2109, the fourth data lines 2110, the fourth high-voltage power lines 2111 and the fourth low-voltage power lines 2112 respectively, and then the first clock signal transfer pad 4401, the first positive power input signal transfer pad 4402, the first negative power input signal transfer pad 4403, the second scan signal transfer pad 4404, the third scan signal transfer pad 4405, the second data signal transfer pad 4406, the second high-voltage power signal transfer pad 4407 and the second low-voltage power signal transfer pad 4408 are respectively electrically connected to the second clock signal transfer pad (not shown), the second positive power input signal transfer pad (not shown), the second negative power input signal transfer pad (not shown), the fifth scan signal transfer pad (not shown), the sixth scan signal transfer pad (not shown), the fourth data signal transfer pad (not shown), the fourth high-voltage power signal transfer pad (not shown) and the fourth low-voltage power signal transfer pad (not shown).

[0132] As shown in FIG. 1, the display panel 1 comprises a plurality of display units 100 arranged in an array. Each display unit 100 comprises a frame display area 102 and a display area 101. The frame display area 102 is arranged around the display area 101. The display area 101 comprises a plurality of pixels 200 arranged in an array. Each pixel 200 comprises a sub-pixel 2001, a sub-pixel 2002 and a sub-pixel 2003. The sub-pixel 2001, the sub-pixel 2002 and the sub-pixel 2003 are arranged in a row and parallel to each other. The sub-pixel 2001, the sub-pixel 2002 and the sub-pixel 2003 are arranged in a column and parallel to each other. Figure 10As shown, in this embodiment, the second signal transition pad 43 penetrates the fourth planarization layer 4207 and is electrically connected to the sixth conductive unit 4206. The sixth conductive unit 4206 penetrates the third planarization layer 4205 and is electrically connected to the fifth conductive unit 4204. The fifth conductive unit 4204 penetrates the second interlayer insulating layer 4203, the fourth gate insulating layer 4202, the third gate insulating layer 4201, and the fourth buffer layer 4107 and is electrically connected to the fourth conductive unit 4106. The fourth conductive unit 4106 penetrates the fourth barrier layer 4105, the fourth flexible layer 4104, the third barrier layer 4103, the third flexible layer 4102, and the third buffer layer 4101 and is electrically connected to the third signal transition pad 44.

[0133] like Figure 10 As shown, in the bezel display area 102 of the present invention, the pixel circuit layer 32 is electrically connected to the first signal transition pad 34, the first signal transition pad 34 is electrically connected to the second signal transition pad 43, the second signal transition pad 43 is electrically connected to the third signal transition pad 44, and the third signal transition pad 44 is electrically connected to the signal line 21. Thus, the signal line 21 can be fabricated using a thick metal process, increasing the thickness of the signal line 21, reducing the sheet resistance of the signal line 21, thereby reducing the voltage drop, improving the display brightness of the display panel 100, and improving the display uniformity of the display panel 100.

[0134] like Figure 8 and Figure 9 As shown, the display panel 100 also includes a second package 6. The second package 6 is located in the bezel display area 102, covering the side of the light-emitting unit 33 away from the first substrate 31, and extending to cover the pixel circuit layer 32, the first substrate 31, the first signal transition pad 34, the second signal transition pad 43, the driving circuit layer 42, and the second substrate 41; the bottom surface of the second package 6 is flush with the bottom surface of the second substrate 41. The second package 6 is mainly used to prevent water and oxygen from entering the pixel circuit module 3, the second signal transition pad 43, the driving circuit layer 42, and the second substrate 41.

[0135] The embodiment also provides a preparation method of the display panel. The pixel circuit layer 32 is prepared on the first substrate 31. Specifically, the pixel circuit layer 32 includes a plurality of pixel circuit units, and a cutting path is reserved between adjacent pixel circuit units. The signals required by the pixel circuit layer 32, such as Scan, Data, VDD and VSS, are conducted to the first signal conversion pad 34 on the side of the first substrate 31 away from the pixel circuit layer 32 by a laser drilling and Ag filling in hole process. The anode 3214 and the first low-voltage power line (cathode) 3215 of the pixel circuit layer 32 are exposed on the surface layer of the pixel circuit layer 32, and then the anode 3302 and the cathode 3303 of the light-emitting unit 33 are electrically connected to the anode 3214 and the first low-voltage power line (cathode) 3215 of the pixel circuit layer 32, respectively, by a piece welding process or other bonding processes such as mass transfer bonding. Then, the first encapsulation body 5 is prepared in the cutting path between the light-emitting unit 33, the pixel circuit layer 32, the first substrate 31 and the pixel circuit units to form a first semi-finished product. The first semi-finished product is separated by a cutting process to form a plurality of pixel circuit modules 3 encapsulating the first encapsulation body 5.

[0136] The pixel circuit module 3 without encapsulation is bonded on the driving circuit module 4, and then the signals required by the pixel circuit module 3 are conducted to the third signal conversion pad 44 on the side of the second substrate 41 away from the driving circuit layer 42 by a laser drilling and Ag filling in hole process or a process of etching a deep hole and then filling metal; meanwhile, the signals required by the driving circuit module 4 are also conducted to the third signal conversion pad 44 on the side of the second substrate 41 away from the driving circuit layer 42 by a laser drilling and Ag filling in hole process or a process of etching a deep hole and then filling metal, and then the second encapsulation body 6 is prepared on the driving circuit module 4 and the pixel circuit module 3 for encapsulation.

[0137] Further, the display panel provided in the application is described in detail above, and the principles and implementation manners of the application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the application, and the above description of the specification should not be understood as a limitation of the application.

Claims

1. A display panel, characterized by, The display panel comprises a main display area and a frame display area. The display panel comprises: a substrate; a metal layer disposed on the substrate, the metal layer comprising a plurality of signal lines, the thickness of the signal lines of the metal layer being greater than 10 microns; a plurality of driving circuit modules disposed on a side of the metal layer away from the substrate and located in the frame display area and spaced apart from each other; and a plurality of pixel circuit modules disposed on a side of the driving circuit modules in the frame display area away from the substrate and spaced apart from each other; each of the pixel circuit modules comprises a first substrate, a pixel circuit layer disposed on the first substrate, a light-emitting unit disposed on a side of the pixel circuit layer away from the first substrate, and a first signal transfer pad disposed on a side of the first substrate away from the pixel circuit layer; each of the driving circuit modules comprises a second substrate, a driving circuit layer disposed on the second substrate, a second signal transfer pad disposed on a side of the driving circuit layer away from the second substrate, and a third signal transfer pad disposed on a side of the second substrate away from the driving circuit layer; in the frame display area, the pixel circuit layer is electrically connected to the first signal transfer pad, the first signal transfer pad is electrically connected to the second signal transfer pad, the second signal transfer pad is electrically connected to the third signal transfer pad, and the third signal transfer pad is electrically connected to the signal lines.

2. The display panel of claim 1, wherein, The first signal transfer pad comprises one or more of a first scan signal transfer pad, a first data signal transfer pad, a first high-voltage power supply signal transfer pad, and a first low-voltage power supply signal transfer pad electrically connected to a first scan line, a first data line, a first high-voltage power supply line, and a first low-voltage power supply line of the pixel circuit layer, respectively. The second signal transfer pad is arranged one-to-one corresponding to the first signal transfer pad.

3. The display panel of claim 2, wherein, The main display area is also provided with a plurality of pixel circuit modules, and the plurality of pixel circuit modules are spaced apart from each other on a side of the metal layer of the main display area away from the substrate; in the main display area, the pixel circuit layer is electrically connected to the first signal transfer pad, and the first signal transfer pad is electrically connected to the signal lines of the main display area; the metal layer of the main display area comprises third data lines arranged in a first direction, fourth scan lines parallel to each other arranged in a second direction intersecting the first direction, a third high-voltage power supply line, and a third low-voltage power supply line; the first scan signal transfer pad, the first data signal transfer pad, the first high-voltage power supply signal transfer pad, and the first low-voltage power supply signal transfer pad are electrically connected to the fourth scan lines, the third data lines, the third high-voltage power supply line, and the third low-voltage power supply line, respectively.

4. The display panel of claim 2, wherein, The third signal conversion pad comprises one or more of a first clock signal conversion pad, a first positive power input signal conversion pad, a first negative power input signal conversion pad, a second scan signal conversion pad, a third scan signal conversion pad, a second data signal conversion pad, a second high-voltage power signal conversion pad, and a second low-voltage power signal conversion pad, which are electrically connected to the first clock signal line, the first positive power input line, the first negative power input line, the second scan line, the third scan line, the second data line, the second high-voltage power line, and the second low-voltage power line of the driving circuit layer, respectively. The metal layer of the frame display area comprises: second clock signal lines, a second positive power input line, a second negative power input line, fourth data lines, a fourth high-voltage power line, and a fourth low-voltage power line arranged parallel to each other along a first direction, and fifth scan lines and sixth scan lines arranged parallel to each other along a second direction intersecting the first direction. The first clock signal conversion pad, the first positive power input signal conversion pad, the first negative power input signal conversion pad, the second scan signal conversion pad, the third scan signal conversion pad, the second data signal conversion pad, the second high-voltage power signal conversion pad, and the second low-voltage power signal conversion pad are electrically connected to the second clock signal line, the second positive power input line, the second negative power input line, the fifth scan line, the sixth scan line, the fourth data line, the fourth high-voltage power line, and the fourth low-voltage power line, respectively.

5. The display panel of claim 4, wherein, The first scan signal conversion pad, the first data signal conversion pad, the first high-voltage power signal conversion pad, and the first low-voltage power signal conversion pad are electrically connected to the third scan signal conversion pad, the second data signal conversion pad, the second high-voltage power signal conversion pad, and the second low-voltage power signal conversion pad, respectively.

6. The display panel of claim 4, wherein The first substrate comprises a first buffer layer, a first flexible layer, a first barrier layer, a second flexible layer, a second barrier layer, a first conductive unit, and a second buffer layer arranged in sequence. The pixel circuit layer comprises a first gate insulating layer, a second gate insulating layer, a first interlayer insulating layer, a second conductive unit, a first planar layer, a third conductive unit, and a second planar layer. The first low-voltage power line is electrically connected to the third conductive unit through the second planar layer, the third conductive unit is electrically connected to the second conductive unit through the first planar layer, the second conductive unit is electrically connected to the first conductive unit through the first interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and the second buffer layer, and the first conductive unit is electrically connected to the first signal conversion pad through the second barrier layer, the second flexible layer, the first barrier layer, the first flexible layer, and the first buffer layer.

7. The display panel of claim 6, wherein, The second substrate comprises a third buffer layer, a third flexible layer, a third barrier layer, a fourth flexible layer, a fourth barrier layer, a fourth conductive unit, and a fourth buffer layer arranged in sequence. The driving circuit layer comprises a third gate insulating layer, a fourth gate insulating layer, a second interlayer insulating layer, a fifth conductive unit, a third planar layer, a sixth conductive unit, and a fourth planar layer; The second signal transfer pad is electrically connected to the sixth conductive unit through the fourth planar layer, the sixth conductive unit is electrically connected to the fifth conductive unit through the third planar layer, the fifth conductive unit is electrically connected to the fourth conductive unit through the second interlayer insulating layer, the fourth gate insulating layer, the third gate insulating layer, and the fourth buffer layer, and the fourth conductive unit is electrically connected to the third signal transfer pad through the fourth barrier layer, the fourth flexible layer, the third barrier layer, the third flexible layer, and the third buffer layer.

8. The display panel of claim 1, wherein, The distance between the two pixel circuit modules in the main display area is equal to the distance between the pixel circuit modules in the frame display area.

9. The display panel of claim 1, wherein, Further comprising: A first encapsulation body located in the main display area; The first encapsulation body covers the side of the light emitting unit away from the first substrate and extends to cover the pixel circuit layer and the first substrate; The bottom surface of the first encapsulation body is flush with the bottom surface of the first substrate.

10. The display panel of claim 1, wherein, Further comprising: A second encapsulation body located in the frame display area; The second encapsulation body covers the side of the light emitting unit away from the first substrate and extends to cover the pixel circuit layer, the first substrate, the first signal transfer pad, the second signal transfer pad, the driving circuit layer, and the second substrate; The bottom surface of the second encapsulation body is flush with the bottom surface of the second substrate.

11. The display panel of claim 1, wherein, The light emitting unit is a light emitting diode, the anode of the light emitting diode is electrically connected to the anode of the pixel circuit layer, and the cathode of the light emitting diode is electrically connected to the cathode of the pixel circuit layer; or The light emitting unit is an organic light emitting diode, the anode of the organic light emitting diode is electrically connected to the anode of the pixel circuit layer, and the cathode of the organic light emitting diode is electrically connected to the cathode of the pixel circuit layer.

Images