Memory and method of manufacturing the same

Abstract

The application discloses a memory and a manufacturing method thereof. The memory comprises a plurality of transistors and further comprises: a substrate; a plurality of silicon columns corresponding to the plurality of transistors one by one, the silicon columns being arranged on the substrate and being spaced apart along a row direction and a column direction, adjacent two columns of the silicon columns having a groove therebetween, and adjacent two columns of the grooves having a plurality of recesses therebetween, each of the recesses being located in the substrate between two silicon columns adjacent along the column direction and extending in the substrate towards a region below the two silicon columns adjacent along the column direction; a plurality of bit lines extending along the column direction and being spaced apart along the row direction, each of the bit lines being located in a column of the recesses and being connected with bottom ends of the silicon columns, the bit lines being metal lines; and an isolation layer located between the bit lines and inner walls of the recesses and being in contact with at least a partial region of the substrate. The substrate is a single crystal silicon substrate, the silicon columns are single crystal silicon columns, and the isolation layer is an amorphous silicon or polycrystalline silicon film layer. The application can improve the thermal stability of the memory by adopting the polycrystalline silicon or amorphous silicon to isolate the bit lines from the single crystal silicon substrate.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of semiconductor devices, and in particular to a memory and a method for manufacturing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a common type of system memory widely used in personal computers, laptops, and consumer electronics. DRAM stores data in memory cells containing capacitors and arrayed transistors. DRAM transistors can utilize Vertical Gate-All-Around Field Effect Transistors (VGAAFETs). The channel of a VGAAFET is completely surrounded by the gate, and it offers significant advantages in 3D integration and wiring, thus possessing considerable potential for increasing integration density. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] This application provides a memory, which includes a plurality of transistors and further includes:

[0005] Substrate;

[0006] Multiple silicon pillars, each corresponding to a plurality of transistors, are located on the substrate; wherein the multiple silicon pillars are arranged at intervals along the row and column directions, and a trench is formed between two adjacent columns of silicon pillars; multiple grooves are formed between two adjacent columns of trenches, each groove being located in the substrate between two adjacent silicon pillars along the column direction and extending in the substrate toward the region below the two adjacent silicon pillars along the column direction;

[0007] Multiple bit lines extend along the column direction and are spaced apart in the row direction. Each bit line is located in a column of the grooves and is connected to the bottom end of the silicon pillar. The bit lines are metal lines.

[0008] Multiple isolation layers are located between the bit line and the inner wall of the groove, and are in contact with at least a portion of the substrate;

[0009] The substrate is a monocrystalline silicon substrate, the plurality of silicon pillars are monocrystalline silicon pillars, and the isolation layer is an amorphous silicon film or a polycrystalline silicon film.

[0010] In embodiments of this application, each groove may have an isolation layer evenly distributed on its inner sidewall.

[0011] In embodiments of this application, each of the isolation layers may extend between each column of silicon pillars and the substrate.

[0012] In embodiments of this application, a hole may be provided between two adjacent silicon pillars along the column direction, each groove is located in the substrate below a hole, and the plurality of grooves below each column of holes are interconnected in the column direction.

[0013] In an embodiment of this application, the metal wire of the bit line may be formed by a first conductive layer, which is disposed on the inner wall of the groove.

[0014] In embodiments of this application, the metal line of the bit line can be formed by a first conductive layer and a second conductive layer. The first conductive layer is disposed on the inner wall of the groove and located between the second conductive layer and the isolation layer. In embodiments of this application, the material of the first conductive layer can be a silicide of a first conductive metal, and the material of the second conductive layer can be a second conductive metal.

[0015] In embodiments of this application, the first conductive metal may be selected from any one or more of titanium, cobalt, and nickel.

[0016] In embodiments of this application, the second conductive metal may be selected from any one or more of tungsten, copper, and aluminum.

[0017] In embodiments of this application, the memory may further include a first barrier layer and a conductive second barrier layer; wherein,

[0018] The first barrier layer may be disposed on the surface of the top end and the surface of the sidewall of the silicon pillar;

[0019] The second barrier layer may be disposed between the first conductive layer and the second conductive layer.

[0020] This application embodiment also provides a method for manufacturing a memory, the method comprising:

[0021] A silicon substrate is provided, on which a plurality of trenches extending in a column direction are etched, the plurality of trenches dividing the upper part of the silicon substrate into a plurality of silicon walls arranged in a row direction and extending in a column direction, and a dielectric layer covering the trenches is deposited on the silicon substrate.

[0022] The silicon wall is etched along a direction perpendicular to the silicon substrate to form a plurality of spaced holes on each silicon wall. The plurality of holes space the silicon wall into a plurality of silicon pillars. Each silicon pillar sequentially includes a source region, a channel region and a drain region. A first barrier layer is deposited on the silicon substrate to cover the surface of the silicon pillars and to expose the silicon substrate between two adjacent silicon pillars along the column direction.

[0023] The exposed silicon substrate is etched to form a groove extending downward into the silicon substrate and extending to the bottom of two adjacent silicon pillars along the column direction under each hole, and the plurality of grooves under each column of holes are interconnected in the column direction;

[0024] A polycrystalline silicon film or an amorphous silicon film is deposited in the groove, and a groove with a polycrystalline silicon film or an amorphous silicon film on the surface is formed by patterning. The patterned polycrystalline silicon film or amorphous silicon film forms an isolation layer, and the isolation layer contacts at least a portion of the silicon substrate.

[0025] Metal lines are deposited in the groove to form bit lines, each bit line extending along the column direction and contacting the isolation layer, and each bit line is connected to the bottom end of a corresponding column of silicon pillars.

[0026] In embodiments of this application, the deposition of a polycrystalline silicon film or an amorphous silicon film in the groove, the patterning of a groove having a polycrystalline silicon film or an amorphous silicon film on its surface, the patterned polycrystalline silicon film or amorphous silicon film forming an isolation layer, and the contact between the isolation layer and at least a portion of the substrate may include:

[0027] A polycrystalline silicon film or an amorphous silicon film is deposited in the groove. A groove with a polycrystalline silicon film or an amorphous silicon film on its surface is formed by patterning. The patterned polycrystalline silicon film or amorphous silicon film forms an isolation layer, which contacts at least a portion of the silicon substrate.

[0028] Each of the grooves has an isolation layer distributed on its inner sidewall; and / or,

[0029] Each of the isolation layers extends beneath the silicon pillars arranged in the column direction, and the isolation layers beneath each column of silicon pillars are connected together.

[0030] In embodiments of this application, the deposition of metal lines in the groove to form bit lines may include:

[0031] A first conductive metal is deposited on the inner wall of the groove, and the first conductive metal reacts with the polycrystalline silicon or amorphous silicon in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer on the inner wall of the groove composed of the silicide of the first conductive metal. The first conductive layer constitutes the metal line, the metal line forms the bit line, and the polycrystalline silicon or amorphous silicon that is not reacted by the first conductive metal forms the isolation layer; or...

[0032] A first conductive metal is deposited on the inner wall of the groove, and the first conductive metal reacts with polycrystalline silicon or amorphous silicon in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer on the inner wall of the groove formed by the silicide of the first conductive metal. The polycrystalline silicon or amorphous silicon that is not reacted by the first conductive metal forms the isolation layer. A conductive second barrier layer is deposited on the surface of the first conductive layer, and the remaining portion of the groove is filled with a second conductive metal to form a second conductive layer. The first conductive layer and the second conductive layer constitute the metal line, and the metal line forms the bit line.

[0033] The memory of this application introduces an isolation layer between the metal bit lines and the single-crystal silicon substrate, and the material of the isolation layer is polycrystalline silicon or amorphous silicon. Since there is no regular crystal phase arrangement inside polycrystalline silicon and amorphous silicon, when the bit lines are interconnected by reacting metal with silicon in polycrystalline silicon or amorphous silicon to form metal silicides, the problem of irregular diffusion of metal silicides along the crystal phase will not occur. This can avoid the problem of metal silicide agglomeration that is easy to occur when forming metal bit lines in a single-crystal silicon substrate, and improve the thermal stability of the memory.

[0034] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0035] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0036] Figure 1 A top view of the memory structure as an exemplary embodiment of this application;

[0037] Figure 2 for Figure 1 The diagram shows a longitudinal section of the memory on section a-a'.

[0038] Figure 3AA schematic diagram of the longitudinal section structure of an intermediate product obtained in an intermediate step of a method for manufacturing a memory, which is an exemplary embodiment of this application, on section a-a'.

[0039] Figure 3B A schematic diagram of the longitudinal section structure of an intermediate product obtained in an intermediate step of a method for manufacturing a memory, which is an exemplary embodiment of this application, on section a-a'.

[0040] Figure 3C This is a schematic diagram of the longitudinal section structure of an intermediate product obtained from an intermediate step in the manufacturing method of a memory, which is an exemplary embodiment of this application, on section a-a'.

[0041] 10-Silicon pillar; 11-Source region; 12-Channel region; 13-Drain region; 20-Bit line; 21-First conductive layer; 22-Second conductive layer; 30-Isolation layer; 31-First barrier layer; 32-Second barrier layer; 40-Substrate; 50-Hole; 50'-Groove; 60-Trench; 70-Word line. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0043] The embodiments described herein can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in many ways without departing from the spirit and scope of this application. Therefore, this application should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0044] The scale of the figures in this application can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The figures described in this application are only schematic diagrams of the structure, and the approach of this application is not limited to the shapes or values ​​shown in the figures.

[0045] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to those described in the specification and may be appropriately replaced as needed.

[0046] In this specification, unless otherwise expressly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0047] In the description of this application, ordinal numbers such as "first" and "second" are used to avoid confusion of constituent elements, rather than to limit the quantity.

[0048] This application provides a memory, which includes a plurality of transistors and further includes:

[0049] Substrate;

[0050] Multiple silicon pillars, each corresponding to a plurality of transistors, are located on the substrate; wherein the multiple silicon pillars are arranged at intervals along the row and column directions, and a trench is formed between two adjacent columns of silicon pillars; multiple grooves are formed between two adjacent columns of trenches, each groove being located in the substrate between two adjacent silicon pillars along the column direction and extending in the substrate toward the region below the two adjacent silicon pillars along the column direction;

[0051] Multiple bit lines extend along the column direction and are spaced apart in the row direction. Each bit line is located in a column of the grooves and is connected to the bottom end of the silicon pillar. The bit lines are metal lines.

[0052] Multiple isolation layers are located between the bit line and the inner wall of the groove, and are in contact with at least a portion of the substrate;

[0053] The substrate is a monocrystalline silicon substrate, the plurality of silicon pillars are monocrystalline silicon pillars, and the isolation layer is an amorphous silicon film or a polycrystalline silicon film.

[0054] To achieve bit line (BL) interconnects in memory, the following method can be used: metal silicides are formed in multiple grooves in a single-crystal silicon substrate by high-temperature annealing of metal and the single-crystal silicon in the substrate. The metal silicides in the multiple grooves are then connected together in a "point-to-point" manner to form a bit line. However, due to the regular crystal orientation of single-crystal silicon, a channel effect in a certain crystal orientation can easily occur during the formation of metal silicides. That is, during annealing or subsequent high-temperature processes, metal silicides can diffuse irregularly along the crystal phase (also known as thermal stability issues), leading to irregular aggregation of metal silicides and affecting memory performance.

[0055] The memory of this application introduces an isolation layer between the metal bit lines and the monocrystalline silicon substrate, and the material of the isolation layer is polycrystalline silicon or amorphous silicon. Since there is no regular crystal phase arrangement inside polycrystalline silicon and amorphous silicon, when the bit lines are interconnected by reacting metal with silicon in polycrystalline silicon and / or amorphous silicon to form metal silicides, the problem of irregular diffusion of metal silicides along the crystal phase will not occur. This can avoid the problem of metal silicide agglomeration that is easy to occur when forming metal bit lines in monocrystalline silicon substrate, and improve the thermal stability of the memory.

[0056] In embodiments of this application, a hole may be provided between two adjacent silicon pillars along the column direction, each groove is located in the substrate below a hole, and the plurality of grooves below each column of holes are interconnected in the column direction.

[0057] Figure 1 A top view of the memory structure as an exemplary embodiment of this application; Figure 2 for Figure 1 The diagram shows a longitudinal cross-sectional structure of the memory on section a-a'.

[0058] like Figure 1 and Figure 2 As shown in the exemplary embodiment of this application, the memory includes a plurality of transistors and may further include: a plurality of silicon pillars 10, a plurality of bit lines 20, a plurality of isolation layers 30 and a substrate 40;

[0059] Substrate 40 is a single-crystal silicon substrate;

[0060] Multiple silicon pillars 10 correspond one-to-one with the multiple transistors and are all disposed on the substrate 40, and are single-crystal silicon pillars. The multiple silicon pillars 10 are arranged at intervals along the row direction and the column direction. There is a hole 50 between two adjacent silicon pillars 10 along the column direction, a trench 60 between two adjacent columns of silicon pillars 10, and multiple grooves 50' between two adjacent columns of trenches 60. Each groove 50' is located in the substrate 40 between two adjacent silicon pillars 10 along the column direction, that is, each groove 50' is located in the substrate 40 below a hole 50 and extends toward the area below the two adjacent silicon pillars 10 along the column direction. The multiple grooves 50' below each column of holes 50 can be interconnected in the column direction.

[0061] Multiple bit lines 20 are arranged at intervals in the row direction; each bit line 20 extends in the column direction and is located in a column of vias 50 extending into the substrate 40 and connected to the bottom end of the silicon pillar 10; the bit lines 20 are metal lines, which may be formed of a material containing a metal element, for example, the metal lines may be formed of a metal or a metal silicide; for example, the vias 50 extend to the bit lines 20 in a direction perpendicular to the substrate 40 and expose the bit lines 20;

[0062] The isolation layer 30 is located between the bit line 20 and the inner wall of the groove 50'. The isolation layer 30 is in contact with at least a portion of the substrate 40. The isolation layer 30 is a polycrystalline silicon film or an amorphous silicon film.

[0063] In the embodiments of this application, such as Figure 2 As shown, an isolation layer 30 can be evenly distributed on the inner sidewall of each groove 50'.

[0064] In the embodiments of this application, such as Figure 2 As shown, bit line 20 and substrate 40 can be completely non-contact.

[0065] In the embodiments of this application, such as Figure 2 As shown, each isolation layer 30 can extend into the region between each row of silicon pillars 10 and the substrate.

[0066] In the embodiments of this application, such as Figure 2 As shown, bit line 20 can be formed by multiple bit line units that are interconnected in the column direction;

[0067] Each bitline unit is located in a recess 50'.

[0068] The multiple grooves 50' below each column hole 50 are interconnected in the column direction, so that multiple bit line units in the multiple grooves 50' below each column hole 50 can be connected together in the column direction to form a bit line 20.

[0069] In an embodiment of this application, the metal wire of the bit line may be formed by a first conductive layer, which is disposed on the inner wall of the groove.

[0070] In the embodiments of this application, such as Figure 2 As shown, the metal wire of bit line 20 can be formed by a first conductive layer 21 and a second conductive layer 22. The first conductive layer 21 is disposed on the inner wall of the groove and is located between the second conductive layer 22 and the isolation layer 30.

[0071] In the embodiments of this application, the material of the first conductive layer may be a silicide of a first conductive metal, and the material of the second conductive layer may be a second conductive metal.

[0072] In embodiments of this application, the first conductive metal may be selected from any one or more of titanium, cobalt, and nickel.

[0073] In embodiments of this application, the second conductive metal may be selected from any one or more of tungsten, copper, and aluminum.

[0074] When the first conductive metal or the second conductive metal comprises multiple materials, the first conductive layer or the second conductive layer can be a multilayer structure formed from multiple materials respectively.

[0075] In the embodiments of this application, such as Figure 2 As shown, the memory may further include a first barrier layer 31, which may be disposed on the surface of the top end and the surface of the sidewall of the silicon pillar 10.

[0076] In the embodiments of this application, such as Figure 2 As shown, the memory may further include a conductive second barrier layer 32, which is disposed between the first conductive layer 21 and the second conductive layer 22. In embodiments of this application, as... Figure 2 As shown, the silicon pillar may sequentially include a source region 11, a channel region 12, and a drain region 13, wherein the source region or the drain region is in contact with and connected to the bit line.

[0077] In embodiments of this application, the source region, the channel region, and the drain region may be located on the sidewall of the silicon pillar; exemplarily, the source region, the channel region, and the drain region may extend from the sidewall of the silicon pillar into the interior of the silicon pillar and penetrate the surfaces of opposite sides of the sidewall of the silicon pillar.

[0078] In embodiments of this application, the memory may further include a gate (not shown in the figure), the gate being disposed on the sidewall of the silicon pillar and surrounding a channel region of the sidewall, a gate insulating layer being disposed between the gate and the channel region, and the gate being connected to a word line.

[0079] In embodiments of this application, a transistor of the memory may include a silicon pillar, a gate insulating layer disposed on the sidewall of the silicon pillar, and a gate.

[0080] In the embodiments of this application, such as Figure 1 As shown, the gates on one side of a row of silicon pillars 10 can be connected together to form a word line 70 extending along the row direction, thereby realizing the connection between the gate and the word line 70.

[0081] In embodiments of this application, the hole may be perpendicular to the substrate, and the trench may be perpendicular to the substrate.

[0082] In the embodiments of this application, the etching selectivity of the substrate and the first barrier layer is relatively high. When the hole is etched to extend into the substrate and to form the groove in the region below the silicon pillars adjacent in the column direction, the first barrier layer is used to protect the sidewalls of the silicon pillars and prevent the silicon pillars from being etched away.

[0083] For example, the etching selectivity ratio of the substrate to the first barrier layer can be ≥20; as another example, the substrate material is single-crystal silicon, and the material of the first barrier layer can be selected from any one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. When the first barrier layer comprises multiple materials, the first barrier layer can be a multilayer structure formed from multiple materials respectively.

[0084] In the embodiments of this application, such as Figure 1 As shown, the blank spaces of the memory, for example, the blank spaces between silicon pillars 10, may be filled with a dielectric layer. The material of the dielectric layer may be selected from any one or more of silicon oxide, silicon nitride, silicon carbonitride, and silicon carbonitride.

[0085] In embodiments of this application, the material of the second barrier layer may be selected from one or more of titanium nitride (TiN) and tantalum nitride (TaN). When the second barrier layer comprises multiple materials, the second barrier layer may be a multilayer structure formed from the multiple materials respectively.

[0086] When depositing the second conductive layer, the second conductive layer is typically deposited first in the hole above the groove and in the groove, and then etched back to remove the second conductive layer in the hole above the groove, leaving only the second conductive layer in the groove. The second barrier layer can protect the silicon pillar from being etched away when etching away excess second conductive layer in the hole.

[0087] In this embodiment, the height of the silicon pillar in the direction perpendicular to the substrate can be set according to actual electrical requirements, for example, it can be 10nm to 50nm.

[0088] In embodiments of this application, the gate material may be titanium nitride (TiN), aluminum, or an aluminum-containing alloy; or,

[0089] The material of the gate can be selected from any one or more conductor materials formed from Group IVA elements. For example, the material of the gate can be selected from any one or more of polycrystalline silicon, polycrystalline silicon germanium, etc.

[0090] In embodiments of this application, the material of the gate insulating layer can be selected from any one or more of silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO), and aluminum oxide (e.g., Al2O3). The gate insulating layer can be a single-layer or multi-layer structure; for example, it can include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer contacts the channel region, and the hafnium oxide layer contacts the gate. The thickness of the gate insulating layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.

[0091] In embodiments of this application, the transistor of the memory can be a vertical gate-all-around (VGAA) transistor; the memory can also be a memory device containing transistors, such as Dynamic Random Access Memory (DRAM), Magnetic Random Access Memory (MRAM), etc.

[0092] This application also provides a method for manufacturing a memory, the method comprising:

[0093] A silicon substrate is provided, on which a plurality of trenches extending in a column direction are etched, the plurality of trenches dividing the upper part of the silicon substrate into a plurality of silicon walls arranged in a row direction and extending in a column direction, and a dielectric layer covering the trenches is deposited on the silicon substrate.

[0094] The silicon wall is etched along a direction perpendicular to the silicon substrate to form a plurality of spaced holes on each silicon wall. The plurality of holes space the silicon wall into a plurality of silicon pillars. Each silicon pillar sequentially includes a source region, a channel region and a drain region. A first barrier layer is deposited on the silicon substrate to cover the surface of the silicon pillars and to expose the silicon substrate between two adjacent silicon pillars along the column direction.

[0095] The exposed silicon substrate is etched to form a groove extending downward into the silicon substrate and extending to the bottom of two adjacent silicon pillars along the column direction under each hole, and the plurality of grooves under each column of holes are interconnected in the column direction;

[0096] A polycrystalline silicon film or an amorphous silicon film is deposited in the groove, and a groove with a polycrystalline silicon film or an amorphous silicon film on the surface is formed by patterning. The patterned polycrystalline silicon film or amorphous silicon film forms an isolation layer, and the isolation layer contacts at least a portion of the silicon substrate.

[0097] Metal lines are deposited in the groove to form bit lines, each bit line extending along the column direction and contacting the isolation layer, and each bit line is connected to the bottom end of a corresponding column of silicon pillars.

[0098] In embodiments of this application, the deposition of a polycrystalline silicon film or an amorphous silicon film in the groove, the patterning of a groove having a polycrystalline silicon film or an amorphous silicon film on its surface, the patterned polycrystalline silicon film or amorphous silicon film forming an isolation layer, and the contact between the isolation layer and at least a portion of the substrate may include:

[0099] A polycrystalline silicon film or an amorphous silicon film is deposited in the groove. A groove with a polycrystalline silicon film or an amorphous silicon film on its surface is formed by patterning. The patterned polycrystalline silicon film or amorphous silicon film forms an isolation layer, which contacts at least a portion of the silicon substrate.

[0100] Each of the grooves has an isolation layer distributed on its inner sidewall; and / or,

[0101] Each of the isolation layers extends beneath the silicon pillars arranged in the column direction, and the isolation layers beneath each column of silicon pillars are connected together.

[0102] In embodiments of this application, the deposition of metal lines in the groove to form bit lines may include:

[0103] A first conductive metal is deposited on the inner wall of the groove, and the first conductive metal reacts with the polycrystalline silicon film or amorphous silicon film in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer on the inner wall of the groove formed by the silicide of the first conductive metal. The first conductive layer constitutes the metal line, the metal line forms the bit line, and the polycrystalline silicon film or amorphous silicon film that is not reacted by the first conductive metal forms the isolation layer.

[0104] In embodiments of this application, the deposition of metal lines in the groove to form bit lines may include:

[0105] A first conductive metal is deposited on the inner wall of the groove, and the first conductive metal reacts with a polycrystalline silicon film or an amorphous silicon film in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer on the inner wall of the groove composed of the silicide of the first conductive metal. The polycrystalline silicon film or amorphous silicon film that is not reacted by the first conductive metal forms the isolation layer; and...

[0106] A conductive second barrier layer is deposited on the surface of the first conductive layer, and the remaining portion of the groove is filled with a second conductive metal to form a second conductive layer. The first conductive layer and the second conductive layer constitute the metal line, and the metal line forms the bit line.

[0107] In embodiments of this application, the step of reacting the first conductive metal with the polycrystalline silicon or amorphous silicon in the isolation layer to form a conductive first conductive metal silicide may include: reacting the first conductive metal with the polycrystalline silicon or amorphous silicon in the isolation layer to form a conductive first conductive metal silicide through an annealing process.

[0108] In embodiments of this application, the method for manufacturing the memory may further include: after forming the silicide of the first conductive metal and before depositing a conductive second barrier layer on the surface of the first conductive layer, removing the first conductive metal that has not reacted with polycrystalline silicon or amorphous silicon by wet etching.

[0109] In the embodiments of this application, the first conductive metal is titanium (Ti), and the reagent used for wet etching can be sulfuric acid or a mixture of sulfuric acid and hydrogen peroxide. In the mixture of sulfuric acid and hydrogen peroxide, with a mass fraction of sulfuric acid of about 98% and a mass fraction of hydrogen peroxide of about 30%, the volume ratio of sulfuric acid to hydrogen peroxide is 2:1 to 10:1. The temperature of wet etching can be from 80°C to 170°C, for example, 80°C, 90°C, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, 160°C, or 170°C. The etching rate of titanium can be from 5 nm / min to 20 nm / min, for example, 5 nm / min, 6 nm / min, 8 nm / min, 10 nm / min, 12 nm / min, 14 nm / min, 16 nm / min, 18 nm / min, or 20 nm / min. When the temperature of wet etching is between 80°C and 170°C and the etching rate of titanium is between 5 nm / min and 20 nm / min, titanium that has not reacted with silicon can be removed more effectively without corroding titanium silicide.

[0110] In embodiments of this application, the method of manufacturing the memory may further include: when removing a portion of the isolation layer in the groove by patterning and retaining the isolation layer on the inner wall of the groove, trimming the isolation layer in the groove so that the isolation layer retained on the inner wall of the groove has a desired shape, such as a bowl shape, an ellipse, a sigma (Σ) shape, a rhombus shape, etc.

[0111] In the embodiments of this application, the silicon substrate can be a single-crystal silicon substrate, or a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-sapphire (SOS) substrate, a silicon-on-glass (SOG) substrate, an epitaxial layer of silicon on a substrate semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si). 1-x Ge x , where x can be, for example, a mole fraction between 0.2 and 0.8, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The substrate may be doped or undoped.

[0112] Figures 3A to 3C This is a schematic diagram of the longitudinal cross-sectional structure of an intermediate product obtained from an intermediate step in the manufacturing method of a memory according to an exemplary embodiment of this application, along section a-a'. Figures 3A to 3C and Figure 2 As shown in an exemplary embodiment of this application, the method for manufacturing the memory may include:

[0113] S10: Provide a substrate 40 (a silicon substrate is used in this embodiment), and etch a plurality of trenches 60 on the substrate 40. Each trench 60 extends along the column direction. The plurality of trenches 60 space the upper part of the substrate 40 as a plurality of silicon walls that are spaced apart along the row direction and extend along the column direction. Fill the trenches 60 with a dielectric layer.

[0114] The silicon wall is etched in a direction perpendicular to the substrate 40, such that a plurality of spaced holes 50 are formed on each silicon wall, and the plurality of holes 50 formed on a silicon wall space the silicon wall into a plurality of silicon pillars 10 spaced apart along the column direction. A first barrier layer 31 is deposited on the sidewall surface and top surface of the silicon pillar 10, and the substrate 40 between two adjacent silicon pillars 10 along the column direction is exposed.

[0115] S20: The exposed substrate 40 is etched to form a groove 50' extending downward into the substrate 40 and extending below two adjacent silicon pillars 10 in the column direction under each hole 50, and the multiple grooves 50' under each column hole 50 are interconnected in the column direction, and the multiple grooves 50' arranged in the row direction are separated by a dielectric layer filled in the trench 60 and are not interconnected.

[0116] S30: A polycrystalline silicon film or an amorphous silicon film is deposited in the groove 50' and the portion of the hole 50 above the groove 50', and the polycrystalline silicon film or amorphous silicon film covers the surface of the first barrier layer 31, resulting in... Figure 3A The intermediate products shown;

[0117] S40: Remove the polycrystalline silicon or amorphous silicon film layer in the hole 50 and a portion of the polycrystalline silicon or amorphous silicon film layer in the groove 50', retaining the polycrystalline silicon or amorphous silicon film layer on the inner wall of the groove 50', and shape the polycrystalline silicon or amorphous silicon film layer in the groove 50' using a patterning method, so that the retained polycrystalline silicon or amorphous silicon film layer on the inner wall of the groove 50' has a desired shape. The retained polycrystalline silicon or amorphous silicon film layer forms an isolation layer 30. For example, the isolation layers 30 in two adjacent grooves 50' along the column direction can be connected to obtain, as shown in the figure. Figure 3B The intermediate products shown;

[0118] S50: A first conductive metal is deposited on the inner wall of the groove 50'. Through an annealing process, the first conductive metal reacts with the polycrystalline silicon or amorphous silicon in the isolation layer to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer 21 formed by the silicide of the first conductive metal on the inner wall of the groove. The first conductive metal that has not reacted with the polycrystalline silicon or amorphous silicon is removed by wet etching. The first conductive layer and the substrate 40 are separated by an isolation layer that has not been reacted with the first conductive metal, resulting in... Figure 3C The intermediate products shown; and

[0119] A conductive second barrier layer is deposited on the surface of the first conductive layer, and the remaining portion of the groove 50' is filled with a second conductive metal to form a second conductive layer. The first and second conductive layers constitute the metal wire, and the metal wires in two adjacent grooves along the column direction are connected to form a bit line, resulting in... Figure 2 The memory shown.

[0120] The memory described above in the embodiments of this application can be obtained by the memory manufacturing method provided in the embodiments of this application above.

[0121] In the embodiments of this application, the methods for forming the holes and the trenches can each be independently selected from any one or more of dry etching and wet etching.

[0122] In embodiments of this application, the groove can be formed by side etching of the lower part of the first trench using any one or more of dry etching and wet etching methods.

[0123] In the embodiments of this application, the methods for depositing the first barrier layer, the isolation layer, the second barrier layer and the dielectric layer can each be independently selected from either atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0124] This application also provides an electronic device, which includes the memory provided in the above embodiments of this application.

[0125] In this application embodiment, the electronic device may include a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank.

[0126] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A memory comprising a plurality of transistors, characterized in that, Also includes: Substrate; Multiple silicon pillars, each corresponding to a plurality of transistors, are located on the substrate; wherein the multiple silicon pillars are arranged at intervals along the row and column directions, and a trench is formed between two adjacent columns of silicon pillars; multiple grooves are formed between two adjacent columns of trenches, each groove being located in the substrate between two adjacent silicon pillars along the column direction and extending in the substrate toward the region below the two adjacent silicon pillars along the column direction; Multiple bit lines extend along the column direction and are spaced apart in the row direction. Each bit line is located in a column of the grooves and is connected to the bottom end of the silicon pillar. The bit lines are metal lines. Multiple isolation layers are located between the bit line and the inner wall of the groove, and are in contact with at least a portion of the substrate; The substrate is a monocrystalline silicon substrate, the plurality of silicon pillars are monocrystalline silicon pillars, and the isolation layer is an amorphous silicon film or a polycrystalline silicon film.

2. The memory according to claim 1, wherein, Each of the grooves has an isolation layer distributed on its inner sidewall.

3. The memory according to claim 2, wherein, Each of the isolation layers extends between each column of silicon pillars and the substrate.

4. The memory according to any one of claims 1 to 3, wherein, A hole is provided between two adjacent silicon pillars along the column direction, each groove is located in the substrate below a hole, and the plurality of grooves below the holes in each column are interconnected in the column direction.

5. The memory according to any one of claims 1 to 3, wherein, The metal wire of the bit line is formed by a first conductive layer, which is disposed on the inner wall of the groove; or, The metal wire of the bit line is formed by a first conductive layer and a second conductive layer. The first conductive layer is disposed on the inner wall of the groove and is located between the second conductive layer and the isolation layer. Wherein, the material of the first conductive layer is a silicide of a first conductive metal, and the material of the second conductive layer is a second conductive metal.

6. The memory according to claim 5, wherein, The first conductive metal is selected from any one or more of titanium, cobalt, and nickel; The second conductive metal is selected from any one or more of tungsten, copper, and aluminum.

7. The memory according to claim 5, further comprising a first barrier layer and a conductive second barrier layer; wherein, The first barrier layer is disposed on the surface of the top end and the surface of the sidewall of the silicon pillar; The second barrier layer is disposed between the first conductive layer and the second conductive layer.

8. A method for manufacturing a memory, characterized in that, include: A silicon substrate is provided, on which a plurality of trenches extending in a column direction are etched, the plurality of trenches dividing the upper part of the silicon substrate into a plurality of silicon walls arranged in a row direction and extending in a column direction, and a dielectric layer covering the trenches is deposited on the silicon substrate. The silicon wall is etched along a direction perpendicular to the silicon substrate to form a plurality of spaced holes on each silicon wall. The plurality of holes space the silicon wall into a plurality of silicon pillars. Each silicon pillar sequentially includes a source region, a channel region and a drain region. A first barrier layer is deposited on the silicon substrate to cover the surface of the silicon pillars and to expose the silicon substrate between two adjacent silicon pillars along the column direction. The exposed silicon substrate is etched to form a groove extending downward into the silicon substrate and extending to the bottom of two adjacent silicon pillars along the column direction under each hole, and the plurality of grooves under each column of holes are interconnected in the column direction; A polycrystalline silicon film or an amorphous silicon film is deposited in the groove, and a groove with a polycrystalline silicon film or an amorphous silicon film on the surface is formed by patterning. The patterned polycrystalline silicon film or amorphous silicon film forms an isolation layer, and the isolation layer contacts at least a portion of the silicon substrate. Metal lines are deposited in the groove to form bit lines, each bit line extending along the column direction and contacting the isolation layer, and each bit line is connected to the bottom end of a corresponding column of silicon pillars.

9. The manufacturing method according to claim 8, wherein, The step of depositing a polycrystalline silicon film or an amorphous silicon film in the groove, forming a groove with a polycrystalline silicon film or an amorphous silicon film on its surface by patterning, forming an isolation layer by the patterned polycrystalline silicon film or amorphous silicon film, and making the isolation layer contact at least a portion of the substrate includes: A polycrystalline silicon film or an amorphous silicon film is deposited in the groove. A groove with a polycrystalline silicon film or an amorphous silicon film on its surface is formed by patterning. The patterned polycrystalline silicon film or amorphous silicon film forms an isolation layer, which contacts at least a portion of the silicon substrate. Each of the grooves has an isolation layer distributed on its inner sidewall; and / or, Each of the isolation layers extends beneath the silicon pillars arranged in the column direction, and the isolation layers beneath each column of silicon pillars are connected together.

10. The manufacturing method according to claim 8 or 9, wherein, The deposition of metal lines in the groove to form bit lines includes: A first conductive metal is deposited on the inner wall of the groove, and the first conductive metal reacts with the polycrystalline silicon or amorphous silicon in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer on the inner wall of the groove composed of the silicide of the first conductive metal. The first conductive layer constitutes the metal line, the metal line forms the bit line, and the polycrystalline silicon or amorphous silicon that is not reacted by the first conductive metal forms the isolation layer; or... A first conductive metal is deposited on the inner wall of the groove, and the first conductive metal reacts with polycrystalline silicon or amorphous silicon in the groove to form a conductive silicide of the first conductive metal, thereby forming a first conductive layer on the inner wall of the groove formed by the silicide of the first conductive metal. The polycrystalline silicon or amorphous silicon that is not reacted by the first conductive metal forms the isolation layer. A conductive second barrier layer is deposited on the surface of the first conductive layer, and the remaining portion of the groove is filled with a second conductive metal to form a second conductive layer. The first conductive layer and the second conductive layer constitute the metal line, and the metal line forms the bit line.

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