A display panel and a display device

Abstract

The present application provides a display panel and a display device. The display panel has a chip bonding area, and the display panel includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group arranged in sequence in the chip bonding area; the display panel further includes an organic layer provided in the chip bonding area. The organic layer includes a first boundary and a second boundary. Among them, the first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, where a ≥ 30 μm; the second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, where b ≥ 30 μm. The display panel and the display device provided by the present application can improve the problem of film layer peeling in the chip bonding area, thereby improving the problem of abnormal chip output signals caused by film layer peeling, and improving the display quality of the display panel and the display device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Compared with liquid crystal displays, organic light-emitting diode (OLED) display panels have the advantages of being lighter, thinner, having better display effects, higher resolution, wider color gamut, lower power consumption, and flexible display. As a result, they have developed rapidly in recent years and have become the preferred display panel type for mobile terminals.

[0003] With the development of OLED display technology, users' requirements for the performance of display panels are gradually increasing. Usually, the double 85 test / HAST test (also known as RA test) is used to test the limits of OLED display panels in harsh environments of high temperature and high humidity. The common defect of OLED display panels in the double 85 test / HAST test is the peeling problem of the film layer in the chip bonding (COP) area. The peeling of the film layer in the COP area will cause abnormal chip output signals, causing vertical bright lines on the OLED display panel, affecting the display quality of the display panel. This problem needs to be solved urgently. Summary of the invention

[0004] The present application provides a display panel and a display device, which can effectively solve the problems of display abnormality and reduced display quality in existing OLED display panels.

[0005] On the one hand, the present application provides a display panel, the display panel having a chip binding area, the display panel including an output terminal group, a multiplexer, a test terminal group and an input terminal group arranged in sequence in the chip binding area; the display panel also includes an organic layer arranged in the chip binding area, the organic layer including a first boundary and a second boundary, wherein the first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, a≥30μm; the second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, b≥30μm.

[0006] Optionally, no electrostatic protection circuit is provided between the output terminal group and the input terminal group.

[0007] Optionally, the organic layer between the first boundary and the second boundary is continuously arranged.

[0008] Optionally, the organic layer located between the first boundary and the second boundary is intermittently arranged. The display panel further includes a dummy terminal group disposed in the chip bonding area, and the dummy terminal group is located between the multiplexer and the test terminal group. The organic layer includes a third boundary and a fourth boundary. The third boundary is located between the multiplexer and the dummy terminal group, and the distance between the third boundary and the dummy terminal group is c, where c > m / 6 and m is the distance between the third boundary and the first boundary. The fourth boundary is located between the test terminal group and the dummy terminal group, and the distance between the fourth boundary and the test terminal group is d, where d > n / 6 and n is the distance between the fourth boundary and the second boundary.

[0009] Optionally, the dummy terminal group includes a plurality of dummy terminals, and the plurality of dummy terminals form a plurality of dummy terminal rows, where c = d ≥ 50 μm.

[0010] Optionally, the organic layer is not provided between any two adjacent dummy terminal rows.

[0011] Optionally, the dummy terminal group includes a plurality of dummy terminals, and the plurality of dummy terminals form a single dummy terminal row, where c = d ≥ 80 μm.

[0012] Optionally, a = b = c = d.

[0013] Optionally, the organic layer is integrally formed.

[0014] On the other hand, the present application provides a display device, which includes a housing and the display panel described in any one of the above. The housing has an accommodation space, and the display panel is disposed in the accommodation space.

[0015] The present application provides a display panel and a display device. The display panel has a chip bonding area and includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group arranged in sequence in the chip bonding area. The display panel further includes an organic layer disposed in the chip bonding area. The organic layer includes a first boundary and a second boundary. The first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, where a ≥ 30 μm. The second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, where b ≥ 30 μm. The display panel and the display device provided by the present application can improve the problem of film layer peeling in the chip bonding area, thereby improving the problem of abnormal chip output signals caused by film layer peeling and improving the display quality. Description of the Drawings

[0016] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0017] Figure 1 It is a schematic plan view of the display area and the chip bonding area of the display panel provided in the first embodiment of the present application;

[0018] Figure 2 It is a schematic plan view of the electrical components and the organic layer in the chip bonding area provided in the first embodiment of the present application;

[0019] Figure 3 It is a schematic diagram of the film layer structure of the display panel provided in the first embodiment of the present application;

[0020] Figure 4 It is a simulation data diagram of the strain difference between the organic layer and the interlayer dielectric layer in the compressed and thermal expansion states provided in the first embodiment of the present application;

[0021] Figure 5 It is a schematic plan view of the electrical components and the organic layer in the chip bonding area provided in the second embodiment of the present application;

[0022] Figure 6 It is a schematic diagram of the film layer structure of the display panel provided in the second embodiment of the present application;

[0023] Figure 7 It is a schematic plan view of the electrical components and the organic layer in the chip bonding area provided in the third embodiment of the present application;

[0024] Figure 8 It is a schematic diagram of the film layer structure of the display panel provided in the third embodiment of the present application.

[0025] Explanation of reference numerals:

[0026] Display panel 01; Display area 10; Chip bonding area 20; Output terminal group 21; Multiplexer 22; Test terminal group 23; Input terminal group 24; dummy terminal group 25; Dummy terminal 251; Substrate 100; First conductive layer 110; Interlayer dielectric layer 120; Second conductive layer 130; Organic layer 140; First boundary 141; Second boundary 142; Third boundary 143; Fourth boundary 144; Third conductive layer 150; Passivation layer 160; Fourth conductive layer 170 Detailed implementation manners

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0028] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0029] Figure 1 It is a schematic plan view of the display area and the chip bonding area of the display panel provided in Embodiment 1 of the present application. Refer to Figure 1As shown in the figure, Embodiment 1 of the present application provides a display panel 01, which has a display area 10 and a chip bonding area 20. Among them, the display area 10 includes a plurality of data lines and a plurality of scan lines, and the positive projections of the data lines and the scan lines on the display area 10 are cross - arranged; the chip bonding area 20, also known as the bonding area, is provided with various electrical components, such as bonding terminals, test terminals, multiplexers, etc. The number of the same type of electrical components can be multiple, and multiple electrical components of the same type can form an electrical component group. Among them, the bonding terminal is electrically connected to the chip, the data line and / or the scan line of the display panel 01 through a bonding process. Exemplarily, the type of the bonding terminal can be an input terminal electrically connected to the chip, an output terminal electrically connected to the data line and / or the scan line, and the input terminal and the output terminal belong to different types of electrical components; the test terminal is used to be electrically connected to a test circuit during the manufacturing process of the display panel 01 to detect the display performance of the display panel 01; the multiplexer is used to implement a multiplexing function to simplify the circuit structure of the display panel 01.

[0030] Figure 2 It is a schematic plan view of the electrical components and the organic layer in the chip bonding area provided by Embodiment 1 of the present application; Figure 3 It is a schematic diagram of the film layer structure of the display panel provided by Embodiment 1 of the present application. Combining Figures 1-3 As shown in the figure, in some embodiments of the present application, the display panel 01 has a chip bonding area 20. The display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23, and an input terminal group 24 arranged in sequence in the chip bonding area 20. The display panel 01 further includes an organic layer 140 provided in the chip bonding area 20. The organic layer 140 includes a first boundary 141 and a second boundary 142. Among them, the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, and the distance between the first boundary 141 and the output terminal group 21 is a, a≥30μm; the second boundary 142 is located between the test terminal group 23 and the input terminal group 24, and the distance between the second boundary 142 and the input terminal group 24 is b, b≥30μm.

[0031] In the related art, during the bonding process, it is necessary to press the bonding terminal and / or other terminals. Since the terminal generally has a certain thickness, when being pressed, the terminal will deform, and the deformation will pull the film layer near the terminal, thereby causing a peeling phenomenon or a peeling trend between the film layers. Since the test environment of the double 85 experiment / HAST experiment is a high - temperature and high - humidity environment, it will further exacerbate the peeling degree between the film layers, resulting in abnormal chip output signals, causing vertical bright lines in the OLED display panel and affecting the display quality of the display panel 01.

[0032] The researchers of this application have found through a large number of experiments that the organic layer 140 is the key film layer among many film layers that is most likely to have peeling problems. In the display panel 01 provided by this application, since the distance between the first boundary 141 and the output terminal group 21 is not less than 30 μm, the distance between the first boundary 141 and the output terminals in the output terminal group 21 can be maintained above the minimum safety distance. Therefore, during the bonding process of the output terminal group 21, the peeling problem caused by the output terminals in the output terminal group 21 deforming under pressure and pulling the first boundary 141 can be improved, thereby reducing the probability of abnormal chip output signals and improving the display quality of the display panel 01; at the same time, since the distance between the second boundary 142 and the input terminal group 24 is not less than 30 μm, the distance between the second boundary 142 and the input terminals in the input terminal group 24 can be maintained above the minimum safety distance. Therefore, during the bonding process of the input terminal group 24, the peeling problem caused by the input terminals in the input terminal group 24 deforming under pressure and pulling the second boundary 142 can be improved, thereby reducing the probability of abnormal chip output signals and improving the display quality of the display panel 01.

[0033] Exemplarily, the arrangement direction of the output terminal group 21, the multiplexer 22, the test terminal group 23, and the input terminal group 24 is the first direction, and the first direction is parallel to the data line. Among them, the output terminal group 21 includes a plurality of output terminals, and the plurality of output terminals are arranged in sequence along the second direction; the test terminal group 23 includes a plurality of test terminals, and the test terminals are arranged in sequence along the second direction; the input terminal group 24 includes a plurality of input terminals, and the plurality of input terminals are arranged in sequence along the second direction, and the first direction and the second direction are cross - set in the orthographic projection of the chip bonding area 20.

[0034] In some embodiments of this application, no electrostatic protection circuit is provided between the output terminal group 21 and the input terminal group 24.

[0035] In the related art, an electrostatic protection circuit is often provided in the chip bonding area 20, and the layout area of the electrostatic protection circuit is relatively large, which compresses the distance between the terminals and the organic layer 140. In the display panel 01 provided by this application, since no electrostatic protection circuit is provided between the output terminal group 21 and the input terminal group 24, the layout area of other electrical components between the output terminal group 21 and the input terminal group 24 can be increased, and the degree of freedom in layout design is greatly improved, so that the distance between the first boundary 141 and the output terminal group 21 is not less than 30 μm, and the distance between the second boundary 142 and the input terminal group 24 is not less than 30 μm.

[0036] In some embodiments of the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is continuously provided.

[0037] In the display panel provided by the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is continuously provided, which can enhance the integrity and stability of the organic layer 140.

[0038] In some embodiments of the present application, a = b.

[0039] In the display panel 01 provided by the present application, a = b, that is, the distance between the first boundary 141 and the output terminal group 21 is equal to the distance between the second boundary 142 and the input terminal group 24, so as to improve the consistency of the film layer design of the display panel 01, which is beneficial to the improvement of production efficiency, and thus achieve the effect of reducing the production and manufacturing cost of the display panel 01.

[0040] In some embodiments of the present application, the display panel 01 includes a substrate 100, a first conductive layer 110, an interlayer dielectric layer 120, a second conductive layer 130, an organic layer 140, a third conductive layer 150, a passivation layer 160, and a fourth conductive layer 170 that are sequentially stacked in the chip bonding area 20.

[0041] Optionally, the substrate 100 may be a flexible substrate or a rigid substrate. The present application does not limit the material of the substrate 100, and its material may be an organic material or an inorganic material; the first conductive layer 110 is, for example, provided on the same layer as the gate layer of the display area 10, and the gate layer includes a gate; the second conductive layer 130 is, for example, provided on the same layer as the first source-drain layer of the display area 10, and the first source-drain layer includes a first source and a first drain; the third conductive layer 150 is, for example, provided on the same layer as the second source-drain layer of the display area 10, and the second source-drain layer includes a second source and a second drain.

[0042] In some embodiments of the present application, the organic layer 140 covers the multiplexer 22 to protect the components in the multiplexer 22; the organic layer 140 does not cover the test terminal, so as to facilitate the staff to test the display panel 01 through the test terminal during the preparation process of the display panel 01.

[0043] In some embodiments of the present application, the organic layer 140 is integrally formed.

[0044] In the related art, the organic layer 140 in the chip bonding region 20 has a double-layer structure, and the double-layer structure increases the thickness of the organic layer 140 and makes the structure more complex, increasing the peeling risk of the organic layer 140 in the bonding process and the expansion limit in the high-temperature and high-humidity environment created by the double 85 experiment / HAST experiment. In the display panel 01 provided by the present application, since the organic layer 140 is integrally formed, the organic layer 140 has a single-layer structure, thereby reducing the strain difference between the organic layer 140 and other film layers during the bonding process and the double 85 experiment / HAST experiment process.

[0045] Figure 4 This is a simulation data graph of the strain difference between the organic layer and the interlayer dielectric layer under compressive and thermal expansion states provided by Embodiment 1 of the present application. From Figure 4 It can be seen that under the compressive state during bonding, the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the double organic layer 140 is as high as 6.872E-04; while the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the single organic layer 140 is only 4.771E-04, and the strain difference is greatly reduced; under the thermal expansion state of the double 85 experiment / HAST experiment, the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the double organic layer 140 is as high as 7.149E-04; while the strain difference between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 with the single organic layer 140 is only 3.408E-04, and the strain difference is greatly reduced.

[0046] In some embodiments of the present application, the thickness of the organic layer 140 is less than or equal to 4 μm.

[0047] Specifically, in the related art, the thickness of each sub-film layer in the organic layer 140 in the chip bonding region 20 is more than 2 μm. Therefore, the thickness of the organic layer 140 with a double-layer structure is more than 4 μm. By thinning the thickness of the organic layer 140, the present application can further reduce the strain difference between the organic layer 140 and other film layers during the bonding process and the double 85 experiment / HAST experiment process.

[0048] On the other hand, the present application also provides a display device, which includes a housing and the display panel 01 described in any one of the above. Wherein, the housing has a receiving space, and the display panel 01 is disposed in the receiving space.

[0049] Embodiment 2

[0050] Figure 5 This is a schematic plan view of the electrical components and the organic layer in the chip bonding region provided by Embodiment 2 of the present application; Figure 6Schematic diagram of the film layer structure of the display panel provided in the second embodiment of the present application. In combination with Figure 1 , Figure 5 and Figure 6 as shown, the second embodiment of the present application provides a display panel 01 and a display device. The display panel 01 has a chip bonding area 20. The display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23, and an input terminal group 24 arranged in sequence in the chip bonding area 20. The display panel 01 further includes an organic layer 140 provided in the chip bonding area 20. The organic layer 140 includes a first boundary 141 and a second boundary 142. Among them, the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, and the distance between the first boundary 141 and the output terminal group 21 is a, a≥30μm; the second boundary 142 is located between the test terminal group 23 and the input terminal group 24, and the distance between the second boundary 142 and the input terminal group 24 is b, b≥30μm. The display device includes a housing and the display panel 01. Among them, the housing has an accommodating space, and the display panel 01 is disposed in the accommodating space.

[0051] It should be noted that the structures of the display panel 01 and the display device provided in the second embodiment of the present application are similar to the structures of the display panel 01 and the display device provided in the first embodiment of the present application. The same parts in the second embodiment of the present application will not be described in detail.

[0052] The difference is that in some embodiments of the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is intermittently provided. Among them, the display panel 01 further includes a dummy terminal group 25 provided in the chip bonding area 20. The dummy terminal group 25 is located between the multiplexer 22 and the test terminal group 23. The organic layer 140 includes a third boundary 143 and a fourth boundary 144. Among them, the third boundary 143 is located between the multiplexer 22 and the dummy terminal group 25, and the distance between the third boundary 143 and the dummy terminal group 25 is c; where c>m / 6, and m is the distance between the third boundary 143 and the first boundary 141; the fourth boundary 144 is located between the test terminal group 23 and the dummy terminal group 25, and the distance between the fourth boundary 144 and the test terminal group 23 is d, where d>n / 6, and n is the distance between the fourth boundary 144 and the second boundary 142.

[0053] In the related art, the function of the dummy terminal group 25 is to play an auxiliary support role during the bonding process. The researchers found that since the dummy terminal group 25 is located between the multiplexer 22 and the test terminal group 23, it is easier to pull the organic layer 140 near the dummy terminal group 25 during the bonding and pressing process, resulting in peeling problems of the organic layer 140 at the third boundary 143 and the fourth boundary 144.

[0054] This application makes a special design based on the special position of the dummy terminal group 25, so that the distance between the third boundary 143 and the dummy terminal group 25 is not less than one-sixth of the distance between the third boundary 143 and the first boundary 141, and the distance between the fourth boundary 144 and the dummy terminal group 25 is not less than one-sixth of the distance between the fourth boundary 144 and the second boundary 142. This can ensure that the distances between the third boundary 143, the fourth boundary 144 and the dummy terminal 251 in the dummy terminal group 25 are all above the safe distance. Therefore, during the bonding process of the output terminal group 21 and the input terminal group 24, it can improve the peeling problem caused by the deformation of the dummy terminal 251 in the dummy terminal group 25 under pressure and pulling the third boundary 143 and the fourth boundary 144, thereby reducing the probability of abnormal chip output signals and improving the display quality of the display panel 01.

[0055] In some embodiments of this application, the dummy terminal group 25 includes a plurality of dummy terminals 251, and the plurality of dummy terminals 251 form a plurality of dummy terminal rows, where c = d ≥ 50 μm, and both m / 6 and n / 6 are less than 50 μm.

[0056] In the display panel 01 provided by this application, the plurality of dummy terminals 251 form a plurality of dummy terminal rows. During the bonding process of the output terminals, the dummy terminal row closest to the output terminal group 21 can play an auxiliary support role; during the bonding process of the input terminals, the dummy terminal row closest to the input terminal group 24 can play an auxiliary support role.

[0057] In the display panel 01 provided by this application, since c = d ≥ 50 μm, the distance between the third boundary and the dummy terminal group and the distance d between the fourth boundary and the test terminal group are both much larger than the safe distance of 30 μm in the first embodiment. Therefore, it can improve the peeling problem caused by the greater pressure and larger deformation of the dummy terminal group, and improve the stability of the display panel.

[0058] Moreover, since c = d, that is, the distance between the third boundary 143 and the output terminal group 21 is equal to the distance between the fourth boundary 144 and the input terminal group 24, the consistency of the film layer design of the display panel 01 can be improved, which is beneficial to the improvement of production efficiency, and thus the production and manufacturing cost of the display panel 01 can be reduced.

[0059] In some embodiments of the present application, the organic layer 140 is not provided between any two adjacent dummy terminal rows.

[0060] In the display panel 01 provided by the present application, since the organic layer 140 is not provided between any two adjacent dummy terminal rows, the probability of film layer peeling when the area between two adjacent dummy terminal rows is pressurized and thermally expanded can be greatly reduced.

[0061] Furthermore, a = b = c = d.

[0062] In the display panel 01 provided by the present application, a = b = c = d, that is, the distances between the first boundary 141 and the output terminal group 21, the second boundary 142 and the input terminal group 24, the third boundary 143 and the dummy terminal group 25, and the fourth boundary 144 and the test terminal group 23 are all equal, so that the consistency of the film layer design of the display panel 01 can be improved, which is beneficial to the improvement of production efficiency, and thus the production and manufacturing cost of the display panel 01 can be reduced.

[0063] Embodiment III

[0064] Figure 7 It is a schematic plan view of electrical components and an organic layer in a chip bonding area provided in Embodiment III of the present application; Figure 8 It is a schematic diagram of a film layer structure of a display panel provided in Embodiment III of the present application. Combining Figure 1 、 Figure 7 and Figure 8As shown in the figure, Embodiment 3 of the present application provides a display panel 01 and a display device. The display panel 01 has a chip bonding area 20. The display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23, and an input terminal group 24 arranged in sequence in the chip bonding area 20. The display panel 01 further includes an organic layer 140 provided in the chip bonding area 20. The organic layer 140 includes a first boundary 141 and a second boundary 142. Among them, the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, and the distance between the first boundary 141 and the output terminal group 21 is a, and a≥30μm; the second boundary 142 is located between the test terminal group 23 and the input terminal group 24, and the distance between the second boundary 142 and the input terminal group 24 is b, and b≥30μm. The display device includes a housing and the display panel 01. Among them, the housing has an accommodation space, and the display panel 01 is disposed in the accommodation space.

[0065] It should be noted that the structures of the display panel 01 and the display device provided in Embodiment 3 of the present application are similar to the structures of the display panel 01 and the display device provided in Embodiment 2 of the present application. The same parts in Embodiment 3 of the present application will not be described in detail.

[0066] The difference is that in some embodiments of the present application, the dummy terminal group 25 includes a plurality of dummy terminals 251, and the plurality of dummy terminals 251 form a dummy terminal row, where c = d≥80μm.

[0067] In the display panel 01 provided by the present application, since the plurality of dummy terminals 251 form a dummy terminal row, during the bonding process of the output terminal and the input terminal, the dummy terminal row needs to be pressed to play an auxiliary support role. By further increasing the distance between the third boundary 143 and the dummy terminal group 25 and further increasing the distance between the fourth boundary 144 and the dummy terminal group 25, the present application can improve the problem of increased risk of film layer peeling caused by the increased deformation amount of the dummy terminal row due to multiple compressions.

[0068] Moreover, since the plurality of dummy terminals 251 form a dummy terminal row, the layout area of the dummy terminal group 25 can be reduced. Thus, the distance between the third boundary 143 and the dummy terminal group 25 can be further increased, and the distance between the fourth boundary 144 and the dummy terminal group 25 can be further increased. Thereby, the peeling problem caused by the deformation of the dummy terminal 251 in the dummy terminal group 25 pulling the first boundary 141 can be further reduced, and the probability of abnormal chip output signals can be reduced, and the display quality of the display panel 01 can be improved.

[0069] In addition, since c = d, that is, the distance between the third boundary 143 and the output terminal group 21 is equal to the distance between the fourth boundary 144 and the input terminal group 24, the consistency of the film layer design of the display panel 01 can be improved, which is beneficial to the improvement of production efficiency, and thus the production and manufacturing cost of the display panel 01 can be reduced.

[0070] Furthermore, a = b = c = d.

[0071] In the display panel 01 provided by the present application, a = b = c = d, that is, the distance between the first boundary 141 and the output terminal group 21, the distance between the second boundary 142 and the input terminal group 24, the distance between the third boundary 143 and the dummy terminal group 25, and the distance between the fourth boundary 144 and the test terminal group 23 are all equal. Therefore, the consistency of the film layer design of the display panel 01 can be improved, which is beneficial to the improvement of production efficiency, and thus the production and manufacturing cost of the display panel 01 can be reduced.

[0072] In summary, the present application provides a display panel and a display device. The display panel has a chip bonding area. The display panel includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group arranged in sequence in the chip bonding area. The display panel further includes an organic layer provided in the chip bonding area. The organic layer includes a first boundary and a second boundary. Among them, the first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, a ≥ 30 μm. The second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, b ≥ 30 μm. The display panel and the display device provided by the present application can improve the film layer peeling problem in the chip bonding area, thereby improving the problem of abnormal chip output signals caused by film layer peeling and improving the display quality.

[0073] The above has introduced in detail a display panel and a display device provided by an embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, the display panel has a chip bonding area, and the display panel includes an output terminal group, a multiplexer, a dummy terminal group, a test terminal group, and an input terminal group arranged in sequence in the chip bonding area; the display panel further includes an organic layer provided in the chip bonding area, and the organic layer includes a first boundary, a third boundary, a fourth boundary, and a second boundary arranged in sequence; the first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, where a≥30μm; the second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, where b≥30μm; the third boundary is located between the multiplexer and the dummy terminal group, and the distance between the third boundary and the dummy terminal group is c, where c>m / 6, and m is the distance between the third boundary and the first boundary; and / or, the fourth boundary is located between the test terminal group and the dummy terminal group, and the distance between the fourth boundary and the test terminal group is d, where d>n / 6, and n is the distance between the fourth boundary and the second boundary.

2. The display panel according to claim 1, characterized in that, no electrostatic protection circuit is provided between the output terminal group and the input terminal group.

3. The display panel according to claim 1, characterized in that, the organic layer between the first boundary and the third boundary is continuous and covers the multiplexer.

4. The display panel according to claim 1, characterized in that, the organic layer between the fourth boundary and the second boundary exposes the test terminal group.

5. The display panel according to claim 1, characterized in that, the dummy terminal group includes a plurality of dummy terminals, and the plurality of dummy terminals form a plurality of dummy terminal rows, where c = d≥50μm.

6. The display panel according to claim 5, characterized in that, no organic layer is provided between any two adjacent dummy terminal rows.

7. The display panel according to claim 1, characterized in that, the dummy terminal group includes a plurality of dummy terminals, and the plurality of dummy terminals form a single dummy terminal row, where c = d≥80μm.

8. The display panel according to claim 1, characterized in that, a = b = c = d.

9. The display panel according to claim 1, characterized in that, the organic layer is integrally formed.

10. A display device, characterized in that, the display device includes: a housing and the display panel according to any one of claims 1-9, where the housing has a receiving space, and the display panel is disposed in the receiving space.

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