Array substrate, manufacturing method thereof and touch display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a touch display panel. The array substrate comprises a substrate, a scan line, a touch signal line and a plurality of touch electrodes arranged in sequence along a direction away from the substrate. A first insulating layer and an etching blocking layer are arranged between the scan line and the touch signal line. The etching blocking layer is arranged between the first insulating layer and the touch signal line. A second insulating layer is arranged between the touch signal line and the touch electrodes. A first contact hole penetrating through the second insulating layer is arranged in an intersection area between the scan line and the touch signal line. The touch electrodes are conductively connected with the touch signal line through the first contact hole. The etching blocking layer corresponds to the first contact hole. A projection area of the etching blocking layer on the substrate completely covers a projection area of the first contact hole on the substrate. The etching blocking layer for blocking the contact hole is arranged in the intersection area between the scan line and the touch signal line, so that the scan line is prevented from being continuously etched downward when the contact hole is etched.

Description

Technical Field

[0001] This invention relates to the field of touch display technology, and in particular to an array substrate and its manufacturing method, and a touch display panel. Background Technology

[0002] Liquid crystal display (LCD) panels have advantages such as high image quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, making them dominant in the flat panel display field. With the rapid development of display technology, touch display panels have become widely accepted and used, such as in smartphones and tablets. Touch display panels utilize embedded touch technology to combine the touch panel and LCD panel into one unit, embedding the touch panel functionality within the LCD panel, thus enabling the LCD panel to simultaneously display and sense touch input.

[0003] Depending on how the touch sensing layer is positioned within the display panel, touch display panels are categorized into add-on, in-cell, and on-cell structures. In-cell touchscreens integrate touch functionality into the display screen, effectively reducing the overall thickness of the display and simplifying the manufacturing process, resulting in thinner, lighter products with lower production costs, making them widely popular.

[0004] Currently, for in-cell touchscreens, the touchscreen structure is typically mounted directly on the array substrate. This mainly involves reusing structural components used for transmitting display signals as touch electrodes within the array substrate. A common approach is to reuse a common electrode as a touch electrode, and then control the common electrode to transmit both common and touch signals. The common electrode needs to be electrically connected to the touch signal line within the display area via contact holes, while the touch signal line needs to be electrically connected to the peripheral traces in the non-display area via contact holes and bridging electrodes, thus guiding the signal to the bonding area. Because the touch signal line and the peripheral traces are located on different layers, the aperture depths in the display and non-display areas differ; furthermore, the etching rate of the ordinary insulating layer (PV) is twice that of the gate insulating layer (GI) (PV is approximately...). GI is approximately Furthermore, the size or position of the opening is not precise enough, meaning the opening area is partially misaligned with the touch signal line. This can lead to the scanning line being etched downwards at the contact hole of the touch signal line during the opening process, causing a short circuit between the touch signal line and the scanning line. Summary of the Invention

[0005] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide an array substrate and its manufacturing method, and a touch display panel, so as to solve the problem that short circuits easily occur in the touch signal lines and scan lines in the prior art.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] This invention provides an array substrate, including a substrate and scan lines, touch signal lines, and a plurality of touch electrodes arranged sequentially along a direction away from the substrate. A first insulating layer and an etch barrier layer are provided between the scan lines and the touch signal lines. The etch barrier layer is located between the first insulating layer and the touch signal lines. A second insulating layer is provided between the touch signal lines and the touch electrodes. A first contact hole penetrating the second insulating layer is provided in the intersection area between the scan lines and the touch signal lines. The touch electrodes are electrically connected to the touch signal lines through the first contact hole. The etch barrier layer corresponds to the first contact hole, and the projection area of ​​the etch barrier layer on the substrate completely covers the projection area of ​​the first contact hole on the substrate.

[0008] Furthermore, the array substrate also includes pixel electrodes, which cooperate with the touch signal lines, and the etch barrier layer is located on the same layer as the pixel electrodes and is insulated from them;

[0009] And / or, the array substrate further includes data lines, wherein the touch signal lines are located on the same layer as the data lines and are insulated from each other.

[0010] Furthermore, the array substrate also includes peripheral traces and bridging electrodes located in the non-display area. One end of the bridging electrode is electrically connected to the touch signal line, and the other end of the bridging electrode is electrically connected to the peripheral traces. The bridging electrode and the touch electrode are located on the same layer.

[0011] Furthermore, the peripheral traces and the scan lines are located on the same layer and are insulated from each other; or, the peripheral traces are located below the scan lines and are separated from each other by an insulating layer.

[0012] This application also provides a method for manufacturing an array substrate, for manufacturing the array substrate as described above, the method comprising:

[0013] A substrate is provided; patterned scan lines and gates are formed on the substrate, the gates being electrically connected to the scan lines;

[0014] A first insulating layer, an etch barrier layer, and a touch signal line are sequentially formed above the scan line and the gate, wherein the etch barrier layer is located in the intersection area between the scan line and the touch signal line;

[0015] A second insulating layer is formed above the touch signal line to cover the touch signal line. The second insulating layer is etched to form a first contact hole corresponding to the etch barrier layer. At least the touch signal line is exposed from the first contact hole. The projection area of ​​the etch barrier layer on the substrate completely covers the projection area of ​​the first contact hole on the substrate.

[0016] Multiple touch electrodes are formed above the second insulating layer, and the touch electrodes are electrically connected to the touch signal line through the first contact hole.

[0017] Furthermore, the array substrate also includes peripheral traces and bridging electrodes located in the non-display area, and the method for manufacturing the peripheral traces and the bridging electrodes includes:

[0018] A first metal layer is formed above the substrate, and the first metal layer is etched to form the scan line, the gate, and the peripheral traces. The first insulating layer covers the scan line, the gate, and the peripheral traces.

[0019] While etching the second insulating layer, the first insulating layer located in the non-display area is also etched, and a second contact hole is formed at the end of the touch signal line and a third contact hole is formed at the peripheral trace position.

[0020] A second transparent conductive layer is formed above the second insulating layer. The second transparent conductive layer is etched to form the patterned touch electrode and the bridging electrode. One end of the bridging electrode is electrically connected to the touch signal line through the second contact hole, and the other end of the bridging electrode is electrically connected to the peripheral trace through the third contact hole.

[0021] Furthermore, the array substrate also includes peripheral traces and bridging electrodes located in the non-display area, and the method for manufacturing the peripheral traces and the bridging electrodes includes:

[0022] A first metal layer is formed on top of the substrate, and the first metal layer is etched to form the peripheral traces;

[0023] An insulating layer is formed on top of the substrate to cover the peripheral traces;

[0024] A second metal layer is formed above the insulating layer, and the second metal layer is etched to form the scan line and the gate. The first insulating layer covers the scan line and the gate.

[0025] When etching the second insulating layer, the first insulating layer and the insulating layer located in the non-display area are etched simultaneously, and a second contact hole is formed at the end of the touch signal line and a third contact hole is formed at the peripheral trace position.

[0026] A second transparent conductive layer is formed above the second insulating layer. The second transparent conductive layer is etched to form the patterned touch electrode and the bridging electrode. One end of the bridging electrode is electrically connected to the touch signal line through the second contact hole, and the other end of the bridging electrode is electrically connected to the peripheral trace through the third contact hole.

[0027] Furthermore, the array substrate further includes a pixel electrode, a data line, a source electrode, a drain electrode, and an active layer, and the manufacturing method of the pixel electrode, the data line, the source electrode, the drain electrode, and the active layer includes:

[0028] The active layer is formed above the first insulating layer;

[0029] A first transparent conductive layer is formed over the first insulating layer to cover the active layer. The first transparent conductive layer is etched to form a patterned etch barrier layer and a pixel electrode. The etch barrier layer is insulated from the pixel electrode.

[0030] A third metal layer is formed above the first transparent conductive layer. The third metal layer is etched to form patterned data lines, the source electrode, the drain electrode, and the touch signal line. The data lines are conductively connected to the source electrode, the drain electrode is conductively connected to the pixel electrode, and the source electrode and the drain electrode are connected through the active layer.

[0031] This application also provides a touch display panel, including an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is the array substrate described above.

[0032] This application also provides a touch display device, including a backlight module and a touch display panel, characterized in that the touch display panel is a touch display panel as described above, and the backlight module is located on the side of the array substrate away from the color filter substrate.

[0033] The beneficial effects of this invention are as follows: by setting an etch barrier layer for blocking the contact hole in the intersection area between the scan line and the touch signal line, the projection area of ​​the etch barrier layer on the substrate completely covers the projection area of ​​the contact hole on the substrate. Thus, when etching the contact hole, the etch barrier layer can prevent further etching and exposure of the scan line, so as to avoid short circuit between the touch signal line and the scan line after the touch electrode is formed, which would lead to abnormal screen display. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the planar structure of the touch electrode in Embodiment 1 of the present invention;

[0035] Figure 2 This is a schematic diagram of the planar structure of the array substrate in Embodiment 1 of the present invention;

[0036] Figure 3 This is a schematic diagram of the planar structure at the edge of the array substrate in Embodiment 1 of the present invention;

[0037] Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure at point AA;

[0038] Figure 5 yes Figure 3 Schematic diagram of the cross-sectional structure at point BB;

[0039] Figure 6 yes Figure 3 Schematic diagram of the cross-sectional structure at point C;

[0040] Figure 7 This is a flowchart of the method for fabricating the array substrate in Embodiment 1 of the present invention;

[0041] Figure 8a-8h2 This is a schematic diagram of the process structure of the array substrate fabrication method in Embodiment 1 of the present invention;

[0042] Figure 9 It is along the second embodiment of the present invention Figure 3 Schematic diagram of the cross-sectional structure at point C;

[0043] Figure 10 This is one of the structural schematic diagrams of the touch display device in this invention;

[0044] Figure 11 This is the second schematic diagram of the touch display device in this invention. Detailed Implementation

[0045] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the array substrate and its manufacturing method, and the touch display panel proposed according to the present invention:

[0046] [Example 1]

[0047] Figure 1 This is a schematic diagram of the planar structure of the touch electrode in Embodiment 1 of the present invention. Figure 2 This is a schematic diagram of the planar structure of the array substrate in Embodiment 1 of the present invention. Figure 3 This is a schematic diagram of the planar structure at the edge of the array substrate in Embodiment 1 of the present invention. Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure at point AA. Figure 5 yes Figure 3 Schematic diagram of the cross-sectional structure at point BB. Figure 6 yes Figure 3 A schematic diagram of the cross-sectional structure at point CC.

[0048] like Figures 1 to 6 As shown, an array substrate provided in Embodiment 1 of the present invention includes a substrate 20 and scan lines 221, touch signal lines 254, and a plurality of touch electrodes 261 sequentially arranged along a direction away from the substrate 20. Please refer to... Figure 4 A first insulating layer 202 and an etch barrier layer 242 are provided between the scan line 221 and the touch signal line 254, with the etch barrier layer 242 located between the first insulating layer 202 and the touch signal line 254. A second insulating layer 203 is provided between the touch signal line 254 and the touch electrode 261. A first contact hole H1 penetrating the second insulating layer 203 is provided in the intersection area between the scan line 221 and the touch signal line 254, and the touch electrode 261 is electrically connected to the touch signal line 254 through the first contact hole H1. The etch barrier layer 242 corresponds to the first contact hole H1, and the projection area of ​​the etch barrier layer 242 on the substrate 20 completely covers the projection area of ​​the first contact hole H1 on the substrate 20.

[0049] This application provides an etch barrier layer 242 for blocking the first contact hole H1 in the intersection area between the scan line 221 and the touch signal line 254. The projection area of ​​the etch barrier layer 242 on the substrate 20 completely covers the projection area of ​​the first contact hole H1 on the substrate 20. Thus, when etching the first contact hole H1, the etch barrier layer 242 can prevent further etching and exposure of the scan line 221. This avoids short circuits between the touch signal line 254 and the scan line 221 after the touch electrode 261 is formed, thus preventing screen abnormalities.

[0050] Furthermore, the array substrate also includes a gate 222, which is electrically connected to the scan line 221. In this embodiment, a portion of the scan line 221 serves as the gate 222, meaning the gate 222 and the scan line 221 are located on the same straight line, thereby increasing the pixel aperture ratio. Of course, in other embodiments, the gate 222 may not be on the same straight line as the scan line 221, meaning the gate 222 may protrude from the scan line 221; this is not a limitation.

[0051] Furthermore, the array substrate also includes a pixel electrode 241, which cooperates with the touch electrode 261. That is, the touch electrode 261 can be reused as a common electrode to apply a common signal in conjunction with the pixel electrode 241. The touch electrode 261 is located above the pixel electrode 241, and the touch electrode 261 has a slit in the area corresponding to the pixel electrode 241. The pixel electrode 241 is a block electrode, thereby realizing fringe field switching (FFS).

[0052] The etch barrier layer 242 and the pixel electrode 241 are located on the same layer and are insulated from each other. That is, the etch barrier layer 242 and the pixel electrode 241 are made of the same transparent metal layer and are produced by the same etching process. In this way, the etch barrier layer 242 and the pixel electrode 241 are etched from the same transparent metal layer, which not only saves manufacturing process, but also prevents the aperture ratio from being affected by the large size of the etch barrier layer 242.

[0053] Furthermore, please refer to the following: Figure 3 and Figure 4 The array substrate also includes a data line 251, a source electrode 252, a drain electrode 253, and an active layer 23. The active layer 23 is disposed above the first insulating layer 202 and corresponds to the gate electrode 222. The data line 251 is electrically connected to the source electrode 252, and the drain electrode 253 is electrically connected to the pixel electrode 241. The source electrode 252 and the drain electrode 253 are connected through the active layer 23, and a channel is formed between the source electrode 252 and the drain electrode 253 above the active layer 23. The touch signal line 254 runs parallel to the data line 251. The touch signal line 254, the data line 251, the source electrode 252, and the drain electrode 253 are located on the same layer and are insulated from each other. That is, the data line 251, the source electrode 252, the drain electrode 253, and the touch signal line 254 are made of the same metal layer and are formed by the same etching process, thereby further saving manufacturing processes.

[0054] In this design, data lines 251 and scan lines 221 intersect to define multiple pixel units SP. Each pixel unit SP has a pixel electrode 241 and a thin-film transistor 1. The pixel electrode 241 is electrically connected to the data line 251 of the adjacent thin-film transistor 1 through the thin-film transistor 1. The thin-film transistor 1 consists of a gate 222, an active layer 23, a source 252, and a drain 253. One touch electrode 261 can correspond to multiple pixel units SP, such as... Figure 2 As shown, one touch electrode 261 can correspond to 9 pixel units SP. Of course, in practical applications, it can also be set according to actual needs.

[0055] Furthermore, the array substrate also includes peripheral traces 211 and bridging electrodes 262 located in the non-display area. One end of the bridging electrode 262 is electrically connected to the touch signal line 254, and the other end of the bridging electrode 262 is electrically connected to the peripheral traces 211. The bridging electrode 262 and the touch electrode 261 are located on the same layer, thereby saving manufacturing processes. The touch signal from the touch driver chip is transmitted to the bonding area of ​​the array substrate through the circuit board, and then sequentially transmitted to the corresponding touch electrode 261 through the peripheral traces 211, the bridging electrode 262, and the touch signal line 254 to realize the touch function.

[0056] In this embodiment, the peripheral traces 211 are located below the scan lines 221 and are spaced apart from each other by the insulating spacer layer 201. For example... Figure 6 As shown, after forming peripheral traces 211 on substrate 20, scan lines 221 and gate 222 are fabricated on insulating spacer layer 201 covering peripheral traces 211. Since scan lines 221 and data lines 251 both need to be led to bonding areas through other signal traces in non-display areas, placing peripheral traces 211 and scan lines 221 on different layers can reduce the design difficulty of scan lines 221 and peripheral traces 211, and reduce the bezel of the touch display panel. A second contact hole H2 is formed at the end of touch signal line 254, and a third contact hole H3 is formed at the location of peripheral trace 211. The second contact hole H2 penetrates the second insulating layer 203, and the third contact hole H3 penetrates the second insulating layer 203, the first insulating layer 202, and the insulating spacer layer 201. The depths of the first contact hole H1 and the second contact hole H2 are approximately... The depth of the third contact hole H3 is The thickness of the second insulating layer 203 is approximately The thicknesses of the insulating spacer layer 201 and the first insulating layer 202 are approximately

[0057] By providing an etch stop layer 242 to block the first contact hole H1 at the intersection of the scan line 221 and the touch signal line 254, the first contact hole H1 in the display area can be fabricated together with the second contact hole H2 and the third contact hole H3 in the non-display area using the same etching process, thus saving fabrication steps. Specifically, the etch stop layer 242 can be provided in the area of ​​the second contact hole H2 to prevent further etching and exposure of the scan line 221 in the non-display area. Alternatively, the etch stop layer 242 may not be provided in the area of ​​the second contact hole H2, because there are some invalid pixels near the non-display area, and the scan lines 221 corresponding to those invalid pixels have no scanning function.

[0058] Furthermore, some of the bridging electrodes 262 can be directly electrically connected to some of the touch electrodes 261, because some of the touch electrodes 261 need to be directly electrically connected to the touch signal line 254 at the edge of the display area.

[0059] Figure 7 This is a flowchart of the method for fabricating the array substrate in Embodiment 1 of the present invention. Figure 8a-8h2 This is a schematic diagram of the process structure for fabricating the array substrate in Embodiment 1 of the present invention. Figures 7-8h2 This application also provides a method for manufacturing an array substrate, used to manufacture the array substrate as described above. A schematic diagram of the fabrication process at point AA in the display area can be found here. Figure 8a-8h2 A schematic diagram of the manufacturing process for the second contact hole H2. The manufacturing method includes:

[0060] Step S1: As Figure 7 and Figure 8a As shown, a substrate 20 is provided. The substrate 20 may be made of materials such as glass, quartz, silicon, acrylic, or polycarbonate. The substrate 20 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or combinations thereof.

[0061] Step S2: A first metal layer 21 is formed above the substrate 20. The first metal layer 21 is etched to form peripheral wiring 211. An insulating spacer layer 201 is formed above the substrate 20, covering the peripheral wiring 211. The insulating spacer layer 201 is a gate insulating layer. Specifically, the first metal layer 21 is directly disposed on the upper surface of the substrate 20, and the first metal layer 21 is etched using a first mask process. The first metal layer 21 forms patterned peripheral wiring 211 in the non-display area. Of course, the first metal layer 21 can also form signal wiring for transmitting signals to the scan line 221 and the data line 251 in the non-display area. The first metal layer 21 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or combinations of the above metals such as Al / Mo, Cu / Mo, etc. The insulating spacer layer 201 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0062] Step S3: As Figure 7 , Figure 8b1 and Figure 8b2As shown, a second metal layer 22 is formed above the insulating spacer layer 201. The second metal layer 22 is etched to form scan lines 221 and gates 222. A first insulating layer 202 is formed above the scan lines 221 and gates 222, covering them. Specifically, the second metal layer 22 is directly disposed on the upper surface of the insulating spacer layer 201, and a second masking process is used to etch the second metal layer 22, forming patterned scan lines 221 and gates 222. The gates 222 are electrically connected to the scan lines 221. The second metal layer 22 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of these metals such as Al / Mo or Cu / Mo. The first insulating layer 202 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0063] Since both the scan line 221 and the data line 251 need to be led to the bonding area through other signal traces in the non-display area, the peripheral trace 211 and the scan line 221 are etched by different first metal layers 21 and second metal layers 22, respectively. This can reduce the design difficulty of the scan line 221 and the peripheral trace 211, as well as reduce the bezel of the touch display panel.

[0064] Step S4: As Figure 7 , Figure 8c , Figure 8d1 and Figure 8d2 As shown, an active layer 23 is formed above the first insulating layer 202; and a first transparent conductive layer 24 covers the active layer 23. The first transparent conductive layer 24 is etched to form a patterned etch barrier layer 242 and a pixel electrode 241. The etch barrier layer 242 and the pixel electrode 241 are mutually insulated. Specifically, as shown... Figure 8c As shown, a semiconductor layer is covered on the upper surface of the first insulating layer 202. A third masking process is used to etch the semiconductor layer, forming a patterned active layer 23. The active layer 23 is located above the first insulating layer 202 and corresponds to the gate 222. Figure 8d1 and Figure 8d2As shown, the first transparent conductive layer 24 is directly disposed on the upper surface of the first insulating layer 202 and covers the active layer 23. A fourth masking process is used to etch the first transparent conductive layer 24, forming a patterned pixel electrode 241 and an etch barrier layer 242. The first transparent conductive layer 24 is made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO). The semiconductor layer is made of amorphous silicon (a-Si) or doped amorphous silicon (N+a-Si). By etching the etch barrier layer 242 and the pixel electrode 241 from the same transparent metal layer, not only are fabrication processes saved, but the transparent etch barrier layer 242 also avoids affecting the aperture ratio due to its large size.

[0065] Step S5: As Figure 7 , Figure 8e1 , Figure 8e2 , Figure 8f1 and Figure 8f2 As shown, a third metal layer 25 is formed above the first transparent conductive layer 24. The third metal layer 25 is etched to form patterned data lines 251, source 252, drain 253, and touch signal lines 254; and a second insulating layer 203 covers the third metal layer 25. Specifically, as... Figure 8e1 and Figure 8e2 As shown, the third metal layer 25 is directly disposed on the upper surface of the first insulating layer 202 and covers the active layer 23, pixel electrode 241, and etch stop layer 242. The third metal layer 25 is etched using a fifth mask process to form patterned data lines 251, source electrode 252, drain electrode 253, and touch signal lines 254. The touch signal lines 254 are parallel to the data lines 251. The data lines 251 are electrically connected to the source electrode 252, and the drain electrode 253 is electrically connected to the pixel electrode 241. The source electrode 252 and drain electrode 253 are connected through the active layer 23, forming a channel between them above the active layer 23. By fabricating the data lines 251, source electrode 252, drain electrode 253, and touch signal lines 254 from the same metal layer using the same etching process, manufacturing processes are further simplified. The etch barrier layer 242 is located in the intersection area between the scan line 221 and the touch signal line 254. The third metal layer 25 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo. The second insulating layer 203 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0066] Data lines 251 and scan lines 221 intersect to define multiple pixel units SP. Each pixel unit SP has a pixel electrode 241 and a thin-film transistor 1. The pixel electrode 241 is electrically connected to the data line 251 of the adjacent thin-film transistor 1 through the thin-film transistor 1. The thin-film transistor 1 consists of a gate 222, an active layer 23, a source 252, and a drain 253. One touch electrode 261 can correspond to multiple pixel units SP, such as... Figure 2 As shown, one touch electrode 261 can correspond to 9 pixel units SP. Of course, in practical applications, it can also be set according to actual needs.

[0067] Step S6: As Figure 7 and Figure 8g As shown, the insulating spacer layer 201, the first insulating layer 202, and the second insulating layer 203 are simultaneously etched to form the first contact hole H1 corresponding to the etch barrier layer 242. Figure 3 and Figure 4 The system includes a second contact hole H2 corresponding to the end position of the touch signal line 254 and a third contact hole H3 corresponding to the position of the peripheral trace 211. Specifically, the insulating spacer layer 201, the first insulating layer 202, and the second insulating layer 203 are simultaneously etched using a sixth mask process. The first contact hole H1 and the second contact hole H2 are formed on the second insulating layer 203, penetrating the second insulating layer 203 so that at least the touch signal line 254 is exposed from the first contact hole H1. The third contact hole H3 is formed together on the insulating spacer layer 201, the first insulating layer 202, and the second insulating layer 203, penetrating the insulating spacer layer 201, the first insulating layer 202, and the second insulating layer 203 to expose the peripheral trace 211. The depths of the first contact hole H1 and the second contact hole H2 are approximately... The depth of the third contact hole H3 is The thickness of the second insulating layer 203 is approximately The thicknesses of the insulating spacer layer 201 and the first insulating layer 202 are approximately

[0068] The etch barrier layer 242, when projected onto the substrate 20, completely covers the projection area of ​​the first contact hole H1 onto the substrate 20. Due to the etch barrier layer 242, further etching down to the first contact hole H1 and the second contact hole H2 prevents the scan lines 221 in the non-display area from being exposed. Figure 4 and Figure 8gAs can be seen, the edges of the touch signal lines 254 have been etched out of the first contact hole H1 and the second contact hole H2. Without the obstruction of the etching barrier layer 242, the first contact hole H1 and the second contact hole H2 would continue to be etched downwards, causing the scan lines 221 to be exposed. Of course, the etching barrier layer 242 can also be set in a different area of ​​the second contact hole H2, because there are some invalid pixels near the non-display area, and the scan lines 221 corresponding to those invalid pixels have no scanning function. By setting the etching barrier layer 242 to block the first contact hole H1 and the second contact hole H2 in the intersection area between the scan lines 221 and the touch signal lines 254, the first contact hole H1 in the display area can be made together with the second contact hole H2 and the third contact hole H3 in the non-display area using the same etching process, thus saving manufacturing processes.

[0069] Step S7: As Figure 7 , Figure 8h1 and Figure 8h2 As shown, a second transparent conductive layer 26 is formed above the second insulating layer 203. The second transparent conductive layer 26 is etched to form patterned touch electrodes 261 and bridging electrodes 262. The touch electrodes 261 are electrically connected to the touch signal line 254 through the first contact hole H1. One end of the bridging electrode 262 is electrically connected to the touch signal line 254 through the second contact hole H2, and the other end of the bridging electrode 262 is electrically connected to the peripheral trace 211 through the third contact hole H3. Specifically, the second transparent conductive layer 26 is directly disposed on the upper surface of the second insulating layer 203. The second transparent conductive layer 26 extends into the first contact hole H1, the second contact hole H2, and the third contact hole H3. The second transparent conductive layer 26 is etched using a seventh mask process to form patterned touch electrodes 261 and bridging electrodes 262. The touch electrode 261 not only has touch functionality but can also cooperate with the pixel electrode 241. That is, the touch electrode 261 can be reused as a common electrode to apply a common signal and cooperate with the pixel electrode 241. The touch electrode 261 is located above the pixel electrode 241, and the touch electrode 261 has a slit in the area corresponding to the pixel electrode 241. The pixel electrode 241 is a block electrode, thereby realizing fringe field switching (FFS). The first transparent conductive layer 24 is made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0070] Furthermore, some of the bridging electrodes 262 can be directly electrically connected to some of the touch electrodes 261, because some of the touch electrodes 261 need to be directly electrically connected to the touch signal line 254 at the edge of the display area.

[0071] [Example 2]

[0072] Figure 9 It is along the second embodiment of the present invention Figure 3 A schematic diagram of the cross-sectional structure at point CC. (See diagram below.) Figure 9 As shown, the array substrate and its manufacturing method provided in Embodiment 2 of the present invention are the same as those in Embodiment 1. Figures 3 to 5 The array substrate and its manufacturing method are basically the same as those in this embodiment, except that:

[0073] The peripheral trace 211 and the scan line 221 are located on the same layer and are insulated from each other. By placing the peripheral trace 211 and the scan line 221 on the same layer, they can be etched together using the same metal film layer, thus saving manufacturing processes. The disadvantage is that since both the scan line 221 and the data line 251 need to be led to the bonding area through other signal traces in the non-display area, placing the peripheral trace 211 and the scan line 221 on the same layer increases the design complexity and the bezel of the touch display panel, but this implementation method is not excluded.

[0074] This embodiment also provides a method for manufacturing an array substrate, used to manufacture the array substrate described above. The manufacturing method includes:

[0075] Step S1: Provide substrate 20. Substrate 20 may be made of materials such as glass, quartz, silicon, acrylic, or polycarbonate. Substrate 20 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET), or combinations thereof.

[0076] Step S2: A first metal layer 21 is formed above the substrate 20. The first metal layer 21 is etched to form scan lines 221, gates 222, and peripheral traces 211. An insulating spacer layer 201 covering the peripheral traces 211 is formed above the substrate 20. Specifically, the first metal layer 21 is directly disposed on the upper surface of the substrate 20, and the first metal layer 21 is etched using a first mask process. The first metal layer 21 forms patterned scan lines 221, gates 222, and peripheral traces 211. The peripheral traces 211 are located in the non-display area, and the gates 222 are electrically connected to the scan lines 221. Of course, the first metal layer 21 can also form signal traces for transmitting signals to the scan lines 221 and data lines 251 in the non-display area. The first metal layer 21 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo. The insulating spacer layer 201 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0077] By etching the peripheral traces 211 and scan lines 221 together using the same metal film layer, manufacturing processes are saved. The disadvantage is that since both scan lines 221 and data lines 251 need to be led to the bonding area through other signal traces in the non-display area, placing the peripheral traces 211 and scan lines 221 on the same layer will increase the design complexity and the bezel of the touch display panel, but this implementation method is not excluded.

[0078] Step S3: An active layer 23 is formed above the insulating spacer layer 201; and a first transparent conductive layer 24 covering the active layer 23 is formed. The first transparent conductive layer 24 is etched to form a patterned etch stop layer 242 and a pixel electrode 241. The etch stop layer 242 and the pixel electrode 241 are insulated from each other. Specifically, a semiconductor layer is covered on the upper surface of the insulating spacer layer 201. A second masking process is used to etch the semiconductor layer to form a patterned active layer 23. The active layer 23 is located above the insulating spacer layer 201 and corresponds to the gate 222. The first transparent conductive layer 24 is directly disposed on the upper surface of the insulating spacer layer 201 and covers the active layer 23. A fourth masking process is used to etch the first transparent conductive layer 24 to form a patterned pixel electrode 241 and an etch stop layer 242. The first transparent conductive layer 24 is made of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The semiconductor layer is made of amorphous silicon (a-Si) and doped amorphous silicon (N+a-Si). By etching the etch barrier layer 242 and the pixel electrode 241 from the same transparent metal layer, not only can the fabrication process be saved, but the transparent etch barrier layer 242 can also avoid affecting the aperture ratio due to the large size of the etch barrier layer 242.

[0079] Step S4: Reference Figure 8e1 , Figure 8e2 , Figure 8f1 and Figure 8f2 As shown, a third metal layer 25 is formed above the first transparent conductive layer 24. The third metal layer 25 is etched to form patterned data lines 251, source 252, drain 253, and touch signal lines 254; and a second insulating layer 203 covers the third metal layer 25. Specifically, as... Figure 8e1 and Figure 8e2As shown, the third metal layer 25 is directly disposed on the upper surface of the insulating spacer layer 201 and covers the active layer 23, pixel electrode 241, and etch stop layer 242. A fourth masking process is used to etch the third metal layer 25, forming patterned data lines 251, source electrodes 252, drain electrodes 253, and touch signal lines 254. The touch signal lines 254 are parallel to the data lines 251. The data lines 251 are electrically connected to the source electrodes 252, and the drain electrodes 253 are electrically connected to the pixel electrode 241. The source electrodes 252 and drain electrodes 253 are connected through the active layer 23, forming a channel between them above the active layer 23. By fabricating the data lines 251, source electrodes 252, drain electrodes 253, and touch signal lines 254 from the same metal layer using the same etching process, manufacturing processes are further simplified. The etch barrier layer 242 is located in the intersection area between the scan line 221 and the touch signal line 254. The third metal layer 25 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo. The second insulating layer 203 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0080] Data lines 251 and scan lines 221 intersect to define multiple pixel units SP. Each pixel unit SP has a pixel electrode 241 and a thin-film transistor 1. The pixel electrode 241 is electrically connected to the data line 251 of the adjacent thin-film transistor 1 through the thin-film transistor 1. The thin-film transistor 1 consists of a gate 222, an active layer 23, a source 252, and a drain 253. One touch electrode 261 can correspond to multiple pixel units SP, such as... Figure 2 As shown, one touch electrode 261 can correspond to 9 pixel units SP. Of course, in practical applications, it can also be set according to actual needs.

[0081] Step S5: Reference Figure 8g As shown, the insulating spacer layer 201 and the second insulating layer 203 are simultaneously etched to form a first contact hole H1 corresponding to the etch barrier layer 242. Figure 3 and Figure 4The system includes a second contact hole H2 corresponding to the end position of the touch signal line 254 and a third contact hole H3 corresponding to the position of the peripheral trace 211. Specifically, the insulating spacer layer 201 and the second insulating layer 203 are simultaneously etched using a fifth mask process. The first contact hole H1 and the second contact hole H2 are formed on the second insulating layer 203, penetrating the second insulating layer 203 so that at least the touch signal line 254 is exposed from the first contact hole H1. The third contact hole H3 is formed together on the insulating spacer layer 201 and the second insulating layer 203, penetrating both the insulating spacer layer 201 and the second insulating layer 203 to expose the peripheral trace 211. The depths of the first contact hole H1 and the second contact hole H2 are approximately... The depth of the third contact hole H3 is The thickness of the second insulating layer 203 is approximately The thickness of the insulating spacer layer 201 is approximately

[0082] In this embodiment, the projection area of ​​the etch barrier layer 242 on the substrate 20 completely covers the projection area of ​​the first contact hole H1 on the substrate 20. Due to the etch barrier layer 242, further etching down to the first contact hole H1 and the second contact hole H2 prevents the scan lines 221 in the non-display area from being exposed. (Reference) Figure 4 and Figure 8g As can be seen, the edges of the touch signal lines 254 have been etched out of the first contact hole H1 and the second contact hole H2. Without the obstruction of the etching barrier layer 242, the first contact hole H1 and the second contact hole H2 would continue to be etched downwards, causing the scan lines 221 to be exposed. Of course, the etching barrier layer 242 does not need to be set in the area of ​​the second contact hole H2, because there are some invalid pixels near the non-display area, and the scan lines 221 corresponding to those invalid pixels have no scanning function. By setting the etching barrier layer 242 to block the first contact hole H1 and the second contact hole H2 in the intersection area between the scan lines 221 and the touch signal lines 254, the first contact hole H1 in the display area can be made together with the second contact hole H2 and the third contact hole H3 in the non-display area using the same etching process, thus saving manufacturing processes.

[0083] Step S6: Reference Figure 8h1 and Figure 8h2As shown, a second transparent conductive layer 26 is formed above the second insulating layer 203. The second transparent conductive layer 26 is etched to form patterned touch electrodes 261 and bridging electrodes 262. The touch electrodes 261 are electrically connected to the touch signal line 254 through the first contact hole H1. One end of the bridging electrode 262 is electrically connected to the touch signal line 254 through the second contact hole H2, and the other end of the bridging electrode 262 is electrically connected to the peripheral trace 211 through the third contact hole H3. Specifically, the second transparent conductive layer 26 is directly disposed on the upper surface of the second insulating layer 203. The second transparent conductive layer 26 extends into the first contact hole H1, the second contact hole H2, and the third contact hole H3. The second transparent conductive layer 26 is etched using a sixth mask process to form patterned touch electrodes 261 and bridging electrodes 262. The touch electrode 261 not only has touch functionality but can also cooperate with the pixel electrode 241. That is, the touch electrode 261 can be reused as a common electrode to apply a common signal and cooperate with the pixel electrode 241. The touch electrode 261 is located above the pixel electrode 241, and the touch electrode 261 has a slit in the area corresponding to the pixel electrode 241. The pixel electrode 241 is a block electrode, thereby realizing fringe field switching (FFS). The second transparent conductive layer 26 is made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0084] Furthermore, some of the bridging electrodes 262 can be directly electrically connected to some of the touch electrodes 261, because some of the touch electrodes 261 need to be directly electrically connected to the touch signal line 254 at the edge of the display area.

[0085] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0086] Figure 10 This is one of the structural schematic diagrams of the touch display device in this invention. Figure 11 This is the second structural schematic diagram of the touch display device in this invention. (See diagram below.) Figure 10 and Figure 11 As shown, the present invention also provides a touch display device, including a backlight module 50 and a touch display panel. The backlight module 50 can be an edge-lit backlight module or a direct-lit backlight module. Preferably, the backlight module 50 adopts a collimated backlight (CBL) mode, which can collect light and ensure display effect. The touch display panel includes an array substrate, a color filter substrate 10, and a liquid crystal layer 30 located between the array substrate and the color filter substrate 10. The array substrate is the array substrate described above (Embodiment 1, Embodiment 2).

[0087] In this embodiment, the backlight module 50 is located on the side of the array substrate away from the color filter substrate 10, that is, the color filter substrate 10 is located outside the touch display device. Of course, in other embodiments, the backlight module 50 may also be located on the side of the color filter substrate 10 away from the array substrate, that is, the array substrate is located outside the touch display panel, so that when the user touches the screen, the distance between the touch electrode 261 and the user can be reduced to enhance touch sensitivity.

[0088] In this liquid crystal layer 30, the liquid crystal molecules are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy). In the initial state, the positive liquid crystal molecules are arranged in a flat position, and the alignment direction of the positive liquid crystal molecules near the color filter substrate 10 is parallel to the alignment direction of the positive liquid crystal molecules near the array substrate. It can be understood that the array substrate and the color filter substrate 10 also have an alignment layer on the layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.

[0089] The color filter substrate 10 has a black matrix 11 and color resist layers 12. The black matrix 11 corresponds to the scan line 221, data line 251, thin film transistor 1, and the peripheral non-display area. The black matrix 11 separates multiple color resist layers 12. The color resist layers 12 include red (R), green (G), and blue (B) color resist materials, and correspondingly form red (R), green (G), and blue (B) sub-pixels.

[0090] The color filter substrate 10 is provided with an upper polarizer 41, and the array substrate is provided with a lower polarizer 42. The light transmission axis of the upper polarizer 41 and the light transmission axis of the lower polarizer 42 are perpendicular to each other.

[0091] like Figure 10 As shown, during the display period, the touch display device applies a common voltage to the touch electrode 261 through the touch signal line 254 and applies a corresponding grayscale voltage to the pixel electrode 241 through the data line 251. A voltage difference is formed between the pixel electrode 241 and the touch electrode 261, generating a horizontal electric field. Figure 10 In the E1 layer, the positive liquid crystal molecules in the liquid crystal layer 30 are deflected in the horizontal direction, thereby controlling the intensity of light passing through the liquid crystal layer 30 and achieving grayscale display. The grayscale voltage includes 0 to 255 grayscale voltage levels. When different grayscale voltages are applied to the pixel electrode 241, the pixel unit SP exhibits different brightness, thereby enabling the display device to display different images. During the touch display period, the touch display device sends a touch signal to the touch electrode 261 through the touch signal line 254, thereby realizing the touch function.

[0092] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0093] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that, The device includes a substrate (20) and scan lines (221), touch signal lines (254), and a plurality of touch electrodes (261) arranged sequentially in a direction away from the substrate (20). A first insulating layer (202) and an etch barrier layer (242) are provided between the scan lines (221) and the touch signal lines (254). The etch barrier layer (242) is located between the first insulating layer (202) and the touch signal lines (254). A second insulating layer (203) is provided between the touch signal lines (254) and the touch electrodes (261). A first contact hole (H1) penetrating the second insulating layer (203) is provided in the intersection area between the scan line (221) and the touch signal line (254). The touch electrode (261) is electrically connected to the touch signal line (254) through the first contact hole (H1). The etch barrier layer (242) corresponds to the first contact hole (H1). The projection area of ​​the etch barrier layer (242) on the substrate (20) completely covers the projection area of ​​the first contact hole (H1) on the substrate (20). The array substrate also includes peripheral traces (211) and bridging electrodes (262) located in the non-display area. One end of the bridging electrode (262) is electrically connected to the touch signal line (254), and the other end of the bridging electrode (262) is electrically connected to the peripheral traces (211). The bridging electrode (262) and the touch electrode (261) are located on the same layer. The peripheral trace (211) and the scan line (221) are located on the same layer and are insulated from each other; or, the peripheral trace (211) is located below the scan line (221) and is separated from each other by an insulating spacer layer (201).

2. The array substrate according to claim 1, characterized in that, The array substrate also includes a pixel electrode (241), which cooperates with the touch signal line (254). The etch barrier layer (242) is located on the same layer as the pixel electrode (241) and is insulated from each other.

3. The array substrate according to claim 1, characterized in that, The array substrate also includes a data line (251), and the touch signal line (254) is located on the same layer as the data line (251) and is insulated from each other.

4. A method for manufacturing an array substrate, characterized in that, The method for manufacturing an array substrate as described in any one of claims 1-3 comprises: Provide substrate (20); Patterned scan lines (221) and gates (222) are formed above the substrate (20), and the gates (222) are electrically connected to the scan lines (221); A first insulating layer (202), an etch barrier layer (242), and a touch signal line (254) are sequentially formed above the scan line (221) and the gate (222), wherein the etch barrier layer (242) is located in the intersection area between the scan line (221) and the touch signal line (254); A second insulating layer (203) is formed above the touch signal line (254) to cover the touch signal line (254). The second insulating layer (203) is etched to form a first contact hole (H1) corresponding to the etch barrier layer (242). At least the touch signal line (254) is exposed from the first contact hole (H1). The projection area of ​​the etch barrier layer (242) on the substrate (20) completely covers the projection area of ​​the first contact hole (H1) on the substrate (20). A plurality of touch electrodes (261) are formed above the second insulating layer (203), and the touch electrodes (261) are electrically connected to the touch signal line (254) through the first contact hole (H1).

5. The manufacturing method according to claim 4, characterized in that, The array substrate further includes peripheral traces (211) and bridging electrodes (262) located in the non-display area, and the manufacturing method of the peripheral traces (211) and the bridging electrodes (262) includes: A first metal layer (21) is formed above the substrate (20), and the first metal layer (21) is etched to form the scan line (221), the gate (222) and the peripheral trace (211). The first insulating layer (202) covers the scan line (221), the gate (222) and the peripheral trace (211). While etching the second insulating layer (203), the first insulating layer (202) located in the non-display area is also etched, and a second contact hole (H2) is formed at the end of the touch signal line (254) and a third contact hole (H3) is formed at the position of the peripheral trace (211). A second transparent conductive layer (26) is formed above the second insulating layer (203). The second transparent conductive layer (26) is etched to form the patterned touch electrode (261) and the bridging electrode (262). One end of the bridging electrode (262) is electrically connected to the touch signal line (254) through the second contact hole (H2), and the other end of the bridging electrode (262) is electrically connected to the peripheral trace (211) through the third contact hole (H3).

6. The manufacturing method according to claim 4, characterized in that, The array substrate further includes peripheral traces (211) and bridging electrodes (262) located in the non-display area, and the manufacturing method of the peripheral traces (211) and the bridging electrodes (262) includes: A first metal layer (21) is formed above the substrate (20), and the first metal layer (21) is etched to form the peripheral trace (211); An insulating spacer layer (201) is formed above the substrate (20) to cover the peripheral traces (211); A second metal layer (22) is formed above the insulating spacer layer (201), and the second metal layer (22) is etched to form the scan line (221) and the gate (222), with the first insulating layer (202) covering the scan line (221) and the gate (222); When etching the second insulating layer (203), the first insulating layer (202) and the insulating spacer layer (201) located in the non-display area are etched simultaneously, and a second contact hole (H2) is formed at the end of the touch signal line (254) and a third contact hole (H3) is formed at the position of the peripheral trace (211). A second transparent conductive layer (26) is formed above the second insulating layer (203). The second transparent conductive layer (26) is etched to form the patterned touch electrode (261) and the bridging electrode (262). One end of the bridging electrode (262) is electrically connected to the touch signal line (254) through the second contact hole (H2), and the other end of the bridging electrode (262) is electrically connected to the peripheral trace (211) through the third contact hole (H3).

7. The manufacturing method according to claim 4, characterized in that, The array substrate further includes a pixel electrode (241), a data line (251), a source electrode (252), a drain electrode (253), and an active layer (23). The manufacturing method of the pixel electrode (241), the data line (251), the source electrode (252), the drain electrode (253), and the active layer (23) includes: The active layer (23) is formed above the first insulating layer (202); A first transparent conductive layer (24) covering the active layer (23) is formed above the first insulating layer (202). The first transparent conductive layer (24) is etched to form a patterned etch barrier layer (242) and a pixel electrode (241). The etch barrier layer (242) and the pixel electrode (241) are mutually insulated. A third metal layer (25) is formed above the first transparent conductive layer (24). The third metal layer (25) is etched to form the patterned data line (251), the source electrode (252), the drain electrode (253), and the touch signal line (254). The data line (251) is conductively connected to the source electrode (252), the drain electrode (253) is conductively connected to the pixel electrode (241), and the source electrode (252) and the drain electrode (253) are connected through the active layer (23).

8. A touch display panel, comprising an array substrate, a color filter substrate (10), and a liquid crystal layer (30) located between the array substrate and the color filter substrate (10), characterized in that, The array substrate is the array substrate as described in any one of claims 1-3.

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