Computing circuitry

Abstract

The application relates to a computing circuit. The computing circuit comprises a plurality of different types of computing units arranged in an array, each computing unit comprising a multiplication computing circuit, a precharge circuit and a computing result output circuit, and the computing result output circuits of the different types of computing units are different; the computing result output circuit is used for outputting the voltage of a computing output node through N output channels after receiving a signal input voltage, so that a first computing result calculated by the multiplication computing circuit is obtained through N times of coupling of the voltage of the computing output node, the first computing result is a computing result calculated according to the signal input voltage and a first neural network weight value, the first neural network weight value is obtained according to an initial neural network weight value and the coupling times N, and the coupling times N corresponding to the computing result output circuit in the different types of computing units are different. The computing circuit provided by the application can realize the calculation of a multi-value neural network while reducing power consumption and improving integration.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a computing circuit. BACKGROUND

[0002] Compared with binary weight neural network or ternary weight neural network, the multi-value weight neural network can use more bits to represent weights and activation values, and thus has better accuracy.

[0003] In the prior art, the multi-value weight neural network is mostly implemented based on static random-access memory (SRAM).

[0004] However, the multi-value weight neural network implemented based on SRAM has high power consumption and low integration. SUMMARY

[0005] Therefore, it is necessary to provide a computing circuit with low power consumption and high integration to solve the above technical problems.

[0006] The present application provides a computing circuit, which comprises a plurality of different types of computing units arranged in an array, each of the computing units comprises a multiplication computing circuit, a pre-charging circuit and a computing result output circuit, and the computing result output circuits of the different types of computing units are different; the multiplication computing circuit comprises a first ferroelectric transistor and a second ferroelectric transistor connected to each other, the pre-charging circuit and the computing result output circuit are electrically connected to a computing output node between the first ferroelectric transistor and the second ferroelectric transistor; the first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistance state under the driving of a write voltage, so as to represent an initial neural network weight value; the pre-charging circuit is used to adjust the computing output node to a target voltage; the first ferroelectric transistor and the second ferroelectric transistor are used to receive a signal input voltage after the computing output node is adjusted to the target voltage; the computing result output circuit is used to output the voltage of the computing output node through N output channels respectively after receiving the signal input voltage, so as to obtain a first computing result calculated by the multiplication computing circuit through N times of coupling of the voltage of the computing output node, the first computing result is a calculation result obtained according to the signal input voltage and the first neural network weight value, the first neural network weight value is obtained according to the initial neural network weight value and the coupling times N, N is a positive integer, and the coupling times N corresponding to the computing result output circuit in the different types of computing units are different.

[0007] In one embodiment, the computing result output circuit comprises N sub-output circuits, wherein each of the sub-output circuits is used to output the voltage of the computing output node through different output channels.

[0008] In one of the embodiments, the sub-output circuit includes a first transistor and a second transistor, a gate of the first transistor and a gate of the second transistor are connected with the calculation output node, a first electrode of the first transistor is connected with a first voltage source, and a first electrode of the second transistor is grounded.

[0009] In one of the embodiments, the calculation circuit further includes a first bit line RBL, a second electrode of the first transistor and a second electrode of the second transistor in each of the sub-output circuits are connected with the first bit line RBL to form an output path.

[0010] In one of the embodiments, the first bit line RBL includes a first sub-bit line RBL and a second sub-bit line RBL, the second electrode of the first transistor is connected with the first sub-bit line RBL, and the second electrode of the second transistor is connected with the second sub-bit line RBL, the first transistor and the second transistor are used to perform a charging operation or a discharging operation on the first sub-bit line RBL and the second sub-bit line RBL respectively under the control of the voltage of the calculation output node.

[0011] In one of the embodiments, the first sub-bit line RBL and the second sub-bit line RBL are connected through a calculation result processing circuit, the calculation result processing circuit includes a first switch, a second switch, a third switch, a fourth switch, a first capacitor and a second capacitor, and the calculation result processing circuit is used to perform an average processing on the voltages of the first sub-bit line RBL and the second sub-bit line RBL to obtain a calculation result of the plurality of calculation units.

[0012] In one of the embodiments, the output circuit includes a third capacitor, a first end of the third capacitor is connected with the calculation output node.

[0013] In one of the embodiments, the calculation circuit further includes a second bit line RBL, a second end of the third capacitor in each of the sub-output circuits is connected with the second bit line RBL, and the third capacitor is used to couple the voltage of the calculation output node to the second bit line RBL.

[0014] In one embodiment, the first ferroelectric transistor and the second ferroelectric transistor are further configured to receive the signal input voltage M times based on M pulses after the pre-charge circuit adjusts the calculation output node to the target voltage; the calculation result output circuit is configured to output the voltage of the calculation output node through N output paths after each reception of the signal input pulse, so as to obtain the second calculation result calculated by the multiplication calculation circuit through N couplings of the voltage of the calculation output node. The second calculation result is a calculation result calculated based on the signal input voltage and the weight value of the second neural network. The weight value of the second neural network is obtained based on the weight value of the first neural network and the number of pulses M, where M is a positive integer.

[0015] In one embodiment, the first terminal of the first ferroelectric transistor and the first terminal of the second ferroelectric transistor are connected, the second terminal of the first ferroelectric transistor is a first signal input node, the second terminal of the second ferroelectric transistor is a second signal input node, the gate of the first ferroelectric transistor is a first write voltage driving node, and the gate of the second ferroelectric transistor is a second write voltage driving node; the first signal input node and the second signal input node are used to input the signal input voltage; the first write voltage driving node and the second write voltage driving node are used to input the write voltage.

[0016] In one embodiment, the computation output node is located between the first pole of the first ferroelectric transistor and the first pole of the second ferroelectric transistor.

[0017] In one embodiment, the pre-charge circuit includes a third transistor whose source is connected to a second voltage source for outputting the target voltage, the drain of the third transistor being connected to the compute output node, and the gate of the third transistor for receiving a pulse signal to adjust the compute output node to the target voltage based on the pulse signal.

[0018] In one embodiment, the computing circuit further includes a word line WL; the gate of the third transistor in the pre-charge circuit of each computing unit is connected to the WL; the WL is used to output the pulse signal to the gate of the third transistor in the pre-charge circuit of each computing unit.

[0019] The aforementioned computing circuit includes multiple computing units of different types arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charge circuit, and a calculation result output circuit. The calculation result output circuits of different types of computing units are different. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charge circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistive state under the drive of a write voltage to characterize the initial neural network weight values. The pre-charge circuit is used to adjust the computing output node to the target voltage. The first and second ferroelectric transistors are used to receive the signal input voltage after the calculation output node is adjusted to the target voltage. The calculation result output circuit is used to output the voltage of the calculation output node through N output paths after receiving the signal input voltage, so as to obtain the first calculation result calculated by the multiplication calculation circuit through N couplings of the voltage of the calculation output node. The first calculation result is calculated based on the signal input voltage and the weight value of the first neural network. The weight value of the first neural network is obtained based on the initial neural network weight value and the number of couplings N, where N is a positive integer. The number of couplings N corresponding to the calculation result output circuit is different in different types of calculation units. The calculation circuit provided in this application can be used for the calculation of multi-valued neural networks. Compared with the calculation circuits in the prior art, the calculation circuit of this application uses fewer components. Therefore, using the calculation circuit provided in this application can effectively reduce circuit power consumption and improve integration. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the computing circuit in one embodiment;

[0021] Figure 2 This is a schematic diagram of the IV characteristics of the first ferroelectric transistor and the second ferroelectric transistor in one embodiment;

[0022] Figure 3 This is a timing diagram of the process of writing initial neural network weight values ​​to a computing unit in one embodiment;

[0023] Figure 4 This is a timing diagram for the case where the computation unit writes a weight value of 0 in one embodiment;

[0024] Figure 5 This is a timing diagram for a computing unit writing a weight value of 1 in one embodiment;

[0025] Figure 6 This is a timing diagram for the computing unit writing a weight value of -1 in one embodiment;

[0026] Figure 7 This is a schematic diagram of another computing circuit in one embodiment;

[0027] Figure 8 This is a schematic diagram of another computing circuit in one embodiment;

[0028] Figure 9 This is a schematic diagram of another computing circuit in one embodiment. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0030] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0031] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0033] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0034] Compared to binary or ternary weighted neural networks, multi-valued weighted neural networks can use more bits to represent weights and activation values, thus achieving better accuracy.

[0035] In existing technologies, most multi-weighted neural networks are implemented based on static random-access memory (SRAM).

[0036] However, this SRAM-based multi-weighted neural network has high power consumption and low integration.

[0037] In view of this, this application provides a computing circuit with low power consumption and high integration, which can be used to implement the computation of multi-valued neural networks.

[0038] In one embodiment, such as Figure 1 As shown, a computing circuit is provided, which includes multiple computing units 100 of different types arranged in an array. Each computing unit 100 includes a multiplication computing circuit 101, a pre-charging circuit 102, and a calculation result output circuit 103. The calculation result output circuit 103 is different for different types of computing units 100. The multiplication computing circuit 101 includes a first ferroelectric transistor 201 and a second ferroelectric transistor 202 that are interconnected. The pre-charging circuit 102 and the calculation result output circuit 103 are both electrically connected to a calculation output node 203 located between the first ferroelectric transistor 201 and the second ferroelectric transistor 202.

[0039] The first ferroelectric transistor 201 and the second ferroelectric transistor 202 are used to enter the target resistive state under the drive of the write voltage to characterize the initial neural network weight values.

[0040] In an optional embodiment of this application, such as Figure 1 As shown, the first terminal of the first ferroelectric transistor 201 and the first terminal of the second ferroelectric transistor 202 are connected, and the second terminal of the first ferroelectric transistor 201 is the first signal input node. Figure 1 Vin1), the second electrode of the second ferroelectric transistor 202 is the second signal input node (in the second polarity).Figure 1 Vin2 in the first ferroelectric transistor 201 has its gate as the first write voltage drive node. Figure 1 In the second ferroelectric transistor 202, the gate of the second ferroelectric transistor 202 is the second write voltage drive node (Vwrite1). Figure 1 Vwrite2 in (the text is incomplete and cannot be translated).

[0041] Optionally, the first signal input node and the second signal input node are used to input the signal input voltage, and the first write voltage driving node and the second write voltage driving node are used to input the write voltage.

[0042] In one possible implementation, such as Figure 2 As shown, Figure 2 The diagram shows the IV characteristics of the first ferroelectric transistor 201 and the second ferroelectric transistor 202. Figure 2 In the figure, -Vc and Vc are the threshold voltages of the first ferroelectric transistor 201 and the second ferroelectric transistor 202 in the positive and negative polarization states, respectively. They are also the coercivity voltages of the ferroelectric transistors. For the first ferroelectric transistor 201 and the second ferroelectric transistor 202, when the applied positive gate-source voltage is greater than Vc, the first ferroelectric transistor 201 and the second ferroelectric transistor 202 will enter the positive polarization state, which is the low resistance state. When the applied negative gate-source voltage is greater than Vc, the first ferroelectric transistor 201 and the second ferroelectric transistor 202 will enter the negative polarization state, which is the high resistance state.

[0043] Optionally, assuming the write voltage is Vwrite, the value range of Vwrite is related to the value of Vc. Specifically, Vwrite > Vc > Vwrite / 2.

[0044] In one possible implementation, assuming the initial neural network weight value to be written to the computing unit 100 is 1, two stages are required. In the first stage, Vwrite is input to the first write voltage driving node, and the second write voltage driving node is grounded. Both the first and second signal input nodes are input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the first ferroelectric transistor, causing the first ferroelectric transistor to enter or remain in a low-resistance state. In the second stage, Vwrite is still input to the first write voltage driving node, and the second write voltage driving node is still grounded. The first signal input node and the second signal input node are both input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the first ferroelectric transistor, causing the first ferroelectric transistor to enter or remain in a low-resistance state. Both the input node and the second signal input node input Vwrite. At this time, it is equivalent to inputting a negative gate-source voltage greater than Vc into the second ferroelectric transistor. The second ferroelectric transistor will enter or remain in a high-resistivity state. The high-resistivity state and the low-resistivity state are the target states mentioned above. The target state is used to characterize the initial neural network weight value corresponding to the computing unit 100. That is, the first ferroelectric transistor is in a low-resistivity state and the second ferroelectric transistor is in a high-resistivity state. This can be used to characterize the initial neural network weight value corresponding to the computing unit 100 as 1. The above process is the process of writing the initial neural network weight value 1 into the computing unit 100.

[0045] In another possible implementation, assuming the initial neural network weight value to be written to the computing unit 100 is -1, two stages are required. In the first stage, Vwrite is input to the second write voltage drive node, and the first write voltage drive node is grounded. Both the first and second signal input nodes are input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the second ferroelectric transistor, causing the second ferroelectric transistor to enter or remain in a low-resistance state. In the second stage, Vwrite is still input to the second write voltage drive node, and the first write voltage drive node is still grounded. The first signal input node and the second signal input node are both input with 0. Both the input node and the second signal input node input Vwrite. At this time, it is equivalent to inputting a negative gate-source voltage greater than Vc to the first ferroelectric transistor. The first ferroelectric transistor will enter or remain in a high-resistivity state. The high-resistivity state and the low-resistivity state are the target states mentioned above. The target state is used to characterize the initial neural network weight value corresponding to the computing unit 100. That is, the second ferroelectric transistor is in a low-resistivity state, and the first ferroelectric transistor is in a high-resistivity state. This can be used to characterize the initial neural network weight value corresponding to the computing unit 100 as -1. The above process is the process of writing the initial neural network weight value -1 to the computing unit 100.

[0046] In another possible implementation, assuming the initial neural network weights to be written to the computing unit 100 are 0, two stages are required. In the first stage, both the first write voltage driving node and the second write voltage driving node are grounded, and both the first signal input node and the second signal input node are input with a value of 0. In this first stage, the resistive states of the first ferroelectric transistor and the second ferroelectric transistor remain unchanged. In the second stage, both the first write voltage driving node and the second write voltage driving node are grounded, and both the first signal input node and the second signal input node are input with a value of Vwri. At this point, it is equivalent to inputting a negative gate-source voltage greater than Vc to both the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor will enter a high-resistivity state, which is the target state mentioned above. This target state characterizes the initial neural network weight value corresponding to the computing unit 100. That is, the fact that both the first ferroelectric transistor and the second ferroelectric transistor are in a high-resistivity state can be used to characterize that the initial neural network weight value corresponding to the computing unit 100 is 0. The above process is the process of writing the initial neural network weight value of 0 to the computing unit 100.

[0047] As described above, this is the process of writing initial neural network weight values ​​into the computing unit 100, such as... Figure 3 The diagram shown is the timing diagram for this process. The specific operation of this process can be found in Table 1. In Table 1, Vin1 (non-write row) and Vin2 (non-write row) refer to Vin1 and Vin2 of other calculation units in the calculation circuit that do not perform the write weight value calculation.

[0048] Table 1

[0049]

[0050] In one possible implementation, the inputs of Vin1 (non-write row) and Vin2 (non-write row) can be kept at Vwrite / 2. This ensures that during the weight writing process, the gate-source voltages of the first and second ferroelectric transistors in the computing units 100 corresponding to Vin1 (non-write row) and Vin2 (non-write row) will not exceed Vwrite / 2, thus ensuring that the first and second ferroelectric transistors in the computing units 100 corresponding to Vin1 (non-write row) and Vin2 (non-write row) will not undergo polarization reversal.

[0051] The pre-charge circuit 102 is used to adjust the calculation output node 203 to the target voltage.

[0052] In an optional embodiment of this application, such as Figure 1As shown, the calculation output node 203 is located between the first terminal of the first ferroelectric transistor 201 and the first terminal of the second ferroelectric transistor 202. Figure 1 Point A in the calculation is the output node 203.

[0053] In an optional embodiment of this application, such as Figure 1 As shown, the pre-charge circuit includes a third transistor 1021, the source of which is connected to a second voltage source ( Figure 1 The second voltage source is connected to the Vprecharge in the third transistor 1021, which is used to output the target voltage. The drain of the third transistor 1021 is connected to the calculation output node 203, and the gate of the third transistor 1021 is used to receive a pulse signal to adjust the calculation output node 203 to the target voltage based on the pulse signal.

[0054] Optionally, the third transistor 1021 can be an NMOS transistor, and the voltage of the second voltage source is constant at V. DD / 2.

[0055] In an optional embodiment of this application, such as Figure 1 As shown, the computing circuit also includes a word line WL104;

[0056] In each of the computing units 100, the gate of the third transistor 1021 in the pre-charge circuit 102 is connected to the WL104; the WL104 is used to output the pulse signal to the gate of the third transistor 1021 in the pre-charge circuit 102 of each computing unit 100.

[0057] Optional, such as Figure 4 , Figure 5 as well as Figure 6 As shown, Figure 4 The timing diagram shows the pre-charging circuit performing the pre-charging process and the inputting different input values ​​after the pre-charging process, given that the initial neural network weights are 0 in the computing unit 100. Figure 6 Given that the initial neural network weight value is 1, the timing diagram shows the pre-charging circuit performing the pre-charging process and the inputting different input values ​​after the pre-charging process. Figure 7When the initial neural network weight value is written to the computing unit 100 as -1, the timing diagram of the pre-charging circuit executing the pre-charging process and inputting different input values ​​after executing the pre-charging process is as follows: After the first ferroelectric transistor 201 and the second ferroelectric transistor 202 enter the target resistive state, that is, after the operation of writing the weight value to the computing unit 100 has been completed, the computing unit 100 needs to perform a multiplication operation based on the written initial neural network weight value. Before performing the multiplication operation, the computing output node 203 needs to be adjusted to the target voltage based on the pre-charging circuit 102.

[0058] In one possible implementation, when the initial neural network weights written to the computing unit 100 are 0, a positive pulse with a large amplitude can be applied to WL104 so that the computing output node 203 is charged to V by the first voltage source. DD / 2, when the applied pulse ends, the voltage on WL104 will return to 0 and remain at 0, at which point the connection between the first voltage source and the calculation output node 203 will be cut off.

[0059] In another possible implementation, when the initial neural network weight value written to the computing unit 100 is 1, a positive pulse with a large amplitude is applied to WL104. At this time, under the combined action of the first signal input node and the first voltage source, the voltage of the computing output node is set to V. DD / 2.

[0060] In another possible implementation, when the initial neural network weight value written to the computing unit 100 is -1, a positive pulse with a large amplitude is applied to WL104. At this time, under the combined action of the second signal input node and the first voltage source, the voltage of the computing output node is set to V. DD / 2.

[0061] The first ferroelectric transistor 301 and the second ferroelectric transistor 302 are used to receive the signal input voltage after the calculation output node 203 is adjusted to the target voltage.

[0062] Optionally, the signal input voltage is used to characterize the input value.

[0063] In one possible implementation, if the voltage input to the first signal input node is V DD If the voltage input to the second signal input node is 0, then the input value can be determined to be 1.

[0064] In another possible implementation, if the voltage input to the first signal input node is V DD / 2, the voltage input to the second signal input node is V DDIf we use / 2, then we can determine that the input value is 0.

[0065] In another possible implementation, if the voltage input to the first signal input node is 0, the voltage input to the second signal input node is V. DD Then the input value can be determined to be -1.

[0066] The calculation result output circuit 103 is used to output the voltage of the calculation output node 203 through N output paths after receiving the signal input voltage, so as to obtain the first calculation result calculated by the multiplication calculation circuit 101 through N couplings of the voltage of the calculation output node 203. The first calculation result is the calculation result calculated based on the signal input voltage and the first neural network weight value. The first neural network weight value is obtained based on the initial neural network weight value and the number of couplings N, where N is a positive integer. The number of couplings N corresponding to the calculation result output circuits in different types of calculation units 100 is different.

[0067] In one embodiment, such as Figure 1 The calculation result output circuit 103 shown includes N sub-output circuits 1031, wherein each sub-output circuit 1031 is used to output the voltage of the calculation output node 203 through different output paths.

[0068] In an optional embodiment of this application, such as Figure 1 As shown, the sub-output circuit 1031 includes a first transistor 301 and a second transistor 302. The gates of both the first transistor 301 and the second transistor 302 are connected to the computation output node 203. The first terminal of the first transistor 301 is connected to a first voltage source ( Figure 1 V in DD The first terminal of the second transistor 302 is grounded.

[0069] In one possible implementation, such as Figure 1 As shown, Figure 1The computing circuit includes two different types of computing units 100, namely a first part and a second part. The first part includes a sub-output circuit 1031, and the second part includes two sub-output circuits 1031. That is, the first part outputs the voltage of the computing output node 203 through only one output path, and the second part outputs the voltage of the computing output node 203 through two output paths. It can be understood that the initial neural network weight values ​​of the first part and the second part are both (-1, 0, 1). The coupling number of the first part is 1, and the coupling number of the second part is 2. The first neural network weight value of the first part is (-1, 0, 1), and the first neural network weight value of the second part is (-2, 0, 2). If the first neural network weight values ​​of the first part and the second part are combined, a neural network calculation with multiple weight values ​​can be realized based on the computing circuit. The weight values ​​of the computing circuit are (-3, -2, -1, 0, 1, 2, 3).

[0070] In another possible implementation, such as Figure 7 As shown, Figure 7 The computational circuit includes three different types of computational units 100, namely a first part, a second part, and a third part. The first part includes one sub-output circuit 1031, the second part includes two sub-output circuits 1031, and the third part includes four sub-output circuits 1031. That is, the first part outputs the voltage of the computational output node 203 through only one output path, the second part outputs the voltage of the computational output node 203 through two output paths, and the third part outputs the voltage of the computational output node 203 through three output paths. It can be understood that the initial neural network weight values ​​of the first part, the second part, and the third part are all (- The coupling times of the first part are 1, the coupling times of the second part are 2, and the coupling times of the third part are 4. The weight values ​​of the first neural network in the first part are (-1, 0, 1), the weight values ​​of the first neural network in the second part are (-2, 0, 2), and the weight values ​​of the first neural network in the third part are (-4, 0, 4). If the weight values ​​of the first, second, and third neural networks are combined, a neural network calculation with multiple weight values ​​can be realized based on the calculation circuit. The weight values ​​of the calculation circuit are (-7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7).

[0071] As mentioned above, with the increase of computing units 100 in the computing circuit, the number of sub-output paths included in the computing unit 100 also increases. Specifically, if the added computing unit 100 is the Mth part, then the added sub-output paths are 2. M-1 The corresponding weight value is [-(2M -1), -(2) M -2), ..., -2, -1, 0, 1, 2, ..., 2 M -2,2 M -1].

[0072] In one embodiment, such as Figure 1 As shown, the computing circuit also includes a first bit line RBL (not shown in the figure), and the second terminals of the first transistor 301 and the second transistor 302 in each of the sub-output circuits 103 are connected to the first bit line RBL to form an output path.

[0073] In one embodiment, such as Figure 1 As shown, the first bit line RBL includes a first sub-bit line RBL501 and a second sub-bit line RBL502. The second terminal of the first transistor 301 is connected to the first sub-bit line RBL501, and the second terminal of the second transistor 302 is connected to the second sub-bit line RBL502.

[0074] The first transistor 301 and the second transistor 302 are used to perform charging or discharging operations on the first sub-bit line RBL501 and the second sub-bit line RBL502 respectively, under the control of the voltage of the calculation output node 203.

[0075] Optionally, the first transistor 301 may be a PMOS transistor, and the second transistor 302 may be an NMOS transistor.

[0076] In one optional embodiment of this application, before the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the first neural network weight value, it is necessary to perform discharge processing and floating processing on the first sub-bit line RBL501 and the second sub-bit line RBL502 based on the transistor.

[0077] In an optional embodiment of this application, such as Figure 1 As shown, the first sub-bit line RBL501 and the second sub-bit line RBL502 are connected through a calculation result processing circuit 106. The calculation result processing circuit 106 includes a first switch 601, a second switch 602, a third switch 603, a fourth switch connection 604, a first capacitor 605, and a second capacitor 606.

[0078] The calculation result processing circuit 106 is used to average the voltages of the first sub-line RBL501 and the second sub-line RBL502 to obtain the calculation results of the plurality of calculation units 100.

[0079] In one possible implementation, during the multiplication calculation circuit 101's calculation based on the signal input voltage and the first neural network weight value, the first switch 601 and the second switch 602 remain closed, while the third switch 603 and the fourth switch 604 remain open.

[0080] As described above, the first transistor and the second transistor are used to perform charging or discharging operations on the first sub-bit line RBL501 and the second sub-bit line RBL502, respectively, under the control of the calculated output node voltage.

[0081] In one possible implementation, when the voltage at point A is V DD At / 2, both the first transistor 301 and the second transistor 302 are not conducting. Therefore, the voltage on the first sub-bit line RBL501 is 0, and the voltage on the second sub-bit line RBL502 is V. DD .

[0082] In another possible implementation, when the voltage at point A is V DD At this time, the first transistor 301 is not turned on, and the second transistor 302 is turned on. Therefore, the voltage on the first sub-bit line RBL501 is 0, and the voltage on the second sub-bit line RBL502 is V. DD -ΔV, where ΔV is the voltage change on the second sub-bit line RBL502 caused by the change in stored charge when the second transistor 302 performs a discharge operation.

[0083] In another possible implementation, when the voltage at point A is 0, the second transistor 301 is turned on, and the second transistor 302 is not turned on. Then, the voltage on the first sub-line RBL501 is ΔV, and the voltage on the second sub-line RBL502 is V. DD ΔV is the voltage change on the first sub-bit line RBL501 caused by the change in stored charge when the first transistor 301 performs a charging operation.

[0084] As described above, the calculation result processing circuit 106 is used to average the voltages of the first sub-line RBL501 and the second sub-line RBL502 to obtain the calculation results of the plurality of calculation units 100.

[0085] In one possible implementation, after the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the first neural network weight value, the first transistor 301 and the second transistor 302, under the control of the voltage of the calculation output node 203, perform charging or discharging operations on the first sub-line RBL501 and the second sub-line RBL502, respectively. At this point, the first switch 601 and the second switch 602 are opened, and the charge on the second capacitor 605 and the third capacitor 606 is still retained. Then, the third switch 603 and the fourth switch 604 are closed, and the charge on the second capacitor 605 and the third capacitor 606 is... Figure 1 Charge sharing is performed at point B in the calculation, and the results can be obtained through ADC. For details, please refer to Table 3.

[0086] Table 3

[0087]

[0088]

[0089] In an optional embodiment of this application, such as Figure 8 As shown, the sub-output circuit 1031 includes a third capacitor 303, the first end of which is connected to the calculation output section 203.

[0090] In one possible implementation, such as Figure 8 As shown, Figure 8 The computational circuit includes three different types of computational units 100, namely a first part, a second part, and a third part. The first part includes one sub-output circuit, the second part includes two sub-output circuits, and the third part includes four sub-output circuits. That is, the first part outputs the voltage of the computational output node 203 through only one output path, the second part outputs the voltage of the computational output node 203 through two output paths, and the third part outputs the voltage of the computational output node 203 through three output paths. It can be understood that the initial neural network weight values ​​of the first part, the second part, and the third part are all (-1, 0, 1). The coupling number of the first part is 1, the coupling number of the second part is 2, and the coupling number of the third part is 4. The weight value of the first neural network in the first part is (-1, 0, 1), the weight value of the first neural network in the second part is (-2, 0, 2), and the weight value of the first neural network in the third part is (-4, 0, 4). If the weight values ​​of the first, second, and third neural networks are combined, a neural network calculation with multiple weight values ​​can be realized based on the calculation circuit. The weight values ​​of the calculation circuit are (-7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7).

[0091] In an optional embodiment of this application, such as Figure 8 As shown, the calculation circuit also includes a second bit line RBL107, and the second end of the third capacitor 303 in each of the sub-output circuits 1031 is connected to the second bit line RBL107; the third capacitor 303 is used to couple the voltage of the calculation output node to the second bit line RBL.

[0092] In one optional embodiment of this application, before the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the first neural network weight value, it is also necessary to perform calculations based on transistors (…). Figure 8 The second bit line RBL107 is discharged and left floating (001 in the code).

[0093] In one possible implementation, after the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the weight value of the first neural network, the third capacitor couples the voltage of the calculation output node to the second bit line RBL107, and finally the calculation result of the calculation circuit can be determined based on the voltage on the second bit line RBL107.

[0094] In one embodiment, when the sub-output circuit includes a first transistor and a second transistor, the first ferroelectric transistor and the second ferroelectric transistor are further configured to receive the signal input voltage M times based on M pulses after the pre-charge circuit adjusts the calculation output node to the target voltage; the calculation result output circuit is configured to output the voltage of the calculation output node through N output paths after each reception of the signal input pulse, so as to obtain the second calculation result calculated by the multiplication calculation circuit through N couplings of the voltage of the calculation output node. The second calculation result is a calculation result calculated based on the signal input voltage and the weight value of the second neural network, and the weight value of the second neural network is obtained based on the weight value of the first neural network and the number of pulses M, where M is a positive integer.

[0095] In one possible implementation, assuming the initial neural network weights of the computing unit are (-1, 0, 1), and the output circuit of the computing unit includes a sub-output circuit with the number of pulses M being 2, then the weights of the second neural network are (-2, 0, 2).

[0096] In another possible implementation, assuming the initial neural network weights of the computing unit are (-1, 0, 1), the output circuit of the computing unit includes two sub-output circuits, the number of pulses M is 2, and the weights of the second neural network are (-4, 0, 4).

[0097] As mentioned above, Figure 9 As shown, the Figure 9The system includes four different types of computing units 100, namely, a zero part, a first part, a second part, and a third part. The zero part includes one sub-output circuit, the first part includes one sub-output circuit, the second part includes two sub-output circuits, and the third part includes four sub-output circuits. That is, the first part outputs the voltage of the computing output node 203 through only one output path, the second part outputs the voltage of the computing output node 203 through two output paths, and the third part outputs the voltage of the computing output node 203 through three output paths. The pulse count M of the zero part is 1, and the pulse count M of the other three parts is 2. This can be understood as the zero part, the first part, the second part, and the third part... The initial neural network weights of the third part are all (-1, 0, 1), the weights of the first neural network of the zeroth part are (-1, 0, 1), the weights of the first neural network of the first part are (-1, 0, 1), the weights of the first neural network of the second part are (-2, 0, 2), the weights of the first neural network of the third part are (-4, 0, 4), the weights of the second neural network of the zeroth part are (-1, 0, 1), the weights of the second neural network of the first part are (-2, 0, 2), the weights of the second neural network of the second part are (-4, 0, 4), and the weights of the second neural network of the third part are (-8, 0, 8). Based on this calculation circuit, neural network calculation with multiple weights can be realized.

[0098] The aforementioned computing circuit includes multiple computing units of different types arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charge circuit, and a calculation result output circuit. The calculation result output circuits of different types of computing units are different. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charge circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistive state under the drive of a write voltage to characterize the initial neural network weight values. The pre-charge circuit is used to adjust the computing output node to the target voltage. The first and second ferroelectric transistors are used to receive the signal input voltage after the calculation output node is adjusted to the target voltage. The calculation result output circuit is used to output the voltage of the calculation output node through N output paths after receiving the signal input voltage, so as to obtain the first calculation result calculated by the multiplication calculation circuit through N couplings of the voltage of the calculation output node. The first calculation result is the calculation result calculated based on the signal input voltage and the first neural network weight value. The first neural network weight value is obtained based on the initial neural network weight value and the number of couplings N, where N is a positive integer. The number of couplings N corresponding to the calculation result output circuit is different in different types of calculation units. The calculation circuit provided in this application can be used for the calculation of multi-valued neural networks. Compared with the calculation circuits in the prior art, the calculation circuit of this application uses fewer components. Therefore, the calculation circuit provided in this application can effectively reduce power consumption and area. Moreover, the calculation circuit provided in this application includes weight values ​​with a sign bit, which can effectively improve inference accuracy.

[0099] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A computing circuit, characterized in that, The computing circuit includes multiple computing units of different types arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charging circuit, and a calculation result output circuit. The calculation result output circuits of different types of computing units are different. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charging circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter the target resistive state under the drive of the write voltage to characterize the initial neural network weight values; The pre-charging circuit is used to adjust the calculation output node to the target voltage; The first ferroelectric transistor and the second ferroelectric transistor are used to receive the signal input voltage after the calculation output node is adjusted to the target voltage; The calculation result output circuit is used to output the voltage of the calculation output node through N output paths after receiving the signal input voltage, so as to obtain the first calculation result calculated by the multiplication calculation circuit through N couplings of the voltage of the calculation output node. The first calculation result is the calculation result calculated based on the signal input voltage and the first neural network weight value. The first neural network weight value is obtained based on the initial neural network weight value and the number of couplings N, where N is a positive integer, and the number of couplings N corresponding to the calculation result output circuit in different types of calculation units is different.

2. The computing circuit according to claim 1, characterized in that, The calculation result output circuit includes N sub-output circuits, wherein each sub-output circuit is used to output the voltage of the calculation output node through a different output path.

3. The computing circuit according to claim 2, characterized in that, The sub-output circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are both connected to the computing output node. The first terminal of the first transistor is connected to a first voltage source, and the first terminal of the second transistor is grounded.

4. The computing circuit according to claim 3, characterized in that, The computing circuit also includes a first bit line RBL, and the second terminal of the first transistor and the second transistor in each of the sub-output circuits are connected to the first bit line RBL to form an output path.

5. The computing circuit according to claim 4, characterized in that, The first bit line RBL includes a first sub-bit line RBL and a second sub-bit line RBL. The second terminal of the first transistor is connected to the first sub-bit line RBL, and the second terminal of the second transistor is connected to the second sub-bit line RBL. The first transistor and the second transistor are used to perform charging or discharging operations on the first sub-bit line RBL and the second sub-bit line RBL respectively under the control of the calculated output node voltage.

6. The computing circuit according to claim 5, characterized in that, The first sub-bit line RBL and the second sub-bit line RBL are connected through a calculation result processing circuit, which includes a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor. The calculation result processing circuit is used to average the voltages of the first sub-bit line RBL and the second sub-bit line RBL to obtain the calculation results of multiple calculation units.

7. The computing circuit according to claim 3, characterized in that, The sub-output circuit includes a third capacitor, the first end of which is connected to the computation output node.

8. The computing circuit according to claim 7, characterized in that, The computing circuit also includes a second bit line RBL, and the second terminal of the third capacitor in each of the sub-output circuits is connected to the second bit line RBL. The third capacitor is used to couple the voltage of the calculation output node to the second bit line RBL.

9. The computing circuit according to any one of claims 1 to 6, characterized in that, The first ferroelectric transistor and the second ferroelectric transistor are further configured to receive the signal input voltage M times based on M pulses after the pre-charge circuit adjusts the calculation output node to the target voltage; The calculation result output circuit is used to output the voltage of the calculation output node through N output paths after each reception of the signal input voltage, so as to obtain the second calculation result calculated by the multiplication calculation circuit through N couplings of the voltage of the calculation output node. The second calculation result is the calculation result calculated based on the signal input voltage and the weight value of the second neural network. The weight value of the second neural network is obtained based on the weight value of the first neural network and the number of pulses M, where M is a positive integer.

10. The computing circuit according to claim 1, characterized in that, The first terminal of the first ferroelectric transistor and the first terminal of the second ferroelectric transistor are connected. The second terminal of the first ferroelectric transistor is a first signal input node, and the second terminal of the second ferroelectric transistor is a second signal input node. The gate of the first ferroelectric transistor is a first write voltage driving node, and the gate of the second ferroelectric transistor is a second write voltage driving node. The first signal input node and the second signal input node are used to input the signal input voltage; The first write voltage driving node and the second write voltage driving node are used to input the write voltage.

11. The computing circuit according to claim 10, characterized in that, The computational output node is located between the first electrode of the first ferroelectric transistor and the first electrode of the second ferroelectric transistor.

12. The computing circuit according to claim 1, characterized in that, The pre-charge circuit includes a third transistor, the source of which is connected to a second voltage source for outputting the target voltage, the drain of which is connected to the computation output node, and the gate of which is used to receive a pulse signal to adjust the computation output node to the target voltage based on the pulse signal.

13. The computing circuit according to claim 12, characterized in that, The computing circuit also includes a word line WL; The gate of the third transistor in the pre-charge circuit of each computing unit is connected to the WL; the WL is used to output the pulse signal to the gate of the third transistor in the pre-charge circuit of each computing unit.

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