Gate drive circuit and display device

Abstract

The application provides a gate drive circuit and a display device. The gate drive circuit comprises a pull-down control module, a pull-up control module, an acceleration control module and an output module. The pull-down control module lowers the potential of a first node according to a clock signal. The pull-up control module raises the potential of the first node and controls the potential of a second node according to the clock signal and a stage transmission signal. The output module comprises a first output transistor which outputs a first voltage to a signal output end of the gate drive circuit according to the potential of a third node. The acceleration control module is electrically connected between the second node and the third node. The acceleration control module is used for accelerating the conduction of the first output transistor, so that the first output transistor is fully turned on in the process of converting the output of the second voltage into the output of the first voltage at the signal output end, and the problems such as crosstalk in the display panel using the gate control signal are improved. The display device comprises the gate drive circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a gate driving circuit and a display device. Background Technology

[0002] In existing gate drive circuits, the gate of a pull-down output transistor is typically electrically connected to a capacitor to maintain its gate potential. However, when the gate potential of the pull-down output transistor is pulled down, the charging rate of the capacitor electrically connected to the gate affects the waveform of the gate control signal Scan output by the gate drive circuit. This causes a step to appear in the transition of the gate control signal Scan from a high potential to a low potential, such as... Figure 1 As shown, this can cause problems such as crosstalk to occur when displaying a panel that uses gate control signals. Summary of the Invention

[0003] This invention provides a gate driving circuit and a display device that can improve the step that occurs during the transition of the gate control signal from a high potential to a low potential.

[0004] This invention provides a gate driving circuit, including a pull-down control module, a pull-up control module, an acceleration control module, and an output module. The pull-down control module is electrically connected to a clock signal line and a first node, and pulls down the potential of the first node according to the clock signal transmitted through the clock signal line. The pull-up control module is electrically connected to the first node, a second node, and the clock signal line, and raises the potential of the first node and controls the potential of the second node according to the clock signal and the transmitted signal. The output module includes a first output transistor, whose control terminal is electrically connected to a third node, whose input terminal is electrically connected to a first voltage terminal, and whose output terminal is electrically connected to the signal output terminal of the gate driving circuit. The acceleration control module is electrically connected between the second node and the third node, and is used to accelerate the conduction of the first output transistor.

[0005] Optionally, in some embodiments of the present invention, the clock signal line includes a first clock signal line for transmitting a first clock signal and a second clock signal line for transmitting a second clock signal. The pull-up control module includes a cascading input unit and a potential maintenance unit. The cascading input unit is electrically connected to the first clock signal line and the second node, and the cascading input unit transmits the cascading signal to the second node according to the first clock signal. The potential maintenance unit is electrically connected to the second node, the second clock signal line, and a fourth node in the pull-down control module, and the potential maintenance unit maintains the potential of the second node according to the potential of the fourth node and the second clock signal. The acceleration control module accelerates the conduction of the first output transistor according to the potential of the second node.

[0006] Optionally, in some embodiments of the present invention, the acceleration control module includes an acceleration control transistor and a first shielding transistor. The control terminal of the acceleration control transistor is electrically connected to the second node, the input terminal of the acceleration control transistor is electrically connected to the second node, and the output terminal of the acceleration control transistor is electrically connected to the third node. The control terminal of the first shielding transistor is electrically connected to the first voltage terminal, the input terminal of the first shielding transistor is electrically connected to the second node, and the output terminal of the first shielding transistor is electrically connected to the third node.

[0007] Optionally, in some embodiments of the present invention, the cascading input unit includes a cascading input transistor, the control terminal of which is electrically connected to the first clock signal line, the input terminal of which is configured to receive the cascading signal, and the output terminal of which is electrically connected to the second node. The potential sustaining unit includes a first sustaining transistor, a second sustaining transistor, and a first capacitor. The control terminal of the first sustaining transistor is electrically connected to the fourth node, the input terminal of which is electrically connected to a second voltage terminal, the output terminal of which is electrically connected to the output terminal of the second sustaining transistor, the input terminal of which is electrically connected to the second clock signal line, the control terminal of which is electrically connected to the second node, and the first capacitor is connected in series between the second node and the output terminal of the second sustaining transistor.

[0008] Optionally, in some embodiments of the present invention, the pull-up control module includes a pull-up control unit, the pull-up control unit includes a pull-up control transistor, the control terminal of the pull-up control transistor is electrically connected to the second node, the input terminal of the pull-up control transistor is electrically connected to the second voltage terminal, and the output terminal of the pull-up control transistor is electrically connected to the first node.

[0009] Optionally, in some embodiments of the present invention, the pull-down control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a second capacitor. The control terminal of the first transistor is electrically connected to the first clock signal line, the input terminal of the first transistor is electrically connected to a first voltage terminal, and the output terminal of the first transistor is electrically connected to the fourth node. The control terminal of the second transistor is electrically connected to the second node, the input terminal of the second transistor is electrically connected to the first clock signal line, and the output terminal of the second transistor is electrically connected to the fourth node. The control terminal of the third transistor is electrically connected to the fourth node, and the input terminal of the third transistor is electrically connected to the second clock signal line. The control terminal of the fourth transistor is electrically connected to the second clock signal line, and the input and output terminals of the fourth transistor are electrically connected between the output terminal of the third transistor and the first node. The second capacitor is connected in series between the control terminal and the output terminal of the third transistor.

[0010] Optionally, in some embodiments of the present invention, the gate driving circuit further includes a second shielding transistor, the control terminal of the second shielding transistor being electrically connected to the first voltage terminal, the input terminal of the second shielding transistor being electrically connected to the fourth node, and the output terminal of the second shielding transistor being electrically connected to the control terminal of the third transistor.

[0011] Optionally, in some embodiments of the present invention, the output module includes a second output transistor and a third capacitor. The control terminal of the second output transistor is electrically connected to the first node, the input terminal of the second output transistor is electrically connected to a second voltage terminal, and the output terminal of the second output transistor is electrically connected to the signal output terminal. The third capacitor is connected in series between the input terminal and the control terminal of the second output transistor.

[0012] Optionally, in some embodiments of the present invention, the gate driving circuit further includes a reset transistor, the control terminal of the reset transistor being electrically connected to a reset control line, the input terminal of the reset transistor being electrically connected to the first voltage terminal, and the output terminal of the reset transistor being electrically connected to the second node.

[0013] The present invention also provides a display device including any of the above-described gate driving circuits.

[0014] This invention provides a gate driving circuit and a display device. The gate driving circuit includes a pull-down control module, a pull-up control module, an acceleration control module, and an output module. The pull-down control module pulls down the potential of a first node according to a clock signal, and the pull-up control module raises the potential of the first node and controls the potential of a second node according to the clock signal and a transmission signal. The output module includes a first output transistor, which outputs a first voltage to the signal output terminal of the gate driving circuit according to the potential of a third node. The acceleration control module is electrically connected between the second and third nodes and is used to accelerate the conduction of the first output transistor. This accelerates the complete conduction of the first output transistor during the transition from a second output voltage to a first output voltage at the signal output terminal, thereby improving the performance of the gate control signal. This addresses issues such as crosstalk that can easily occur when displaying a screen using the gate control signal, which has a stepped characteristic. The display device includes the gate driving circuit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a timing diagram of the gate control signal output by the existing gate drive circuit;

[0017] Figure 2 This is a schematic diagram of the gate driving circuit provided in an embodiment of the present invention;

[0018] Figure 3 This is a simulation timing diagram of the gate driving circuit provided in an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the structure of the display device provided in an embodiment of the present invention;

[0020] Figure 5 This is a timing diagram of the gate control signal provided in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0023] Specifically, such as Figure 2 This is a schematic diagram of the gate driving circuit provided in an embodiment of the present invention. The embodiment of the present invention provides a gate driving circuit including a pull-down control module 100, a pull-up control module 200, an output module 300, and an acceleration control module 400.

[0024] The pull-down control module 100 is electrically connected to the clock signal line and the first node N1. The pull-down control module 100 pulls down the potential of the first node N1 according to the clock signal transmitted by the clock signal line.

[0025] The pull-up control module 200 is electrically connected to the first node N1, the second node N2 and the clock signal line. The pull-up control module 200 raises the potential of the first node N1 and controls the potential of the second node N2 according to the clock signal and the cascade signal Scan(C-1).

[0026] The output module 300 is electrically connected to the first node N1 and the third node N3, and the output module 300 outputs a gate control signal Scan(C) according to the potentials of the first node N1 and the third node N3.

[0027] Optionally, the output module 300 includes a first output transistor Tto1, a second output transistor Tto2, and a third capacitor C3.

[0028] The control terminal of the first output transistor Tto1 is electrically connected to the third node N3, the input terminal of the first output transistor Tto1 is electrically connected to the first voltage terminal VGL, and the output terminal of the first output transistor Tto1 is electrically connected to the signal output terminal Out of the gate control signal Scan(C) output by the gate drive circuit. The first output transistor Tto1 is configured to output the first voltage transmitted from the first voltage terminal VGL to the signal output terminal Out according to the potential of the third node N3.

[0029] The control terminal of the second output transistor Tto2 is electrically connected to the first node N1, the input terminal of the second output transistor Tto2 is electrically connected to the second voltage terminal VGH, and the output terminal of the second output transistor Tto2 is electrically connected to the signal output terminal Out. The second output transistor Tto2 is configured to output a second voltage transmitted from the second voltage terminal VGH to the signal output terminal Out according to the potential of the first node N1.

[0030] The third capacitor C3 is connected in series between the input terminal of the second output transistor Tto2 and the control terminal of the second output transistor Tto2.

[0031] Optionally, the first voltage is less than the second voltage.

[0032] Please continue reading. Figure 2 The acceleration control module 400 is electrically connected between the second node N2 and the third node N3, and the acceleration control module 400 is used to accelerate the conduction of the first output transistor Tto1.

[0033] Optionally, the first output transistor Tto1 is a P-type transistor, and the acceleration control module 400 is used to accelerate the pull-down of the potential of the third node N3 to accelerate the control of the first output transistor Tto1 to turn on.

[0034] Optionally, the first output transistor Tto1 is an N-type transistor, and the acceleration control module 400 is used to accelerate the rise of the potential of the third node N3 in order to accelerate the control of the first output transistor Tto1 to turn on.

[0035] By setting up a pull-up control module 200 and an acceleration control module 400, the conduction speed of the first output transistor Tto1 is accelerated during the process of the signal output terminal Out changing from the output second voltage to the output first voltage. This allows the first output transistor Tto1 to be fully turned on in a timely manner according to the potential of the third node N3, thereby enabling the first voltage to be output to the signal output terminal Out more effectively. This improves the situation where the gate control signal Scan(C) has a step, which can cause crosstalk and other problems when displaying a display panel that uses the gate control signal Scan(C).

[0036] Alternatively, please continue reading Figure 2The acceleration control module 400 includes an acceleration control transistor Tsc and a first shielding transistor Ta1. The output terminal of the acceleration control module 400 is electrically connected to the third node N3, the control terminal of the first shielding transistor Ta1 is electrically connected to the third voltage terminal, the input terminal of the first shielding transistor Ta1 is electrically connected to the second node N2, and the output terminal of the first shielding transistor Ta1 is electrically connected to the third node N3.

[0037] Optionally, the first shielding transistor Ta1 is a P-type transistor, and its control terminal is electrically connected to the first voltage terminal VGL (i.e., the third voltage terminal is at the same potential as the first voltage terminal VGL); or the first shielding transistor Ta1 is an N-type transistor, and its control terminal is electrically connected to the second voltage terminal VGH (i.e., the third voltage terminal is at the same potential as the second voltage terminal VGH). Optionally, the first shielding transistor Ta1 can also be used to shield ultra-low potentials.

[0038] Optionally, the control terminal of the acceleration control transistor Tsc can be electrically connected to the acceleration control line. The acceleration control transistor Tsc is synchronously turned on at the moment when the first output transistor Tto1 needs to be turned on, according to the acceleration control signal transmitted by the acceleration control line. Optionally, the first output transistor Tto1 is a P-type transistor, and the input terminal of the acceleration control transistor Tsc can be electrically connected to a fourth voltage terminal; or the first output transistor Tto1 is an N-type transistor, and the input terminal of the acceleration control transistor Tsc can be electrically connected to a second voltage terminal VGH. The voltage transmitted at the fourth voltage terminal can be lower than the first voltage transmitted at the first voltage terminal VGL.

[0039] Optionally, the input terminal of the acceleration control transistor Tsc can also be electrically connected to a node in the gate drive circuit to control the conduction speed of the first output transistor Tto1 through the interconnection between nodes.

[0040] Optionally, the control terminal of the acceleration control transistor Tsc can also be electrically connected to a node in the gate drive circuit to reduce the number of control signals used by the gate drive circuit. This reduces control complexity and saves layout space while enabling the interconnection between the acceleration control transistor Tsc and the first output transistor Tto1.

[0041] Optionally, the control terminal of the acceleration control transistor Tsc can be electrically connected to the first node N1, so as to control the conduction or cutoff of the acceleration control transistor Tsc through the potential of the first node N1, thereby controlling the conduction speed of the first output transistor Tto1. Optionally, the acceleration control transistor Tsc is an N-type transistor.

[0042] Optionally, the control terminal of the acceleration control transistor Tsc can be electrically connected to the second node N2 in the pull-up control module 200, so as to control the acceleration control transistor Tsc to cooperate with the first shielding transistor Ta1 to accelerate the conduction of the first output transistor Tto1 according to the potential of the second node N2. Optionally, the acceleration control transistor Tsc is a P-type transistor.

[0043] Alternatively, please continue reading Figure 2 The clock signal lines include a first clock signal line CKL1 for transmitting the first clock signal XCK and a second clock signal line CKL2 for transmitting the second clock signal CK. The pull-up control module 200 includes a cascade input unit and a potential maintenance unit.

[0044] The cascade input unit is electrically connected to the first clock signal line CKL1 and the second node N2. The cascade input unit transmits the cascade signal Scan(C-1) to the second node N2 according to the first clock signal line CKL1 to control the potential of the second node N2.

[0045] The potential maintenance unit is electrically connected to the second node N2, the second clock signal line CKL2, and the fourth node N4 in the pull-down control module 100. The potential maintenance unit maintains the potential of the second node N2 according to the potential of the fourth node N4 and the second clock signal CK.

[0046] Optionally, the control terminal of the acceleration control transistor Tsc is electrically connected to the second node N2, the input terminal of the acceleration control transistor Tsc is electrically connected to the second node N2, and the output terminal of the acceleration control transistor Tsc is electrically connected to the third node N3. The second node N2 controls the on / off state of the acceleration control transistor Tsc, so that when the potential of the second node N2 is interconnected with the potential of the third node N3, the acceleration control transistor Tsc can be turned on in time. This, in conjunction with the first shielding transistor Ta1, utilizes the potential of the second node N2 to further influence the potential of the third node N3, thereby allowing the first output transistor Tto1 included in the output module 300 to be fully turned on in advance, so that the first voltage is more fully output to the signal output terminal Out via the first output transistor Tto1.

[0047] Alternatively, please continue reading Figure 2The cascade input unit includes a cascade input transistor Ttr. The control terminal of the cascade input transistor Ttr is electrically connected to the first clock signal line CKL1. The input terminal of the cascade input transistor Ttr is configured to receive the cascade signal Scan(C-1). The output terminal of the cascade input transistor Ttr is electrically connected to the second node N2. The cascade input transistor Ttr transmits the cascade signal Scan(C-1) to the second node N2 according to the first clock signal XCK.

[0048] The potential maintenance unit includes a first maintenance transistor Th1, a second maintenance transistor Th2, and a first capacitor C1. The control terminal of the first maintenance transistor Th1 is electrically connected to the fourth node N4, the input terminal of the first maintenance transistor Th1 is electrically connected to the second voltage terminal VGH, the output terminal of the first maintenance transistor Th1 is electrically connected to the output terminal of the second maintenance transistor Th2, the input terminal of the second maintenance transistor Th2 is electrically connected to the second clock signal line CKL2, the control terminal of the second maintenance transistor Th2 is electrically connected to the second node N2, and the first capacitor C1 is connected in series between the second node N2 and the output terminal of the second maintenance transistor Th2.

[0049] The control terminal of the second sustaining transistor Th2 is directly electrically connected to the second node N2. This reduces the problem that the parasitic capacitance between the first clock signal line CKL1 and the second node N2 causes fluctuations in the potential of the second node N2 due to parasitic capacitance coupling when the first clock signal XCK changes, thus affecting the output state of the gate control signal Scan(C). By setting the acceleration control transistor Tsc and the first shielding transistor Ta1, the influence of the first capacitor C1 on the third node N3 can be isolated when the gate control signal Scan(C) needs to output the first voltage.

[0050] Alternatively, please continue reading Figure 2 The pull-up control module 200 includes a pull-up control unit, which includes a pull-up control transistor Tu. The control terminal of the pull-up control transistor Tu is electrically connected to the second node N2, the input terminal of the pull-up control transistor Tu is electrically connected to the second voltage terminal VGH, and the output terminal of the pull-up control transistor Tu is electrically connected to the first node N1.

[0051] Alternatively, please continue reading Figure 2 The pull-down control module 100 includes a first transistor Tt1, a second transistor Tt2, a third transistor Tt3, a fourth transistor Tt4, and a second capacitor C2.

[0052] The control terminal of the first transistor Tt1 is electrically connected to the first clock signal line CKL1, the input terminal of the first transistor Tt1 is electrically connected to the first voltage terminal VGL, and the output terminal of the first transistor Tt1 is electrically connected to the fourth node N4.

[0053] The control terminal of the second transistor Tt2 is electrically connected to the second node N2, the input terminal of the second transistor Tt2 is electrically connected to the first clock signal line CKL1, and the output terminal of the second transistor Tt2 is electrically connected to the fourth node N4.

[0054] The control terminal of the third transistor Tt3 is electrically connected to the fourth node N4, and the input terminal of the third transistor Tt3 is electrically connected to the second clock signal line CKL2.

[0055] The control terminal of the fourth transistor Tt4 is electrically connected to the second clock signal line CKL2, and the input and output terminals of the fourth transistor Tt4 are electrically connected between the output terminal of the third transistor Tt3 and the first node N1.

[0056] The second capacitor C2 is connected in series between the control terminal of the third transistor Tt3 and the output terminal of the third transistor Tt3.

[0057] Alternatively, please continue reading Figure 2 The gate drive circuit further includes a second shielded transistor Ta2, the control terminal of the second shielded transistor Ta2 is electrically connected to the fifth voltage terminal, the input terminal of the second shielded transistor Ta2 is electrically connected to the fourth node N4, and the output terminal of the second shielded transistor Ta2 is electrically connected to the control terminal of the third transistor Tt3.

[0058] Optionally, the second shielding transistor Ta2 is a P-type transistor, and the control terminal of the second shielding transistor Ta2 is electrically connected to the first voltage terminal VGL (i.e., the fifth voltage terminal is at the same potential as the first voltage terminal VGL); or the second shielding transistor Ta2 is an N-type transistor, and the control terminal of the second shielding transistor Ta2 is electrically connected to the second voltage terminal VGH (i.e., the fifth voltage terminal is at the same potential as the second voltage terminal VGH).

[0059] Alternatively, please continue reading Figure 2The gate driving circuit further includes a reset module, which includes a reset transistor Ta3. The control terminal of the reset transistor Ta3 is electrically connected to the reset control line CL, the input terminal of the reset transistor Ta3 is electrically connected to the sixth voltage terminal, and the output terminal of the reset transistor Ta3 is electrically connected to the second node N2. The reset transistor Ta3 transmits the sixth voltage transmitted from the sixth voltage terminal to the second node N2 according to the reset control signal transmitted through the reset control line CL, thereby resetting the second node N2. Optionally, the reset transistor Ta1 is a P-type transistor, and the sixth voltage terminal is at the same potential as the first voltage terminal.

[0060] like Figure 3 This is a simulation timing diagram of the gate driving circuit provided in the embodiment of the present invention; taking the gate driving circuit as an example where each transistor is a P-type transistor, the working principle of the gate driving circuit is explained as follows.

[0061] In the first stage t1: the first clock signal XCK is low, the second clock signal CK is high, and the gate drive circuit receives the stage transmission signal Scan(C-1) at a low level.

[0062] The cascade input transistor Ttr and the first transistor Tt1 are turned on according to the first clock signal XCK. The cascade signal Scan(C-1) is transmitted to the second node N2 via the cascade input transistor Ttr, causing the second transistor Tt2, the second sustaining transistor Th2, the pull-up control transistor Tu, and the acceleration control transistor Tsc to turn on. The first clock signal XCK is transmitted to the fourth node N4 via the second transistor Tt2. The first voltage is transmitted to the fourth node N4 via the first transistor Tt1. The first sustaining transistor Th1 and the third transistor Tt3 are turned on according to the first voltage and the first clock signal XCK. The second clock signal CK is transmitted to the input terminal of the fourth transistor Tt4 via the third transistor Tt3. The second voltage is transmitted to the output terminal of the first sustaining transistor Th1 via the first sustaining transistor Th1. The second clock signal CK is transmitted to the output terminal of the second sustaining transistor Th2 via the second sustaining transistor Th2. The second voltage is transmitted to the first node N1 via the pull-up control transistor Tu, causing the second output transistor Tto2 to turn off. The cascaded signal Scan(C-1) transmitted to the second node N2 is transmitted to the third node N3 via the first shielding transistor Ta1 and the acceleration control transistor Tsc, so that the first output transistor Tto1 is turned on, and the first voltage is transmitted to the signal output terminal Out. The fourth transistor Tt4 is turned off according to the second clock signal CK.

[0063] In the second stage t2: the first clock signal XCK is high, the second clock signal CK is low, and the gate drive circuit receives the stage transmission signal Scan(C-1) at a high level.

[0064] The input transistor Ttr and the first transistor Tt1 are turned off according to the first clock signal XCK. The fourth transistor Tt4 is turned on according to the second clock signal CK. The first capacitor C1 keeps the second transistor Tt2, the second sustaining transistor Th2, the acceleration control transistor Tsc, and the pull-up control transistor Tu on, so that the first clock signal XCK is transmitted to the fourth node N4 via the second transistor Tt2. The third transistor Tt3 and the first sustaining transistor Th1 are turned off according to the second clock signal line CKL2 transmitted to the fourth node N4. The first clock signal XCK is coupled to the first node N1 via the second capacitor C2 and the fourth transistor Tt4. The second voltage is transmitted to the first node N1 via the pull-up control transistor Tu, so that the second output transistor Tto2 remains off. The second clock signal CK is transmitted to the output terminal of the second sustaining transistor Th2 via the second sustaining transistor Th2, so that the potential of the second node N2 is coupled through the first capacitor C1, further reducing the potential of the second node N2, thereby ensuring that the first output transistor Tto1 remains fully on, so that the first voltage is transmitted to the signal output terminal Out via the first output transistor Tto1.

[0065] In the third stage t3: the first clock signal XCK is low, the second clock signal CK is high, and the gate drive circuit receives the stage transmission signal Scan(C-1) at a high level.

[0066] The stage input transistor Ttr and the first transistor Tt1 are turned on according to the first clock signal XCK. The stage signal Scan(C-1) is transmitted to the second node N2 through the stage input transistor Ttr, causing the second transistor Tt2, the second sustaining transistor Th2, the pull-up control transistor Tu, and the acceleration control transistor Tsc to turn off. The second voltage is transmitted to the fourth node N4 through the first transistor Tt1, causing the first sustaining transistor Th1 and the third transistor Tt3 to turn on. The second clock signal CK is transmitted to the input terminal of the fourth transistor Tt4 through the third transistor Tt3, and the fourth transistor Tt4 is turned off according to the second clock signal CK. The second voltage is transmitted to the output terminal of the first sustaining transistor Th1 through the first sustaining transistor Th1 to raise the potential of the second node N2 through the first capacitor C1. The third capacitor C3 keeps the second output transistor Tto2 in the on state, and the gate control signal Scan(C) maintains the same output state as the second stage t2.

[0067] In the fourth stage t4: the first clock signal XCK is high, the second clock signal CK is low, the gate drive circuit receives the stage transmission signal Scan(C-1) at a high level, and the reset control signal is high.

[0068] The input transistor Ttr and the first transistor Tt1 are turned off according to the first clock signal XCK. The fourth transistor Tt4 is turned on according to the second clock signal CK. The first capacitor C1 keeps the second transistor Tt2, the second sustaining transistor Th2, the acceleration control transistor Tsc, and the pull-up control transistor Tu off. The second capacitor C2 keeps the third transistor Tt3 on. The second clock signal CK is coupled to the fourth node N4 through the third transistor Tt3 and the second capacitor C2. The second clock signal CK is transmitted to the first node N1 through the third transistor Tt3 and the fourth transistor Tt4, causing the first sustaining transistor Th1 and the second output transistor Tto2 to turn on. The second voltage is transmitted to the output terminal of the first sustaining transistor Th1 through the first sustaining transistor Th1, and coupled to the potential of the second node N2 through the first capacitor C1, so that the second transistor Tt2, the second sustaining transistor Th2, the acceleration control transistor Tsc, and the pull-up control transistor Tu remain off. The second voltage is transmitted to the signal output terminal Out through the second output transistor Tto2.

[0069] In the fifth stage t5: the first clock signal XCK is low, the second clock signal CK is high, and the gate drive circuit receives the stage transmission signal Scan(C-1) at a low level.

[0070] The stage input transistor Ttr and the first transistor Tt1 are turned on, and the stage signal Scan(C-1) is transmitted to the second node N2, causing the second transistor Tt2, the second sustaining transistor Th2, the pull-up control transistor Tu, and the acceleration control transistor Tsc to turn on. This allows the stage signal Scan(C-1) to be transmitted to the third node N3 via the first shielding transistor Ta1 and the acceleration control transistor Tsc, thereby accelerating the potential drop rate of the third node N3. Consequently, the first output transistor Tto1 can be more fully output to the signal output terminal Out, shortening the transition process when the signal output terminal Out changes from the second output voltage to the first output voltage, and improving the problem of the step in the gate control signal Scan(C). The first transistor Tt1 and the second transistor Tt2 are turned on, causing the third transistor Tt3 and the first sustaining transistor Th1 to turn on according to the second voltage and the first clock signal XCK. The second clock signal CK is transmitted to the input terminal of the fourth transistor Tt4, the second voltage is transmitted to the output terminal of the first sustaining transistor Th1, and the second clock signal CK is transmitted to the output terminal of the second sustaining transistor Th2. The pull-up control transistor Tu is turned on, causing the second output transistor Tto2 to be turned off according to the second voltage.

[0071] During the first stage t1 to the fifth stage t5, the reset control signal is at a high level, and the reset transistor Ta3 is turned off according to the reset control signal. Optionally, when the device using the gate drive circuit (such as a display panel, display device, etc.) is powered on, the reset transistor Ta3 resets the potential of the second node N2 according to the reset control signal to prevent problems such as screen flickering during power-on.

[0072] Optionally, between the fourth stage t4 and the fifth stage t5, the first clock signal XCK and the second clock signal CK may each have multiple high and low level switches, so that the effective pulse of the gate control signal Scan(C) output by the gate drive circuit has a pulse width that meets the usage requirements.

[0073] The inventor of this invention has the following implications: Figure 2The gate drive circuit shown was simulated and analyzed. The simulation results show that this application can further pull down the potential of the third node N3 when the potential of the third node N3 begins to be pulled down. When the potential of the third node N3 begins to be pulled down, the potential of the third node N3 can be reduced from -6.7V in the prior art to -9.6V, and the first output transistor Tto1 can be fully turned on, so that the first voltage can be fully output through the first output transistor Tto1, and the step of the gate control signal Scan(C) disappears.

[0074] like Figure 4 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. The present invention also provides a display device, including any of the above-mentioned gate driving circuits and display panels.

[0075] Optionally, the display panel includes a plurality of sub-pixels Pi, and the plurality of sub-pixels Pi are electrically connected to a plurality of gate drive circuits through a plurality of gate control lines SL.

[0076] Optionally, multiple gate driving circuits are cascaded so that when the gate control signal Scan(C) output by the current gate driving circuit is supplied to the desired sub-pixel Pi, the next-level gate driving circuit can use the gate control signal Scan(C) output by the current gate driving circuit as a cascade signal Scan(C-1), thereby enabling the multi-level gate driving circuits to sequentially output gate control signals, such as... Figure 5 The figure shown is a timing diagram of the gate control signal provided in an embodiment of the present invention.

[0077] Optionally, a plurality of gate driving circuits are located in the non-display area 100b of the display panel, and a plurality of sub-pixels Pi are located in the display area 100a of the display panel, wherein the non-display area 100b and the display area 100a are adjacent.

[0078] Optionally, the sub-pixel Pi includes a pixel driving circuit and a light-emitting device. For example... Figure 6 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present invention. The pixel driving circuit includes a driving transistor Tdr, a compensation transistor Tc, and a reset transistor Ti1.

[0079] The driving transistor Tdr and the light-emitting device Di are connected in series between the first power line Vdd and the second power line Vss. The input and output terminals of the compensation transistor Tc are electrically connected between the control terminal and the output terminal of the driving transistor Tdr. The input and output terminals of the reset transistor Ti1 are electrically connected between the first reset line VI1 and the control terminal of the driving transistor Tdr.

[0080] Optionally, the multiple gate control lines SL include multiple first gate control lines SL1 and multiple second gate control lines SL2. Multiple cascaded gate drive circuits can be electrically connected to the control terminals of the reset transistors Ti1 of multiple sub-pixels Pi through the multiple first gate control lines SL1; or multiple cascaded gate drive circuits can be electrically connected to the control terminals of the compensation transistors Tc of multiple sub-pixels Pi through the multiple second gate control lines SL2.

[0081] When the control terminal of the reset transistor Tc or the compensation transistor Ti1 is electrically connected to the existing gate drive circuit through multiple gate control lines SL, the gate control signal Scan(C) received by the control terminal of the reset transistor Tc or the compensation transistor Ti1 has a step, which affects the potential of the control terminal of the drive transistor Tdr, causing potential fluctuations at the control terminal of the drive transistor Tdr. This leads to fluctuations in the data signal stored at the control terminal of the drive transistor Tdr, which in turn affects the drive current generated by the drive transistor Tdr, causing display problems such as crosstalk on the display panel. However, the gate drive circuit of this application can provide the pixel drive circuit with a stepless gate control signal Scan(C). Therefore, it can reduce the potential fluctuations at the control terminal of the drive transistor Tdr caused by the step in the gate control signal Scan(C), thus reducing display problems such as crosstalk.

[0082] Optionally, the pixel driving circuit of each sub-pixel Pi further includes a data transistor Tda, the input terminal of the data transistor Tda is electrically connected to the corresponding data line DL, the output terminal of the data transistor Tda is electrically connected to the input terminal of the driving transistor Tdr, and the control terminal of the data transistor Tda is electrically connected to the corresponding gate control line GL, the gate control line GL transmits the data write control signal.

[0083] Optionally, the pixel driving circuit of each sub-pixel Pi further includes an initial transistor Ti2, the input terminal of the initial transistor Ti2 is electrically connected to the second reset line VI2, the output terminal of the initial transistor Ti2 is electrically connected to the light-emitting device Di, and the control terminal of the initial transistor Ti2 is electrically connected to the initial control line VL.

[0084] Optionally, the pixel driving circuit of each sub-pixel Pi further includes a first light-emitting control transistor Ts1 and a second light-emitting control transistor Ts2. The input and output terminals of the first light-emitting control transistor Ts1 are electrically connected between the first power supply line Vdd and the input terminal of the driving transistor Tdr. The input and output terminals of the second light-emitting control transistor Ts2 are electrically connected between the light-emitting device Di and the output terminal of the driving transistor Tdr. The control terminals of the first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 are electrically connected to the corresponding light-emitting control line EML.

[0085] Optionally, the pixel driving circuit for each sub-pixel Pi also includes a sixth capacitor Cst, which is connected in series between the first power supply line Vdd and the control terminal of the driving transistor Tdr.

[0086] Optionally, the pixel driving circuit of each sub-pixel Pi also includes a seventh capacitor Cboost, which is connected in series between the control terminal of the driving transistor Tdr and the control terminal of the data transistor Tda.

[0087] Optionally, the pixel driving circuit of each sub-pixel Pi further includes a first additional transistor Ti3, the input terminal of the first additional transistor Ti3 is electrically connected to the third reset line VI3, the output terminal of the first additional transistor Ti3 is electrically connected to the input terminal of the driving transistor Tdr, and the control terminal of the first additional transistor Ti3 is electrically connected to the initial control line VL.

[0088] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A gate driving circuit, characterized in that, include: A pull-down control module is electrically connected to the clock signal line and the first node. The pull-down control module pulls down the potential of the first node according to the clock signal transmitted by the clock signal line. A pull-up control module is electrically connected to the first node, the second node, and the clock signal line. The pull-up control module raises the potential of the first node and controls the potential of the second node according to the clock signal and the cascade signal. The output module includes a first output transistor, the control terminal of which is electrically connected to a third node, the input terminal of which is electrically connected to a first voltage terminal, and the output terminal of which is electrically connected to the signal output terminal of the gate drive circuit; and An acceleration control module is electrically connected between the second node and the third node, and the acceleration control module is used to accelerate the conduction of the first output transistor; The clock signal line includes a first clock signal line that transmits a first clock signal and a second clock signal line that transmits a second clock signal; The pull-up control module includes: The cascade input unit is electrically connected to the first clock signal line and the second node, and transmits the cascade signal to the second node according to the first clock signal; The potential maintenance unit is electrically connected to the second node, the second clock signal line, and the fourth node in the pull-down control module. The potential maintenance unit maintains the potential of the second node according to the potential of the fourth node and the second clock signal. The acceleration control module accelerates the conduction of the first output transistor based on the potential of the second node.

2. The gate driving circuit according to claim 1, characterized in that, The acceleration control module includes: An acceleration control transistor, wherein the control terminal of the acceleration control transistor is electrically connected to the second node, the input terminal of the acceleration control transistor is electrically connected to the second node, and the output terminal of the acceleration control transistor is electrically connected to the third node; and The first shielding transistor has its control terminal electrically connected to the first voltage terminal, its input terminal electrically connected to the second node, and its output terminal electrically connected to the third node.

3. The gate driving circuit according to claim 1, characterized in that, The cascade input unit includes a cascade input transistor. The control terminal of the cascade input transistor is electrically connected to the first clock signal line. The input terminal of the cascade input transistor is configured to receive the cascade signal. The output terminal of the cascade input transistor is electrically connected to the second node. The potential sustaining unit includes a first sustaining transistor, a second sustaining transistor, and a first capacitor. The control terminal of the first sustaining transistor is electrically connected to the fourth node, the input terminal of the first sustaining transistor is electrically connected to the second voltage terminal, the output terminal of the first sustaining transistor is electrically connected to the output terminal of the second sustaining transistor, the input terminal of the second sustaining transistor is electrically connected to the second clock signal line, the control terminal of the second sustaining transistor is electrically connected to the second node, and the first capacitor is connected in series between the second node and the output terminal of the second sustaining transistor.

4. The gate driving circuit according to claim 1, characterized in that, The pull-up control module includes: The pull-up control unit includes a pull-up control transistor, the control terminal of which is electrically connected to the second node, the input terminal of which is electrically connected to the second voltage terminal, and the output terminal of which is electrically connected to the first node.

5. The gate driving circuit according to claim 1, characterized in that, The drop-down control module includes: The first transistor has its control terminal electrically connected to the first clock signal line, its input terminal electrically connected to the first voltage terminal, and its output terminal electrically connected to the fourth node. The second transistor has its control terminal electrically connected to the second node, its input terminal electrically connected to the first clock signal line, and its output terminal electrically connected to the fourth node. The third transistor, the control terminal of which is electrically connected to the fourth node, and the input terminal of which is electrically connected to the second clock signal line; A fourth transistor, the control terminal of which is electrically connected to the second clock signal line, and the input and output terminals of which are electrically connected between the output terminal of the third transistor and the first node; and The second capacitor is connected in series between the control terminal and the output terminal of the third transistor.

6. The gate driving circuit according to claim 5, characterized in that, Also includes: The second shielding transistor has its control terminal electrically connected to the first voltage terminal, its input terminal electrically connected to the fourth node, and its output terminal electrically connected to the control terminal of the third transistor.

7. The gate driving circuit according to claim 1, characterized in that, The output module also includes: A second output transistor, the control terminal of which is electrically connected to the first node, the input terminal of which is electrically connected to a second voltage terminal, and the output terminal of which is electrically connected to the signal output terminal; and A third capacitor is connected in series between the input terminal of the second output transistor and the control terminal of the second output transistor.

8. The gate driving circuit according to claim 1, characterized in that, Also includes: A reset transistor, wherein the control terminal of the reset transistor is electrically connected to the reset control line, the input terminal of the reset transistor is electrically connected to the first voltage terminal, and the output terminal of the reset transistor is electrically connected to the second node.

9. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 8.

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