Circuit and method for controlling a switching regulator with ultrasonic mode

Abstract

A control circuit for controlling a switching regulator includes a timer, a comparator, a driver circuit, and a controller. The timer is configured to generate an input signal indicative of whether a predetermined time has elapsed since a drive signal was enabled. The comparator is configured to compare a feedback voltage to a reference voltage to generate a comparison signal. The driver circuit is controlled by a control signal to generate the drive signal based on one of the input signal and the comparison signal. The control signal is indicative of whether a mode has been enabled. When the mode is enabled, the driver circuit is configured to generate the drive signal based on the input signal. The controller is configured to generate the control signal based on a result of comparing the feedback voltage to another reference voltage higher than the reference voltage in response to the input signal being enabled.

Description

Technical Field

[0001] This invention relates to the control of switching voltage regulator operation, and more particularly to a control circuit for controlling a switching voltage regulator, and a control method for controlling a switching voltage regulator. Background Technology

[0002] Switching regulators typically utilize loop control to convert the input voltage to the output voltage. This loop control feeds the output voltage back to a control circuit, which chops and smooths the input voltage to match the desired output voltage. This control circuit can employ pulse width modulation (PWM) or pulse frequency modulation (PFM) techniques to control the switching operation. Under light load conditions, PWM control, due to its fixed switching frequency, suffers from significant switching loss. Therefore, PFM is often used (allowing for a lower switching frequency) to improve efficiency in light load operation. However, when the switching frequency falls within the audible frequency range, such as 20Hz to 20kHz, the piezoelectric effect of the capacitor produces noticeable audible noise. Summary of the Invention

[0003] Embodiments of this disclosure provide a control circuit for controlling a switching voltage regulator, and a control method for controlling a switching voltage regulator.

[0004] Some embodiments of this disclosure provide a control circuit for controlling a switching regulator. The control circuit includes a first timer, a first comparator, a drive circuit, and a controller. The first timer generates a first input signal indicating whether a first predetermined time has elapsed since a drive signal was activated. A first switch of the switching regulator is controlled by the drive signal. The first comparator compares a feedback voltage with a first reference voltage to generate a first comparison signal. The feedback voltage reflects an output voltage of the switching regulator. The drive circuit is coupled to the first timer and the first comparator and is controlled by a control signal to generate the drive signal based on one of the first input signal and the first comparison signal. The control signal indicates whether a mode of the switching regulator is enabled. When the control signal indicates that the mode is enabled, the drive circuit generates the drive signal based on the first input signal. The controller is coupled to the drive circuit and the first timer. The controller is used to generate the control signal in response to the activation of the first input signal, based on the result of comparing the feedback voltage with a second reference voltage that is higher than the first reference voltage.

[0005] Some embodiments of this disclosure provide a control method for a switching regulator. The control method includes: measuring a first elapsed time since the activation of a first switch of the switching regulator, and generating a first input signal indicating whether the first elapsed time has reached a first predetermined time; comparing a feedback voltage with a first reference voltage to generate a first comparison signal, wherein the feedback voltage reflects an output voltage of the switching regulator; comparing the feedback voltage with a second reference voltage higher than the first reference voltage to generate a second comparison signal; generating a control signal based on the second comparison signal when the first input signal is enabled, wherein the control signal indicates whether a mode of the switching regulator is enabled; turning on the first switch based on the first input signal when the control signal indicates that the mode is enabled; and turning on the first switch based on one of the first input signal and the first comparison signal when the control signal indicates that the mode is disabled.

[0006] According to the control method provided in this disclosure, the control circuit for the switching regulator can be implemented with a relatively simple circuit structure to maintain the switching frequency under light load conditions outside the audible audio range, thereby reducing / eliminating audible noise caused by the switching operation. Furthermore, the control circuit can flexibly extend the on-time of the switch (e.g., the switch on the low-voltage side) to achieve energy balance without causing functional failure. Attached Figure Description

[0007] The various embodiments of this disclosure can be clearly understood by reading the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of certain features may be arbitrarily enlarged or reduced for clear description.

[0008] Figure 1 This is a schematic diagram of an exemplary switching regulator according to certain embodiments of this disclosure.

[0009] Figure 2 This is a partial embodiment of the present disclosure. Figure 1 The implementation method of the control circuit shown.

[0010] Figure 3 This is a partial embodiment of the present disclosure. Figure 2 The flowchart shows the control method of the switching voltage regulator.

[0011] Figure 4 This is a partial embodiment of the present disclosure. Figure 2 The diagram shows the signal waveforms involved in the operation of the control circuit.

[0012] Figure 5A In some embodiments Figure 2 The diagram shows the signal waveforms involved in the operation of the control circuit.

[0013] Figure 5B This is a partial embodiment of the present disclosure. Figure 2 The diagram shows the signal waveforms involved in the operation of the control circuit.

[0014] Figure 6 This is a flowchart of a control method for a switching regulator according to certain embodiments of this disclosure.

[0015] Figure 7 This is a flowchart of a control method for a switching regulator according to certain embodiments of this disclosure.

[0016] Symbol explanation:

[0017] 100, 200: Switching voltage regulator

[0018] 101, 201: Control circuit

[0019] 102: Voltage divider

[0020] 103: Load

[0021] 110, 160: Timers

[0022] 120, 220, 242, 244: Comparators

[0023] 130, 230: Drive circuit

[0024] 140, 240: Controller

[0025] 150, 250: Detection circuit

[0026] 232,234: Drivers

[0027] 236: On-time signal generator

[0028] 238, 246: Logic Circuits

[0029] 300, 600, 700: Control methods

[0030] 302-332, 602-608, 702-712: Operation

[0031] A1, A2, A3, A4: AND gates

[0032] CP1, CP2, CP2b, CP3:

[0033] CS,COUT: Capacitors

[0034] CS, CSb: Control signals

[0035] D1: Diode

[0036] DT: Detection signal

[0037] GD1, GD2: Drive signals

[0038] IL: Inductor current

[0039] I OUT Output current

[0040] I ZCD Current threshold value

[0041] L: Inductance

[0042] LH1, LH2, LH3: SR latches

[0043] L INI : Position

[0044] N1, N2, N3: Inverters

[0045] N S Endpoint

[0046] Q: Output

[0047] Q1, Q2: Switches

[0048] R: Reset input terminal

[0049] R1, R2, R3: OR gates

[0050] r1, r2: Resistors

[0051] S: Set input terminal

[0052] SS: On-time control signal

[0053] t0-t4, tA-tD, tA'-tD': Time

[0054] T EXT0 A period of time

[0055] T MAX ,T EXT :Reservation Time

[0056] TR1, TR2: Trigger signals

[0057] TS1, TS2: Input signals

[0058] V CC Supply voltage

[0059] V FB Feedback voltage

[0060] V IN Input voltage

[0061] V OUT Output voltage

[0062] V REF1 V REF2 V REF3 Reference voltage

[0063] V S :Voltage

[0064] V ZCD Reference voltage. Detailed Implementation

[0065] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of components and configurations described below are for simplification purposes. It is understood that these descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, it is understood that if a component is described as "connected to" or "coupled to" another component, the two components may be directly connected or coupled, or there may be other intervening components between them. Furthermore, component symbols and / or reference numerals may be reused in various embodiments of this disclosure. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0066] The embodiments of this disclosure are described in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that can be implemented in various specific situations. The specific embodiments described below are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0067] The pulse frequency modulation operation of a switching regulator can be achieved using a constant-on-time (COT) control method. To reduce audible noise from a constant-on-time switching regulator under light load, the switching frequency is typically maintained above the upper audible limit of human hearing. Another method to maintain the switching frequency outside the audible audio range is to detect the peak value of the output voltage and control the switching operation accordingly. However, this method requires applying an offset voltage to determine the peak value. Therefore, an offset cancellation circuit is also needed, increasing the complexity of the circuit design.

[0068] This disclosure provides various exemplary control circuits, each of which utilizes a timer to set the switching cycle of a switching regulator under light load. For example, the timer may have a timeout period, the reciprocal of which is greater than the upper limit of the audible audio range. The timer may start when a drive signal is asserted / activated to turn on a first switch. After a period of time, the drive signal is then de-asserted / deactivated. When the timeout period has elapsed since the drive signal was asserted, the timer may output a control signal to re-assert / activate the drive signal. Thus, when the switching frequency is above the upper limit of the audible audio range, the first switch can be forcibly turned on. The first switch may be (but is not limited to) the high-side switch of a switching regulator. In some embodiments, the control circuit may include another timer that determines whether to extend the on-time of a second switch under light load. The second switch can be (but is not limited to) the low-side switch of a switching regulator. Therefore, even under very light load conditions, the control circuit of this disclosure can still effectively achieve energy balance.

[0069] This disclosure provides various exemplary control methods for switching regulators. The control methods of this disclosure enable a switching regulator to enter a mode in which the switching frequency of the switching regulator is maintained above the upper limit of the audible audio range. For example, before the switching regulator enters this mode, the control methods of this disclosure can adjust an output voltage by comparing a feedback voltage with a first reference voltage. Simultaneously, the control methods of this disclosure can determine whether to enable the mode by comparing the feedback voltage with a second reference voltage higher than the first reference voltage. In some embodiments, when the mode is enabled, the control methods of this disclosure can determine whether to disable the mode by comparing the feedback voltage with a third reference voltage lower than the first reference voltage. Further explanation follows.

[0070] Figure 1 This is a schematic diagram of an exemplary switching regulator according to certain embodiments of this disclosure. The switching regulator 100 is used to switch the input voltage V... IN Converted to output voltage V OUT In this embodiment, for ease of explanation, the switching regulator 100 may be implemented as a buck / step-down converter. Those skilled in the art will understand that the switching regulator 100 may be implemented as other types of power converters without departing from the scope of this disclosure.

[0071] The switching regulator 100 may include switches Q1 and Q2, inductor L, and capacitor C. OUT and control circuit 101. Switch Q1 (which can be called the high-voltage side switch) is used to change the input voltage V according to the drive signal GD1. IN Coupled to terminal NS. Switch Q2 (which can be called the low-voltage side switch) is used to switch terminal N according to the drive signal GD2. S Coupled to a reference potential. For example, switch Q1 can be coupled to terminal N according to drive signal GD1. S Voltage V on S The level difference between the two determines whether the switch is turned on or off. Switch Q2 can be turned on or off based on the level difference between the drive signal GD2 and the reference potential (e.g., ground potential). Inductor L and capacitor C... OUT It can be used as a filter to filter the voltage VS and generate the output voltage V. OUT .

[0072] Control circuit 101 is coupled to switches Q1 and Q2 and is used to generate drive signals GD1 and GD2. Drive signals GD1 and GD2 can be two non-overlapping signals. In this embodiment, control circuit 101 can employ a constant on-time control scheme for output regulation. For example, switch Q1 used to control drive signal GD1 contains a series of pulses, each with the same pulse width. Under light load conditions, control circuit 101 can maintain the pulse frequency of drive signal GD1 outside the audible audio range (e.g., 20Hz to 20kHz) to reduce / eliminate audible noise.

[0073] The control circuit 101 may include a timer 110, a comparator 120, a drive circuit 130, a controller 140, a detection circuit 150, and a timer 160. The timer 110 generates an input signal TS1, which indicates whether a predetermined time T has elapsed since the drive signal GD1 was activated / asserted. MAX For example, timer 110 can be used to measure the elapsed time since the drive signal GD1 was enabled to turn on switch Q1. Input signal TS1 can indicate whether the elapsed time has reached a predetermined time T. MAX .

[0074] In this embodiment, timer 110 is activated by trigger signal TR1. The activation of trigger signal TR1 can trigger the activation of drive signal GD1. Therefore, timer 110 can be used to measure (or calculate) the elapsed time since drive signal GD1 was activated. A predetermined time T... MAX This can be used as the timeout period for timer 110. Input signal TS1 can indicate whether the timeout period has been reached / expired. In some embodiments, trigger signal TR1 can be implemented by other signals that indicate the activation of drive signal GD1 without departing from the scope of this disclosure. For example, drive signal GD1 can be used as trigger signal TR1, allowing timer 110 to be directly started by drive signal GD.

[0075] Comparator 120 is used to convert the feedback voltage V FB With reference voltage V REF1 A comparison is performed to generate a comparison signal CP1. Feedback voltage V FB It can reflect the output voltage V of the switching regulator 100 OUT For example, a feedback network 101 is used in response to an output voltage V applied thereto. OUT To provide feedback voltage VFB Feedback network 101 can be implemented using voltage divider 102 comprising resistors r1 and r2. Drive circuit 130 is coupled to timer 110 and comparator 120. Drive circuit 130 is controllable by control signal CS to generate drive signal GD1 based on either input signal TS1 or comparison signal CP1. Control signal CS can indicate whether a mode of switching regulator 100 is enabled. Switching regulator 100 operating in this mode can have a switching frequency higher than the upper limit of the audible audio range. This mode can therefore be called ultrasonic mode.

[0076] In this embodiment, when the control signal CS indicates that the mode is enabled, the drive circuit 130 can be used to generate a drive signal GD1 based on the input signal TS1. The drive signal GD1 may have a time interval T. MAX (For example, the timeout period of timer 110) equal to the period. When this mode is enabled, the frequency of the drive signal GD1 can be maintained outside the range of human hearing. For example, the predetermined time T MAX This can be equal to the maximum permissible switching period of the switching regulator 100. The reciprocal of the maximum permissible switching period is greater than the upper limit of the audible audio range. Therefore, when this mode is enabled, even under light load conditions, the switching frequency of the switching regulator 100 can still be maintained above the upper limit of the audible audio range.

[0077] When the control signal CS indicates that the mode is disabled, the drive circuit 130 can generate a drive signal GD1 based on either the input signal TS1 or the comparison signal CP1. For example, when the input signal TS1 indicates that the timer 110 has expired, the drive circuit 130 can activate the switch Q1 in response to the input signal TS1. If the input signal TS1 indicates that the timer 110 has not expired, the drive circuit 130 can activate the switch Q1 based on the comparison signal CP1.

[0078] Controller 140 is coupled to drive circuit 130 and timer 110. Controller 140 can respond to the enable signal TS1 by adjusting the feedback voltage V. FB With reference voltage V REF2 (It is higher than the reference voltage V) REF1 The comparison yields a control signal CS. For example, when input signal TS1 is enabled and feedback voltage V... FB Higher than the reference voltage V REF2At this time, controller 140 may generate a control signal CS, indicating that the mode has been enabled. In this embodiment, controller 140 may also provide a feedback voltage V. FB With reference voltage V REF3 (It is lower than the reference voltage V) REF1 This is compared to the input voltage V, which then generates a control signal CS. For example, when the feedback voltage V... FB Below the reference voltage V REF3 When this happens, the control signal CS can indicate that the mode has been disabled.

[0079] The detection circuit 150 is coupled to the drive circuit 130 to detect the inductor current I flowing through the inductor L. L A detection signal DT is generated based on whether a current threshold (e.g., a zero current threshold) has been reached. When the control signal CS indicates that the mode is disabled, the drive circuit 130 can turn off switch Q2 based on the detection signal DT. When the control signal CS indicates that the mode is enabled, the drive circuit 130 can use the comparison signal CP2 (i.e., the feedback voltage V) to generate a detection signal DT. FB With reference voltage V REF2 (Based on the comparison results) Switch Q2 is turned on.

[0080] In this embodiment, the detection circuit 150 can detect voltage V S Has the reference voltage V been reached? ZCD To detect the inductor current I L Whether the current threshold has been reached. The detection signal DT indicates the voltage V. S Has it dropped below the reference voltage V? ZCD When the detection signal DT indicates the voltage V S Higher than the reference voltage V ZCD At this time, the inductor current IL can exceed the current threshold. When the detection signal DT indicates the voltage V S Drops below reference voltage V ZCD When, the inductor current I L The current threshold may have been reached.

[0081] Timer 160 is coupled to drive circuit 130 and detection circuit 150 to generate input signal TS2, which indicates the current from inductor I. L Has a predetermined time T elapsed since the current threshold was reached? EXT When the control signal CS indicates that this mode is enabled, the drive circuit 130 can turn off switch Q2 according to the input signal TS2. For example, timer 160 can be started by the detection signal DT to measure the voltage V. S Reaching reference voltage V ZCD The elapsed time since then. Input signal TS2 can indicate whether the input signal TS2 has reached the predetermined time T.EXT (For example, the timeout period of timer 160). When timer 160 times out in this mode, drive circuit 130 can generate drive signal GD2 according to input signal TS2, thereby turning off switch Q2.

[0082] During operation, timer 110 can be started (start timing) in response to the activation of switch Q1. After a predetermined on-time, drive circuit 130 can turn off switch Q1 and turn on switch Q2. Under relatively heavy loads, the feedback voltage V FB It will drop below the reference voltage V before timer 110 times out. REF1 The switching regulator 100 can operate at a switching frequency outside the audible audio range. The control signal CS can have a signal level or bit pattern to indicate that the switching regulator 100 is not in a mode (i.e., ultrasonic mode). When the detection signal DT indicates that the inductor current I... L When the current threshold is reached, the drive circuit 130 can generate a drive signal GD2 to turn off switch Q2.

[0083] When the load connected to the switching regulator 100 is reduced, the timer 110 may adjust the feedback voltage V. FB Drops below reference voltage V REF1 Previously, a timeout occurred. For example, under a relatively light load, input signal TS1 would be enabled. When the feedback voltage V... FB Higher than the reference voltage V REF2 When the input signal TS1 is enabled, the controller 140 generates a control signal CS (indicating that the mode is enabled). The drive circuit 130 turns on switch Q1 according to the input signal TS1. The switching period of the switching regulator 100 can be equal to a predetermined time T. MAX Similarly, starting from the activation of switch Q1, after a predetermined on-time, the drive circuit 130 can turn off switch Q1 and turn on switch Q2. It should be noted that in this mode, the drive circuit 130 can delay the time at which switch Q2 turns off. For example, when the detection signal DT indicates the inductor current I... L When the current threshold is reached, the drive circuit 130 will not turn off switch Q2. Instead, the drive circuit 130 can indicate the feedback voltage V on the comparison signal CP2. FB Below the reference voltage V REF2 When this happens, switch Q2 is turned off. For example, when the detection signal DT indicates the inductor current I... L Timer 160 can be started when the current threshold is reached. Timer 160 can be activated based on the feedback voltage V. FB Drops below reference voltage V REF2The previous timeout occurred. The drive circuit 130 can respond to the enable / disable switch Q2 of the input signal TS2.

[0084] Next, when the load connected to the switching regulator 100 increases, this mode can be disabled or released, allowing the switching regulator 100 to exit this mode. For example, when the feedback voltage V... FB Drops below reference voltage V REF3 At this time, the control signal CS can indicate that the mode has been disabled. Reference voltage V REF3 It can be lower than the reference voltage V REF1 .

[0085] Figure 1 The architecture shown is for illustrative purposes only and is not intended to limit the scope of this disclosure. In some embodiments, timer 160 may be omitted. In some embodiments, the reference voltage V... REF1 It can be used as a reference voltage V REF3 In some embodiments, the switching regulator 100 may be implemented using other buck converter circuit topologies. For ease of understanding of this disclosure, the following is provided. Figure 1 The embodiment of the control circuit 101 shown is used to further illustrate the control scheme for a switching regulator provided in this disclosure. Figure 1 Other circuit implementations based on the architecture shown are all within the scope of this disclosure.

[0086] Figure 2 This is a partial embodiment of the present disclosure. Figure 1 The control circuit 201 shown is an embodiment of the control circuit 201. In this embodiment, the control circuit 201 is used to control the switching regulator 200, which can serve as... Figure 1 The illustrated embodiment of the switching regulator 100. The control circuit 201 may include a comparator 220, a drive circuit 230, a controller 240, a detection circuit 250, and... Figure 1 The timers 110 and 160 are shown. Comparator 220, drive circuit 230, controller 240, and detection circuit 250 can each serve as... Figure 1 The embodiment of the comparator 120, drive circuit 130, controller 140 and detection circuit 150 shown.

[0087] The driving circuit 230 may include (but is not limited to) drivers 232 and 234, an on-time signal generator 236, and logic circuitry 238. Driver 232 may be supplied with voltage V. CC Power is supplied via diode D1. Diode D1 is connected to capacitor C. S Coupled to terminal N SDriver 232 is used to generate drive signal GD1 based on trigger signal TR1. Driver 234 is supplied with voltage V. CC Power is supplied to generate a drive signal GD2 based on the trigger signal TR2. The on-time signal generator 236 generates an on-time control signal SS based on the trigger signal TR1. For example, after a predetermined time has elapsed since the trigger signal TR1 was enabled, the on-time signal generator 236 can activate the on-time control signal SS.

[0088] Logic circuit 238 may include AND gates A1-A3, inverters N1 and N2, OR gates R1-R3, and SR latches LH1 and LH2. The reset input R of SR latch LH1 and the set input S of SR latch LH2 are both coupled to the on-time control signal SS. Therefore, when SR latch LH1 enters the reset state, SR latch LH2 can enter the set state. That is, when driver 232 (triggered by trigger signal TR1) closes switch Q1, driver 234 (triggered by trigger signal TR2) can turn on switch Q2.

[0089] The controller 240 may include comparators 242 and 244, and logic circuitry 246. Comparator 242 is used to convert the feedback voltage V... FB With reference voltage V REF2 A comparison is performed to generate a comparison signal CP2. Comparator 244 is used to convert the feedback voltage V... FB With reference voltage V REF3 A comparison is performed to generate a comparison signal CP3. Logic circuit 246 is coupled to timer 110, comparator 242, and comparator 244. When input signal TS1 is enabled, logic circuit 246 can set control signal CS to a signal level according to comparison signal CP2. Logic circuit 246 can also set control signal CS to another signal level according to comparison signal CP3. For example, logic circuit 246 may include AND gate A4, inverter N3, and SR latch LH3. When input signal TS1 is enabled due to timer 110 timeout, AND gate A4 can set the state of the set input S of SR latch LH3 according to comparison signal CP2. In addition, comparison signal CP3 is input to the reset input R of SR latch LH3, thereby setting the state of the reset input R.

[0090] Figure 3 This is a partial embodiment of the present disclosure. Figure 2 The flowchart illustrates the control method for the switching regulator 200. Note that control method 300 can be used to control... Figure 1The switching regulator 100 is shown without departing from the scope of this disclosure. Furthermore, in some embodiments, the control method 300 may include other operations / steps. In some embodiments, the operations / steps of the control method 300 may be performed based on different sequences and / or different implementation methods.

[0091] Please include Figure 2 Please refer to Figure 3 In operation 302, timer 110 is started to measure the elapsed time since trigger signal TR1 was enabled. In operation 304, driver 232 can activate drive signal GD1 in response to the activation of trigger signal TR1, thereby turning on switch Q1. In operation 306, on-time signal generator 236 can be activated by trigger signal TR1 to calculate the elapsed time since trigger signal TR1 was enabled. In operation 308, when the calculated elapsed time reaches a predetermined on-time, on-time signal generator 236 can activate on-time control signal SS. The output Q of SR latch LH1 turns low, and the output Q of SR latch LH2 turns high. Therefore, driver 232 turns off switch Q1, and driver 234 turns on switch Q2. Inductor current I L The reduction leads to a decrease in voltage V. S decline.

[0092] In operation 310, the detection circuit 250 can generate a detection signal DT, which indicates the inductor current I. L The current drops to or below the current threshold I. ZCD For example, voltage V S It can drop below the reference voltage V ZCD This enables the detection signal DT to be activated, thus indicating the inductor current I. L Reaching (or falling below) the current threshold I ZCD In operation 312, logic circuit 238 can determine whether a mode of the switching regulator 200 is enabled. In this mode, drive circuit 230 can extend the interval between the time point when switch Q2 is turned off and the time point when switch Q2 is turned off. If it is determined that the mode is disabled or not yet enabled, operation 314 is executed. Otherwise, operations 324 and 326 are executed.

[0093] In operation 314, since both the control signal CSb and the detection signal DT are logic high, AND gate A2 can output a logic high signal. OR gate R2 can reset the SR latch LH2 based on this logic high signal. Therefore, driver 234 can turn off switch Q2. In operation 316, the feedback voltage V... FB Because of capacitance C OUT The discharge reduces the voltage. When the feedback voltage V... FB Drops below reference voltage VREF1 Return to operation 302.

[0094] In operation 318, input signal TS1 indicates the time elapsed since trigger signal TR1 was activated, which is the time until the predetermined time T is reached. MAX The scheduled time T MAX This is equal to the maximum allowable switching cycle of the switching regulator 200. Input signal TS1 is in the enabled state. During operation 320, logic circuit 246 can determine the feedback voltage V. FB Is it higher than the reference voltage V? REF2 When the feedback voltage V is determined FB Higher than the reference voltage V REF2 When the signal is at its lowest, operation 322 is executed. Otherwise, operation 302 is executed. For example, when the comparison signal CP2 is at a logic low level, logic circuit 246 can determine the feedback voltage V. FB It is lower than the reference voltage V REF2 When the comparison signal CP2 is at a logic high level, logic circuit 246 can determine the feedback voltage V. FB Is it higher than the reference voltage V? REF2 In operation 322, the SR latch LH3 can be switched to the set state. The control signal CS goes high to indicate that the mode has been enabled.

[0095] In operation 324, logic circuit 238 can determine the feedback voltage V. FB Has it dropped below the reference voltage V? REF2 When the feedback voltage V is determined FB Drops below reference voltage V REF2 When this occurs, step 328 is executed. For example, when the comparison signal CP2b (i.e., the inverted signal of the comparison signal CP2) is at a logic high level, logic circuit 238 can determine the feedback voltage V. FB Drops below reference voltage V REF2 In operation 326, the detection signal DT can start timer 160 to measure the elapsed time since the detection signal DT was activated. When the elapsed time reaches a predetermined time T... EXT At this time, operation 328 is executed. In operation 328, both OR gate R3 and AND gate A3 output a logic high signal. OR gate R2 can reset SR latch LH2. Therefore, driver 234 can turn off switch Q2.

[0096] In operation 330, logic circuit 246 can determine the feedback voltage V. FB Is it lower than the reference voltage V? REF3 When the feedback voltage V is determined FB Below the reference voltage V REF3When the condition is met, operation 332 is executed. Otherwise, operation 318 is executed. For example, when the comparison signal CP3 is at a logic high level, logic circuit 246 can determine the feedback voltage V. FB Below the reference voltage V REF3 When the comparison signal CP3 is at a logic low level, logic circuit 246 can determine the feedback voltage V. FB Higher than the reference voltage V REF3 In operation 332, the SR latch LH3 can be switched to the reset state. The control signal CS goes low to indicate that the mode has been deactivated. Operations 316 and 318 can then be performed.

[0097] Figure 4 This is a partial embodiment of the present disclosure. Figure 2 The diagram shows the signal waveforms involved in the operation of the control circuit 201. Please refer to the diagram. Figure 2 Please refer to Figure 4 Before time t0, the switching regulator 200 may be under heavy load or moderate load conditions. For example, the load 103 connected to the switching regulator 200 is a heavy load or moderate load. Between time t0 and time t1, the load 103 is reduced, and the output current I... OUT The voltage drops accordingly. Control circuit 201 can reduce the switching frequency of switching regulator 200.

[0098] At time t1, timer 110 can be started to measure the elapsed time since trigger signal TR1 was enabled. At time t2, input signal TS1 can be rendered active to indicate that the elapsed time has reached a predetermined time T. MAX In response to the enable signal TS1, the controller 240 can adjust the feedback voltage V. FB Higher than the reference voltage V REF2 In this case, the control signal CS is set to a logic high level. The switching regulator 200 enters a mode in which the switching frequency of the switching regulator 200 is maintained at an upper limit above the audible audio range. For example, the maximum permissible switching period of the switching regulator 200 can be set to a predetermined time T. MAX .

[0099] In this embodiment, when the control signal CS indicates that the mode is enabled, the drive circuit 230 can prevent the comparison signal CP1 from controlling the switch Q1. For example, between time t2 and time t3, since the control signal CSb is at a logic low level, the AND gate A1 can block the comparison signal CP1. The SR latch LH1 can transition to the set state in response to the input signal TS1. Even if the feedback voltage V FB The voltage drops below the reference voltage V before the input signal TS1 is enabled.REF1 The switching regulator 200 can still have a constant (or substantially constant) switching frequency.

[0100] Furthermore, when the control signal CS indicates that the mode is enabled, the drive circuit 230 can be used to prevent the detection signal DT from turning off switch Q2. For example, between time t2 and time t3, since the control signal CSb is at a logic low level, the AND gate A2 can block the detection signal DT. This continues until the feedback voltage V... FB Drops below reference voltage V REF1 Previously, the SR latch LH2 could remain in the reset state without transitioning to the reset state.

[0101] At time t3, the output current I OUT The current increases with the load 103. This is due to the output current I. OUT Increase, feedback voltage V FB The valley point will drop to a lower voltage value. At time t4, the feedback voltage V FB Drops below reference voltage V REF3 The SR latch LH3 can transition to a reset state in response to the comparator signal CP3. The control signal CS transitions to a logic low level to indicate that the switching regulator 200 has left / exited this mode.

[0102] In some embodiments, when the inductor current I L It has a relatively long recovery time and / or capacitance C OUT When discharged through load 103, the output voltage V OUT Undershoot may occur, potentially causing the switching regulator 200 to unexpectedly exit the mode. Voltage undershoot is particularly likely to occur in high duty cycle applications. By using timer 160, control circuitry 201 can reduce the likelihood of functional failure caused by voltage undershoot, or prevent functional failure from occurring altogether.

[0103] Figure 5A In some embodiments where timer 160 is omitted or disabled, Figure 2 The diagram shows the signal waveforms involved in the operation of the control circuit 201. Please refer to the diagram. Figure 2 Please refer to Figure 5A The switching regulator 200 can operate in this mode and has a time interval T. MAX Equal switching periods. At time tA, the inductor current I... L The current rises because switch Q1 is turned on. At time tB, the detection signal DT indicates the inductor current I.L Reaching the current threshold value I ZCD Since this mode is enabled, switch Q2 remains on, while the inductor current I... L It continues to decrease. At time tC, due to the feedback voltage V FB Drop to reference voltage V REF2 Therefore, switch Q2 is closed. From the inductor current I... L Reaching current threshold I ZCD Since then, some time has passed. EXT0 Because it takes a relatively long time for the inductor current I to... L Return to position L INI And capacitor C OUT Continuous discharge, therefore, the feedback voltage V FB It will drop below the reference voltage V at time tD. REF3 When the next switching cycle begins, the switching regulator 200 may unexpectedly exit the mode.

[0104] Figure 5B This is a partial embodiment of the present disclosure. Figure 2 The diagram shows the signal waveforms involved in the operation of the control circuit 201. In this embodiment, when the detection signal DT indicates the inductor current I... L Reaching the current threshold value I ZCD Timer 160 can be started at this time. Please include... Figure 2 Please refer to Figure 5B At time tA', the inductor current I L The current rises because switch Q1 is turned on. At time tB', the detection signal DT indicates the inductor current I. L Reaching the current threshold value I ZCD Since this mode is enabled, switch Q2 remains on. Furthermore, timer 160 can be started in response to the detection signal DT. At time tC', input signal TS2 indicates that a predetermined time T has elapsed. EXT Scheduled time T EXT Will be more Figure 5A The time period T shown EXT0 It comes quickly. Therefore, even if the feedback voltage V FB Higher than the reference voltage V REF2 Switch Q2 can still be turned off. At time tD', the feedback voltage V FB Higher than the reference voltage V REF3 Functional failures caused by voltage downscaling will not occur.

[0105] The control scheme provided in this disclosure allows for the implementation of a relatively simple circuit structure for a switching regulator, enabling the switching frequency to remain outside the audible audio range under light load conditions, thereby reducing / eliminating audible noise caused by switching operations. Furthermore, the control circuit can flexibly extend the on-time of the switch (e.g., the low-voltage side switch) to achieve energy balance without causing functional failure.

[0106] One embodiment of the control scheme employing two reference voltages provided in this disclosure can be broadly summarized as follows: Figure 6 Please include Figure 2 Please refer to Figure 6 In operation 602, timer 110 activates input signal TS1 to indicate that the elapsed time since switch Q1 was enabled has reached a maximum permissible switching cycle (e.g., a predetermined time T). MAX In operation 604, when the feedback voltage V FB Rise above the reference voltage V REF2 When activated by input signal TS1, controller 240 can set control signal CS to a signal level or bit pattern. Switching regulator 200 enters a mode, such as ultrasonic mode.

[0107] In operation 606, the drive circuit 230 can keep switch Q2 on until the feedback voltage V FB Drops below reference voltage V REF2 Up to this point. In operation 608, timer 160 is started to reduce the possibility of functional failure caused by voltage undershoot, or to avoid functional failure altogether. For example, the timeout period of timer 160 can be the maximum allowable time interval between the time when switch Q2 is turned on and the time when switch Q2 is turned off. In operation 610, when the feedback voltage V... FB Drops below reference voltage V REF3 At this time, the controller 240 can set the control signal CS to another signal level or bit pattern to disable / turn off the mode.

[0108] It should be noted that control method 600 can be used to control Figure 1 The switching regulator 100 shown is described without departing from the scope of this disclosure. Furthermore, in some embodiments, the control method 600 may include other operations. In some embodiments, the operation of the control method 600 may be performed based on different sequences and / or different implementation methods. As those skilled in the art will understand from the above description… Figures 1 to 5B Following the paragraph description, the operational details of control method 600 should be clear, so further explanation will not be repeated here.

[0109] Figure 7This is a flowchart of a control method for a switching regulator according to certain embodiments of this disclosure. For ease of explanation, control method 700 is based on... Figure 2 The switching regulator 200 shown is used as an example. It should be noted that control method 700 can be applied to... Figure 1 The switching regulator 100 shown or other types of switching regulators may be used without departing from the scope of this disclosure. Furthermore, in some embodiments, the control method 700 may include other operations. In some embodiments, the operation of the control method 700 may be performed based on different sequences and / or different implementation methods.

[0110] In operation 702, a first elapsed time since the first switch of the switching regulator was activated is measured, and a first input signal is generated accordingly, indicating whether the first elapsed time has reached a first predetermined time. For example, timer 110 can measure the elapsed time since switch Q1 was activated and generate an input signal TS1 accordingly, indicating whether the elapsed time has reached a predetermined time T. MAX In this embodiment, the input signal TS1 can be implemented as a pulse signal that transitions to a high level to indicate that the elapsed time has reached a predetermined time T. MAX .

[0111] In operation 704, a feedback voltage is compared with a first reference voltage to generate a first comparison signal, wherein the feedback voltage reflects an output voltage of the switching regulator. For example, comparator 220 can convert the feedback voltage V... FB With reference voltage V REF1 A comparison is performed to generate a comparison signal CP1.

[0112] In operation 706, the feedback voltage is compared with a second reference voltage that is higher than the first reference voltage to generate a second comparison signal. For example, controller 240 can convert the feedback voltage V... FB With voltage higher than reference voltage V REF1 Reference voltage V REF2 A comparison is made to generate a comparison signal CP2.

[0113] In operation 708, when the first input signal is enabled, a control signal is generated based on the second comparison signal. This control signal indicates whether a mode of the switching regulator is enabled. For example, when input signal TS1 is enabled, controller 240 can generate control signal CS based on comparison signal CP2. In this embodiment, the output of AND gate A4 is coupled to the setting input S of SR latch LH3. Therefore, when input signal TS1 is logic high, the output of SR latch LH3 can be determined based on comparison signal CP2.

[0114] In operation 710, when the control signal indicates that the mode is enabled, the first switch is turned on according to the first input signal. For example, when the control signal CS indicates that the mode is enabled, the drive circuit 230 may turn on switch Q1 according to input signal TS1. In this embodiment, when the control signal CS indicates that the mode is enabled, the drive circuit 230 may prevent the comparison signal CP1 from controlling switch Q1. The switching period of switch Q1 may be equal to or substantially equal to the timeout period of timer 110.

[0115] In operation 712, when the control signal indicates that the mode is disabled, the first switch is turned on according to one of the first input signal and the first comparison signal. For example, when the control signal CS indicates that the mode is disabled, the drive circuit 230 may turn on switch Q1 according to one of the input signal TS1 and the comparison signal CP1. In this embodiment, when the input signal TS1 indicates that a predetermined time T has elapsed since the switch Q1 was enabled. MAX When the input signal TS1 indicates that the elapsed time since switch Q1 was activated is longer than a predetermined time T, the drive circuit 230 can turn on switch Q1. MAX If the timer 110 has not yet expired, the drive circuit 230 can turn on switch Q1 according to the comparison signal CP1.

[0116] In some embodiments, the feedback voltage may be compared with a third reference voltage to set the signal level or bit pattern of the control signal. The third reference voltage is lower than or equal to the first reference voltage. For example, comparator 244 may compare the feedback voltage V... FB With reference voltage V REF3 A comparison is made to set the state of the output Q of the SR latch LH3. This is only necessary when the feedback voltage V... FB Drops below reference voltage V REF3 The switching regulator 200 can exit this mode.

[0117] In some embodiments, a detection signal can be generated by detecting whether the inductor current flowing through an inductor reaches a current threshold. The inductor is coupled to an endpoint located between the first switch and a second switch of the switching regulator. When the control signal indicates that the mode is enabled, the second switch is controlled according to the second comparison signal. For example, the detection circuit 250 can detect the inductor current I. L Whether a current threshold value has been reached is used to generate a measurement signal DT. When the control signal CS indicates that this mode is enabled, since AND gate A2 can prevent the detection signal DT from controlling switch Q2, switch Q2 can be controlled according to the comparison signal CP2b (instead of the detection signal DT). Furthermore, if timer 160 is at the feedback voltage V... FBDrops below reference voltage V REF2 If the timeout occurs, switch Q2 can be turned off in response to the activation of input signal TS2, thereby reducing the possibility of functional failure caused by voltage undershoot.

[0118] Because those skilled in the art will understand the above regarding Figures 1 to 6 Following the paragraph description, the operational details of control method 700 should be clear, so further explanation will not be repeated here.

[0119] The foregoing description briefly outlines the features of certain embodiments of this disclosure, enabling those skilled in the art to gain a more comprehensive understanding of the various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A control circuit for controlling a switching voltage regulator, comprising: A first timer is used to generate a first input signal indicating whether a first predetermined time has elapsed since a drive signal has been enabled, and a first switch of the switching regulator is controlled by the drive signal. A first comparator is used to compare a feedback voltage with a first reference voltage to generate a first comparison signal, the feedback voltage reflecting an output voltage of the switching regulator; A drive circuit, coupled to the first timer and the first comparator, is controlled by a control signal to generate a drive signal based on one of the first input signal and the first comparison signal. The control signal indicates whether a mode of the switching regulator is enabled. When the control signal indicates that the mode is enabled, the drive circuit generates the drive signal based on the first input signal. A controller, coupled to the drive circuit and the first timer, generates the control signal in response to the activation of the first input signal, based on the result of comparing the feedback voltage with a second reference voltage higher than the first reference voltage.

2. The control circuit as described in claim 1, characterized in that, When the feedback voltage is higher than the second reference voltage, the control signal indicates that the mode has been enabled.

3. The control circuit as described in claim 1, characterized in that, The controller is also configured to compare the feedback voltage with a third reference voltage to generate the control signal; the third reference voltage is lower than or equal to the first reference voltage.

4. The control circuit as described in claim 3, characterized in that, When the feedback voltage is lower than the third reference voltage, the control signal indicates that the mode has been disabled.

5. The control circuit as described in claim 3, characterized in that, The controller contains: A second comparator is used to compare the feedback voltage with the second reference voltage to generate a second comparison signal; A third comparator is used to compare the feedback voltage with the third reference voltage to generate a third comparison signal; as well as A logic circuit coupled to the first timer, the second comparator, and the third comparator, wherein the logic circuit is configured to set the control signal to a signal level according to the second comparison signal when the first input signal is enabled; and the logic circuit is configured to set the control signal to another signal level according to the third comparison signal.

6. The control circuit as described in claim 1, characterized in that, When the control signal indicates that the mode is enabled, the drive circuit is also configured to prevent the first comparison signal from controlling the first switch.

7. The control circuit as described in claim 1, characterized in that, Also includes: A detection circuit, coupled to the drive circuit, is configured to generate a detection signal by detecting whether the inductor current flowing through an inductor reaches a current threshold value, wherein the inductor is coupled to an end located between the first switch and a second switch of the switching regulator. Specifically, when the control signal indicates that the mode is disabled, the drive circuit is used to turn off the second switch according to the detection signal; when the control signal indicates that the mode is enabled, the drive circuit is configured to turn off the second switch according to the result obtained by comparing the feedback voltage with the second reference voltage.

8. The control circuit as described in claim 7, characterized in that, When the feedback voltage drops below the second reference voltage in this mode, the drive circuit is configured to turn off the second switch.

9. The control circuit as described in claim 7, characterized in that, Also includes: A second timer, coupled to the drive circuit and the detection circuit, is configured to generate a second input signal indicating whether a second predetermined time has elapsed since the inductor current reached the current threshold. When the control signal indicates that the mode is enabled, the drive circuit turns off the second switch according to the second input signal.

10. The control circuit as described in claim 9, characterized in that, When the control signal indicates that the mode is enabled, and the second input signal indicates that a second predetermined time has elapsed since the inductor current reached the current threshold, the drive circuit turns off the second switch.

11. The control circuit as described in claim 1, characterized in that, When the control signal indicates that the mode is enabled, the drive signal has a period equal to the first predetermined time.

12. A control method for a switching voltage regulator, comprising: Measure a first elapsed time since the first switch of the switching regulator is activated, and generate a first input signal accordingly, the first input signal indicating whether the first elapsed time has reached a first predetermined time. A feedback voltage is compared with a first reference voltage to generate a first comparison signal, wherein the feedback voltage reflects an output voltage of the switching regulator; The feedback voltage is compared with a second reference voltage that is higher than the first reference voltage to generate a second comparison signal; When the first input signal is enabled, a control signal is generated based on the second comparison signal, wherein the control signal indicates whether a mode of the switching regulator has been enabled. When the control signal indicates that the mode is enabled, the first switch is turned on according to the first input signal; and When the control signal indicates that the mode is disabled, the first switch is turned on according to one of the first input signal and the first comparison signal.

13. The control method as described in claim 12, characterized in that, When the second comparison signal indicates that the feedback voltage is higher than the second reference voltage, the control signal indicates that the mode has been enabled.

14. The control method of claim 12, further comprising: The control signal is generated based on the result of comparing the feedback voltage with a third reference voltage, wherein the third reference voltage is lower than or equal to the first reference voltage.

15. The control method as described in claim 14, characterized in that, When the feedback voltage is lower than the third reference voltage, the control signal indicates that the mode has been disabled.

16. The control method of claim 12, further comprising: When the control signal indicates that the mode is enabled, it prevents the first comparison signal from controlling the first switch.

17. The control method of claim 12, further comprising: A detection signal is generated by detecting whether the current flowing through one of the inductors reaches a current threshold value, wherein the inductor is coupled to an end located between the first switch and the second switch of the switching regulator; When the control signal indicates that the mode is disabled, the second switch is controlled according to the detection signal; and When the control signal indicates that the mode is enabled, the second switch is controlled according to the second comparison signal.

18. The control method as described in claim 17, characterized in that, The step of controlling the second switch according to the second comparison signal includes: When the second comparison signal indicates that the feedback voltage has dropped below the second reference voltage, the second switch is turned off.

19. The control method of claim 17, further comprising: The system measures a second elapsed time since the detection signal indicates that the inductor current has reached the current threshold, and generates a second input signal accordingly, indicating whether the second elapsed time has reached a second predetermined time; and When the control signal indicates that the mode is enabled, and the second input signal indicates that the second elapsed time has reached the second predetermined time, the second switch is turned off.

20. The control method as described in claim 12, characterized in that, The step of turning on the first switch based on one of the first input signal and the first comparison signal includes: When the first input signal indicates that the first elapsed time has reached the first predetermined time, the first switch is turned on according to the first input signal; and When the first input signal indicates that the first elapsed time is shorter than the first predetermined time, the first switch is turned on according to the first comparison signal.

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