Display panel and manufacturing method thereof

Abstract

The present invention relates to a display panel and a method for manufacturing the same. The present invention prepares a first polycrystalline oxide active portion on a first channel portion of a first amorphous oxide active portion, and utilizes a stacked structure formed by the first channel portion and the first polycrystalline oxide active portion to achieve a high-mobility carrier channel effect; and utilizes a single-layer structure of a first contact portion and a second contact portion to achieve a low cutoff current effect. The present invention prepares a second polycrystalline oxide active portion and a third polycrystalline oxide active portion on a third contact portion and a fourth contact portion of a second amorphous oxide active portion, respectively, and utilizes a single-layer structure of the second channel portion to achieve high stability and low cutoff current effects; utilizes a stacked structure of the third contact portion and the second polycrystalline oxide active portion to optimize the ohmic contact characteristics with the second source electrode; and utilizes a stacked structure of the fourth contact portion and the third polycrystalline oxide active portion to optimize the ohmic contact characteristics with the second drain electrode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] Low-temperature poly-oxide thin-film transistor (LTPOTFT) technology is an emerging thin-film transistor technology. LTPO backplane technology combines the low cutoff current of IGZO TFTs (IGZOTFTs) with the high carrier mobility of low-temperature poly-silicon TFTs (LTPS TFTs), enabling features such as variable refresh rates and always-on displays.

[0003] However, there are problems with the uniformity of large-scale LTPS produced by the excimer laser annealing (ELA) process. The changes in thin-film transistor characteristics caused by the unevenness of LTPS will lead to a decline in display quality. In addition, LTPO backplane technology requires the preparation of LTPS driving TFT and oxide switching TFT on different film layers respectively. The process is complex and costly, which is not conducive to large-scale mass production. For thin-film transistors using polycrystalline silicon active materials, hydrogenation of the polycrystalline silicon layer can improve the device characteristics of low-temperature polycrystalline silicon thin-film transistors, while for thin-film transistors using oxide active materials, when hydrogen or water vapor enters the oxide active layer from the film layer adjacent to the oxide active layer, the characteristics of the oxide active thin-film transistor will be degraded. Therefore, LTPO technology must overcome the conflicting characteristics caused by the influence of hydrogen, etc. Summary of the Invention

[0004] The purpose of the present invention is to provide a display panel and a preparation method thereof, which can solve the problems existing in the existing LTPO technology, such as LTPS unevenness causing a decline in display quality, complex process, high cost, unfavorable for large-size mass production, and hydrogen or water vapor entering the oxide active layer causing degradation of the characteristics of the oxide active part thin film transistor.

[0005] In order to solve the above problems, the present invention provides a display panel, which includes: a substrate; a first active layer, arranged on the substrate, whose material is amorphous oxide, and includes a first amorphous oxide active portion and a second amorphous oxide active portion spaced apart from each other; a second active layer, arranged on a side of the first active layer away from the substrate, whose material is polycrystalline oxide, and includes a first polycrystalline oxide active portion, a second polycrystalline oxide active portion and a third polycrystalline oxide active portion spaced apart from each other; the first amorphous oxide active portion includes a first channel portion and a first contact portion and a second contact portion respectively located at two ends of the first channel portion, and the first polycrystalline oxide active portion is arranged correspondingly to the first channel portion; the second amorphous oxide active portion includes a second channel portion and a third contact portion and a fourth contact portion respectively located at two ends of the second channel portion, the second polycrystalline oxide active portion is arranged correspondingly to the third contact portion, and the third polycrystalline oxide active portion is arranged correspondingly to the fourth contact portion.

[0006] Furthermore, the display panel also includes: a light-shielding layer, arranged between the substrate and the first active layer, and arranged corresponding to the first amorphous oxide active portion; a buffer layer, arranged between the light-shielding layer and the first active layer; and a blocking layer, arranged between the buffer layer and the first active layer.

[0007] Furthermore, the display panel also includes: a gate insulating layer, which is arranged on a side of the second active layer away from the substrate, and includes a first gate insulating unit and a second gate insulating unit respectively arranged corresponding to the first channel portion and the second channel portion; a first metal layer, which is arranged on a side of the gate insulating layer away from the substrate, and includes a first gate and a second gate respectively arranged corresponding to the first channel portion and the second channel portion; an interlayer insulating layer, which is arranged on a side of the first metal layer away from the substrate and extends to cover the barrier layer; a second metal layer, which is arranged on a side of the interlayer insulating layer away from the substrate, and includes a first drain, a first source, a second drain and a second source spaced apart from each other, the first drain, the first source, the second drain and the second source being electrically connected to the first contact portion, the second contact portion, the third contact portion and the fourth contact portion, respectively; a passivation layer, which is arranged on a side of the second metal layer away from the substrate; a flat layer, which is arranged on a side of the passivation layer away from the substrate; and a pixel electrode, which is arranged on a side of the flat layer away from the substrate and electrically connected to the first drain.

[0008] Furthermore, a projection of the first amorphous oxide active portion on the substrate falls within a projection of the light shielding layer on the substrate.

[0009] Furthermore, the material of the barrier layer includes: one or more of aluminum oxide, hafnium oxide, zirconium oxide and yttrium oxide; the thickness of the barrier layer ranges from 100 angstroms to 500 angstroms.

[0010] In order to solve the above problems, the present invention provides a method for preparing a display panel, which includes the following steps: providing a substrate; preparing amorphous oxide on the substrate to form a first active part material layer; preparing polycrystalline oxide on the side of the first active part material layer away from the substrate to form a second active part material layer; etching the second active part material layer and the first active part material layer using a halftone mask, the second active part material layer is etched into a first polycrystalline oxide active part, a second polycrystalline oxide active part and a third polycrystalline oxide active part that are spaced apart from each other, and the first active part material layer is etched into a first amorphous oxide active part and a second amorphous oxide active part that are spaced apart from each other; the first amorphous oxide active part includes a first channel part and a first contact part and a second contact part respectively located at two ends of the first channel part, and the first polycrystalline oxide active part is arranged corresponding to the first channel part; the second amorphous oxide active part includes a second channel part and a third contact part and a fourth contact part respectively located at two ends of the second channel part, the second polycrystalline oxide active part is arranged corresponding to the third contact part, and the third polycrystalline oxide active part is arranged corresponding to the fourth contact part.

[0011] Furthermore, the step of etching the second active portion material layer and the first active portion material layer using a halftone mask includes: dividing the first active portion material layer into the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion and the fourth contact portion; the halftone mask includes a shading area, a semi-transparent area and a fully transparent area, the shading area is arranged corresponding to the first channel portion, the third contact portion and the fourth contact portion, and the semi-transparent area is arranged corresponding to the first contact portion, the second contact portion and the second channel portion.

[0012] Furthermore, the step of etching the second active portion material layer and the first active portion material layer using a halftone mask also includes: setting a photoresist layer on a side away from the substrate at positions of the second active portion material layer corresponding to the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion and the fourth contact portion; and thinning the photoresist layer corresponding to the first contact portion, the second contact portion and the second channel portion through an exposure and development process.

[0013] Furthermore, the thickness of the photoresist layer corresponding to the first contact portion, the second contact portion, and the second channel portion is the same, and the thickness of the photoresist layer corresponding to the first channel portion, the third contact portion, and the fourth contact portion is the same.

[0014] Furthermore, the step of etching the second active material layer and the first active material layer using a halftone mask further includes: etching the first active material layer and the second active material layer by a dry etching process; and stripping and removing the photoresist layer.

[0015] The advantages of the present invention are as follows: It utilizes the high mobility of polycrystalline oxide, its on-current similar to that of LTPS, its lower off-current, and its improved large-scale uniformity to improve the poor large-scale uniformity of LTPO backplane technology. A first polycrystalline oxide active portion is formed on the first channel portion of the first amorphous oxide active portion, and the stacked structure formed by the first channel portion and the first polycrystalline oxide active portion achieves a high-mobility carrier channel effect; the single-layer structure of the first contact portion and the second contact portion achieves a low off-current effect.

[0016] The present invention prepares a second polycrystalline oxide active portion and a third polycrystalline oxide active portion on the third contact portion and the fourth contact portion of the second amorphous oxide active portion, respectively, and utilizes the single-layer structure of the second channel portion to achieve high stability and low cut-off current; utilizes the stacked structure of the third contact portion and the second polycrystalline oxide active portion to optimize the ohmic contact characteristics with the second source electrode; and utilizes the stacked structure of the fourth contact portion and the third polycrystalline oxide active portion to optimize the ohmic contact characteristics with the second drain electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic structural diagram of a display panel of the present invention;

[0019] Figure 2 It is a schematic structural diagram of preparing a light-shielding layer on a substrate according to the present invention;

[0020] Figure 3 is Figure 2 Schematic diagram of the structure of preparing a buffer layer, a barrier layer, a first active layer and a second active layer based on the above;

[0021] Figure 4It is a schematic diagram of the structure of etching using a half-tone mask;

[0022] Figure 5 It is a schematic diagram of the structure after etching using a half-tone mask;

[0023] Figure 6 It is a schematic structural diagram of preparing a gate insulating layer and a first metal layer on the second active layer;

[0024] Figure 7 It is a schematic diagram of the structure of preparing an interlayer insulating layer on the first metal layer;

[0025] Figure 8 It is a schematic diagram of the structure of preparing a second metal layer on the interlayer insulating layer;

[0026] Figure 9 It is a schematic diagram of the structure of preparing a passivation layer and a flat layer on the second metal layer.

[0027] Description of reference numerals:

[0028] 100. Display panel;

[0029] 1. Substrate; 2. Light-shielding layer;

[0030] 3. Buffer layer; 4. Barrier layer;

[0031] 5. First active layer; 6. Second active layer;

[0032] 7. Gate insulating layer; 8. First metal layer;

[0033] 9. Interlayer insulation layer; 10. Second metal layer;

[0034] 11. Passivation layer; 12. Flat layer;

[0035] 13. pixel electrode; 14. first active material layer;

[0036] 15. Second active material layer; 16. Halftone mask;

[0037] 17. Photoresist layer;

[0038] 51. First amorphous oxide active portion; 52. Second amorphous oxide active portion;

[0039] 511, first channel portion; 512, first contact portion;

[0040] 513, second contact portion; 521, second channel portion;

[0041] 522, third contact portion; 523, fourth contact portion;

[0042] 61. First polycrystalline oxide active portion; 62. Second polycrystalline oxide active portion;

[0043] 63. a third polycrystalline oxide active portion;

[0044] 71. A first gate insulating unit; 72. A second gate insulating unit;

[0045] 81. First gate; 82. Second gate;

[0046] 101. First drain; 102. First source;

[0047] 103. A second drain electrode; 104. A second source electrode;

[0048] 161, shading area; 162, semi-transparent area;

[0049] 163. Fully transparent area. DETAILED DESCRIPTION

[0050] The following describes in detail preferred embodiments of the present invention in conjunction with the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, to illustrate that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the scope of the present invention.

[0051] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate the present invention, and are not used to limit the scope of protection of the present invention.

[0052] In the accompanying drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for ease of understanding and description, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

[0053] Example 1

[0054] like Figure 1 As shown, this embodiment provides a display panel 100. The display panel 100 includes: a substrate 1, a light shielding layer 2, a buffer layer 3, a barrier layer 4, a first active layer 5, a second active layer 6, a gate insulating layer 7, a first metal layer 8, an interlayer insulating layer 9, a second metal layer 10, a passivation layer 11, a planarization layer 12, and a pixel electrode 13.

[0055] The material of the substrate 1 includes polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, etc. In this embodiment, the material of the substrate 1 is polyimide, so the substrate 1 has good impact resistance and can effectively protect the display panel 100 .

[0056] The light shielding layer 2 is disposed on the substrate 1. The light shielding layer 2 has a three-layer structure, with a lower layer comprising one or more of Mo, Ti, and Ni, a middle layer comprising Cu or a Cu alloy, and an upper layer comprising one or more of Mo, Ti, and Ni. The lower layer has a thickness ranging from 50 angstroms to 500 angstroms, the middle layer has a thickness ranging from 2,000 angstroms to 10,000 angstroms, and the upper layer has a thickness ranging from 50 angstroms to 500 angstroms.

[0057] The buffer layer 3 is disposed on the side of the light-shielding layer 2 away from the substrate 1 and extends over the substrate 1. The buffer layer 3 primarily serves as a buffer and is made of one or more of SiOx and SiNx. The thickness of the buffer layer 3 ranges from 2000 angstroms to 10,000 angstroms.

[0058] Wherein, the barrier layer 4 is arranged on the side of the buffer layer 3 away from the substrate 1. The material of the barrier layer 4 includes: one or more of aluminum oxide (AlOx), hafnium oxide (HfO2), zirconium oxide (ZrO2) and yttrium oxide (Y2O3). In this embodiment, the material of the barrier layer 4 is aluminum oxide. The thickness of the barrier layer 4 ranges from 100 angstroms to 500 angstroms. Since the material of the first active layer is amorphous oxide and the material of the second active layer is polycrystalline oxide, the barrier layer 4 is mainly used to prevent hydrogen or water vapor from affecting the characteristics of the first active layer and the second active layer, thereby improving the reliability of the display panel 100.

[0059] The first active layer 5 is disposed on a side of the barrier layer 4 away from the substrate 1. The first active layer 5 is made of amorphous oxide. The thickness of the first active layer 5 ranges from 100 angstroms to 1000 angstroms. The first active layer 5 includes a first amorphous oxide active portion 51 and a second amorphous oxide active portion 52 spaced apart from each other.

[0060] The first amorphous oxide active portion 51 includes a first channel portion 511 and first and second contacts 512 and 513 located at both ends of the first channel portion 511. The second amorphous oxide active portion 52 includes a second channel portion 521 and third and fourth contacts 522 and 523 located at both ends of the second channel portion 521.

[0061] The light shielding layer 2 is provided corresponding to the first amorphous oxide active portion 51. In this embodiment, the projection of the first amorphous oxide active portion 51 on the substrate 1 falls within the projection of the light shielding layer 2 on the substrate 1.

[0062] The second active layer 6 is disposed on a side of the first active layer 5 away from the substrate 1. The second active layer 6 is made of polycrystalline oxide. The thickness of the second active layer 6 ranges from 100 angstroms to 500 angstroms. The second active layer 6 includes a first polycrystalline oxide active portion 61, a second polycrystalline oxide active portion 62, and a third polycrystalline oxide active portion 63, which are spaced apart from each other.

[0063] The first polycrystalline oxide active portion 61 is disposed corresponding to the first channel portion 511 , the second polycrystalline oxide active portion 62 is disposed corresponding to the third contact portion 522 , and the third polycrystalline oxide active portion 63 is disposed corresponding to the fourth contact portion 523 .

[0064] This embodiment utilizes the high mobility of polycrystalline oxide, its on-current similar to that of LTPS, its lower off-current, and its improved large-scale uniformity to improve the poor large-scale uniformity of LTPO backplane technology. A first polycrystalline oxide active portion 61 is formed on the first channel portion 511 of the first amorphous oxide active portion 51. The stacked structure formed by the first channel portion 511 and the first polycrystalline oxide active portion 61 creates a high-mobility carrier channel. The single-layer structure of the first contact portion 512 and the second contact portion 513 achieves a low off-current.

[0065] In this embodiment, a second polycrystalline oxide active portion 62 and a third polycrystalline oxide active portion 63 are respectively prepared on the third contact portion 522 and the fourth contact portion 523 of the second amorphous oxide active portion 52, and the single-layer structure of the second channel portion 521 is utilized to achieve high stability and low cut-off current; the stacked structure of the third contact portion 522 and the second polycrystalline oxide active portion 62 is utilized to optimize the ohmic contact characteristics with the second drain 103; and the stacked structure of the fourth contact portion 523 and the third polycrystalline oxide active portion 63 is utilized to optimize the ohmic contact characteristics with the second source 104.

[0066] The gate insulating layer 7 is provided on a side of the second active layer 6 away from the substrate 1. The material of the gate insulating layer 7 includes one or more of aluminum oxide (AlOx), hafnium oxide (HfO2), zirconium oxide (ZrO2) and yttrium oxide (Y2O3). In this embodiment, the material of the gate insulating layer 7 is aluminum oxide. The thickness of the gate insulating layer 7 ranges from 500 angstroms to 1000 angstroms. The gate insulating layer 7 includes a first gate insulating unit 71 and a second gate insulating unit 72 respectively provided corresponding to the first channel portion 511 and the second channel portion 521. The first gate insulating unit 71 is used to prevent a short circuit phenomenon between the first channel portion 511 and the first gate 81. The second gate insulating unit 72 is used to prevent a short circuit phenomenon between the second channel portion 521 and the second gate 82.

[0067] The first metal layer 8 is disposed on the side of the gate insulating layer 7 away from the substrate 1. The first metal layer 8 has a three-layer structure, with the lower layer comprising one or more of Mo, Ti, and Ni, the middle layer comprising Cu or a Cu alloy, and the upper layer comprising one or more of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2,000 angstroms to 10,000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms. The first metal layer 8 includes a first gate 81 and a second gate 82, which are respectively disposed corresponding to the first channel portion 511 and the second channel portion 521.

[0068] The interlayer insulating layer 9 is disposed on a side of the first metal layer 8 away from the substrate 1 and extends over the barrier layer 4. The thickness of the interlayer insulating layer 9 ranges from 2000 angstroms to 10000 angstroms. The material of the interlayer insulating layer 9 includes one or more of SiOx and SiNx. In this embodiment, the material of the interlayer insulating layer 9 is SiOx.

[0069] The second metal layer 10 is arranged on the side of the interlayer insulating layer 9 away from the substrate 1. The second metal layer 10 has a three-layer structure, wherein the lower layer includes one or more of Mo, Ti, and Ni, the middle layer is Cu or a Cu alloy, and the upper layer includes one or more of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms. The second metal layer 10 includes a first drain 101, a first source 102, a second drain 103, and a second source 104 spaced apart from each other. The first drain 101, the first source 102, the second drain 103, and the second source 104 are electrically connected to the first contact portion 512, the second contact portion 513, the third contact portion 522, and the fourth contact portion 523, respectively.

[0070] The passivation layer 11 is disposed on a side of the second metal layer 10 away from the substrate 1. The passivation layer 11 is made of one or more of SiOx and SiNx. In this embodiment, the passivation layer 11 is made of SiOx. The thickness of the passivation layer 11 ranges from 1000 angstroms to 5000 angstroms.

[0071] The planar layer 12 is disposed on a side of the passivation layer 11 away from the substrate 1. The material of the planar layer 12 is an organic layer.

[0072] The pixel electrode 13 is disposed on a side of the planar layer 12 away from the substrate 1 and is electrically connected to the first drain electrode 101. Specifically, the pixel electrode 13 is electrically connected to the first drain electrode 101 through a via hole penetrating the planar layer and the passivation layer. The pixel electrode 13 may have a stacked structure of indium tin oxide / silver / indium tin oxide / .

[0073] This embodiment also provides a method for preparing the display panel of this embodiment, which includes the following steps.

[0074] like Figure 2 As shown, a substrate 1 is provided, and a light shielding layer 2 is prepared on the substrate 1 .

[0075] like Figure 3 As shown, a buffer layer 3 is formed on the side of the light shielding layer 2 away from the substrate 1, and the buffer layer 3 extends and covers the substrate 1. A barrier layer 4 is formed on the side of the buffer layer 3 away from the substrate 1.

[0076] like Figure 3 and Figure 4As shown, a first active layer 5 and a second active layer 6 are formed on the side of the barrier layer 4 away from the substrate 1. Specifically, an amorphous oxide is formed on the side of the barrier layer 4 away from the substrate 1 to form a first active material layer 14; and a polycrystalline oxide is formed on the side of the first active material layer 14 away from the substrate 1 to form a second active material layer 15. The first active material layer 14 is divided into a first channel portion 511, a second channel portion 521, a first contact portion 512, a second contact portion 513, a third contact portion 522, and a fourth contact portion 523. The second active material layer 15 and the first active material layer 14 are etched using a halftone mask 16. The halftone mask 16 includes a light-shielding area 161, a semi-transparent area 162, and a fully-transparent area 163. The light-shielding area 161 is provided corresponding to the first channel portion 511, the third contact portion 522, and the fourth contact portion 523, and the semi-transparent area 162 is provided corresponding to the first contact portion 512, the second contact portion 513, and the second channel portion 521. A photoresist layer 17 is provided on a side away from the substrate 1 at locations of the second active portion material layer 15 corresponding to the first channel portion 511, the second channel portion 521, the first contact portion 512, the second contact portion 513, the third contact portion 522, and the fourth contact portion 523. The photoresist layer 17 corresponding to the first contact portion 512, the second contact portion 513, and the second channel portion 521 is thinned through an exposure and development process. In this embodiment, the thickness of the photoresist layer 17 corresponding to the first contact portion 512, the second contact portion 513, and the second channel portion 521 is the same, the thickness of the photoresist layer 17 corresponding to the first channel portion 511, the third contact portion 522, and the fourth contact portion 523 is the same, and the thickness of the photoresist layer 17 corresponding to the first contact portion 512 is less than the thickness of the photoresist layer 17 corresponding to the third contact portion 522. The first active portion material layer 14 and the second active portion material layer 15 are etched by a dry etching process to form Figure 5 After the etching is completed, the photoresist layer 17 needs to be stripped off to form Figure 3 structure.

[0077] like Figure 4As shown, the second active portion material layer 15 is etched into a first polycrystalline oxide active portion 61, a second polycrystalline oxide active portion 62, and a third polycrystalline oxide active portion 63 that are spaced apart from each other, and the first active portion material layer 14 is etched into a first amorphous oxide active portion 51 and a second amorphous oxide active portion 52 that are spaced apart from each other. The first polycrystalline oxide active portion 61 is disposed correspondingly to the first channel portion 511; the second polycrystalline oxide active portion 62 is disposed correspondingly to the third contact portion 522; and the third polycrystalline oxide active portion 63 is disposed correspondingly to the fourth contact portion 523.

[0078] This embodiment utilizes the high mobility of polycrystalline oxide, its on-current similar to that of LTPS, its lower off-current, and its improved large-scale uniformity to improve the poor large-scale uniformity of LTPO backplane technology. A first polycrystalline oxide active portion 61 is formed on the first channel portion 511 of the first amorphous oxide active portion 51. The stacked structure formed by the first channel portion 511 and the first polycrystalline oxide active portion 61 creates a high-mobility carrier channel. The single-layer structure of the first contact portion 512 and the second contact portion 513 achieves a low off-current.

[0079] In this embodiment, a second polycrystalline oxide active portion 62 and a third polycrystalline oxide active portion 63 are respectively prepared on the third contact portion 522 and the fourth contact portion 523 of the second amorphous oxide active portion 52, and the single-layer structure of the second channel portion 521 is utilized to achieve high stability and low cut-off current; the stacked structure of the third contact portion 522 and the second polycrystalline oxide active portion 62 is utilized to optimize the ohmic contact characteristics with the second drain 103; and the stacked structure of the fourth contact portion 523 and the third polycrystalline oxide active portion 63 is utilized to optimize the ohmic contact characteristics with the second source 104.

[0080] In this embodiment, the first active portion material layer 14 and the second active portion material layer 15 are etched simultaneously using a half-tone mask, which is beneficial to reducing process complexity and improving process yield.

[0081] like Figure 6 As shown, a gate insulating layer 7 is formed on the side of the second active layer 6 away from the substrate 1. A first metal layer 8 is formed on the side of the gate insulating layer 7 away from the substrate 1. The first gate 81 and the second gate 82 are formed simultaneously, which helps reduce process complexity and improve process yield.

[0082] Specifically, it also includes a top-gate self-aligned structure formed by the gate insulating layer 7 and the first metal layer 8, and the use of He Plasma to realize the conductorization of the single layer of amorphous oxide of the first contact part 512, the single layer of amorphous oxide of the second contact part 513, the stacked layer of amorphous oxide and polycrystalline oxide of the third contact part 522, and the stacked layer of amorphous oxide and polycrystalline oxide of the fourth contact part 523.

[0083] like Figure 7 As shown, an interlayer insulating layer 9 is formed on the side of the first metal layer 8 away from the substrate 1. Specifically, the process further includes patterned etching to form contact holes for the first drain 101, the first source 102, the second drain 103, and the second source 104.

[0084] like Figure 8 As shown, a second metal layer 10 is formed on a side of the interlayer insulating layer 9 away from the substrate 1 .

[0085] like Figure 9 As shown, a passivation layer 11 and a planar layer 12 are sequentially formed on the side of the second metal layer 10 away from the substrate 1. Specifically, a contact hole for the pixel electrode 13 is patterned using a half-tone mask.

[0086] The above is a detailed introduction to a display panel and a preparation method thereof provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: substrate; A first active layer is provided on the substrate and is made of amorphous oxide, comprising a first amorphous oxide active portion and a second amorphous oxide active portion spaced apart from each other; a second active layer, disposed on a side of the first active layer away from the substrate, made of polycrystalline oxide and comprising a first polycrystalline oxide active portion, a second polycrystalline oxide active portion, and a third polycrystalline oxide active portion spaced apart from each other; The first amorphous oxide active portion includes a first channel portion and a first contact portion and a second contact portion respectively located at two ends of the first channel portion, and the first polycrystalline oxide active portion is disposed corresponding to the first channel portion; The second amorphous oxide active portion includes a second channel portion and a third contact portion and a fourth contact portion respectively located at two ends of the second channel portion. The second polycrystalline oxide active portion is arranged corresponding to the third contact portion, and the third polycrystalline oxide active portion is arranged corresponding to the fourth contact portion.

2. The display panel according to claim 1, wherein: Also includes: a light shielding layer disposed between the substrate and the first active layer and corresponding to the first amorphous oxide active portion; a buffer layer, disposed between the light shielding layer and the first active layer; as well as The barrier layer is disposed between the buffer layer and the first active layer.

3. The display panel according to claim 2, wherein: Also includes: a gate insulating layer, disposed on a side of the second active layer away from the substrate, comprising a first gate insulating unit and a second gate insulating unit respectively disposed corresponding to the first channel portion and the second channel portion; a first metal layer, disposed on a side of the gate insulating layer away from the substrate, comprising a first gate and a second gate disposed corresponding to the first channel portion and the second channel portion, respectively; an interlayer insulating layer, disposed on a side of the first metal layer away from the substrate and extending to cover the barrier layer; a second metal layer, disposed on a side of the interlayer insulating layer away from the substrate, comprising a first drain, a first source, a second drain, and a second source spaced apart from each other, wherein the first drain, the first source, the second drain, and the second source are electrically connected to the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion, respectively; a passivation layer, disposed on a side of the second metal layer away from the substrate; a planar layer, disposed on a side of the passivation layer away from the substrate; as well as The pixel electrode is disposed on a side of the planar layer away from the substrate and is electrically connected to the first drain.

4. The display panel according to claim 2, wherein: A projection of the first amorphous oxide active portion on the substrate falls within a projection of the light shielding layer on the substrate.

5. The display panel according to claim 2, wherein: The material of the barrier layer includes: one or more of aluminum oxide, hafnium oxide, zirconium oxide and yttrium oxide; the thickness of the barrier layer ranges from 100 angstroms to 500 angstroms.

6. A method for preparing a display panel, characterized in that: The following steps are involved: providing a substrate; preparing an amorphous oxide on the substrate to form a first active material layer; Forming a second active portion material layer by forming a polycrystalline oxide on a side of the first active portion material layer away from the substrate; Using a halftone mask, etching the second active portion material layer and the first active portion material layer, wherein the second active portion material layer is etched into a first polycrystalline oxide active portion, a second polycrystalline oxide active portion, and a third polycrystalline oxide active portion that are spaced apart from each other, and the first active portion material layer is etched into a first amorphous oxide active portion and a second amorphous oxide active portion that are spaced apart from each other; The first amorphous oxide active portion includes a first channel portion and a first contact portion and a second contact portion respectively located at two ends of the first channel portion, and the first polycrystalline oxide active portion is disposed corresponding to the first channel portion; The second amorphous oxide active portion includes a second channel portion and a third contact portion and a fourth contact portion respectively located at two ends of the second channel portion. The second polycrystalline oxide active portion is arranged corresponding to the third contact portion, and the third polycrystalline oxide active portion is arranged corresponding to the fourth contact portion.

7. The method for manufacturing a display panel according to claim 6, wherein: The step of etching the second active portion material layer and the first active portion material layer using a halftone mask comprises: dividing the first active portion material layer into the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion; The halftone mask includes a light-shielding area, a semi-transparent area, and a fully transparent area. The light-shielding area is corresponding to the first channel portion, the third contact portion, and the fourth contact portion. The semi-transparent area is corresponding to the first contact portion, the second contact portion, and the second channel portion.

8. The method for manufacturing a display panel according to claim 7, wherein: The step of etching the second active portion material layer and the first active portion material layer using a halftone mask further comprises: Disposing a photoresist layer on a side away from the substrate at positions of the second active portion material layer corresponding to the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion; The photoresist layer corresponding to the first contact portion, the second contact portion, and the second channel portion is thinned through an exposure and development process.

9. The method for manufacturing a display panel according to claim 8, wherein: The thickness of the photoresist layer corresponding to the first contact portion, the second contact portion, and the second channel portion is the same, and the thickness of the photoresist layer corresponding to the first channel portion, the third contact portion, and the fourth contact portion is the same.

10. The method for manufacturing a display panel according to claim 8, wherein: The step of etching the second active portion material layer and the first active portion material layer using a halftone mask further comprises: etching the first active portion material layer and the second active portion material layer by a dry etching process; and The photoresist layer is removed by stripping.

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