Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel; the array substrate is provided with a padding structure under the second connecting line so that the padding structure is provided beyond the second connecting line on the side close to the via hole, and the third connecting line is overlapped on the second connecting line and the part of the padding structure that exceeds the second connecting line, and the third connecting line passes through the via hole to connect to the first connecting line, so that the third connecting line can connect the first connecting line and the second connecting line, realizing the line rotation of the first connecting line, and reducing the frame of the array substrate compared to the double-hole connection method. At the same time, the padding structure can increase the distance between the first connecting line and the second connecting line, thereby reducing the probability of static electricity generation and improving the yield of the array substrate, taking into account the high yield and narrow frame of the array substrate when the first connecting line and the second connecting line are connected through the third connecting line.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In a display device, the signal lines in the gate layer are connected to the connecting lines in the source / drain layer, and then connected to the driver chip through the connecting lines in the source / drain layer to realize the scanning function of the display device. In the production process of existing display devices, in order to reduce the number of masks, thereby reducing costs and improving production efficiency, electrodes in the pixel electrode layer are used to bridge the signal lines in the gate layer and the connecting lines in the source / drain layer. Specifically, the existing methods of bridging the signal lines and connecting lines by electrodes in the pixel electrode layer include a half-overlapping hole method and a double-hole connection method. However, the half-overlapping hole method is prone to electrostatic damage to the electrodes in the pixel electrode layer, resulting in a low yield of the display device. The double-hole connection method has the problem of occupying a large space, resulting in a larger bezel of the display device.

[0003] Therefore, in existing display devices, the method of connecting signal lines and connection lines through electrodes in the pixel electrode layer has a technical problem of not being able to achieve both high yield and narrow frame. Summary of the Invention

[0004] Embodiments of the present application provide an array substrate and a display panel to alleviate the technical problem in existing display devices that a method of connecting signal lines and connection lines through electrodes in a pixel electrode layer cannot achieve both high yield and narrow bezel.

[0005] An embodiment of the present application provides an array substrate, which includes:

[0006] substrate;

[0007] A first metal layer is provided on one side of the substrate, wherein the first metal layer includes a first connecting line;

[0008] a gate insulating layer, disposed on a side of the first metal layer away from the substrate, the gate insulating layer comprising a via;

[0009] a second metal layer, disposed on a side of the gate insulating layer away from the first metal layer, the second metal layer comprising a second connecting line;

[0010] a pixel electrode layer, disposed on a side of the second metal layer away from the gate insulating layer, the pixel electrode layer including a third connecting line;

[0011] In which, the array substrate also includes a padding structure, which is arranged between the second connecting line and the gate insulation layer, and the padding structure is arranged beyond the second connecting line on the side close to the via hole. The third connecting line is overlapped on the second connecting line and the part of the padding structure that exceeds the second connecting line, and the third connecting line passes through the via hole to connect to the first connecting line, and the padding structure is insulated from the second connecting line.

[0012] In some embodiments, the array substrate further includes an active layer, the active layer is disposed between the gate insulating layer and the second metal layer, the active layer includes an active pattern and the padding structure, and the padding structure is insulated from the active pattern.

[0013] In some embodiments, the active pattern includes a doping portion and a channel portion, and a doping ion concentration of the pad structure is greater than or equal to a doping ion concentration of the channel portion.

[0014] In some embodiments, the doping portion includes a first doping portion and a second doping portion, the second doping portion is arranged between the first doping portion and the channel portion, the doping ion concentration of the second doping portion is greater than the doping ion concentration of the channel portion, the doping ion concentration of the second doping portion is less than the doping ion concentration of the first doping portion, the doping ion concentration of the padding structure is equal to the doping ion concentration of the second doping portion, or the doping ion concentration of the padding structure is equal to the doping ion concentration of the channel portion.

[0015] In some embodiments, the doped portion includes multiple parts, the second metal layer also includes a source and a drain, the source and the drain are respectively connected to the multiple parts of the doped portion, the doped portion is in contact with the channel portion, and the doping ion concentration of the padding structure is equal to the doping ion concentration of the channel portion.

[0016] In some embodiments, the array substrate further includes a padding layer and an active layer, the padding layer is disposed between the gate insulating layer and the second metal layer, and the padding layer includes the padding structure.

[0017] In some embodiments, a projection of the pad structure on the substrate contacts a projection of the via on the substrate.

[0018] In some embodiments, a distance between a side surface of the pad structure close to the via hole and a side surface of the second connecting line close to the via hole is greater than or equal to 1 micron.

[0019] In some embodiments, the material of the pad structure includes one of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide.

[0020] At the same time, an embodiment of the present application provides a display panel, which includes the array substrate as described in any of the above embodiments.

[0021] Beneficial effects: The present application provides an array substrate and a display panel; the array substrate includes a substrate, a first metal layer, a gate insulating layer, a second metal layer and a pixel electrode layer, the first metal layer is arranged on one side of the substrate, the first metal layer includes a first connecting line, the gate insulating layer is arranged on a side of the first metal layer away from the substrate, the gate insulating layer includes a via, the second metal layer is arranged on a side of the gate insulating layer away from the first metal layer, the second metal layer includes a second connecting line, the pixel electrode layer is arranged on a side of the second metal layer away from the gate insulating layer, the pixel electrode layer includes a third connecting line, wherein the array substrate also includes a padding structure, the padding structure is arranged between the second connecting line and the gate insulating layer, the padding structure is arranged on a side close to the via and exceeds the second connecting line, the third connecting line is overlapped on the second connecting line and the part of the padding structure exceeding the second connecting line, and the third connecting line passes through the via to connect to the first connecting line, and the padding structure is insulated from the second connecting line. The present application sets a padding structure under the second connecting line so that the padding structure is set beyond the second connecting line on the side close to the via hole. The third connecting line is overlapped on the second connecting line and the part of the padding structure that exceeds the second connecting line, and the third connecting line passes through the via hole to connect to the first connecting line, so that the third connecting line can connect the first connecting line and the second connecting line, thereby realizing the line rotation of the first connecting line and reducing the border of the array substrate compared to the double-hole connection method. At the same time, the padding structure can increase the distance between the first connecting line and the second connecting line, thereby reducing the probability of static electricity generation and improving the yield of the array substrate, taking into account the high yield and narrow border of the array substrate when the first connecting line and the second connecting line are connected through the third connecting line. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0023] Figure 1 A schematic diagram of an existing display device.

[0024] Figure 2 This is a first schematic diagram of an array substrate provided in an embodiment of the present application.

[0025] Figure 3 This is a second schematic diagram of the array substrate provided in an embodiment of the present application.

[0026] Figure 4 Schematic diagram of an array substrate corresponding to each step of the method for preparing an array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0028] like Figure 1 As shown, Figure 1 (a) is a schematic diagram of a display device in which electrodes are connected to signal lines and connection lines using half-lapped holes. Figure 1 (b) is a schematic diagram of a display device in which electrodes use double holes to connect signal lines and connection lines. Figure 1 As shown, the display device includes a substrate 11, a signal line 12, a first insulating layer 13, a connecting line 14, a second insulating layer 15 and an electrode 16. Figure 1 As shown in (a) of FIG, in order to reduce the number of masks used in the manufacturing process, the existing display device uses a half-lapped hole method to connect the signal line 12 and the connecting line 14 through the electrode 16. However, since the side of the connecting line 14 close to the via hole is close to the signal line 12 in the via hole, the connecting line 14 is prone to tip discharge, which may burn out the electrode 16 and make the connection between the connecting line 14 and the signal line 12 invalid. Figure 1 As shown in (b) of Figure 1, existing display devices use dual vias to connect signal line 12 and connection line 14 to address the issues associated with the semi-lapped via method. Specifically, the distance between signal line 12 and connection line 14 is increased, allowing electrode 16 to connect to signal line 12 and connection line 14 through two vias, respectively. However, this approach results in a larger bezel for the display device. Therefore, the existing display device method of connecting signal lines and connection lines through electrodes in the pixel electrode layer suffers from the technical problem of being unable to achieve both high yield and a narrow bezel.

[0029] In response to the above technical problems, embodiments of the present application provide an array substrate and a display panel to alleviate the above technical problems.

[0030] like Figure 2 As shown, an embodiment of the present application provides an array substrate, and the array substrate 2 includes:

[0031] substrate 21;

[0032] A first metal layer 22 is provided on one side of the substrate 21 , and the first metal layer 22 includes a first connecting line 221 ;

[0033] a gate insulating layer 23 , disposed on a side of the first metal layer 22 away from the substrate 21 , the gate insulating layer 23 including a via 231 ;

[0034] A second metal layer 25 is disposed on a side of the gate insulating layer 23 away from the first metal layer 22 , and the second metal layer 25 includes a second connecting line 251 ;

[0035] a pixel electrode layer 31 disposed on a side of the second metal layer 25 away from the gate insulating layer 23 , the pixel electrode layer 31 including a third connecting line 311 ;

[0036] In which, the array substrate 2 also includes a padding structure 32, which is arranged between the second connecting line 251 and the gate insulation layer 23, and the padding structure 32 is arranged beyond the second connecting line 251 on the side close to the via 231. The third connecting line 311 is overlapped on the second connecting line 251 and the part of the padding structure 32 that exceeds the second connecting line 251, and the third connecting line 311 passes through the via 231 to connect to the first connecting line 221, and the padding structure 32 is insulated from the second connecting line 251.

[0037] An embodiment of the present application provides an array substrate, which is provided with a padding structure under the second connecting line so that the padding structure is arranged beyond the second connecting line on a side close to the via hole. The third connecting line is overlapped on the second connecting line and the portion of the padding structure that exceeds the second connecting line, and the third connecting line passes through the via hole to connect to the first connecting line, so that the third connecting line can connect the first connecting line and the second connecting line, thereby realizing the line rotation of the first connecting line and reducing the border of the array substrate compared to the double-hole connection method. At the same time, the padding structure can increase the distance between the first connecting line and the second connecting line, thereby reducing the probability of static electricity generation and improving the yield of the array substrate, taking into account the high yield and narrow border of the array substrate when the first connecting line and the second connecting line are connected through the third connecting line.

[0038] Specifically, such as Figure 2 As shown, a side surface 321 of the padding structure 32 near the via hole 231 extends toward the via hole 231. The side surface 321 of the padding structure 32 near the via hole 231 is located to the right of a side surface 251a of the second connecting line 251 near the via hole 231, so that the padding structure 32 extends beyond the second connecting line 251 on the side near the via hole 231. Specifically, the width of the portion of the padding structure 32 near the via hole 231 that extends beyond the second connecting line 251 is the distance L1 between the side surface 321 of the padding structure 32 near the via hole 231 and the side surface 251a of the second connecting line 251 near the via hole 231.

[0039] Specifically, since the side surface 321 of the padding structure 32 close to the via hole 231 and the side surface 251a of the second connecting line 251 close to the via hole 231 may be inclined surfaces, when determining the spacing between the side surface 321 of the padding structure 32 close to the via hole 231 and the side surface 251a of the second connecting line 251 close to the via hole 231, the rightmost endpoint of the side surface 321 of the padding structure 32 close to the via hole 231 and the rightmost endpoint of the side surface 251a of the second connecting line 251 close to the via hole 231 can be used simultaneously to determine the spacing. However, the embodiments of the present application are not limited to this. For example, the spacing between the two can be determined by the midpoint of the side surface 321 of the padding structure 32 close to the via hole 231 and the midpoint of the side surface 251a of the second connecting line 251 close to the via hole 231. The spacing between the two can also be determined by the leftmost endpoint of the side surface 321 of the padding structure 32 close to the via hole 231 and the leftmost endpoint of the side surface 251a of the second connecting line 251 close to the via hole 231.

[0040] Specifically, in an array substrate, since traces are arranged on different metal layers, some traces need to cross over to connect to binding terminals. Therefore, a second connection line on a second metal layer is connected to a first connection line, thereby achieving crossover of the traces on the first metal layer. For example, if a scan line needs to cross over to the second metal layer to connect to a binding terminal, the first connection line can be a scan line or a trace connecting the scan line. If other signal lines need to cross over to the second metal layer to connect to a binding terminal, the first connection line can also be other signal lines or traces connecting other signal lines.

[0041] Specifically, when the second connecting line is connected to the routing of other film layers, the second connecting line will transmit the signal of the routing of other film layers. Therefore, the second connecting line can be kept insulated from other routings and electrodes in the second metal layer. For example, if the second metal layer includes a data line, a source and a drain, the second connecting line needs to be kept insulated from the data line, the source and the drain.

[0042] Specifically, the third connecting line connects the first connecting line and the second connecting line, and the third connecting line transmits the signal on the first connecting line. Therefore, the third connecting line can be insulated from other signal lines and / or electrodes in the same layer. For example, if the pixel electrode also includes a pixel electrode, the pixel electrode is insulated from the third connecting line.

[0043] Specifically, the padding structure and the second connecting line are insulated from each other, which means that the padding structure is not conductive and will not be connected to the second connecting line.

[0044] In order to solve the problem that setting up the pad structure will increase the process steps of the array substrate and reduce the production efficiency of the array substrate, in one embodiment, Figure 2As shown, the array substrate 2 further includes an active layer 24, which is disposed between the gate insulating layer 23 and the second metal layer 25. The active layer 24 includes an active pattern 241 and the padding structure 32, and the padding structure 32 is insulated from the active pattern 241. By having the active layer include the active pattern and the padding structure, the active pattern and the padding structure can be formed simultaneously when forming the active layer, without having to form the padding structure separately. This eliminates the need to increase the process steps for the array substrate, thereby improving the production efficiency of the array substrate. Moreover, since the active layer includes the padding structure, providing the padding structure does not increase the thickness of the array substrate, thereby reducing the thickness of the array substrate.

[0045] Specifically, such as Figure 2 As shown, the active layer 24 includes an active pattern 241 and a pad structure 32. During the fabrication of the active layer 24, the active pattern 241 and the pad structure 32 can be formed simultaneously using the same mask, eliminating the need for additional process steps or masks. This improves array substrate fabrication efficiency and reduces costs. Furthermore, the pad structure 32 is located within the active layer 24, allowing for adjustment of the thickness of the insulating layer above the pad structure 32, eliminating the need to increase the thickness of the array substrate.

[0046] In one embodiment, if Figure 2 As shown, the active pattern 241 includes a doped portion 241a and a channel portion 241b. The doping ion concentration of the pad structure 32 is greater than or equal to the doping ion concentration of the channel portion 241b. By ensuring that the doping ion concentration of the pad structure is greater than or equal to the doping ion concentration of the channel portion, ion doping can be omitted or partially performed during the formation of the pad structure. This allows the pad structure to be fabricated simultaneously with the active pattern, avoiding additional fabrication steps for the array substrate. Furthermore, the pad structure is insulated from the second connecting line, increasing the distance between the second connecting line and the first connecting line, reducing the probability of static electricity generation, and improving the yield of the display panel.

[0047] Specifically, if the doping ion concentration of the padding structure is greater than or equal to the doping ion concentration of the channel portion, the padding structure may not be ion doped, or the padding structure may be partially ion doped, which will not increase the process steps of the array substrate and can keep the padding structure and the second connecting line insulated.

[0048] In one embodiment, if Figure 3As shown, the doping portion 241a includes a first doping portion 341 and a second doping portion 342. The second doping portion 342 is disposed between the first doping portion 341 and the channel portion 241b. The doping ion concentration of the second doping portion 342 is greater than the doping ion concentration of the channel portion 241b, and less than the doping ion concentration of the first doping portion 341. The doping ion concentration of the padding structure 32 is equal to the doping ion concentration of the second doping portion 342, or the doping ion concentration of the padding structure 32 is equal to the doping ion concentration of the channel portion 241b. By ensuring that the doping ion concentration of the padding structure is equal to the doping ion concentration of the channel portion or the second doping portion, the padding structure can be shielded during formation, without undergoing ion doping, or lightly doped, without increasing the number of processing steps for the array substrate. Furthermore, the padding structure is insulated from the second connecting line, preventing static electricity between the first and second connecting lines, thereby improving the yield of the array substrate.

[0049] Specifically, the doping ion concentration of the second doping part is greater than the doping ion concentration of the channel part, and the doping ion concentration of the second doping part is less than the doping ion concentration of the first doping part. This can avoid the problem of excessive power consumption of the thin film transistor due to the potential barrier between the channel part and the first doping part being too large, and the channel part will not directly contact the first doping part, avoiding the channel being directly turned on and causing leakage of the thin film transistor.

[0050] Specifically, when forming the padding structure, the padding structure and the channel portion can be blocked so that the doping ion concentration of the padding structure is equal to the doping ion concentration of the channel portion. The padding structure and the second doping portion can also be doped at the same time so that the doping ion concentration of the padding structure and the second doping portion are the same.

[0051] In one embodiment, if Figure 2 As shown, the doped portion 241a includes multiple portions, and the second metal layer 25 further includes a source 252 and a drain 253. The source 252 and the drain 253 are respectively connected to the multiple portions of the doped portion 241a. The doped portion 241a is in contact with the channel portion 241b. The doping ion concentration of the padding structure 32 is equal to the doping ion concentration of the channel portion 241b. By ensuring that the doping ion concentration of the padding structure is equal to the doping ion concentration of the channel portion, the padding structure can be shielded during formation, and ion doping is not performed on the padding structure, thereby eliminating the need to increase the process steps of the array substrate. Furthermore, since the padding structure is not ion doped, it is non-conductive, insulated from the second connecting line, and the distance between the first connecting line and the second connecting line is increased, thereby preventing static electricity from being generated between the first connecting line and the second connecting line, and improving the yield of the array substrate.

[0052] In one embodiment, the material of the active layer includes one of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide. By using metal oxide to form the active layer, after the padding structure is formed, the padding structure will not be etched when the gate insulating layer is dry-etched, so that the padding structure can increase the distance between the first connecting line and the second connecting line, and the padding structure can be used as a mask when the gate insulating layer is dry-etched to avoid static electricity and improve the yield of the array substrate.

[0053] Specifically, when a non-metallic oxide is used to form a padding structure, the gate insulating layer needs to be dry-etched later, which will cause the non-metallic oxide to be etched away, and then the non-metallic oxide located under the padding structure will be etched away, and the distance between the first connecting line and the second connecting line cannot be increased. In the embodiment of the present application, by making the material of the active layer a metal oxide, when the gate insulating layer is dry-etched, the padding structure can protect the gate insulating layer located under the padding structure, thereby increasing the distance between the first connecting line and the second connecting line, avoiding the generation of static electricity between the first connecting line and the second connecting line, and improving the yield of the array substrate. Moreover, when dry-etching the gate insulating layer to form a via, the padding structure can be used as a mask, reducing the number of masks and eliminating the need for alignment, thereby improving the preparation efficiency of the array substrate. Moreover, using the padding structure as a mask can reduce static electricity when dry-etching the gate insulating layer, thereby improving the yield of the array substrate.

[0054] In one embodiment, the array substrate further includes a padding layer and an active layer, wherein the padding layer is disposed between the gate insulating layer and the second metal layer, and the padding layer includes the padding structure. When providing the padding structure, the padding layer may be further provided so that the padding layer forms a padding structure, thereby increasing the distance between the first connecting line and the second connecting line, preventing static electricity from being generated between the first connecting line and the second connecting line, and improving the yield of the array substrate.

[0055] In one embodiment, the material of the padding layer includes one of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide. By using a metal oxide to form the padding layer, after the padding structure is formed, the padding structure is not etched away during dry etching of the gate insulation layer. This allows the padding structure to increase the distance between the first connecting line and the second connecting line. Furthermore, the padding structure can serve as a mask during dry etching of the gate insulation layer, preventing static electricity and improving the yield of the array substrate.

[0056] The above embodiments are described in detail using the example of the active layer including the padding structure and the padding layer including the padding structure, but the embodiments of the present application are not limited thereto. For example, the padding structure may include multiple layers, and the active layer and the padding layer may be used to form multiple layers of the padding structure respectively.

[0057] In one embodiment, if Figure 2 As shown, the projection of the pad structure 32 on the substrate 21 contacts the projection of the via 231 on the substrate 21. By making the projection of the pad structure on the substrate contact the projection of the via on the substrate, the pad structure can be used as a mask for etching the gate insulating layer, reducing the number of masks and eliminating the need for alignment, thereby improving the production efficiency of the array substrate. In addition, using the pad structure as a mask can reduce static electricity during dry etching of the gate insulating layer, thereby improving the yield of the array substrate.

[0058] Specifically, after forming each film layer in the array substrate, the gate insulating layer will be etched to form a via hole, so that the third connecting line can pass through the via hole and connect to the first connecting line. By using a padding structure as a mask for etching the gate insulating layer, the side of the padding structure close to the via hole and the side of the via close to the padding structure are on the same straight line. The padding structure can protect the gate insulating layer under the padding structure, so that the distance between the edge of the second connecting line close to the via hole and the part of the first connecting line corresponding to the via hole position is increased, thereby avoiding the generation of static electricity and improving the yield of the array substrate.

[0059] In one embodiment, if Figure 2 As shown, a distance L1 between a side surface 321 of the padding structure 32 on the side near the via hole 231 and a side surface 251a of the second connecting line 251 on the side near the via hole 231 is greater than or equal to 1 micron. By ensuring that the width of the portion of the padding structure on the side near the via hole that extends beyond the second connecting line is greater than or equal to 1 micron, a larger distance is created between the side of the second connecting line near the via hole and the first connecting line at the corresponding via hole location, thereby preventing static electricity from being generated between the first and second connecting lines and improving the yield of the array substrate.

[0060] In one embodiment, the material of the padding structure includes one of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide. By using a metal oxide to form the padding structure, after the padding structure is formed, the padding structure is not etched away during dry etching of the gate insulation layer. This allows the padding structure to increase the distance between the first connecting line and the second connecting line. Furthermore, the padding structure can serve as a mask during dry etching of the gate insulation layer, preventing static electricity and improving the yield of the array substrate.

[0061] In one embodiment, if Figure 2 As shown, the first metal layer 22 further includes a gate 222 , and the gate 222 is insulated from the first connection line 221 .

[0062] In one embodiment, if Figure 2As shown, the array substrate 2 further includes a first passivation layer 26 , an organic layer 27 , a common electrode layer 28 , and a second passivation layer 29 .

[0063] Specifically, in Figure 2 The common electrode layer 28 and the pixel electrode layer 31 are located on the array substrate as an example, but the embodiments of the present application are not limited to this. For example, when the array substrate is applied to a liquid crystal display panel, the common electrode layer can be set on the color film substrate side. When the array substrate is applied to an organic light emitting diode display panel, the array substrate can be set on the light emitting layer.

[0064] In one embodiment, if Figure 2 As shown, the pixel electrode layer 31 further includes a pixel electrode 312 , and the pixel electrode 312 is insulated from the third connection line 311 .

[0065] At the same time, an embodiment of the present application provides a method for preparing an array substrate, which is used to prepare an array substrate as described in any of the above embodiments. The method includes:

[0066] A substrate is provided, and a first metal layer, a gate insulating layer, an active layer, and a second metal layer are sequentially formed on the substrate; the structure of the array substrate corresponding to this step is as follows: Figure 4 As shown in (a);

[0067] A first passivation layer, an organic layer, a common electrode layer, and a second passivation layer are sequentially formed on the second metal layer; the structure of the array substrate corresponding to this step is as follows: Figure 4 As shown in (b);

[0068] The gate insulating layer, the first passivation layer and the second passivation layer are etched to form a via hole; the structure of the array substrate corresponding to this step is as follows Figure 4 As shown in (c);

[0069] A pixel electrode layer is formed on the second passivation layer; the structure of the column substrate corresponding to this step is as follows Figure 2 shown.

[0070] At the same time, an embodiment of the present application provides a display panel, which includes the array substrate as described in any of the above embodiments.

[0071] In one embodiment, the display panel includes a liquid crystal display panel, which includes the array substrate as described in any of the above embodiments, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate.

[0072] In one embodiment, the display panel includes an organic light emitting diode display panel, which includes the array substrate as described in any of the above embodiments, and a light emitting layer and a common electrode layer provided on the array substrate.

[0073] According to the above embodiments, it can be seen that:

[0074] An embodiment of the present application provides an array substrate and a display panel; the array substrate includes a substrate, a first metal layer, a gate insulating layer, a second metal layer and a pixel electrode layer, the first metal layer is arranged on one side of the substrate, the first metal layer includes a first connecting line, the gate insulating layer is arranged on a side of the first metal layer away from the substrate, the gate insulating layer includes a via, the second metal layer is arranged on a side of the gate insulating layer away from the first metal layer, the second metal layer includes a second connecting line, the pixel electrode layer is arranged on a side of the second metal layer away from the gate insulating layer, the pixel electrode layer includes a third connecting line, wherein the array substrate also includes a padding structure, the padding structure is arranged between the second connecting line and the gate insulating layer, the padding structure is arranged on a side close to the via and exceeds the second connecting line, the third connecting line is overlapped on the second connecting line and the part of the padding structure exceeding the second connecting line, and the third connecting line passes through the via to connect to the first connecting line, and the padding structure is insulated from the second connecting line. The present application sets a padding structure under the second connecting line so that the padding structure is set beyond the second connecting line on the side close to the via hole. The third connecting line is overlapped on the second connecting line and the part of the padding structure that exceeds the second connecting line, and the third connecting line passes through the via hole to connect to the first connecting line, so that the third connecting line can connect the first connecting line and the second connecting line, thereby realizing the line rotation of the first connecting line and reducing the border of the array substrate compared to the double-hole connection method. At the same time, the padding structure can increase the distance between the first connecting line and the second connecting line, thereby reducing the probability of static electricity generation and improving the yield of the array substrate, taking into account the high yield and narrow border of the array substrate when the first connecting line and the second connecting line are connected through the third connecting line.

[0075] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0076] The above is a detailed introduction to an electronic device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first metal layer is provided on one side of the substrate, wherein the first metal layer includes a first connecting line; a gate insulating layer, disposed on a side of the first metal layer away from the substrate, the gate insulating layer comprising a via; a second metal layer, disposed on a side of the gate insulating layer away from the first metal layer, the second metal layer comprising a second connecting line; a pixel electrode layer, disposed on a side of the second metal layer away from the gate insulating layer, the pixel electrode layer including a third connecting line; In which, the array substrate also includes a padding structure, which is arranged between the second connecting line and the gate insulation layer, and the padding structure is arranged beyond the second connecting line on the side close to the via hole. The third connecting line is overlapped on the second connecting line and the part of the padding structure that exceeds the second connecting line, and the third connecting line passes through the via hole to connect to the first connecting line, and the padding structure is insulated from the second connecting line.

2. The array substrate according to claim 1, wherein: The array substrate further includes an active layer, which is disposed between the gate insulating layer and the second metal layer. The active layer includes an active pattern and the padding structure, and the padding structure is insulated from the active pattern.

3. The array substrate according to claim 2, wherein: The active pattern includes a doping portion and a channel portion, and a doping ion concentration of the pad structure is greater than or equal to a doping ion concentration of the channel portion.

4. The array substrate according to claim 3, wherein: The doping portion includes a first doping portion and a second doping portion, the second doping portion is arranged between the first doping portion and the channel portion, the doping ion concentration of the second doping portion is greater than the doping ion concentration of the channel portion, the doping ion concentration of the second doping portion is less than the doping ion concentration of the first doping portion, the doping ion concentration of the padding structure is equal to the doping ion concentration of the second doping portion, or the doping ion concentration of the padding structure is equal to the doping ion concentration of the channel portion.

5. The array substrate according to claim 3, wherein: The doped portion includes multiple parts, and the second metal layer also includes a source and a drain, the source and the drain are respectively connected to the multiple parts of the doped portion, the doped portion is in contact with the channel portion, and the doping ion concentration of the padding structure is equal to the doping ion concentration of the channel portion.

6. The array substrate according to claim 1, wherein: The array substrate further includes a padding layer and an active layer. The padding layer is disposed between the gate insulating layer and the second metal layer. The padding layer includes the padding structure.

7. The array substrate according to claim 1, wherein: A projection of the pad structure on the substrate contacts a projection of the via hole on the substrate.

8. The array substrate according to claim 1, wherein: A distance between a side surface of the pad structure close to the via hole and a side surface of the second connecting line close to the via hole is greater than or equal to 1 micron.

9. The array substrate according to claim 1, wherein: The material of the pad structure includes one of indium gallium zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, and indium tin oxide.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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