A high-gain, gain-adjustable low-noise amplifier

Abstract

The application discloses a high-gain, gain-adjustable low-noise amplifier, which comprises an input stage, an amplification stage, an intermediate stage, an output stage and a gain-boosting and gain-controlling stage, is used for improving the gain of the amplifier and performing multi-stage control on the gain, and comprises a gain-boosting capacitor and a gain-controlling switch composed of two transistors.The amplification stage of the application gradually increases the amplitude of a signal and the overall gain by cascading multiple cascode structures, and the gain-boosting capacitor is connected in series between the gate of the second transistor in the cascode structure and a power supply rejection resistor.The application adopts the gain-controlling switch through the setting of the gain-boosting and gain-controlling stage, so that multi-stage control on the gain can be realized, the gain adjustability enables the low-noise amplifier to adapt to different input signal strengths and output requirements, and in different application scenarios, the low-noise amplifier can better adapt to different signal conditions by adjusting the gain.

Description

Technical Field

[0001] This invention relates primarily to the field of radio frequency electronics, and more specifically to the field of wireless communication and radio frequency receiving systems. Background Technology

[0002] Low-noise amplifiers (LNOA) play a crucial role in wireless communication, amplifying weak received signals to enable transmission over longer distances and improve coverage and stability. This is essential for the connectivity and communication of various wireless devices in modern society. With technological advancements, the demands for high integration and miniaturization in radio frequency (RF) electronics are increasing. The design and manufacture of LNOA are critical for achieving highly integrated RF chips and systems. They enable the integration of multiple functional modules onto a single chip, reducing system cost, power consumption, and footprint.

[0003] For example, the cascaded distributed low-noise amplifier provided by Chinese Patent Publication No. CN108336978A has an unadjustable and uncontrollable amplifier gain. Low-noise amplifiers with adjustable gain are of great significance in radio frequency (RF) systems. Low-noise amplifiers with adjustable gain can provide RF systems with greater flexibility, optimized performance, better power consumption control and better signal quality, thereby improving the performance and reliability of the entire system. Summary of the Invention

[0004] 1. The technical problem that the invention aims to solve The present invention provides a high-gain, gain-adjustable, low-noise amplifier to solve the technical problems existing in the background art.

[0005] 2. Technical Solution To achieve the above objectives, the technical solution provided by this invention is: a high-gain, adjustable-gain, low-noise amplifier, comprising: The input stage is an input matching circuit, which includes an input matching capacitor and a source degenerate inductor. It is used to achieve impedance matching and noise matching of the input signal and to receive the input signal. An amplification stage, comprising N cascaded cascode structures, is used to amplify the input signal, where N is an integer greater than or equal to 2, and each stage has the same cascode structure. Intermediate stage, which includes matching inductors and capacitors, is used to match interstage impedance and noise and transmit signals; The output stage is the output matching circuit, which is used for impedance matching and noise matching of the output signal. The gain boost and gain control stage is used to increase the amplifier gain and perform multi-stage gain control. It includes a gain boost capacitor and a gain control switch consisting of two transistors.

[0006] 3. Beneficial effects Compared with the prior art, the technical solution provided by this invention has the following advantages: The amplification stage of this invention increases the signal amplitude and overall gain by cascading multiple cascode structures, making the entire amplification stage stable and noise-free during signal enhancement. This invention can provide high gain, good input-output matching, and improved amplifier linearity.

[0007] This invention employs a gain enhancement technique by connecting the gain enhancement capacitor in series between the gate of the second transistor and the power supply suppression resistor in the cascode structure, thereby making the gain more significant.

[0008] This invention employs a gain control switch through gain enhancement and gain control stage settings, enabling multi-level control of the gain. The gain adjustability allows the low-noise amplifier to adapt to different input signal strengths and output requirements. In different application scenarios, adjusting the gain allows the low-noise amplifier to better adapt to different signal conditions. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the low-noise amplifier of the present invention; Figure 2 The S11 curve is the input-output matching diagram of the low-noise amplifier of the present invention. Figure 3 The input-output matching curve of the low-noise amplifier of the present invention is curve S21. Figure 4 The input-output matching curve of the low-noise amplifier of the present invention is curve S22. Figure 5 This is a noise figure curve of the low-noise amplifier of the present invention; Figure 6 The low-noise amplifier of this invention is connected to different numbers of gain boost capacitors to achieve gain switching control, and the output gain curve S21 is compared. Detailed Implementation

[0010] To facilitate understanding of the present invention, a more complete description of the invention will be given below with reference to the accompanying drawings, which illustrate several embodiments of the invention. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the invention will be more thorough and complete.

[0011] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "page," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0012] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0013] In this invention, unless otherwise explicitly specified and limited, the terms "installed," "connected," "linked," "fixed," and "equipped" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0014] It should be noted that the structures not described in this invention are not related to the design points and improvement directions of this invention, and are the same as or can be implemented using existing technologies, so they will not be elaborated here. Example

[0015] like Figure 1 As shown, a high-gain, gain-adjustable, low-noise amplifier includes: The input stage is the input matching circuit, which includes an input matching capacitor and a source degenerate inductor. It is used to achieve impedance matching and noise matching of the input signal and to receive the input signal. The amplification stage consists of N cascaded cascode structures used to amplify the input signal, where N is an integer greater than or equal to 2, and each cascode structure is identical. Intermediate stage, which includes matching inductors and capacitors, is used to match interstage impedance and noise and transmit signals; The output stage is the output matching circuit, which is used for impedance matching and noise matching of the output signal. The gain boost and gain control stage is used to increase the amplifier gain and perform multi-stage gain control. It includes a gain boost capacitor and a gain control switch consisting of two transistors.

[0016] In this embodiment, the amplifier of the present invention is described using N=3 as an example.

[0017] The input stage includes a first inductor employing an input matching inductor and a third inductor employing a source degenerate inductor. One end of the first inductor is connected to the input signal vin, and the other end is connected to a first capacitor employing a DC blocking capacitor. The other end of the first capacitor is connected to the gate of the first transistor in the first stage cascode structure of the amplifier. One end of the second inductor is connected to the source of the first transistor, and the other end is grounded. One end of the input bias voltage vb1 is connected to the second inductor employing a power supply rejection inductor, and the other end of the second inductor is connected to the gate of the first transistor.

[0018] The first-stage cascode structure includes a first transistor and a second transistor. The gate of the first transistor is connected to the input signal, its source is connected to a source degenerate inductor, and its drain is connected to the source of the second transistor. The gate of the second transistor is connected to a second capacitor and one end of a gain control switch, and its drain is connected to a fourth inductor and a third capacitor. The second capacitor is a gain boost capacitor, the third capacitor is a matching capacitor, and the fourth inductor is an intermediate matching inductor. The input bias voltage vb1 of the first-stage cascode structure is input to the first transistor through the power supply rejection inductor and the second inductor. The second-stage cascode structure includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected to the input signal, its source is connected to the source degenerate inductor, and its drain is connected to the source of the eighth transistor. The gate of the eighth transistor is connected to the fourth capacitor (which uses a gain boost capacitor) and one end of the gain control switch. Its drain is connected to the seventh inductor (which uses an output stage matching inductor) and one end of the fifth capacitor (which uses a matching capacitor). The input bias voltage VB2 of the second-stage cascode structure is input to the seventh transistor through the fifth inductor of the power supply rejection inductor. The third-stage cascode structure includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is connected to the input signal, its source is connected to the source degenerate inductor, and its drain is connected to the source of the twelfth transistor. The gate of the twelfth transistor is connected to the sixth capacitor (which is a gain boost capacitor) and one end of the gain control switch. Its drain is connected to one end of the tenth inductor, the seventh capacitor, and the eighth capacitor. The tenth inductor is an output stage matching inductor, and the seventh and eighth capacitors are matching capacitors. The input bias voltage VB3 of the third-stage cascode structure is input to the eleventh transistor through the power supply rejection inductor and the eighth inductor. The intermediate matching structure between the first-level cascode structure and the second-level cascode structure includes a fourth inductor, a third capacitor, and a sixth inductor using a source degenerate inductor. One end of the fourth inductor is connected to the drain of the second transistor, and the other end is connected to the power supply. One end of the third capacitor is connected to the drain of the second transistor, and the other end is connected to the gate of the seventh transistor. The intermediate matching structure between the second-level cascode structure and the third-level cascode structure includes a seventh inductor, a fifth capacitor, and a ninth inductor using a source degenerate inductor. One end of the seventh inductor is connected to the drain of the eighth transistor, and the other end is connected to the power supply. One end of the fifth capacitor is connected to the drain of the seventh transistor, and the other end is connected to the gate of the eleventh transistor.

[0019] The output stage includes a tenth inductor, a seventh capacitor, and an eighth capacitor, all of which use output matching inductors. One end of the tenth inductor is connected to the drain of the twelfth transistor, and the other end is connected to the power supply. One end of the seventh capacitor is connected to the drain of the twelfth transistor, and the other end is grounded. One end of the eighth capacitor is connected to the drain of the twelfth transistor, and the other end is connected to the output vout.

[0020] The first-level cascode structure also includes a first resistor with a power supply suppression resistor, a second capacitor connected in series between the second transistor and the first resistor, one end of the second capacitor connected to the gate of the second transistor, the other end connected to the first resistor, and the other end of the first resistor connected to the power supply. The second-level cascode structure also includes a second resistor with a power supply suppression resistor, a fourth capacitor connected in series between the eighth transistor and the second resistor, one end of the second capacitor connected to the gate of the eighth transistor, the other end connected to the second resistor, and the other end of the second resistor connected to the power supply. The third-level cascode structure also includes a third resistor with a power supply suppression resistor, a sixth capacitor connected in series between the twelfth transistor and the third resistor, one end of the sixth capacitor connected to the gate of the twelfth transistor and the other end connected to the third resistor, and the other end of the third resistor connected to the power supply.

[0021] In the gain boost and gain control stage, a gain control switch is connected in parallel across the gain boost capacitor. This switch consists of a PMOS transistor and an NMOS transistor. The drains of both the PMOS and NMOS transistors are connected to the gate of the second transistor in a cascode structure, and their sources are connected to a power supply rejection resistor. The gates are connected to a switching voltage signal. The switching voltage signals of the NMOS and PMOS transistors are inverted by an inverter. The second transistor consists of transistors 2, 8, and 12. The first transistor consists of transistors 1, 7, and 11.

[0022] The input stage is used to implement wideband input matching and noise matching, receiving and amplifying the input signal. The input stage includes a first-stage cascode structure and an input matching circuit. The first-stage cascode structure consists of a first transistor and a second transistor. The input matching network includes a first inductor and a source-degenerate inductor (third inductor).

[0023] The intermediate stage is used to transmit the signal from the input stage to the output stage and perform two-stage signal amplification. The intermediate stage includes a second-stage cascode structure, an input matching circuit, and an output matching circuit. The second-stage cascode structure consists of a seventh and an eighth transistor. The input matching network includes a fourth inductor and a third capacitor, and the output matching network includes a seventh inductor and a fifth capacitor.

[0024] The gain boost and control stage comprises stages for boosting and controlling the amplifier gain. Gain boost capacitors, designated second, fourth, and sixth, are connected in series between the gate of the second transistor in each stage's cascode structure and the power supply rejection resistor. A gain control switch, consisting of an NMOS transistor and a PMOS transistor, is connected in parallel across these three capacitors, with the gates of the two transistors receiving opposite input signals to activate the switch. The first-stage control switches are the third and fourth transistors, the second-stage control switches are the fifth and sixth transistors, and the third-stage control switches are the ninth and tenth transistors.

[0025] Furthermore, in the three-stage cascode structure, the source of the first transistor is connected in series with a source degenerate inductor, and the other end of the source degenerate inductor is grounded.

[0026] The advantages of adopting the above scheme are: the series source decoupling inductor can adjust the impedance of the input circuit to match the impedance of the preceding signal source. This allows the input signal to be effectively delivered to the transistor's gate, maximizing the cancellation of reflected power. The role of the series source decoupling inductor is to provide additional feedback, increasing the transistor's input impedance. This helps improve the transistor's gain and enhances the overall performance of the low-noise amplifier.

[0027] Furthermore, a DC blocking capacitor is connected in series in front of the gate of the first transistor in the first-stage cascode structure.

[0028] The beneficial effects of adopting the above scheme are as follows: the main purpose of the gate DC series capacitor is to block DC signals, preventing DC voltage from passing through the cascaded structure, allowing only AC signals to enter subsequent amplifier stages. This helps stabilize the amplifier's operating state and prevents DC bias interference, as well as preventing transistor burnout caused by DC bias.

[0029] Furthermore, the input matching inductor connected in series before the first-stage cascode structure, together with the source degenerate inductor and DC blocking capacitor of the first-stage cascode structure, forms an input matching network used to match the real and imaginary parts of the input impedance.

[0030] The advantages of adopting the above scheme are as follows: The input matching network, composed of an inductor and a source degenerate inductor, allows adjustment of the input circuit impedance to match the impedance of the preceding signal source. This maximizes power transfer efficiency, minimizes losses, and reduces echo. Properly matching the input impedance reduces input noise power loss, thereby improving the signal-to-noise ratio of the low-noise amplifier. Matching the input impedance allows the amplifier to better adapt to the input signal, reducing nonlinear distortion and maintaining a linear relationship between the output and input signals.

[0031] Furthermore, the gates of both the three-stage and cascode structures are connected to the power supply, forming a diode connection structure. A power supply rejection resistor and a gain-enhancing capacitor are connected in series between them.

[0032] The advantages of adopting the above scheme are: using a diode equivalent circuit with the gate directly connected to the power supply simplifies the circuit structure and ensures that the transistor operates in the saturation region. The power supply rejection resistor has a very high resistance, typically tens of kiloohms or more. This high-impedance path restricts small signals from directly returning to ground through the power supply, thus preventing small signal leakage to ground. Adding a capacitor in series with the gate, i.e., a gain-enhancing capacitor, reduces the reverse amplification effect of the gate on small signals, thereby increasing the amplifier's gain.

[0033] Furthermore, in the three-stage cascode structure, the drain of the second transistor is connected to an inductive load to the power supply.

[0034] The beneficial effects of adopting the above scheme are: since inductive components do not consume power, they do not introduce additional noise compared to resistive loads, and using inductive loads helps reduce noise.

[0035] Furthermore, the source of the second transistor in the first-stage cascode structure and the gate of the seventh transistor in the second-stage cascode structure, as well as the source of the eighth transistor in the second-stage cascode structure and the gate of the eleventh transistor in the third-stage cascode structure, are connected by DC blocking capacitors.

[0036] The advantages of adopting the above scheme are as follows: In a cascode structure, each stage of the transistor may have a different DC bias voltage. By connecting the DC blocking capacitor, it can be ensured that the DC voltage of each stage will not affect other stages, while reducing nonlinear distortion caused by DC bias. Through the DC blocking capacitor connection, an input matching network can be formed with the inductive load of the previous stage of the cascode structure, and an output matching network can be formed with the source degenerate inductor of the next stage of the cascode structure. This adjusts the input and output impedance of the cascaded structure, allowing the input signal to be better transmitted to subsequent stages, thus improving the overall matching efficiency.

[0037] Furthermore, the drain of the second transistor in the third-stage cascode structure is connected to form an L-type matching network for the output capacitor matching network.

[0038] The advantages of adopting the above scheme are: by matching the real and imaginary parts of the input resistance through the L-shaped output capacitor network, noise is reduced and gain and linearity are improved. At the same time, the matching capacitor can also act as a DC blocking capacitor.

[0039] Furthermore, a gain-boosting capacitor is connected in series between the gate and the power supply suppression resistor of the three-stage cascode transistor.

[0040] The advantage of adopting the above approach is that an appropriate DC bias voltage is typically required at the transistor gate to ensure it operates within the proper operating region. However, the DC bias voltage should not affect the AC portion of the amplified signal. By connecting a capacitor in series, the DC bias voltage can be blocked, preventing it from affecting the passage of the amplified signal and thus maintaining the amplifier's linear performance. Simultaneously, the presence of the capacitor reduces feedback effects from the output to the input, as it presents higher impedance at higher frequencies, thus limiting the propagation of the feedback signal. This helps reduce amplifier stability issues while improving gain.

[0041] Furthermore, gain control switches are connected in parallel across the gain boost capacitors of the three-stage cascode transistors.

[0042] The advantages of adopting the above scheme are that the on and off states of the gain control switch can control whether the gain boost capacitor is connected to the amplifier circuit, thereby achieving gain control. The multi-stage cascode control switch allows for multi-stage control of the overall amplification gain. Simultaneously, the overall noise and matching of the amplifier are not affected by the gain control switch.

[0043] In this implementation, the operating frequency is 2.4 GHz.

[0044] In this implementation, the gain at the 2.4 GHz frequency is 39.4 dB.

[0045] In the implementation example described in this article, the noise figure at the 2.4 GHz frequency is 1.32 dB.

[0046] The above-described embodiments are merely illustrative of certain implementations of the present invention, and are described in a relatively specific and detailed manner. However, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements are all within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A high-gain, gain-adjustable, low-noise amplifier, characterized in that, include: The input stage is an input matching circuit, which includes an input matching capacitor and a source degenerate inductor. It is used to achieve impedance matching and noise matching of the input signal and to receive the input signal. An amplification stage, comprising N cascaded cascode structures, is used to amplify the input signal, where N is an integer greater than or equal to 2, and each stage has the same cascode structure. Intermediate stage, which includes matching inductors and capacitors, is used to match interstage impedance and noise and transmit signals; The output stage, which is the output matching circuit, is used for impedance matching and noise matching of the output signal; and The gain boost and gain control stage is used to increase the amplifier gain and perform multi-stage gain control. It includes a gain boost capacitor and a gain control switch consisting of two transistors. N is 3. The first stage cascode structure includes a first transistor and a second transistor. The gate of the first transistor is connected to the input signal, its source is connected to the source degenerate inductor, and its drain is connected to the source of the second transistor. The gate of the second transistor is connected to a second capacitor and one end of a gain control switch, and its drain is connected to a fourth inductor and a third capacitor. The second capacitor is a gain boost capacitor, the third capacitor is a matching capacitor, and the fourth inductor is an intermediate stage matching inductor. The input bias voltage vb1 of the first stage cascode structure is input to the first transistor through the power supply rejection inductor and the second inductor. The second-stage cascode structure includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected to the input signal, its source is connected to a source degenerate inductor, and its drain is connected to the source of the eighth transistor. The gate of the eighth transistor is connected to a fourth capacitor (using a gain boost capacitor) and one end of a gain control switch. Its drain is connected to a seventh inductor (using an output stage matching inductor) and one end of a fifth capacitor (using a matching capacitor). The input bias voltage vb2 of the second-stage cascode structure is input to the seventh transistor through the fifth inductor of the power supply suppression inductor. The third-stage cascode structure includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is connected to the input signal, its source is connected to a source degenerate inductor, and its drain is connected to the source of the twelfth transistor. The gate of the twelfth transistor is connected to one end of the sixth capacitor (which is a gain boost capacitor) and the gain control switch. Its drain is connected to one end of the tenth inductor, the seventh capacitor, and the eighth capacitor. The tenth inductor is an output stage matching inductor, and the seventh and eighth capacitors are matching capacitors. The input bias voltage VB3 of the third-stage cascode structure is input to the eleventh transistor through the power supply rejection inductor, the eighth inductor. The first-level cascode structure also includes a first resistor with a power supply suppression resistor, a second capacitor connected in series between the second transistor and the first resistor, one end of the second capacitor connected to the gate of the second transistor, the other end connected to the first resistor, and the other end of the first resistor connected to the power supply. The second-level cascode structure also includes a second resistor using a power supply suppression resistor. The fourth capacitor is connected in series between the eighth transistor and the second resistor. One end of the second capacitor is connected to the gate of the eighth transistor, and the other end is connected to the second resistor. The other end of the second resistor is connected to the power supply. The third-level cascode structure also includes a third resistor with a power supply suppression resistor. The sixth capacitor is connected in series between the twelfth transistor and the third resistor. One end of the sixth capacitor is connected to the gate of the twelfth transistor, and the other end is connected to the third resistor. The other end of the third resistor is connected to the power supply. A gain control switch is connected in parallel across the gain boost capacitor of the gain boost and gain control stage. The gain control switch consists of a PMOS transistor and an NMOS transistor. The drains of the PMOS transistor and the NMOS transistor are connected to the gate of the second transistor in the cascode structure, the sources are connected to the power supply rejection resistor, and the gates are connected to the switching voltage signal. The switching voltage signals of the NMOS transistor and the PMOS transistor are converted into inverted signals by an inverter. The second transistor is the second transistor, the eighth transistor, and the twelfth transistor.

2. The high-gain, gain-adjustable, low-noise amplifier according to claim 1, characterized in that: The input stage includes a first inductor employing an input matching inductor and a third inductor employing a source degenerate inductor. One end of the first inductor is connected to the input signal vin, and the other end is connected to a first capacitor employing a DC blocking capacitor. The other end of the first capacitor is connected to the gate of the first transistor of the first stage cascode structure of the amplifier. One end of the second inductor is connected to the source of the first transistor, and the other end is grounded. One end of the input bias voltage vb1 is connected to the second inductor employing a power supply rejection inductor, and the other end of the second inductor is connected to the gate of the first transistor.

3. The high-gain, gain-adjustable, low-noise amplifier according to claim 2, characterized in that: The intermediate matching structure between the first-level cascode structure and the second-level cascode structure includes a fourth inductor, a third capacitor, and a sixth inductor using a source degenerate inductor. One end of the fourth inductor is connected to the drain of the second transistor, and the other end is connected to the power supply. One end of the third capacitor is connected to the drain of the second transistor, and the other end is connected to the gate of the seventh transistor. The intermediate matching structure between the second-level cascode structure and the third-level cascode structure includes a seventh inductor, a fifth capacitor, and a ninth inductor using a source degenerate inductor. One end of the seventh inductor is connected to the drain of the eighth transistor, and the other end is connected to the power supply. One end of the fifth capacitor is connected to the drain of the seventh transistor, and the other end is connected to the gate of the eleventh transistor.

4. A high-gain, gain-adjustable, low-noise amplifier according to claim 3, characterized in that: The output stage includes a tenth inductor, a seventh capacitor, and an eighth capacitor, all of which employ an output matching inductor. One end of the tenth inductor is connected to the drain of the twelfth transistor, and the other end is connected to the power supply. One end of the seventh capacitor is connected to the drain of the twelfth transistor, and the other end is grounded. One end of the eighth capacitor is connected to the drain of the twelfth transistor, and the other end is connected to the output vout.

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