Display substrate, display panel, and display device

Abstract

An embodiment of the present disclosure provides a display substrate, comprising: a substrate; a plurality of light-emitting elements located in a display area; a plurality of pixel driving circuits located on the substrate; the plurality of pixel driving circuits are respectively connected to the plurality of light-emitting elements; the pixel driving circuit comprises an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit are located on the substrate and are distributed in at least one side frame area outside the display area; the first and third gate driving circuits are connected to the P-type transistor; the second gate driving circuit is connected to the N-type transistor; the third, second and first gate driving circuits are arranged in sequence in a direction away from the display area and their orthographic projections on the substrate do not overlap with each other; the adjacent boundary areas of the orthographic projections of the first and second gate driving circuits on the substrate are at least partially nested; a flat layer is located between the pixel driving circuit and the light-emitting elements, and the flat layer also extends to cover the entire surface of the first, second and third gate driving circuits.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display substrate, a display panel, and a display device. Background Art

[0002] For low-temperature polycrystalline oxide (LTPO) display products, the disclosed technology primarily replaces the channel material of some transistors (such as the threshold compensation transistor and reset transistor connected to the gate of the driver transistor) in the low-temperature polysilicon (LTPS) pixel circuit with metal oxide materials. This allows the low-temperature polysilicon transistors in the pixel circuit to drive the screen display, while the metal oxide transistors serve as switches. This new process combines the strong driving capability of low-temperature polysilicon transistors with the low leakage and low power consumption of metal oxide transistors, thereby significantly reducing the power consumption of display products and achieving advantages such as dynamic high and low refresh rates. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate, a display panel, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising: a base;

[0005] A plurality of light-emitting elements are located in the display area;

[0006] A plurality of pixel driving circuits are located on the substrate, and the light-emitting elements are located on a side of the pixel driving circuit away from the substrate; the plurality of pixel driving circuits are connected to the plurality of light-emitting elements respectively;

[0007] The pixel driving circuit includes an N-type transistor and a P-type transistor;

[0008] A first gate driving circuit, a second gate driving circuit and a third gate driving circuit are located on the substrate and are distributed in at least one side frame area outside the display area;

[0009] The first gate driving circuit and the third gate driving circuit are connected to the P-type transistors in each of the pixel driving circuits;

[0010] The second gate driving circuit is connected to the N-type transistor in each of the pixel driving circuits;

[0011] The third gate driving circuit, the second gate driving circuit and the first gate driving circuit are arranged in sequence in a direction away from the display area, and their orthographic projections on the substrate do not overlap with each other;

[0012] Wherein, adjacent boundary areas of the orthographic projections of the first gate driving circuit and the second gate driving circuit on the substrate are at least partially nested;

[0013] A planar layer is located between the pixel driving circuit and the light-emitting element, and the planar layer also extends to entirely cover the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit.

[0014] In some embodiments, adjacent boundary regions of the orthographic projections of the second gate driving circuit and the third gate driving circuit on the substrate are at least partially nested.

[0015] In some embodiments, a first notch region is partially formed in a boundary region of the first gate driving circuit close to the second gate driving circuit; and a local boundary region of the second gate driving circuit close to the first gate driving circuit extends toward the region where the first gate driving circuit is located to form a first protruding region.

[0016] The first protruding area is correspondingly located in the first notch area, and the first protruding area and the first notch area are adapted to the orthographic projection shape on the substrate;

[0017] And / or, a second notch area is partially formed in a boundary area of the second gate driving circuit close to the first gate driving circuit; and a local boundary area of the first gate driving circuit close to the second gate driving circuit extends toward the area where the second gate driving circuit is located to form a second protruding area;

[0018] The second protruding area is correspondingly located in the second notch area, and the second protruding area and the second notch area are matched in orthographic projection shape on the substrate.

[0019] In some embodiments, in an adjacent boundary area between the first gate driving circuit and the second gate driving circuit, part of the wiring of the first gate driving circuit extends to an area where the second gate driving circuit is located;

[0020] And / or, part of the wiring of the second gate driving circuit extends to the area where the first gate driving circuit is located.

[0021] In some embodiments, a third notch region is partially formed in a boundary region of the second gate driving circuit close to the third gate driving circuit; and a local boundary region of the third gate driving circuit close to the second gate driving circuit extends toward the region where the second gate driving circuit is located to form a third protruding region.

[0022] The third protruding area is correspondingly located in the third notch area, and the third protruding area is adapted to the orthographic projection shape of the third notch area on the substrate;

[0023] And / or, a fourth notch area is partially formed in a boundary area of the third gate driving circuit close to the second gate driving circuit; and a local boundary area of the second gate driving circuit close to the third gate driving circuit extends toward the area where the third gate driving circuit is located to form a fourth protruding area;

[0024] The fourth protruding area is correspondingly located in the fourth notch area, and the orthographic projection shapes of the fourth protruding area and the fourth notch area on the substrate are adapted.

[0025] In some embodiments, in an adjacent boundary area between the second gate driving circuit and the third gate driving circuit, part of the wiring of the second gate driving circuit extends to an area where the third gate driving circuit is located;

[0026] And / or, part of the wiring of the third gate driving circuit extends to the area where the second gate driving circuit is located.

[0027] In some embodiments, the method comprises a first semiconductor layer and a first conductive layer, which are sequentially stacked on the substrate, and a gate insulating layer is provided between the first semiconductor layer and the first conductive layer;

[0028] The first gate driving circuit, the second gate driving circuit and the third gate driving circuit each include a plurality of transistors and a plurality of capacitors;

[0029] The first semiconductor layer includes a pattern of an active layer of the transistor;

[0030] The first conductive layer includes a pattern of a gate of the transistor, a first connecting line connected to the gate, a first plate of the capacitor, and a second connecting line connected to the first plate;

[0031] Part of the pattern of the active layer in the first semiconductor layer is located in the first protruding area;

[0032] Part of the gate electrode and part of the first connection line pattern in the first conductive layer are located in the first protruding area.

[0033] In some embodiments, the invention further comprises a second conductive layer located on a side of the first conductive layer away from the substrate; a first passivation layer is disposed between the second conductive layer and the first conductive layer;

[0034] The second conductive layer includes a pattern of a second plate of the capacitor and a third connecting line;

[0035] Part of the pattern of the third connecting line in the second conductive layer is located in the first protruding area.

[0036] In some embodiments, the second conductive layer further includes a pattern of fourth connecting lines;

[0037] Part of the fourth connecting lines extends from the area where the first gate driving circuit is located to the area where the second gate driving circuit is located.

[0038] In some embodiments, part of the fourth connecting line further extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

[0039] In some embodiments, the invention further comprises a third conductive layer located on a side of the second conductive layer away from the substrate; a second passivation layer is disposed between the third conductive layer and the second conductive layer;

[0040] The third conductive layer includes a pattern of fifth connecting lines;

[0041] Part of the fifth connecting lines extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

[0042] In some embodiments, a fourth conductive layer is further included, located on a side of the third conductive layer facing away from the substrate;

[0043] A first intermediate dielectric layer and a second intermediate dielectric layer are provided between the fourth conductive layer and the third conductive layer; the first intermediate dielectric layer and the second intermediate dielectric layer are stacked in sequence away from the third conductive layer;

[0044] A first layer of via holes is provided in the first intermediate dielectric layer, and the first layer of via holes is used to connect the conductive pattern in the fourth conductive layer with the conductive pattern in the third conductive layer;

[0045] The second intermediate dielectric layer is provided with a second layer of via holes, the second layer of via holes being used to connect the conductive pattern in the fourth conductive layer with the conductive pattern in the first conductive layer and the conductive pattern in the second conductive layer respectively;

[0046] The fourth conductive layer includes a source electrode, a drain electrode and a pattern of a sixth connecting line of the transistor; the sixth connecting line is used to connect the source electrode, the drain electrode and the gate electrode;

[0047] Part of the source electrode, part of the drain electrode, and part of the sixth connection line pattern in the fourth conductive layer are located in the first protruding area.

[0048] In some embodiments, the fourth conductive layer further includes a pattern of a seventh connecting line;

[0049] Part of the seventh connecting line extends from the area where the first gate driving circuit is located to the area where the second gate driving circuit is located;

[0050] Part of the seventh connecting line extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

[0051] In some embodiments, the fourth conductive layer further includes a pattern of an eighth connecting line;

[0052] Part of the eighth connecting line extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

[0053] In some embodiments, further comprising:

[0054] A first group of signal lines connected to the first gate drive circuit;

[0055] a second group of signal lines connected to the second gate drive circuit;

[0056] A third group of signal lines connected to the third gate drive circuit;

[0057] The orthographic projection of the first group of signal lines on the substrate overlaps with the first gate driving circuit;

[0058] The orthographic projection of the second group of signal lines on the substrate overlaps with the second gate driving circuit;

[0059] An orthographic projection of the third group of signal lines on the substrate overlaps with the third gate driving circuit.

[0060] In some embodiments, the first group of signal lines, the second group of signal lines, and the third group of signal lines each include a power signal line, a clock signal line, and a trigger signal line;

[0061] The power signal line includes a first power signal line and a second power signal line;

[0062] The clock signal lines in the first group of signal lines and the second group of signal lines include a first clock signal line, a second clock signal line and a third clock signal line;

[0063] The fourth conductive layer further includes patterns of the second power signal line in the first group of signal lines and the second clock signal line in the second group of signal lines.

[0064] In some embodiments, a fifth conductive layer is further included, located on a side of the fourth conductive layer facing away from the substrate;

[0065] The planar layer includes a first sublayer, and the first sublayer is located between the fourth conductive layer and the fifth conductive layer;

[0066] The fifth conductive layer further includes patterns of other signal lines in the first group of signal lines, the second group of signal lines, and the third group of signal lines except the second power signal line in the first group of signal lines and the second clock signal line in the second group of signal lines.

[0067] In some embodiments, the pixel driving circuit is connected to a first reset power line and a second reset power line;

[0068] The fifth conductive layer further includes patterns of a first reset power line and a second reset power line;

[0069] The orthographic projections of the first reset power line and the second reset power line on the substrate overlap with the third gate driving circuit;

[0070] An orthographic projection of the first reset power line on the substrate covers the capacitor in the third gate driving circuit.

[0071] In some embodiments, a sixth conductive layer is further included, located on a side of the fifth conductive layer facing away from the substrate;

[0072] The planar layer further includes a second sublayer, wherein the second sublayer is located between the fifth conductive layer and the sixth conductive layer;

[0073] The sixth conductive layer includes a pattern of the first group of signal lines, the second group of signal lines, the third group of signal lines, the first reset power line, and the second reset power line;

[0074] The sixth conductive layer overlaps with the orthographic projection of the same signal line in the fifth conductive layer and the fourth conductive layer on the substrate and is connected through a via hole opened in the second sub-layer.

[0075] In some embodiments, further comprising:

[0076] A first group of signal lines connected to the first gate drive circuit;

[0077] a second group of signal lines connected to the second gate drive circuit;

[0078] A third group of signal lines connected to the third gate drive circuit;

[0079] The first group of signal lines is arranged on a side of the first gate driving circuit away from the display area;

[0080] The second group of signal lines and the third group of signal lines are arranged on a side of the third gate driving circuit close to the display area, and orthographic projections of the third group of signal lines and the second group of signal lines on the substrate do not overlap with each other.

[0081] In some embodiments, further comprising:

[0082] A first group of signal lines connected to the first gate drive circuit;

[0083] a second group of signal lines connected to the second gate drive circuit;

[0084] The first group of signal lines is arranged on a side of the first gate driving circuit away from the display area;

[0085] The second group of signal lines is arranged in a region between the second gate driving circuit and the third gate driving circuit.

[0086] In some embodiments, the invention further includes: a third group of signal lines connected to the third gate driving circuit;

[0087] The third group of signal lines is arranged in a region between the second gate driving circuit and the third gate driving circuit, and the orthographic projections of the third group of signal lines and the second group of signal lines on the substrate do not overlap with each other;

[0088] Alternatively, the third group of signal lines is arranged on a side of the third gate driving circuit close to the display area.

[0089] In some embodiments, the pixel driving circuit includes: a first reset subcircuit, a threshold compensation subcircuit, a driving subcircuit, a data writing subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, a second reset subcircuit, and a storage subcircuit;

[0090] The first reset sub-circuit is connected to the control end of the driving sub-circuit and the second gate driving circuit respectively, and is configured to reset the control end of the driving sub-circuit under the control of the first reset signal and the scanning signal output by the second gate driving circuit;

[0091] The threshold compensation sub-circuit is connected to the control terminal and the second terminal of the driving sub-circuit and the second gate driving circuit respectively, and is configured to perform threshold compensation on the driving sub-circuit under the control of the scanning signal output by the second gate driving circuit;

[0092] The data writing sub-circuit is connected to the first end of the driving sub-circuit and the third gate driving circuit respectively, and is configured to write a data signal into the storage sub-circuit under the control of a scan signal output by the third gate driving circuit;

[0093] The storage sub-circuit is electrically connected to the control terminal and the first power supply voltage line of the driving sub-circuit respectively, and is configured to store a data signal;

[0094] The first light-emitting control sub-circuit is connected to the first power supply voltage line, the first end of the driver sub-circuit, and the first gate driver circuit, respectively, and is configured to connect or disconnect the driver sub-circuit and the first power supply voltage line under the control of a light-emitting control signal output by the first gate driver circuit;

[0095] The second light-emitting control subcircuit is connected to the second end of the driving subcircuit, the first electrode of the light-emitting element, and the first gate driving circuit, respectively, and is configured to realize connection or disconnection between the driving subcircuit and the light-emitting element under the control of the light-emitting control signal output by the first gate driving circuit;

[0096] The second reset sub-circuit is connected to the first electrode of the light-emitting element and the third gate drive circuit, respectively, and is configured to reset the control end of the drive sub-circuit and the first electrode of the light-emitting element under the control of the second reset signal and the scan signal output by the third gate drive circuit;

[0097] The first reset sub-circuit, the threshold compensation sub-circuit, the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, the second light-emitting control sub-circuit and the second reset sub-circuit each include at least one transistor;

[0098] The transistors in the first reset sub-circuit and the threshold compensation sub-circuit are metal oxide transistors;

[0099] The transistors in the driving sub-circuit, the data writing sub-circuit, the first light emitting control sub-circuit, the second light emitting control sub-circuit and the second reset sub-circuit are low-temperature polysilicon transistors.

[0100] In some embodiments, the plurality of pixel driving circuits are arranged in an array;

[0101] The first gate driving circuit includes a plurality of first shift registers, and the plurality of first shift registers are cascaded in sequence;

[0102] The second gate driving circuit includes a plurality of second shift registers, and the plurality of second shift registers are cascaded in sequence;

[0103] The third gate driving circuit includes a plurality of third shift registers, and the plurality of third shift registers are cascaded in sequence;

[0104] One of the first shift registers is correspondingly connected to two rows of the pixel driving circuits;

[0105] One second shift register is correspondingly connected to four rows of pixel driving circuits;

[0106] One of the third shift registers is correspondingly connected to two rows of pixel driving circuits.

[0107] In some embodiments, the 2n-1th first shift register and the 2nth first shift register are respectively disposed in the border areas on two opposite sides of the periphery of the display area;

[0108] The 2n-1th first shift registers are sequentially arranged along the column direction in which the pixel driving circuits are arranged; the 2nth first shift registers are sequentially arranged along the column direction in which the pixel driving circuits are arranged;

[0109] The 2n-1th second shift register and the 2nth second shift register are respectively arranged in the frame areas on two opposite sides of the periphery of the display area;

[0110] The 2n-1th second shift registers are sequentially arranged along the column direction of the pixel driving circuits; the 2nth second shift registers are sequentially arranged along the column direction of the pixel driving circuits;

[0111] The 2n-1th third shift register and the 2nth third shift register are respectively arranged in the frame areas on two opposite sides of the periphery of the display area;

[0112] The 2n-1th second shift registers are sequentially arranged along the column direction of the pixel driving circuits; the 2nth second shift registers are sequentially arranged along the column direction of the pixel driving circuits;

[0113] Wherein, n≥1, and n is an integer.

[0114] In some embodiments, in the border area on either side of the border areas on opposite sides of the periphery of the display area, a distribution area of the first shift register corresponds to a distribution area of the second shift register;

[0115] The distribution area of one first shift register corresponds to the distribution areas of four third shift registers.

[0116] In a second aspect, an embodiment of the present disclosure further provides a display panel, which includes the above-mentioned display substrate.

[0117] In a third aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0119] Figure 1 This is a circuit diagram of a pixel driving circuit for a low-temperature polysilicon OLED display panel.

[0120] Figure 2 For Figure 1 A top view of the arrangement of the gate driving circuit for providing gate driving signals to the transistors in the pixel driving circuit.

[0121] Figure 3 A circuit diagram of a pixel driving circuit for a low-temperature polycrystalline oxide OLED display panel.

[0122] Figure 4 For Figure 3 A top view of the arrangement of the gate driving circuit for providing gate driving signals to the transistors in the pixel driving circuit.

[0123] Figure 5 For the disclosed technology Figure 3 Schematic diagram of the partitioned top view of the LTPO OLED display panel with the pixel driving circuit in the middle.

[0124] Figure 6 For the Figure 5 Schematic diagram of the structural section along the AA' section line.

[0125] Figure 7 for Figure 5 Schematic diagram of the gate drive circuit layout in the border area on one side of the LTPO OLED display panel.

[0126] Figure 8 Schematic diagram of an arrangement of a gate driving circuit in the border area of a display substrate in an embodiment of the present disclosure.

[0127] Figure 9 For the Figure 8 Schematic diagram of the structural section along the BB' section line.

[0128] Figure 10 FIG. 2 is a schematic diagram of another arrangement of the gate driving circuit in the border area of the display substrate in an embodiment of the present disclosure.

[0129] Figure 11 For the Figure 10 Schematic diagram of the structural section along the CC' section line.

[0130] Figure 12AThis is a schematic layout showing the first semiconductor layer and the first conductive layer within the border region of the substrate in an embodiment of the present disclosure.

[0131] Figure 12B FIG. 1 is a schematic diagram showing a second conductive layer within a border region of a substrate in an embodiment of the present disclosure.

[0132] Figure 12C Schematic diagram showing the third conductive layer within the border region of the substrate in an embodiment of the present disclosure.

[0133] Figure 12D Schematic diagram showing the first layer of vias and the second layer of vias in the border area of the substrate in an embodiment of the present disclosure.

[0134] Figure 12E Schematic diagram showing the fourth conductive layer within the border region of the substrate in an embodiment of the present disclosure.

[0135] Figure 12F Schematic diagram showing the fifth conductive layer within the border region of the substrate in an embodiment of the present disclosure.

[0136] Figure 13 4 is a circuit diagram of a shift register unit in a first gate driving circuit according to an embodiment of the present disclosure.

[0137] Figure 14 4 is a circuit diagram of a shift register unit in the second gate driving circuit according to an embodiment of the present disclosure.

[0138] Figure 15 4 is a circuit diagram of a shift register unit in a third gate driving circuit according to an embodiment of the present disclosure.

[0139] Figure 16 Schematic diagram of another arrangement of the gate driving circuit in the border area of the display substrate in an embodiment of the present disclosure.

[0140] Figure 17 4 is a circuit diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0141] Figure 18 Schematic diagram of the principle of one-push-two unilateral driving of the display substrate using a gate drive circuit in an embodiment of the present disclosure.

[0142] Figure 19 This is a schematic diagram of the principle of a one-push-two double-sided drive using a gate drive circuit for a display substrate in the disclosed technology.

[0143] Figure 20 This is a schematic diagram showing the principle that the first and second gate driving circuits in the substrate adopt one-push-two unilateral driving, and the third gate driving circuit adopts one-push-one bilateral driving.

[0144] Figure 21A schematic diagram of a gate drive circuit arrangement is provided to disclose a technology display substrate in which the first and second gate drive circuits adopt one-push-two double-side drive, and the third gate drive circuit adopts one-push-one double-side drive.

[0145] Figure 22 This is a schematic diagram of the gate drive circuit arrangement in which the first and second gate drive circuits in the display substrate adopt one-push-two unilateral drive, and the third gate drive circuit adopts one-push-one bilateral drive.

[0146] Figure 23 For the embodiment of the present disclosure Figure 17 Working timing diagram of the pixel driving circuit. DETAILED DESCRIPTION

[0147] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display substrate, a display panel and a display device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0148] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0149] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0150] In the disclosed technology, refer to Figure 1 , a circuit diagram of a pixel drive circuit for a low-temperature polysilicon (LTPS) OLED (Organic Light-Emitting Diode) display panel. The pixel drive circuit includes a first reset transistor, a threshold compensation transistor, a drive transistor, a data write transistor, a first emission control transistor, a second emission control transistor, a second reset transistor, and a storage capacitor. All transistors in the pixel drive circuit are P-type transistors with channels made of low-temperature polysilicon material.

[0151] Reference Figure 2 , for Figure 1Schematic diagram of the top view of the arrangement of the gate drive circuit that provides gate drive signals to the transistors of the pixel drive circuit. The gate drive circuit that provides gate drive signals to the pixel drive circuit includes a light-emitting control gate drive circuit (i.e., EM GOA), a gate drive circuit for threshold compensation control and data writing control, and a gate drive circuit for first reset control and second reset control (i.e., Gate PGOA). A first gap S1 is formed between the EM GOA and the Gate PGOA. The gate drive circuit that provides gate drive signals to the pixel drive circuit is located in the border areas 102 on opposite sides of the display area 101 of the display panel.

[0152] In the disclosed technology, refer to Figure 3 , is a circuit diagram of a pixel drive circuit for a low-temperature polycrystalline oxide (LTPO) OLED (Organic Light-Emitting Diode) display panel. The pixel drive circuit also includes a first reset transistor, a threshold compensation transistor, a drive transistor, a data write transistor, a first emission control transistor, a second emission control transistor, a second reset transistor, and a storage capacitor. The first reset transistor and the threshold compensation transistor are N-type transistors with metal oxide channels; the drive transistor, the data write transistor, the first emission control transistor, the second emission control transistor, and the second reset transistor are P-type transistors with low-temperature polysilicon channels.

[0153] Reference Figure 4 , for Figure 3 A top view of the arrangement of the gate drive circuit for providing gate drive signals to the transistors in the pixel drive circuit. Figure 1 The pixel driving circuit in Figure 3 In addition to the P-type transistor, the pixel driving circuit in the CMOS also introduces the N-type transistor, so compared with Figure 2 The gate drive circuit in Figure 4The gate drive circuit in the embodiment also adds a gate drive circuit (i.e., Gate N GOA) that provides a gate drive signal to the N-type transistor (i.e., the first reset transistor and the threshold compensation transistor). A second gap S2 is formed between Gate N GOA and Gate P GOA. Therefore, compared with the LTPS OLED display panel, the LTPO OLED display panel needs to arrange corresponding Gate N GOA circuits in the border areas on both sides of the display area on the basis of arranging the EM GOA circuit and the Gate P GOA circuit. This will greatly increase the width of the border area of the display panel. For example, if the width of the Gate N GOA circuit is about 200μm, the width of the corresponding border area needs to be increased by about 20% of the original width, that is, the border area size will increase from the 1.0mm width of the left and right border areas of the LTPS OLED display panel in the disclosed technology to the 1.2mm width of the left and right border areas of the LTPO OLED display panel in the disclosed technology. For this reason, the introduction of the Gate N GOA circuit will greatly affect the development of the narrow border design of LTPO OLED display products in the future.

[0154] In addition, refer to Figure 5-Figure 7 , Figure 5 For the disclosed technology Figure 3 A top-down diagram of the LTPO OLED display panel with pixel drive circuits. Figure 6 For the Figure 5 Schematic diagram of the structural section along the AA' section line; Figure 7 for Figure 5 Schematic diagram of the gate drive circuit layout in the border area on one side of the LTPOOLED display panel. Figure 6 As can be seen in the figure, each gate driving circuit that provides a gate driving signal to the transistor in the pixel driving circuit is located on the substrate, and the Gate P GOA circuit, the Gate NGOA circuit and the EM GOA circuit are arranged in sequence away from the display area, and the three do not overlap with each other. In the display area, the pixel driving circuit is formed on the substrate 1, and a flat layer 5 is formed on the side of the pixel driving circuit away from the substrate 1, so as to form the various film layers of the OLED light-emitting element on the flat surface of the flat layer 5 away from the substrate 1; the flat layer 5 also extends from the display area 101 to the frame area 102, and covers the various gate driving circuits located in the frame area 102. In the disclosed technology, refer to Figure 6 and Figure 7 Gaps are formed between any two adjacent Gate P GOA circuits, Gate N GOA circuits, and EM GOA circuits, respectively. The gaps are formed by grooving or disconnecting an insulating film layer (such as a gate insulating layer, a passivation layer, etc.) between the two adjacent circuits. The planar layer 5 is disconnected in the gap between the Gate N GOA circuit and the EM GOA circuit.

[0155] In order to solve the technical problem that the introduction of the Gate N GOA circuit in the frame area increases the width of the frame area in the disclosed technology, in the first aspect, the embodiment of the present disclosure provides a display substrate, referring to Figure 8 , is a schematic diagram of an arrangement of a gate driving circuit in a border area of a display substrate in an embodiment of the present disclosure; Figure 9 For the Figure 8 BB' section line structural diagram; wherein the display substrate comprises: a substrate 1; a plurality of light-emitting elements, located in the display area 101; a plurality of pixel driving circuits, located on the substrate 1, the light-emitting elements are located on the side of the pixel driving circuit away from the substrate 1; the plurality of pixel driving circuits are respectively connected to the plurality of light-emitting elements; the pixel driving circuit comprises an N-type transistor and a P-type transistor; a first gate driving circuit 2, a second gate driving circuit 3 and a third gate driving circuit 4, located on the substrate 1 and distributed at least on one side frame area 102 outside the display area 101; the first gate driving circuit 2 and the third gate driving circuit 4 are connected to each pixel driving circuit. The first gate driving circuit 102 is connected to the P-type transistor in the pixel driving circuit; the second gate driving circuit 3 is connected to the N-type transistor in each pixel driving circuit; the third gate driving circuit 4, the second gate driving circuit 3 and the first gate driving circuit 2 are arranged in sequence in a direction away from the display area 101, and their orthographic projections on the substrate 1 do not overlap with each other; wherein, the adjacent boundary areas of the orthographic projections of the first gate driving circuit 2 and the second gate driving circuit 3 on the substrate 1 are at least partially nested; the flat layer 5 is located between the pixel driving circuit and the light-emitting element, and the flat layer 5 also extends to cover the entire surface of the first gate driving circuit 2, the second gate driving circuit 3 and the third gate driving circuit 4.

[0156] The boundary region of the first gate driver circuit 2 refers to the boundary region of the region where the circuit portion of the first gate driver circuit 2 is projected onto the substrate 1; the boundary region of the second gate driver circuit 3 refers to the boundary region of the region where the circuit portion of the second gate driver circuit 3 is projected onto the substrate 1. Adjacent boundary regions of the orthographic projections of the first gate driver circuit 2 and the second gate driver circuit 3 on the substrate 1 are at least partially nested, meaning that the circuitry of the boundary region of the first gate driver circuit 2 is partially arranged in an area where no circuitry is arranged within the area where the second gate driver circuit 3 is located; and that the circuitry of the boundary region of the second gate driver circuit 3 is partially arranged in an area where no circuitry is arranged within the area where the first gate driver circuit 2 is located.

[0157] In some embodiments, reference Figure 8A first notch area 201 is partially formed in the boundary area of the first gate driving circuit 2 close to the second gate driving circuit 3; a local boundary area of the second gate driving circuit 3 close to the first gate driving circuit 2 extends toward the area where the first gate driving circuit 2 is located to form a first protruding area 301; the first protruding area 301 is correspondingly located in the first notch area 201, and the first protruding area 301 is adapted to the orthographic projection shape of the first notch area 201 on the substrate 1.

[0158] In some embodiments, reference Figure 8 A second notch area 302 is partially formed in the boundary area of the second gate driving circuit 3 close to the first gate driving circuit 2; a local boundary area of the first gate driving circuit 2 close to the second gate driving circuit 3 extends toward the area where the second gate driving circuit 3 is located to form a second protruding area 202; the second protruding area 202 is correspondingly located in the second notch area 302, and the second protruding area 202 is adapted to the orthographic projection shape of the second notch area 302 on the substrate.

[0159] In some embodiments, reference Figure 8 In the adjacent boundary area between the first gate driving circuit 2 and the second gate driving circuit 3 , part of the wiring of the first gate driving circuit 2 extends to the area where the second gate driving circuit 3 is located.

[0160] In some embodiments, in the adjacent boundary region between the first gate driving circuit and the second gate driving circuit, part of the wiring of the second gate driving circuit extends to the region where the first gate driving circuit is located (not shown in the figure).

[0161] In some embodiments, reference Figure 10 , is a schematic diagram of another arrangement of the gate driving circuit in the border area of the display substrate in an embodiment of the present disclosure; Figure 11 For the Figure 10 Schematic cross-sectional view of the structure along the CC' section line; the adjacent boundary areas of the orthographic projections of the second gate driving circuit 3 and the third gate driving circuit 4 on the substrate 1 are at least partially nested.

[0162] The boundary region of the third gate drive circuit 4 refers to the boundary region of the region where the orthographic projection of the circuit portion of the third gate drive circuit 4 is located on the substrate 1. Adjacent boundary regions of the orthographic projections of the second gate drive circuit 3 and the third gate drive circuit 4 on the substrate 1 are at least partially nested, meaning that: the boundary region circuit of the second gate drive circuit 3 is partially arranged in an area where no circuit is arranged within the region where the third gate drive circuit 4 is located; and the boundary region circuit of the third gate drive circuit 4 is partially arranged in an area where no circuit is arranged within the region where the second gate drive circuit 3 is located.

[0163] In some embodiments, reference Figure 10A third notch area 303 is partially formed in the boundary area of the second gate driving circuit 3 close to the third gate driving circuit 4; a local boundary area of the third gate driving circuit 4 close to the second gate driving circuit 3 extends toward the area where the second gate driving circuit 3 is located to form a third protruding area 401; the third protruding area 401 is correspondingly located in the third notch area 303, and the third protruding area 401 is adapted to the orthographic projection shape of the third notch area 303 on the substrate 1.

[0164] In some embodiments, reference Figure 10 A fourth notch area 402 is partially formed in the boundary area of the third gate driving circuit 4 close to the second gate driving circuit 3; a local boundary area of the second gate driving circuit 3 close to the third gate driving circuit 4 extends toward the area where the third gate driving circuit 4 is located to form a fourth protruding area 304; the fourth protruding area 304 is correspondingly located in the fourth notch area 402, and the fourth protruding area 304 is adapted to the orthographic projection shape of the fourth notch area 402 on the substrate 1.

[0165] In some embodiments, reference Figure 10 In the adjacent boundary area between the second gate driving circuit 3 and the third gate driving circuit 4 , part of the wiring of the second gate driving circuit 3 extends to the area where the third gate driving circuit 4 is located.

[0166] In some embodiments, in the adjacent boundary region between the second gate driving circuit and the third gate driving circuit, part of the wiring of the third gate driving circuit extends to the region where the second gate driving circuit is located (not shown in the figure).

[0167] In the embodiment of the present disclosure, compared with the design in the disclosed technology in which gaps are formed between adjacent Gate P GOA circuits, Gate N GOA circuits and EM GOA circuits, the gaps are formed by grooving or disconnecting the insulating film layer (such as a gate insulating layer, a passivation layer, etc.) between the two adjacent ones; and the flat layer is disconnected in the gap between the Gate N GOA circuit and the EM GOA circuit, in the embodiment of the present disclosure, no gaps are set between the adjacent boundary areas of the first gate driving circuit 2, the second gate driving circuit 3 and the third gate driving circuit 4, and the flat layer 5 is not disconnected between the adjacent boundary areas of any two, but is set on the entire surface; in this way, the gap setting between any two adjacent ones of the first gate driving circuit 2, the second gate driving circuit 3 and the third gate driving circuit 4 is eliminated, so that at least partial circuits in the adjacent boundary areas between the three are interspersed with each other in the spatial area where each other is located, realizing the mixing or mutual borrowing of space between any two adjacent gate driving circuits, thereby reducing the width of the border area 102 of the display substrate.

[0168] In some embodiments, reference Figure 12A, is a schematic layout of the first semiconductor layer and the first conductive layer in the border area of the display substrate in an embodiment of the present disclosure; the display substrate includes a first semiconductor layer 6 and a first conductive layer 7, which are stacked in sequence on a base, with a gate insulating layer provided between the first semiconductor layer 6 and the first conductive layer 7; the first gate drive circuit 2, the second gate drive circuit 3, and the third gate drive circuit 4 each include a plurality of transistors and a plurality of capacitors; the first semiconductor layer 6 includes a pattern of an active layer 61 of the transistor; the first conductive layer 7 includes a pattern of a gate 71 of the transistor, a first connecting line 72 connected to the gate 71, a first plate 73 of the capacitor, and a second connecting line 74 connected to the first plate 73; the pattern of a portion of the active layer 61 in the first semiconductor layer 6 is located in the first protruding area 301; the pattern of a portion of the gate 71 and a portion of the first connecting line 72 in the first conductive layer 7 are located in the first protruding area 301.

[0169] In some embodiments, reference Figure 13-15 , Figure 13 is a circuit diagram of a shift register unit in a first gate driving circuit according to an embodiment of the present disclosure; Figure 14 is a circuit diagram of a shift register unit in a second gate driving circuit according to an embodiment of the present disclosure; Figure 15 FIG. 1 is a circuit diagram of a shift register unit in the third gate drive circuit of the present disclosure. Figure 12A The shift register unit in the first gate drive circuit 2 forms a first notch area 201 at a position close to the eighth transistor T8, the fifth transistor T5, and the second capacitor C2; the gate 71 and active layer 61 of the first transistor T1, the gate 71 and active layer 61 of the third transistor T3, the gate 71 of the second transistor T2, and the pattern of the first connecting line 72 connecting the gate 71 of the first transistor T1 and the gate 71 of the third transistor T3 of the shift register unit in the second gate drive circuit 3 are located in the first protruding area 301.

[0170] In some embodiments, reference Figure 12B , a schematic layout of the second conductive layer within the border region of the display substrate in an embodiment of the present disclosure. The display substrate further includes a second conductive layer 8 located on the side of the first conductive layer 7 facing away from the substrate 1; a first passivation layer is disposed between the second conductive layer 8 and the first conductive layer 7; the second conductive layer 8 includes a second capacitor plate 81 and a pattern of third connecting lines 82; a portion of the pattern of third connecting lines 82 in the second conductive layer 8 is located in the first protruding region 301.

[0171] In some embodiments, reference Figure 14 and Figure 12B The third connection line 82 is a connection line between the source (or drain) of the second transistor T2, the source (or drain) of the third transistor T3 and the gate 71 of the fifth transistor T5 in the second gate driving circuit 3.

[0172] In some embodiments, reference Figure 12B The second conductive layer 8 further includes a pattern of fourth connecting lines 83 ; a portion of the fourth connecting lines 83 extends from the area where the first gate driving circuit 2 is located to the area where the second gate driving circuit 3 is located.

[0173] In some embodiments, the fourth connection line 83 is an output line of the first gate driving circuit 2 .

[0174] In some embodiments, part of the fourth connection line 83 further extends from the area where the second gate driving circuit 3 is located to the area where the third gate driving circuit 4 is located. That is, the output line of the first gate driving circuit 2 further extends from the area where the second gate driving circuit 3 is located to the area where the third gate driving circuit 4 is located.

[0175] In some embodiments, reference Figure 12C , a schematic layout of the third conductive layer within the border region of the display substrate in an embodiment of the present disclosure. The display substrate further includes a third conductive layer 9 located on the side of the second conductive layer 8 facing away from the substrate; a second passivation layer is disposed between the third conductive layer 9 and the second conductive layer 8; the third conductive layer 9 includes a pattern of fifth connecting lines 91; portions of the fifth connecting lines 91 extend from the area where the second gate drive circuit 3 is located to the area where the third gate drive circuit 4 is located.

[0176] In some embodiments, the fifth connection line 91 is a signal input line of the second gate driving circuit 3 .

[0177] In some embodiments, reference Figure 12D and Figure 12E , Figure 12D A schematic diagram showing first-layer via holes and second-layer via holes in a substrate border region in an embodiment of the present disclosure; Figure 12EThe schematic diagram of the fourth conductive layer in the border area of the display substrate in the embodiment of the present disclosure is shown in FIG. The display substrate further includes a fourth conductive layer 10, which is located on the side of the third conductive layer 9 away from the substrate; a first intermediate dielectric layer and a second intermediate dielectric layer (not shown in the figure) are provided between the fourth conductive layer 10 and the third conductive layer 9; the first intermediate dielectric layer and the second intermediate dielectric layer are stacked away from the third conductive layer 9 in sequence; a first layer of vias 11 are provided in the first intermediate dielectric layer, and the first layer of vias 11 are used to connect the conductive pattern in the fourth conductive layer 10 with the conductive pattern in the third conductive layer 9; a second layer of vias 11 are provided in the second intermediate dielectric layer. The second layer of vias 12 are used to connect the conductive patterns in the fourth conductive layer 10 with the conductive patterns in the first conductive layer 7 and the conductive patterns in the second conductive layer 8 respectively; the fourth conductive layer 10 includes the source 103, the drain 104 and the pattern of the sixth connecting line 105 of the transistor; the sixth connecting line 105 is used to connect the source 103, the drain 104 and the gate 71; the pattern of part of the source 103, part of the drain 104 and part of the sixth connecting line 105 in the fourth conductive layer 10 is located in the first protruding area 301.

[0178] Among them, the graphics of the source 103 and drain 104 of the transistor in the fourth conductive layer 10 refer to the graphics of the source 103 and drain 104 of each transistor in the first gate drive circuit 2, the second gate drive circuit 3 and the third gate drive circuit 4; the graphics of the sixth connecting line 105 in the fourth conductive layer 10 refers to the connecting line between the source 103, drain 104 and / or gate 71 of the transistor in the first gate drive circuit 2, the second gate drive circuit 3 and the third gate drive circuit 4 according to their respective circuit connection relationships.

[0179] In some embodiments, the source 103 and drain 104 of the first transistor T1 of the second gate driving circuit 3, the source 103 and drain 104 of the third transistor T3 in the fourth conductive layer 10, and the pattern of a portion of the sixth connecting line 105 connecting the source 103 (or drain 104) of the first transistor T1, the source 103 (or drain 104) of the twelfth transistor T12, the gate 71 of the second transistor T2 and the source 103 (or drain 104) of the third transistor T3 are located in the first protruding area 301.

[0180] In some embodiments, reference Figure 12E The fourth conductive layer 10 further includes a pattern of a seventh connecting line 106; part of the seventh connecting line 106 extends from the area where the first gate driving circuit 2 is located to the area where the second gate driving circuit 3 is located; and part of the seventh connecting line 106 extends from the area where the second gate driving circuit 3 is located to the area where the third gate driving circuit 4 is located.

[0181] In some embodiments, the seventh connection line 106 is an input line of the first gate driving circuit 2 .

[0182] In some embodiments, reference Figure 12E , the fourth conductive layer 10 further includes a pattern of an eighth connecting line 107 ; a portion of the eighth connecting line 107 extends from the area where the second gate driving circuit 3 is located to the area where the third gate driving circuit 4 is located.

[0183] In some embodiments, the eighth connection line 107 is an output line of the second gate driving circuit 3 .

[0184] In some embodiments, reference Figure 16 , which is another arrangement diagram of the gate driving circuit in the border area of the display substrate in an embodiment of the present disclosure; wherein, the display substrate further includes: a first group of signal lines 13, connected to the first gate driving circuit 2; a second group of signal lines 14, connected to the second gate driving circuit 3; a third group of signal lines 15, connected to the third gate driving circuit 4; the orthographic projection of the first group of signal lines 13 on the substrate overlaps with the first gate driving circuit 2; the orthographic projection of the second group of signal lines 14 on the substrate overlaps with the second gate driving circuit 3; and the orthographic projection of the third group of signal lines 15 on the substrate overlaps with the third gate driving circuit 4.

[0185] In some embodiments, reference Figure 16 and Figure 12E The first group of signal lines 13, the second group of signal lines 14 and the third group of signal lines 15 respectively include power signal lines, clock signal lines and trigger signal lines; the power signal lines include first power signal lines and second power signal lines; the clock signal lines in the first group of signal lines 13 and the second group of signal lines 14 include first clock signal lines, second clock signal lines and third clock signal lines; the fourth conductive layer 10 also includes graphics of the second power signal lines 108 in the first group of signal lines 13 and the second clock signal lines 109 in the second group of signal lines 14.

[0186] In some embodiments, reference Figure 12F , which is a schematic layout of the fifth conductive layer within the border region of the display substrate in an embodiment of the present disclosure. The display substrate further includes a fifth conductive layer 16, located on the side of the fourth conductive layer 10 facing away from the substrate. The planar layer includes a first sublayer, which is located between the fourth conductive layer 10 and the fifth conductive layer 16. The fifth conductive layer 16 also includes the patterns of the remaining signal lines in the first group of signal lines 13, the second group of signal lines 14, and the third group of signal lines 15, excluding the second power signal line 108 in the first group of signal lines 13 and the second clock signal line 109 in the second group of signal lines 14.

[0187] In some embodiments, reference Figure 12FThe fifth conductive layer 16 includes the trigger signal line ESTV, the first clock signal line ECK, the second clock signal line ECB, the third clock signal line EVX and the first power signal line VGH in the first group of signal lines 13; the fifth conductive layer 16 also includes the trigger signal line NSTV, the first clock signal line NCK, the third clock signal line NCB, the first power signal line VGH and the second power signal line VGL in the second group of signal lines 14; the fifth conductive layer 16 also includes the trigger signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, and the first power signal line VGH in the third group of signal lines 15; wherein, the third gate drive circuit 4 and the second gate drive circuit 3 share the second power signal line VGL.

[0188] In some embodiments, reference Figure 12F The pixel drive circuit is connected to the first reset power line Vinit1 and the second reset power line Vinit2; the fifth conductive layer 16 also includes patterns of the first reset power line Vinit1 and the second reset power line Vinit2; the orthographic projections of the first reset power line Vinit1 and the second reset power line Vinit2 on the substrate overlap with the third gate drive circuit 4; and the orthographic projection of the first reset power line Vinit1 on the substrate covers the capacitors C1 and C2 in the third gate drive circuit 4. This arrangement eliminates the need for the first reset power line Vinit1 and the second reset power line Vinit2 to occupy the width of the display substrate frame area, thereby further narrowing the display substrate frame and achieving a narrow display substrate frame.

[0189] In some embodiments, the display substrate further comprises a sixth conductive layer (not shown) located on a side of the fifth conductive layer facing away from the substrate; the planar layer further comprises a second sublayer located between the fifth and sixth conductive layers; the sixth conductive layer comprises a pattern of a first group of signal lines, a second group of signal lines, a third group of signal lines, a first reset power line, and a second reset power line; the sixth conductive layer overlaps with the orthographic projections of the same signal lines in the fifth and fourth conductive layers on the substrate and are connected via vias provided in the second sublayer. With this arrangement, each signal line is connected in parallel to two conductive layers, which is equivalent to increasing the cross-sectional area of each signal line, thereby reducing the routing circuit of each signal line, thereby reducing signal attenuation on each signal line, lowering the display power consumption of the display substrate, and improving the display effect of the display substrate.

[0190] In the present disclosure, referring to Figure 16 The display substrate in the left and right border areas 102 of the display substrate can be compressed to an extremely narrow width. For example, the width of the area occupied by the entire gate drive circuit can be reduced from 600 μm to about 300 μm. Figure 4The width of the area occupied by the gate drive circuit in the embodiment of the present disclosure Figure 16 The narrowing rate of the width of the area occupied by the gate drive circuit in the embodiment of the present disclosure is about 50%. Figure 16 The border region 102 of the display substrate is suitable for display products requiring an extremely narrow border (eg, a border region width of less than 0.7 mm).

[0191] In some embodiments, reference Figure 10 The display substrate further includes: a first group of signal lines 13 connected to the first gate drive circuit 2; a second group of signal lines 14 connected to the second gate drive circuit 3; and a third group of signal lines 15 connected to the third gate drive circuit 4; the first group of signal lines 13 is arranged on a side of the first gate drive circuit 2 away from the display area 101; the second group of signal lines 14 and the third group of signal lines 15 are arranged on a side of the third gate drive circuit 4 close to the display area 101, and the orthographic projections of the third group of signal lines 15 and the second group of signal lines 14 on the substrate do not overlap with each other.

[0192] In some embodiments, reference Figure 8 The display substrate also includes: a first group of signal lines 13, connected to the first gate driving circuit 2; a second group of signal lines 14, connected to the second gate driving circuit 3; the first group of signal lines 13 are arranged on the side of the first gate driving circuit 2 away from the display area 101; the second group of signal lines 14 are arranged in the area between the second gate driving circuit 3 and the third gate driving circuit 4.

[0193] In some embodiments, reference Figure 8 The display substrate further includes: a third group of signal lines 15 connected to the third gate driving circuit 4; the third group of signal lines 15 are arranged in the area between the second gate driving circuit 3 and the third gate driving circuit 4, and the orthographic projections of the third group of signal lines 15 and the second group of signal lines 14 on the substrate do not overlap with each other.

[0194] In some embodiments, the third group of signal lines is arranged on a side of the third gate driving circuit close to the display area (not shown in the figure).

[0195] In some embodiments, the pixel driving circuit includes: a first reset subcircuit, a threshold compensation subcircuit, a driving subcircuit, a data writing subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, a second reset subcircuit and a storage subcircuit; the first reset subcircuit is connected to the control end of the driving subcircuit and the second gate driving circuit, respectively, and is configured to reset the control end of the driving subcircuit under the control of the first reset signal and the scan signal output by the second gate driving circuit; the threshold compensation subcircuit is connected to the control end and the second end of the driving subcircuit and the second gate driving circuit, respectively, and is configured to perform threshold compensation on the driving subcircuit under the control of the scan signal output by the second gate driving circuit; the data writing subcircuit is connected to the first end of the driving subcircuit and the third gate driving circuit, respectively, and is configured to write the data signal into the storage subcircuit under the control of the scan signal output by the third gate driving circuit; the storage subcircuit is electrically connected to the control end of the driving subcircuit and the first power supply voltage line, respectively, and is configured to store the data signal; the first light-emitting control subcircuit is connected to the first power supply voltage line, the first end of the driving subcircuit and the first gate driving circuit, respectively. And it is configured to realize the connection between the driving subcircuit and the first power supply voltage line under the control of the light-emitting control signal output by the first gate driving circuit; the second light-emitting control subcircuit is respectively connected to the second end of the driving subcircuit, the first pole of the light-emitting element and the first gate driving circuit, and is configured to realize the connection between the driving subcircuit and the light-emitting element under the control of the light-emitting control signal output by the first gate driving circuit; the second reset subcircuit is respectively connected to the first pole of the light-emitting element and the third gate driving circuit, and is configured to reset the control end of the driving subcircuit and the first pole of the light-emitting element under the control of the second reset signal and the scanning signal output by the third gate driving circuit; the first reset subcircuit, the threshold compensation subcircuit, the driving subcircuit, the data writing subcircuit, the first light-emitting control subcircuit, the second light-emitting control subcircuit and the second reset subcircuit each include at least one transistor; the transistors in the first reset subcircuit and the threshold compensation subcircuit are metal oxide transistors; the transistors in the data writing subcircuit of the driving subcircuit, the first light-emitting control subcircuit, the second light-emitting control subcircuit and the second reset subcircuit are low-temperature polysilicon transistors.

[0196] Among them, the pixel driving circuit includes N-type transistors of metal oxide and P-type transistors of low-temperature polysilicon; the display substrate combines the advantages of strong driving capability of low-temperature polysilicon transistors and low leakage and low power consumption of metal oxide transistor processes, thereby greatly reducing the power consumption capacity of the display substrate and achieving advantages such as dynamic high and low refresh rates.

[0197] In some embodiments, reference Figure 17, is a circuit diagram of a pixel driving circuit in an embodiment of the present disclosure. The first reset subcircuit includes a first reset transistor T1, the threshold compensation subcircuit includes a threshold compensation transistor T2, the driving subcircuit includes a driving transistor T3, the control end of the driving subcircuit includes the control electrode of the driving transistor T3, the first end of the driving subcircuit includes the first electrode of the driving transistor T3, and the second end of the driving subcircuit includes the second electrode of the driving transistor T3. The data write subcircuit includes a data write transistor T4, the storage subcircuit includes a storage capacitor Cst, the first light emission control subcircuit includes a first light emission control transistor T5, the second light emission control subcircuit includes a second light emission control transistor T6, and the second reset subcircuit includes a second reset transistor T7.

[0198] In this embodiment, the first reset transistor T1 and the threshold compensation transistor T2 are N-type transistors; the second gate drive circuit is connected to the gates of the first reset transistor T1 and the threshold compensation transistor T2, respectively, and is configured to be turned on or off in response to a gate drive signal output by the second gate drive circuit. The first emission control transistor T5 and the second emission control transistor T6 are P-type transistors; the first gate drive circuit is connected to the gates of the first emission control transistor T5 and the second emission control transistor T6, respectively, and is configured to be turned on or off in response to a gate drive signal output by the first gate drive circuit. The driving transistor T3, the data write transistor T4, and the second reset transistor T7 are P-type transistors; the third gate drive circuit is connected to the gates of the data write transistor T4 and the second reset transistor T7, respectively, and is configured to be turned on or off in response to a gate drive signal output by the third gate drive circuit.

[0199] It should be noted that, in the embodiment of the present disclosure, the pixel driving circuit can Figure 17 In addition to the 7T1C structure shown (i.e., seven transistors and one capacitor), a circuit structure including other numbers of transistors and capacitors may also be used, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0200] In some embodiments, the first reset transistor T1 and the threshold compensation transistor T2 are bottom-gate transistors; the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6 and the second reset transistor T7 are top-gate transistors.

[0201] In some embodiments, there is no specific limitation on whether the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the second reset transistor T7 are top-gate or bottom-gate types, and each transistor can be a top-gate type or a bottom-gate type.

[0202] In some embodiments, reference Figure 18 , a schematic diagram illustrating the principle of a gate drive circuit for one-push-two unilateral drive of a display substrate in an embodiment of the present disclosure. Multiple pixel drive circuits are arranged in an array; a first gate drive circuit includes multiple first shift registers EM, which are cascaded in sequence; a second gate drive circuit includes multiple second shift registers Gate N, which are cascaded in sequence; and a third gate drive circuit includes multiple third shift registers Gate P, which are cascaded in sequence. One first shift register EM is connected to two rows of pixel drive circuits; one second shift register Gate N is connected to four rows of pixel drive circuits; and one third shift register Gate P is connected to two rows of pixel drive circuits.

[0203] In some embodiments, reference Figure 17 A first shift register EM is connected to two adjacent rows of pixel driving circuits, i.e., the output of the first shift register EM is connected to the gate of the first emission control transistor T5 and the second emission control transistor T6 of each pixel driving circuit in the two adjacent rows of pixel driving circuits. A second shift register GateN is connected to the pixel driving circuits in the 2nth, 2n+1th, 2n-14th, and 2n-13th rows, i.e., the output of the second shift register Gate N is connected to the gate of the threshold compensation transistor T2 of each pixel driving circuit in the 2nth and 2n+1th rows; and is also connected to the gate of the first reset transistor T1 of each pixel driving circuit in the 2n-14th and 2n-13th rows. A third shift register Gate P is connected to two adjacent rows of pixel driving circuits, i.e., the output of the third shift register Gate P is connected to the gate of the data write transistor T4 of each pixel driving circuit in the 2nth row of pixel driving circuits; and is also connected to the gate of the second reset transistor T7 of each pixel driving circuit in the 2n+1th row of pixel driving circuits.

[0204] In some embodiments, reference Figure 18, the 2n-1th first shift register EM (2n-1) and the 2nth first shift register EM (2n) are respectively arranged in the border areas 102 on the two opposite sides of the periphery of the display area 101; the 2n-1th first shift register EM (2n-1) is sequentially arranged along the column direction of the pixel driving circuit arrangement; the 2nth first shift register EM (2n) is sequentially arranged along the column direction of the pixel driving circuit arrangement; the 2n-1th second shift register Gate N (2n-1) and the 2nth second shift register Gate N (2n) are respectively arranged in the border areas 102 on the two opposite sides of the periphery of the display area 101; the 2n-1th second shift register Gate N (2n-1) is sequentially arranged along the column direction of the pixel driving circuit arrangement; the 2nth second shift register Gate N (2n) is sequentially arranged along the column direction of the pixel driving circuit arrangement; the 2n-1th third shift register Gate The third shift registers Gate P(2n-1) and the 2nth third shift register Gate P(2n) are respectively arranged in the border areas 102 on opposite sides of the periphery of the display area 101; the 2n-1th third shift register Gate P(2n-1) is arranged in sequence along the column direction of the pixel driving circuit arrangement; and the 2nth third shift register Gate P(2n) is arranged in sequence along the column direction of the pixel driving circuit arrangement; wherein n≥1, and n is an integer.

[0205] In some embodiments, reference Figure 19The present invention is a schematic diagram of the principle of a display substrate using a gate drive circuit for one-push-two bilateral driving in the disclosed technology; wherein, the 2n-1th first shift register EM (2n-1) in the first gate drive circuit is symmetrically distributed in the left and right side frame areas 102 of the display substrate, and the two symmetrically distributed 2n-1th first shift registers EM (2n-1) respectively drive the same two rows of pixel drive circuits from the left and right ends; the 2nth first shift register EM (2n) is symmetrically distributed in the left and right side frame areas 102 of the display substrate; and the two symmetrically distributed 2nth first shift registers EM (2n) respectively drive the same two rows of pixel drive circuits from the left and right ends. The 2n-1th second shift register Gate N(2n-1) in the second gate driving circuit is symmetrically distributed in the left and right side frame areas 102 of the display substrate, and the two symmetrically distributed 2n-1th second shift registers Gate N(2n-1) respectively drive the same two rows of pixel driving circuits from the left and right ends; the 2nth second shift register Gate N(2n) is symmetrically distributed in the left and right side frame areas 102 of the display substrate; and the two symmetrically distributed 2nth second shift registers Gate N(2n) respectively drive the same two rows of pixel driving circuits from the left and right ends. The 2n-1th third shift register Gate P(2n-1) in the third gate drive circuit is symmetrically distributed in the left and right side frame regions 102 of the display substrate. The two symmetrically distributed 2n-1th third shift registers Gate P(2n-1) drive the same two rows of pixel drive circuits from the left and right ends, respectively. The 2nth third shift register Gate P(2n) is symmetrically distributed in the left and right side frame regions 102 of the display substrate. The two symmetrically distributed 2nth third shift registers Gate P(2n) drive the same two rows of pixel drive circuits from the left and right ends, respectively. This achieves one-push-two-side dual-edge drive of the display substrate by the first, second, and third gate drive circuits.

[0206] In some embodiments, reference Figure 20, is a schematic diagram showing the principle that the first and second gate driving circuits in the display substrate of the embodiment of the present disclosure adopt one-push-two unilateral driving, and the third gate driving circuit adopts one-push-one bilateral driving; that is, the 2n-1th first shift register EM (2n-1) in the first gate driving circuit is distributed in the left side frame area 102 of the display substrate, and every 2n-1th first shift register EM (2n-1) drives two rows of pixel driving circuits from the left side; the 2nth first shift register EM (2n) is distributed in the right side frame area 102 of the display substrate; and every 2nth first shift register EM (2n) drives two rows of pixel driving circuits from the right side; the two rows of pixel driving circuits driven by every 2n-1th first shift register EM (2n-1) and every 2nth first shift register EM (2n) are different. The 2n-1th second shift register Gate N(2n-1) in the second gate drive circuit is distributed in the left side frame area 102 of the display substrate, and every 2n-1th second shift register Gate N(2n-1) drives four rows of pixel drive circuits from the left side. The 2nth second shift register Gate N(2n) is distributed in the right side frame area 102 of the display substrate, and every 2nth second shift register Gate N(2n) drives four rows of pixel drive circuits from the right side. The four rows of pixel drive circuits driven by every 2n-1th second shift register Gate N(2n-1) and every 2nth second shift register Gate N(2n) are different. This achieves one-push-two unilateral drive of the display substrate by the first and second gate drive circuits. The 2n-1th third shift register Gate P(2n-1) in the third gate drive circuit is symmetrically distributed in the left and right side frame areas 102 of the display substrate, and the two symmetrically distributed 2n-1th third shift registers Gate P(2n-1) drive the same row of pixel drive circuits from the left and right ends respectively. The 2nth third shift register Gate P(2n) is symmetrically distributed in the left and right side frame areas 102 of the display substrate, and the two symmetrically distributed 2nth third shift registers Gate P(2n) drive the same row of pixel drive circuits from the left and right ends respectively. Each 2n-1th third shift register Gate P(2n-1) and each 2nth third shift register Gate P(2n) drive a different row of pixel drive circuits. This achieves one-push-one-double-side drive of the display substrate by the third gate drive circuit.

[0207] In some embodiments, reference Figure 21 and Figure 22 , Figure 21 A schematic diagram of a gate drive circuit arrangement in which the first and second gate drive circuits in a technical display substrate adopt one-push-two double-side drive, and the third gate drive circuit adopts one-push-one double-side drive; Figure 22The present invention is a schematic diagram of the arrangement of gate drive circuits in which the first and second gate drive circuits in the display substrate adopt one-push-two unilateral drive, and the third gate drive circuit adopts one-push-one bilateral drive. The 2n-1th first shift register EM (2n-1) in the first gate drive circuit is distributed in the left side frame area 102 of the display substrate, and every 2n-1th first shift register EM (2n-1) drives two rows of pixel drive circuits from the left side. The 2nth first shift register EM (2n) is distributed in the right side frame area 102 of the display substrate, and every 2nth first shift register EM (2n) drives two rows of pixel drive circuits from the right side. The two rows of pixel drive circuits driven by every 2n-1th first shift register EM (2n-1) and every 2nth first shift register EM (2n) are different. The 2n-1th second shift register Gate N(2n-1) in the second gate drive circuit is distributed in the left side frame area 102 of the display substrate, and every 2n-1th second shift register Gate N(2n-1) drives four rows of pixel drive circuits from the left side. The 2nth second shift register Gate N(2n) is distributed in the right side frame area 102 of the display substrate, and every 2nth second shift register Gate N(2n) drives four rows of pixel drive circuits from the right side. The four rows of pixel drive circuits driven by every 2n-1th second shift register Gate N(2n-1) and every 2nth second shift register Gate N(2n) are different. This achieves one-push-two unilateral drive of the display substrate by the first and second gate drive circuits. The 2n-1th third shift register Gate P(2n-1) in the third gate drive circuit is symmetrically distributed in the left and right side frame areas 102 of the display substrate, and the two symmetrically distributed 2n-1th third shift registers Gate P(2n-1) drive the same row of pixel drive circuits from the left and right ends respectively. The 2nth third shift register Gate P(2n) is symmetrically distributed in the left and right side frame areas 102 of the display substrate, and the two symmetrically distributed 2nth third shift registers Gate P(2n) drive the same row of pixel drive circuits from the left and right ends respectively. Each 2n-1th third shift register Gate P(2n-1) and each 2nth third shift register Gate P(2n) drive a different row of pixel drive circuits. This achieves one-push-one-double-side drive of the display substrate by the third gate drive circuit.

[0208] Among them, compared with Figure 21 The distribution of the gate drive circuit, Figure 22The number of the first shift register EM and the second shift register Gate N distributed in the left and right border areas 102 and 102 of the display substrate is relatively reduced, thereby reducing the border width occupied by the first and second gate driving circuits in the left and right border areas 102, which is conducive to achieving a narrow border of the display substrate.

[0209] In some embodiments, reference Figure 22 In any of the two side frame areas 102 on the periphery of the display area 101, the distribution area of one first shift register EM corresponds to the distribution area of one second shift register Gate N; and the distribution area of one first shift register EM corresponds to the distribution area of four third shift register Gate P. In particular, since the number of the first shift register EM and the second shift register Gate N in the left and right side frame areas 102 of the display substrate is relatively large, the distribution area of the first shift register EM and the second shift register Gate N is relatively large. Figure 21 The distribution of the gate drive circuit is significantly reduced, so the distribution area of the first shift register EM and the second shift register Gate N in the frame area 102 on either side can be relatively elongated, thereby reducing the occupied area and space of the first shift register EM and the second shift register Gate N in the width direction of the frame area 102 on either side, thereby reducing the width of the left and right side frame areas 102 of the display substrate and achieving a narrow frame.

[0210] In some embodiments, reference Figure 17, the circuit connection relationship of each transistor in the 7T1C pixel driving circuit is as follows: the drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the source of the data writing transistor T4 is configured to be electrically connected to the data line Data to receive the data signal, and the gate of the data writing transistor T4 is configured to be electrically connected to the second scanning line Gate P(2n) to receive the scanning signal; the second plate of the storage capacitor Cst is electrically connected to the first power supply voltage line VDD, and the first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3; the source of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3, and the gate of the threshold compensation transistor T2 is configured to be electrically connected to the first scanning line Gate N(2n) is electrically connected to receive the compensation control signal; the source of the first reset transistor T1 is configured to be electrically connected to the first reset power line Vinit1 to receive the first reset signal, the drain of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the first reset transistor T1 is configured to be electrically connected to the first reset control line Gate N(2n-14) to receive the first reset control signal; the drain of the second reset transistor T7 is configured to be electrically connected to the second reset power line Vinit2 to receive the first reset signal, the source of the second reset transistor T7 is electrically connected to the first electrode of the light emitting element D, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control line Gate P(2n+1) is electrically connected to receive a second reset control signal; the source of the first light-emitting control transistor T5 is electrically connected to the first power supply voltage line VDD, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control line EM(2n) to receive the light-emitting control signal; the source of the second light-emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element D, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the light-emitting control line EM(2n) to receive the light-emitting control signal; the second electrode of the light-emitting element D is electrically connected to the second power supply terminal VSS.

[0211] For example, one of the first power supply voltage line VDD and the second power supply terminal VSS may be a high voltage terminal, and the other may be a low voltage terminal. For example, the first power supply voltage line VDD may be a voltage source that outputs a constant first voltage, where the first voltage is a positive voltage; and the second power supply terminal VSS may be a voltage source that outputs a constant second voltage, where the second voltage is a negative voltage. For example, in some examples, the second power supply terminal VSS may be grounded.

[0212] In some embodiments, the light-emitting element D may be a micro inorganic light-emitting diode, and further, may be a current-type light-emitting diode, such as a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED). Of course, the light-emitting element D in the embodiments of the invention may also be an organic light-emitting diode (OLED). One of the first electrode and the second electrode of the light-emitting element D is an anode, and the other is a cathode; in the embodiments of the present disclosure, the first electrode of the light-emitting element D is an anode, and the second electrode is a cathode.

[0213] In some embodiments, reference Figure 23 , for the embodiment of the present disclosure Figure 17 The working timing diagram of the pixel driving circuit in FIG. The driving method of the pixel driving circuit may include the following stages:

[0214] Reset phase (t1): A high-level signal is written to the first reset control line Gate N (2n-14), a high-level signal is written to the second reset control line Gate P (2n+1), a low-level signal is written to the first scan line Gate N (2n), a high-level signal is written to the second scan line Gate P (2n), and a high-level signal is written to the light-emitting control line EM (2n). The first reset transistor T1 and the second reset transistor T7 are turned on, driving the initialization voltage written by the first reset power line Vinit1 to the gate of the transistor T3, preparing for the writing of the data voltage Vdata for the next frame. The anode of the light-emitting element D is written with the initialization voltage (initialization voltage ≤ VSS) via the second reset power line Vinit2 connected to the second reset transistor T7, so that the light-emitting element D is no longer in the forward conduction state, and the internal electric field formed by the directional movement of impurity ions in the light-emitting element D gradually disappears, thereby restoring the characteristics of the light-emitting element D.

[0215] Data writing and threshold compensation phase (t2): A high-level signal is written to the first scan line Gate N (2n), a low-level signal is written to the first reset control line Gate N (2n-14), and a high-level signal is written to the emission control line EM (2n). The data writing transistor T4 and the threshold compensation transistor T2 are turned on. The driving transistor T3 is connected to form a diode structure by the threshold compensation transistor T2. The data voltage Vdata written on the data line Data is written to the gate of the driving transistor T3 through the data writing transistor T4 and the threshold compensation transistor T2 until the driving transistor T3 is turned off. The gate voltage of the driving transistor T3 is Vdata + Vth (Vth < 0, Vth is the threshold voltage of the driving transistor T3) and is stored in the storage capacitor Cst. The voltages of the first and second plates of the storage capacitor Cst are Vdata + Vth and Vd, respectively.

[0216] Light-emitting phase (t3): A low-level signal is written to the light-emitting control line EM (2n), and low-level signals are written to the first scan line Gate N (2n) and the first reset control line Gate N (2n-14). The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both turned on. The source of the driving transistor T3 is connected to the first power supply voltage line VDD, and the source voltage of the driving transistor T3 changes instantaneously from Vdata in the previous phase to Vdd. The light-emitting element D emits light under the drive transistor T3. At this time, the driving transistor T3 operates in the saturation region. The gate voltage of the driving transistor T3 is Vdata + Vth, and the source voltage of the driving transistor T3 is Vdd. Therefore, the gate-source voltage of the driving transistor T3 is: Vgs = (Vdata + Vth) - Vdd, until the reset phase of the next frame.

[0217] The light-emitting current of the light-emitting element D is equal to the current flowing through the driving transistor T3, and its expression is as follows:

[0218] ID=β(Vgs-Vth) 2

[0219] =β(Vdata+Vth-dd-Vth) 2

[0220] =β(Vdata-Vdd) 2 (1)

[0221] in, μ n is the electron mobility of the driving transistor T3, C ox is the insulation capacitance per unit area, is the width-to-length ratio of the driving transistor T3.

[0222] In the display substrate provided in the embodiment of the present disclosure, no gap is set between the adjacent boundary areas between the first gate drive circuit 2, the second gate drive circuit 3 and the third gate drive circuit 4, and the flat layer 5 is not disconnected between the adjacent boundary areas of any two, but is set on the entire surface; in this way, the gap setting between any two adjacent ones of the first gate drive circuit 2, the second gate drive circuit 3 and the third gate drive circuit 4 is eliminated, so that at least partial circuits in the adjacent boundary areas between the three are interspersed with each other in the spatial areas where each other is located, realizing the mixing or mutual borrowing of the space between any two adjacent gate drive circuits, thereby reducing the width of the border area 102 of the display substrate; in addition, the display substrate combines the advantages of strong driving capability of low-temperature polysilicon transistors and low leakage and low power consumption of metal oxide transistor processes, thereby greatly reducing the power consumption capability of the display substrate and achieving advantages such as dynamic high and low refresh rates.

[0223] In a second aspect, an embodiment of the present disclosure further provides a display panel, comprising the display substrate in the above embodiment.

[0224] By adopting the display substrate in the above embodiment, not only the display advantages of the display panel such as low power consumption and dynamic high and low refresh rates are achieved, but also the narrow frame of the display panel is achieved.

[0225] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel in the above embodiment.

[0226] By adopting the display panel in the above embodiment, not only the display advantages of the display device such as low power consumption and dynamic high and low refresh rates are achieved, but also the narrow frame of the display device is achieved.

[0227] The display device can be any product or component with a display function, such as an OLED panel, an OLED TV, a mobile phone, a tablet computer, a laptop computer, a monitor, a digital photo frame, a navigator, or the like.

[0228] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising: substrate; A plurality of light-emitting elements are located in the display area; A plurality of pixel driving circuits are located on the substrate, and the light-emitting element is located on a side of the pixel driving circuit away from the substrate; The plurality of pixel driving circuits are connected to the plurality of light emitting elements respectively; The pixel driving circuit includes an N-type transistor and a P-type transistor; A first gate driving circuit, a second gate driving circuit and a third gate driving circuit are located on the substrate and are distributed in at least one side frame area outside the display area; The first gate driving circuit and the third gate driving circuit are connected to the P-type transistors in each of the pixel driving circuits; The second gate driving circuit is connected to the N-type transistor in each of the pixel driving circuits; The third gate driving circuit, the second gate driving circuit and the first gate driving circuit are arranged in sequence in a direction away from the display area, and their orthographic projections on the substrate do not overlap with each other; Wherein, adjacent boundary areas of the orthographic projections of the first gate driving circuit and the second gate driving circuit on the substrate are at least partially nested; A planar layer is located between the pixel driving circuit and the light-emitting element, and the planar layer also extends to entirely cover the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit.

2. The display substrate according to claim 1, wherein The adjacent boundary areas of the orthographic projections of the second gate driving circuit and the third gate driving circuit on the substrate are at least partially nested.

3. The display substrate according to claim 2, wherein: A first notch region is formed in a portion of the boundary region of the first gate driving circuit close to the second gate driving circuit; a first protrusion region is formed in a portion of the boundary region of the second gate driving circuit close to the first gate driving circuit extending toward the region where the first gate driving circuit is located; The first protruding area is correspondingly located in the first notch area, and the first protruding area and the first notch area are adapted to the orthographic projection shape on the substrate; And / or, a second notch area is partially formed in a boundary area of the second gate driving circuit close to the first gate driving circuit; and a local boundary area of the first gate driving circuit close to the second gate driving circuit extends toward the area where the second gate driving circuit is located to form a second protruding area; The second protruding area is correspondingly located in the second notch area, and the second protruding area and the second notch area are matched in orthographic projection shape on the substrate.

4. The display substrate according to claim 3, wherein: In an adjacent boundary area between the first gate driving circuit and the second gate driving circuit, part of the wiring of the first gate driving circuit extends to an area where the second gate driving circuit is located; And / or, part of the wiring of the second gate driving circuit extends to the area where the first gate driving circuit is located.

5. The display substrate according to claim 3 or 4, wherein: A third notch area is formed partially in the boundary area of the second gate driving circuit close to the third gate driving circuit; and a local boundary area of the third gate driving circuit close to the second gate driving circuit extends toward the area where the second gate driving circuit is located to form a third protruding area; The third protruding area is correspondingly located in the third notch area, and the third protruding area is adapted to the orthographic projection shape of the third notch area on the substrate; And / or, a fourth notch area is partially formed in a boundary area of the third gate driving circuit close to the second gate driving circuit; and a local boundary area of the second gate driving circuit close to the third gate driving circuit extends toward the area where the third gate driving circuit is located to form a fourth protruding area; The fourth protruding area is correspondingly located in the fourth notch area, and the orthographic projection shapes of the fourth protruding area and the fourth notch area on the substrate are adapted. The display substrate according to claim 5 , wherein: In an adjacent boundary area between the second gate driving circuit and the third gate driving circuit, part of the wiring of the second gate driving circuit extends to an area where the third gate driving circuit is located; And / or, part of the wiring of the third gate driving circuit extends to the area where the second gate driving circuit is located.

7. The display substrate according to claim 6, wherein: comprising a first semiconductor layer and a first conductive layer, which are sequentially stacked on the substrate, with a gate insulating layer provided between the first semiconductor layer and the first conductive layer; The first gate driving circuit, the second gate driving circuit and the third gate driving circuit each include a plurality of transistors and a plurality of capacitors; The first semiconductor layer includes a pattern of an active layer of the transistor; The first conductive layer includes a pattern of a gate of the transistor, a first connecting line connected to the gate, a first plate of the capacitor, and a second connecting line connected to the first plate; Part of the pattern of the active layer in the first semiconductor layer is located in the first protruding area; Part of the gate electrode and part of the first connection line pattern in the first conductive layer are located in the first protruding area.

8. The display substrate according to claim 7, wherein: It also includes a second conductive layer located on a side of the first conductive layer away from the substrate; a first passivation layer is provided between the second conductive layer and the first conductive layer; The second conductive layer includes a pattern of a second plate of the capacitor and a third connecting line; Part of the pattern of the third connecting line in the second conductive layer is located in the first protruding area.

9. The display substrate according to claim 8, wherein: The second conductive layer further includes a pattern of fourth connecting lines; Part of the fourth connecting lines extends from the area where the first gate driving circuit is located to the area where the second gate driving circuit is located.

10. The display substrate according to claim 9, wherein: Part of the fourth connecting lines further extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

11. The display substrate according to any one of claims 8 to 10, wherein: It also includes a third conductive layer located on a side of the second conductive layer away from the substrate; a second passivation layer is provided between the third conductive layer and the second conductive layer; The third conductive layer includes a pattern of fifth connecting lines; Part of the fifth connecting lines extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

12. The display substrate according to claim 11, wherein: Also comprising a fourth conductive layer located on a side of the third conductive layer away from the substrate; A first intermediate dielectric layer and a second intermediate dielectric layer are provided between the fourth conductive layer and the third conductive layer; the first intermediate dielectric layer and the second intermediate dielectric layer are stacked in sequence away from the third conductive layer; A first layer of via holes is provided in the first intermediate dielectric layer, and the first layer of via holes is used to connect the conductive pattern in the fourth conductive layer with the conductive pattern in the third conductive layer; The second intermediate dielectric layer is provided with a second layer of via holes, the second layer of via holes being used to connect the conductive pattern in the fourth conductive layer with the conductive pattern in the first conductive layer and the conductive pattern in the second conductive layer respectively; The fourth conductive layer includes a source electrode, a drain electrode and a pattern of a sixth connecting line of the transistor; the sixth connecting line is used to connect the source electrode, the drain electrode and the gate electrode; Part of the source electrode, part of the drain electrode, and part of the sixth connection line pattern in the fourth conductive layer are located in the first protruding area.

13. The display substrate according to claim 12, wherein: The fourth conductive layer further includes a pattern of a seventh connecting line; Part of the seventh connecting line extends from the area where the first gate driving circuit is located to the area where the second gate driving circuit is located; Part of the seventh connecting line extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

14. The display substrate according to claim 13, wherein: The fourth conductive layer further includes a pattern of an eighth connecting line; Part of the eighth connecting line extends from the area where the second gate driving circuit is located to the area where the third gate driving circuit is located.

15. The display substrate according to claim 12, wherein: Also includes: A first group of signal lines connected to the first gate drive circuit; a second group of signal lines connected to the second gate drive circuit; A third group of signal lines connected to the third gate drive circuit; The orthographic projection of the first group of signal lines on the substrate overlaps with the first gate driving circuit; The orthographic projection of the second group of signal lines on the substrate overlaps with the second gate driving circuit; The orthographic projection of the third group of signal lines on the substrate overlaps with the third gate driving circuit.

16. The display substrate according to claim 15, wherein: The first group of signal lines, the second group of signal lines and the third group of signal lines respectively include a power signal line, a clock signal line and a trigger signal line; The power signal line includes a first power signal line and a second power signal line; The clock signal lines in the first group of signal lines and the second group of signal lines include a first clock signal line, a second clock signal line and a third clock signal line; The fourth conductive layer further includes patterns of the second power signal line in the first group of signal lines and the second clock signal line in the second group of signal lines.

17. The display substrate according to claim 16, wherein: Also comprising a fifth conductive layer located on a side of the fourth conductive layer away from the substrate; The planar layer includes a first sublayer, and the first sublayer is located between the fourth conductive layer and the fifth conductive layer; The fifth conductive layer further includes patterns of other signal lines in the first group of signal lines, the second group of signal lines, and the third group of signal lines except the second power signal line in the first group of signal lines and the second clock signal line in the second group of signal lines.

18. The display substrate according to claim 17, wherein: The pixel driving circuit is connected to a first reset power line and a second reset power line; The fifth conductive layer further includes patterns of a first reset power line and a second reset power line; The orthographic projections of the first reset power line and the second reset power line on the substrate overlap with the third gate driving circuit; An orthographic projection of the first reset power line on the substrate covers the capacitor in the third gate driving circuit.

19. The display substrate according to claim 18, wherein: Also comprising a sixth conductive layer located on a side of the fifth conductive layer away from the substrate; The planar layer further includes a second sublayer, wherein the second sublayer is located between the fifth conductive layer and the sixth conductive layer; The sixth conductive layer includes a pattern of the first group of signal lines, the second group of signal lines, the third group of signal lines, the first reset power line, and the second reset power line; The sixth conductive layer overlaps with the orthographic projection of the same signal line in the fifth conductive layer and the fourth conductive layer on the substrate and is connected through a via hole opened in the second sub-layer.

20. The display substrate according to claim 1, wherein Also includes: A first group of signal lines connected to the first gate drive circuit; a second group of signal lines connected to the second gate drive circuit; A third group of signal lines connected to the third gate drive circuit; The first group of signal lines is arranged on a side of the first gate driving circuit away from the display area; The second group of signal lines and the third group of signal lines are arranged on a side of the third gate driving circuit close to the display area, and orthographic projections of the third group of signal lines and the second group of signal lines on the substrate do not overlap with each other.

21. The display substrate according to claim 1, wherein Also includes: A first group of signal lines connected to the first gate drive circuit; a second group of signal lines connected to the second gate drive circuit; The first group of signal lines is arranged on a side of the first gate driving circuit away from the display area; The second group of signal lines is arranged in a region between the second gate driving circuit and the third gate driving circuit.

22. The display substrate according to claim 21, wherein Also includes: A third group of signal lines connected to the third gate drive circuit; The third group of signal lines is arranged in a region between the second gate driving circuit and the third gate driving circuit, and orthographic projections of the third group of signal lines and the second group of signal lines on the substrate do not overlap with each other; Alternatively, the third group of signal lines is arranged on a side of the third gate driving circuit close to the display area.

23. The display substrate according to claim 1, wherein The plurality of pixel driving circuits are arranged in an array; The first gate driving circuit includes a plurality of first shift registers, and the plurality of first shift registers are cascaded in sequence; The second gate driving circuit includes a plurality of second shift registers, and the plurality of second shift registers are cascaded in sequence; The third gate driving circuit includes a plurality of third shift registers, and the plurality of third shift registers are cascaded in sequence; One of the first shift registers is correspondingly connected to two rows of the pixel driving circuits; One second shift register is correspondingly connected to four rows of pixel driving circuits; One of the third shift registers is correspondingly connected to two rows of pixel driving circuits.

24. The display substrate according to claim 23, wherein: The 2n-1th first shift register and the 2nth first shift register are respectively arranged in the frame areas on two opposite sides of the periphery of the display area; The 2n-1th first shift registers are sequentially arranged along the column direction in which the pixel driving circuits are arranged; the 2nth first shift registers are sequentially arranged along the column direction in which the pixel driving circuits are arranged; The 2n-1th second shift register and the 2nth second shift register are respectively arranged in the frame areas on two opposite sides of the periphery of the display area; The 2n-1th second shift registers are sequentially arranged along the column direction of the pixel driving circuits; the 2nth second shift registers are sequentially arranged along the column direction of the pixel driving circuits; The 2n-1th third shift register and the 2nth third shift register are respectively arranged in the frame areas on two opposite sides of the periphery of the display area; The 2n-1th second shift registers are sequentially arranged along the column direction of the pixel driving circuits; the 2nth second shift registers are sequentially arranged along the column direction of the pixel driving circuits; Wherein, n≥1, and n is an integer.

25. The display substrate according to claim 24, wherein: In the frame area on either side of the frame areas on two opposite sides of the periphery of the display area, a distribution area of the first shift register corresponds to a distribution area of the second shift register; The distribution area of one first shift register corresponds to the distribution areas of four third shift registers.

26. A display panel, wherein: A display substrate comprising any one of claims 1-25.

27. A display device, wherein: Includes the display panel according to claim 26.

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