Array substrate and display panel
By designing repair holes on the transparent shielding electrode, the problem of short circuit between the transparent electrode layer and the metal line in the TSS pixel structure is solved, and the repair yield of the array substrate is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2023-02-03
- Publication Date
- 2026-06-05
AI Technical Summary
In the TSS pixel structure, short circuits are prone to occur between the TSS transparent electrode layer and the metal lines, which leads to a decrease in the repair yield of the array substrate.
By designing repair holes on the transparent shielding electrode, the molten metal on the laser cross-section can be formed inside the repair holes, reducing the probability of short circuits between the transparent shielding electrode and the metal wire and improving the repair yield.
By setting repair holes on the transparent shielding electrode, the probability of short circuits between the molten metal and the data lines or scan lines is reduced, thereby improving the repair yield of the array substrate.
Smart Images
Figure CN117492288B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology
[0002] The existing TSS (Transparent Storage Capacity and Shielding Layer) pixel structure (adding a TSS transparent electrode layer to replace DBS (data line BM less)). The TSS transparent electrode layer overlaps with the data line, which can shield the electric field of the data line. In addition, a large transparent storage capacitance is formed between the TSS transparent electrode layer and the pixel electrode layer, which can significantly improve transmittance and storage capacitance. However, in the TSS pixel structure, since the TSS transparent electrode layer covers the metal line (data line, etc.), there will be molten metal on the laser cut surface during the laser repair process. The molten metal causes a short circuit between the TSS transparent electrode layer and the metal line, which affects the repair success rate of the array substrate and leads to a decrease in the repair yield of the array substrate. Summary of the Invention
[0003] In view of this, this application provides an array substrate and display panel that can reduce the probability of short circuits between the TSS transparent electrode layer and the metal lines, and improve the repair yield of the metal lines of the array substrate.
[0004] To solve the above problems, the technical solution provided in this application is as follows:
[0005] This application provides an array substrate, comprising:
[0006] First base;
[0007] A first metal layer is located on the first substrate and includes scan lines;
[0008] The second metal layer is located on the side of the first metal layer opposite to the first substrate and includes data lines;
[0009] A third metal layer, located on the side of the second metal layer opposite to the first metal layer, and including a pixel electrode; and
[0010] A fourth metal layer, located between the third metal layer and the second metal layer, includes a transparent shielding electrode. The orthographic projection of the transparent shielding electrode on the first substrate covers the orthographic projection of at least one of the data line and the scan line on the first substrate. The connection electrode is electrically connected to the transparent shielding electrode and to the common signal line.
[0011] The transparent shielding electrode has at least one repair hole, and the orthogonal projection of the repair hole on the first substrate covers a portion of the orthogonal projection of the data line or the scan line on the first substrate.
[0012] In one optional embodiment of this application, the size of the repair hole is greater than the width of the data cable in the direction perpendicular to the extension direction of the data cable; or
[0013] The size of the repair hole is greater than the width of the scan line in the direction perpendicular to the extension direction of the scan line.
[0014] In an optional embodiment of this application, two adjacent data lines and two adjacent scan lines constitute a sub-pixel region, and each data line and each scan line located within the same sub-pixel region has at least one repair hole.
[0015] In an optional embodiment of this application, each data line and each scan line located within the same sub-pixel region has one repair hole; or
[0016] Each of the data lines and the scan lines located within the same sub-pixel region has at least two repair holes; or
[0017] The number of repair holes on each of the scan lines or data lines located within the same sub-pixel region is less than the number of repair holes on the other of the scan lines or data lines.
[0018] In an optional embodiment of this application, the number of repair holes is multiple, the transparent shielding electrode covers the data line and the scan line, and the orthographic projection of some of the repair holes on the first substrate covers the partial orthographic projection of the data line on the first substrate; the orthographic projection of another part of the repair holes on the first substrate covers the partial orthographic projection of the scan line on the first substrate.
[0019] In an optional embodiment of this application, the first metal layer further includes a gate electrode, which is electrically connected to the scan line; the second metal layer further includes a source electrode and a drain electrode spaced apart, which are electrically connected to the data line; the source electrode and the drain electrode are respectively positioned opposite to the gate electrode; the pixel electrode is electrically connected to the drain electrode; the data signal enters the source electrode, the drain electrode and the pixel electrode sequentially from the data line; the common signal enters the connection electrode and the transparent shielding electrode sequentially from the common signal line.
[0020] In an optional embodiment of this application, the connecting electrode is electrically connected to the transparent shielding electrode through a first connecting hole and electrically connected to the common signal line through a second connecting hole.
[0021] In an optional embodiment of this application, the first connecting hole and the second connecting hole are spaced apart or connected.
[0022] In an optional embodiment of this application, the array substrate further includes a color resist layer and a passivation layer. The passivation layer is located between the second metal layer and the color resist layer, and the color resist layer is located between the passivation layer and the fourth metal layer. The orthogonal projections of the first connection hole and the second connection hole on the first substrate fall on or outside the orthogonal projection of the color resist layer on the first substrate.
[0023] This application also provides a display panel, including a color filter substrate and a liquid crystal, wherein the display panel further includes an array substrate as described above, and the liquid crystal is located between the color filter substrate and the array substrate.
[0024] The array substrate and display panel provided in this application form at least one repair hole on the transparent shielding electrode of the corresponding data line or scan line. When the data line or scan line needs to be laser-repaired due to breakage, damage, or other factors affecting its conductivity, the molten metal on the laser cut surface can be formed in the repair hole. The probability of the molten metal contacting the transparent shielding electrode is reduced, and the probability of a short circuit between the transparent shielding electrode and the metal lines such as the data line or scan line is reduced, thereby improving the repair yield of the metal lines of the array substrate. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a cross-sectional view of a display panel provided in a preferred embodiment of this application.
[0027] Figure 2 for Figure 1 The diagram shows a top view of the array substrate (including data lines, scan lines, and transparent shielding electrodes) of the display panel.
[0028] Figure 3 for Figure 1 A top view of another array substrate (including data lines, scan lines, and transparent shielding electrodes) of the display panel shown.
[0029] Figure 4 for Figure 1 The cross-sectional view of the first metal layer shown.
[0030] Figure 5 for Figure 1 The cross-sectional view of the second metal layer shown.
[0031] Figure 6 for Figure 1 The cross-sectional view of the third metal layer shown. Detailed Implementation
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0033] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0034] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.
[0035] The array substrate and display panel provided in this application will be described in detail below with reference to specific embodiments and accompanying drawings.
[0036] Please see Figure 1 A preferred embodiment of this application provides a display panel 1000, which includes an array substrate 100, a color filter substrate 200, and a liquid crystal (not shown). The liquid crystal is located between the color filter substrate 200 and the array substrate 100.
[0037] The array substrate 100 includes a first substrate 10, a first metal layer 20, a second metal layer 50, a third metal layer 90, and a fourth metal layer 70. The first metal layer 20 is located on the first substrate 10 and includes scan lines 21. The second metal layer 50 is located on the side of the first metal layer 20 opposite to the first substrate 10 and includes data lines 51. The third metal layer 90 is located on the side of the second metal layer 50 opposite to the first metal layer 20 and includes pixel electrodes 91. The fourth metal layer 70 is located between the third metal layer 90 and the second metal layer 50 and includes a transparent shielding electrode 71. The orthographic projection of the transparent shielding electrode 71 on the first substrate 10 covers the orthographic projection of at least one of the data lines 51 and the scan lines 21 on the first substrate 10. The transparent shielding electrode 71 has at least one repair hole 711, and the orthographic projection of the repair hole 711 on the first substrate 10 covers a portion of the orthographic projection of the data lines 51 or the scan lines 21 on the first substrate 10. That is, some of the data lines 51 can be exposed from the corresponding repair holes 711.
[0038] In this embodiment, at least one repair hole 711 is formed on the transparent shielding electrode 71 corresponding to the data line 51 or the scan line 21. When the data line 51 or the scan line 21 needs to be laser-repaired due to breakage, damage, or other factors affecting its conductivity, the molten metal on the laser cut surface can be formed in the repair hole. This reduces the probability of the molten metal coming into contact with the transparent shielding electrode 71 and reduces the probability of a short circuit between the transparent shielding electrode 71 and the metal lines such as the data line 51 or the scan line 21, thereby improving the repair yield of the array substrate 100.
[0039] In an optional embodiment of this application, the orthographic projection of the transparent shielding electrode 71 on the first substrate 10 also covers the orthographic projection of the scan line 21 on the first substrate 10, and the orthographic projection of the repair hole 711 on the first substrate 10 covers a portion of the orthographic projection of the scan line 21 on the first substrate 10. That is, a portion of the scan line 21 can be exposed from the corresponding repair hole 711.
[0040] In an optional embodiment of this application, the size of the repair hole 711 is greater than the width of the data line 51 or the scan line 21 in a direction perpendicular to the extension direction of the data line 51 or the scan line 21. This further reduces the probability of molten metal on the laser cut surface contacting the transparent shielding electrode 71 during laser repair of the data line 51 and / or scan line 21 of the array substrate 100, thereby further reducing the probability of a short circuit between the transparent shielding electrode 71 and the metal lines such as the data line 51 or the scan line 21, and thus further improving the repair yield of the array substrate 100.
[0041] The data line 51 extends along the first direction X, the scan line 21 extends along the second direction Y, and the array substrate 100 and the color filter substrate 200 are stacked on the third direction Z. The first direction X, the second direction Y, and the third direction Z constitute an XYZ coordinate system, where the first direction X is perpendicular to the second direction Y, and the third direction Z is perpendicular to both the first direction X and the second direction Y.
[0042] Please see Figure 2 and Figure 3 In an optional embodiment of this application, two adjacent data lines 51 and two adjacent scan lines 21 constitute a sub-pixel region, and each data line 51 and each scan line 21 located in the same sub-pixel region has at least one repair hole 711.
[0043] Specifically, please refer to Figure 2 In an optional embodiment of this application, each data line 51 and each scan line 21 located within the same sub-pixel region has a repair hole 711.
[0044] Specifically, please refer to Figure 3 In an optional embodiment of this application, please refer to Figure 3Each data line 51 located within the same sub-pixel region has two repair holes 711, and each scan line 21 located within the same sub-pixel region has one repair hole 711. Of course, in other embodiments, the number of repair holes 711 on each data line 51 and / or each scan line 21 located within the same sub-pixel region is not limited to two, but can be two or more. Compared to having only one repair hole 711 on each data line 51 and each scan line 21 located within the same sub-pixel region, providing at least two repair holes 711 on at least one of each data line 51 and each scan line 21 located within the same sub-pixel region can increase the selectivity of the repair location for the data line or the scan line, and improve the repair yield.
[0045] The number of repair holes on each of the scan lines or data lines located within the same sub-pixel region is less than the number of repair holes on the other of the scan lines or data lines.
[0046] Of course, the number and position of the repair holes 711 on each of the data lines 51 and each of the scan lines 21 need to be set according to the actual situation, and are not limited to the data in the examples mentioned above.
[0047] Please see Figure 1 , Figure 4 and Figure 5 In an optional embodiment of this application, the first metal layer 20 further includes a common signal line 22 and a gate 23. The common signal line 22 is disposed on the same layer as the scan line 21 and the gate 23, and the extension direction of the common signal line 22 is consistent with the extension direction of the scan line 21. The gate 23 is electrically connected to the scan line 21.
[0048] The second metal layer 50 further includes a source electrode 52 and a drain electrode 53 spaced apart. The source electrode 52 is electrically connected to the data line 51, and the source electrode 52 and the drain electrode 53 are respectively positioned opposite the gate electrode 23. The array substrate 100 also includes an active layer 40 located on one side of the gate electrode 23. The array substrate 100 also includes a plurality of transistors, each transistor including a gate electrode 23, an active layer 40, and a source electrode 52 and a drain electrode 53 corresponding to the gate electrode 23 and the active layer 40. The pixel electrode 91 is electrically connected to the drain electrode 53. Data signals sequentially enter the source electrode 52, the drain electrode 53, and the pixel electrode 91 from the data line 51.
[0049] Please see Figure 1In an optional embodiment of this application, the third metal layer 90 further includes a connecting electrode 92, which is electrically connected to the transparent shielding electrode 71 and to the common signal line 22. The common signal enters the connecting electrode 92 and the transparent shielding electrode 71 sequentially from the common signal line 22.
[0050] The connecting electrode 92 is electrically connected to the transparent shielding electrode 71 through a first connecting hole 94 and to the common signal line 22 through a second connecting hole 95. The pixel electrode 91 is electrically connected to the drain electrode 53 through a third connecting hole 93.
[0051] Specifically, please refer to [the relevant document] again. Figure 1 In one optional embodiment of this application, the first connecting hole 94 and the second connecting hole 95 are spaced apart. In other embodiments of this application, the first connecting hole 94 and the second connecting hole 95 may also be connected (not shown in the figure). Of course, if the first connecting hole 94 and the second connecting hole 95 are connected, an undercut structure may occur at the connection position, posing a risk of wire breakage. Spaced arrangement of the first connecting hole 94 and the second connecting hole 95 can avoid the undercut structure, thereby avoiding the risk of wire breakage.
[0052] In an optional embodiment of this application, the array substrate 100 further includes a color resist layer 62 and a passivation layer 61. The passivation layer 61 is located between the second metal layer 50 and the color resist layer 62, and the color resist layer 62 is located between the passivation layer 61 and the fourth metal layer 70. A portion of the fourth metal layer 70 is also formed on a portion of the passivation layer 61.
[0053] Specifically, please refer to [the relevant document] again. Figure 1 In an optional embodiment of this application, the orthographic projections of the first connection hole 94 and the second connection hole 95 on the first substrate 10 fall outside the orthographic projection of the color resist layer 62 on the first substrate 10.
[0054] The color resist layer 62 may include a plurality of color resist blocks spaced apart. In this embodiment, the color resist blocks are red, green, and blue color resist blocks.
[0055] In an optional embodiment of this application, the orthographic projections of the first connection hole 94 and the second connection hole 95 on the first substrate 10 may also fall on the orthographic projection of the color resist layer 62 on the first substrate 10.
[0056] Specifically, since the light transmittance of the blue color resist is lower than that of the red and green color resists, the orthographic projections of the first connecting hole 94 and the second connecting hole 95 on the first substrate 10 can also fall on the orthographic projection of the blue color resist on the first substrate 10. This increases the aperture ratio of the blue color resist, thereby increasing the light transmittance of the color resist layer 62. Of course, the orthographic projections of the first connecting hole 94 and the second connecting hole 95 on the first substrate 10 can also fall on the orthographic projections of the red and green color resists on the first substrate 10.
[0057] In an optional embodiment of this application, the first connecting hole 94 and the second connecting hole 95 may be located on different blue color resist blocks or on the same blue color resist block. The first connecting hole 94 and the second connecting hole 95 may be located on two blue color resist blocks of two adjacent pixels, or on two blue color resist blocks of two non-adjacent pixels. Here, the two blue color resist blocks of two non-adjacent pixels may be two blue color resist blocks of two pixels in the same row, or two blue color resist blocks of two pixels in different rows.
[0058] Please continue reading. Figure 1 The array substrate 100 further includes a planarization layer 80 and a gate insulating layer 30. The planarization layer is formed on the color resist layer 62 and covers the fourth metal layer 70 and a portion of the passivation layer 61. The gate insulating layer 30 is formed on the first substrate 10 and covers the first metal layer 20. The active layer 40 is formed on the gate insulating layer 30. The passivation layer 61 also covers a portion of the gate insulating layer 30. The third connection hole 93 penetrates the planarization layer 80 and the passivation layer 61. The first connection hole 94 penetrates the planarization layer 80. The second connection hole 95 penetrates the planarization layer 80, the passivation layer 61, and the gate insulating layer 30.
[0059] The color filter substrate 200 includes a second substrate 201, a patterned black matrix 202 formed on the second substrate 201, and a common electrode 203 formed on the second substrate 201 and covering the black matrix 202, wherein the common electrode 203 faces the pixel electrode 91.
[0060] Please see Figure 6In an optional embodiment of this application, the pixel electrode 91 includes a first main stem 911, a second main stem 912, a first branch 913, and a second branch 914. The first main stem 911 and the second main stem 912 are arranged in a cross shape. A plurality of first branches 913 are obliquely fixed to the first main stem 911, and a plurality of second branches 914 are obliquely fixed to the second main stem 912. The plurality of first branches 913 extend away from the second main stem 912, and the plurality of second branches 914 extend away from the first main stem 911. In this embodiment, the pixel electrode 91 has 4 domains, and the first branches 913 and second branches 914 within the same domain extend in the same direction. In other embodiments, the number of domains of the pixel electrode 91 is not limited to 4 and can be other numbers. The shape of the pixel electrode 91 is also not limited to the above-described structure.
[0061] The connecting electrode 92 includes a first connecting portion 921 and a second connecting portion 922. The first connecting portion 921 corresponds to the first connecting hole 94 and / or the second connecting hole 95, and is electrically connected to the transparent shielding electrode 71 and / or to the common signal line 22. The second connecting portion 922 is connected to the first connecting portion 921 and covers the scan line 21.
[0062] Both the pixel electrode 91 and the connecting electrode 92 are transparent, and the material of the pixel electrode 91 and the connecting electrode 92 is indium tin oxide (ITO). Of course, the material of the pixel electrode 91 and the connecting electrode 92 is not limited to ITO, and can also be other transparent electrode materials.
[0063] The array substrate and display panel provided in this application form at least one repair hole on the transparent shielding electrode of the corresponding data line or scan line. When the data line or scan line needs to be laser-repaired due to breakage, damage, or other factors affecting its conductivity, the molten metal on the laser cut surface can be formed in the repair hole. The probability of the molten metal contacting the transparent shielding electrode is reduced, and the probability of a short circuit between the transparent shielding electrode and the metal lines such as the data line or scan line is reduced, thereby improving the repair yield of the metal lines of the array substrate.
[0064] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.
Claims
1. An array substrate, characterized in that, include: First base; A first metal layer is located on the first substrate and includes scan lines; A second metal layer is located on one side of the first metal layer and includes data lines; A third metal layer is located on the side of the second metal layer opposite to the first metal layer and includes a pixel electrode; and A fourth metal layer, located between the third metal layer and the second metal layer, includes a transparent shielding electrode, the orthographic projection of which onto the first substrate covers the orthographic projection of at least one of the data line and the scan line onto the first substrate; The transparent shielding electrode has at least one repair hole, and the orthogonal projection of the repair hole on the first substrate covers a portion of the orthogonal projection of the data line or the scan line on the first substrate.
2. The array substrate as described in claim 1, characterized in that, The size of the repair hole is greater than the width of the data cable in the direction perpendicular to the extension direction of the data cable; or The size of the repair hole is greater than the width of the scan line in the direction perpendicular to the extension direction of the scan line.
3. The array substrate as described in claim 1, characterized in that, Two adjacent data lines and two adjacent scan lines constitute a sub-pixel region, and each data line and each scan line located within the same sub-pixel region has at least one repair hole.
4. The array substrate as described in claim 3, characterized in that, Each data line and each scan line located within the same sub-pixel region has one of the repair holes; or Each of the data lines and the scan lines located within the same sub-pixel region has at least two repair holes; or The number of repair holes on one of the scan lines or data lines located within the same sub-pixel region is less than the number of repair holes on the other.
5. The array substrate as described in claim 1, characterized in that, The number of repair holes is multiple, and the transparent shielding electrode covers the data line and the scan line. The orthographic projection of some of the repair holes on the first substrate covers the orthographic projection of the data line on the first substrate; the orthographic projection of another part of the repair holes on the first substrate covers the orthographic projection of the scan line on the first substrate.
6. The array substrate according to any one of claims 1-5, characterized in that, The first metal layer also includes a common signal line and a gate, wherein the gate is electrically connected to the scan line; The second metal layer further includes a source electrode and a drain electrode spaced apart, the source electrode being electrically connected to the data line; the source electrode and the drain electrode are respectively positioned opposite to the gate electrode; the pixel electrode is electrically connected to the drain electrode; The third metal layer also includes connecting electrodes; The data signal enters the source electrode, the drain electrode, and the pixel electrode sequentially from the data line; the common signal enters the connection electrode and the transparent shielding electrode sequentially from the common signal line.
7. The array substrate as described in claim 6, characterized in that, The connecting electrode is electrically connected to the transparent shielding electrode through the first connecting hole and to the common signal line through the second connecting hole.
8. The array substrate as described in claim 7, characterized in that, The first connecting hole and the second connecting hole are spaced apart or connected.
9. The array substrate as described in claim 8, characterized in that, The array substrate further includes a color resist layer and a passivation layer. The passivation layer is located between the second metal layer and the color resist layer, and the color resist layer is located between the passivation layer and the fourth metal layer. The orthogonal projections of the first connection hole and the second connection hole on the first substrate fall on or outside the orthogonal projection of the color resist layer on the first substrate.
10. A display panel, comprising a color filter substrate and a liquid crystal, characterized in that, The display panel further includes an array substrate as described in any one of claims 1-9, wherein the liquid crystal is located between the color filter substrate and the array substrate.