Computing circuitry

Abstract

The application relates to a computing circuit, comprising a plurality of different types of computing units arranged in an array, each computing unit comprising a multiplication computing circuit, a pre-charging circuit and a computing result output circuit; the computing result output circuit comprises N output channels, and is used for turning off M output channels in the N output channels according to a first target voltage signal, so as to perform charging operation or discharging operation according to N-M output channels under the control of a computing output node voltage after receiving a signal input voltage, and obtain a computing result of the multiplication computing circuit of the computing unit through N-M times of charging operation or discharging operation, wherein the computing result is a computing result obtained by the computing unit according to the signal input voltage and a first neural network weight value, and the first neural network weight value is obtained according to an initial neural network weight value and the number N-M of charging operation or discharging operation. The computing circuit provided by the application can reduce power consumption and improve integration.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a computing circuit. Background Technology

[0002] Reconfigurable Neural Network Array Circuits (RNNA) are a type of neural network architecture that allows weights to be modified at runtime to adapt to different tasks and application scenarios.

[0003] In existing technologies, most weight-reconfigurable neural networks are implemented based on static random-access memory (SRAM).

[0004] However, this SRAM-based weighted reconfigurable neural network has high power consumption and low integration density. Summary of the Invention

[0005] Therefore, it is necessary to provide a computing circuit with low power consumption and high integration to address the above-mentioned technical problems and realize a weight-reconfigurable neural network.

[0006] This application provides a computing circuit comprising multiple computing units of different types arranged in an array. Each computing unit includes a multiplication calculation circuit, a pre-charge circuit, and a calculation result output circuit, and the calculation result output circuits of different types of computing units are different. The multiplication calculation circuit includes a first ferroelectric transistor and a second ferroelectric transistor interconnected. The pre-charge circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistive state under the drive of a write voltage to characterize the initial neural network weight values. The pre-charge circuit is used to adjust the computing output node to the target voltage. The circuit is used to receive the signal input voltage after the calculation output node is adjusted to the target voltage. The calculation result output circuit includes N output paths and is used to turn off M of the N output paths according to the first target voltage signal. After receiving the signal input voltage, under the control of the voltage of the calculation output node, the circuit performs charging or discharging operations according to the NM output paths respectively. The calculation result is obtained by the multiplication calculation circuit of the calculation unit through NM charging or discharging operations. The calculation result is the calculation result obtained by the calculation unit according to the signal input voltage and the first neural network weight value. The first neural network weight value is obtained according to the initial neural network weight value and the number of charging or discharging operations NM, where N and M are positive integers.

[0007] In one embodiment, the calculation result output circuit includes N sub-output circuits, each of which is used to perform the charging operation or the discharging operation through a different output path.

[0008] In one embodiment, the sub-output circuit includes a first transistor and a second transistor, the gates of the first transistor and the second transistor being connected to the compute output node.

[0009] In one embodiment, the calculation result output circuit is used to adjust the voltage of the first terminal of the first transistor and the second transistor in the M output paths according to the first target voltage signal, so as to turn off the M output paths.

[0010] In one embodiment, the calculation result output circuit is further configured to adjust the voltage of the first terminal of the first transistor and the second transistor in the N output paths according to the second target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or discharging operation is performed according to the N output paths respectively. The second target voltage signal is used to adjust the charging current or discharging current when the N output paths perform the charging operation or the discharging operation to a target charging current or a target discharging current. The target charging current is half of the charging current, and the target discharging current is half of the discharging current, so that the calculation result calculated by the multiplication calculation circuit of the calculation unit is obtained by performing N charging operations or discharging operations through the N output paths. The calculation result is the calculation result calculated by the calculation unit according to the signal input voltage and the second neural network weight value, where the second neural network weight value is half of the initial neural network weight value.

[0011] In one embodiment, the computing circuit includes multiple first computing groups, each first computing group including four computing units: a first computing unit, a second computing unit, a third computing unit, and a fourth computing unit. The calculation result output circuits of the first and third computing units each include one output path, and the calculation result output circuits of the second and fourth computing units each include two output paths. The first and second ferroelectric transistors of the four computing units are used to receive different signal input voltages after the calculation output node is adjusted to the target voltage. The calculation result output circuits of the second and fourth computing units are used to turn off one of the two output paths according to the first target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or the discharging operation is performed according to one output path. The calculation result output circuits of the first and third computing units are used to perform the charging operation or the discharging operation according to one output path under the control of the voltage of the calculation output node after receiving the signal input voltage.

[0012] In one embodiment, the computing circuit includes multiple second computing groups, each second computing group including four computing units: a first computing unit, a second computing unit, a third computing unit, and a fourth computing unit. The calculation result output circuits of the first and third computing units each include one output path, while the calculation result output circuits of the second and fourth computing units each include two output paths. The first and second ferroelectric transistors of the first and second computing units are used to receive a first signal input voltage after the calculation output node is adjusted to the target voltage. The first ferroelectric transistor of the third and fourth computing units... The first and second ferroelectric transistors are used to receive a second signal input voltage after the calculation output node is adjusted to the target voltage; the calculation result output circuits of the second and fourth calculation units are used to perform the charging operation or the discharging operation according to the two output paths under the control of the voltage of the calculation output node after receiving the first and second signal input voltages; the calculation result output circuits of the first and third calculation units are used to perform the charging operation or the discharging operation according to the one output path under the control of the voltage of the calculation output node after receiving the first and second signal input voltages.

[0013] In one embodiment, the computing circuit includes multiple third computing groups, each third computing group including four computing units: a first computing unit, a second computing unit, a third computing unit, and a fourth computing unit. The calculation result output circuits of the first and third computing units each include one output path, while the calculation result output circuits of the second and fourth computing units each include two output paths. The first and second ferroelectric transistors of the four computing units are used to receive the same signal input voltage after the calculation output node is adjusted to the target voltage. The calculation result output circuit of the first computing unit is used to perform the charging or discharging operation according to one output path under the control of the voltage of the calculation output node after receiving the signal input voltage. The calculation result output circuit of the second computing unit is used to... Upon receiving the signal input voltage, the third calculation unit performs the charging or discharging operation according to the two output paths under the control of the voltage of the calculation output node; the calculation result output circuit of the third calculation unit is used to adjust the voltage of the first electrode of the first transistor and the second transistor in one of the output paths according to the second target voltage signal, so that upon receiving the signal input voltage, the fourth calculation unit performs the charging or discharging operation according to the two output paths under the control of the voltage of the calculation output node; the calculation result output circuit of the fourth calculation unit is used to adjust the voltage of the first electrode of the first transistor and the second transistor in the two output paths according to the second target voltage signal, so that upon receiving the signal input voltage, the fourth calculation unit performs the charging or discharging operation according to the two output paths under the control of the voltage of the calculation output node.

[0014] In one embodiment, the calculation result output circuit of the fourth calculation unit is further configured to shut off one of the two output paths according to the first target voltage signal, so that after receiving the signal input voltage, the charging operation or the discharging operation is performed according to one of the output paths under the control of the voltage of the calculation output node.

[0015] In one embodiment, the computing circuit further includes a first bit line RBL and a second bit line RBL. The first bit line RBL includes a first sub-bit line RBL1 and a first sub-bit line RBL2, and the second bit line RBL includes a second sub-bit line RBL1 and a second sub-bit line RBL2. The second terminals of the first transistors in the calculation result output circuits of the first computing unit and the second computing unit are both connected to the first sub-bit line RBL1, and the second terminals of the second transistors in the calculation result output circuits of the first computing unit and the second computing unit are both connected to the second sub-bit line RBL1. The second terminals of the first transistors in the calculation result output circuits of the third computing unit and the fourth computing unit are both connected to the first sub-bit line RBL2, and the second terminals of the second transistors in the calculation result output circuits of the third computing unit and the fourth computing unit are both connected to the second sub-bit line RBL2.

[0016] In one embodiment, the first sub-bit line RBL1 and the second sub-bit line RBL2 are connected through a first calculation result processing circuit, and the first sub-bit line RBL2 and the second sub-bit line RBL2 are connected through a second calculation result processing circuit. Both the first calculation result processing circuit and the second calculation result processing circuit include a first switch, a second switch, a third switch, a fourth switch connection, a first capacitor, and a second capacitor. The calculation result processing circuit is used to average the voltage of the first sub-bit line RBL and the second sub-bit line RBL to obtain the calculation results of the plurality of calculation units.

[0017] In one embodiment, the first terminal of the first ferroelectric transistor and the first terminal of the second ferroelectric transistor are connected, the second terminal of the first ferroelectric transistor is a first signal input node, the second terminal of the second ferroelectric transistor is a second signal input node, the gate of the first ferroelectric transistor is a first write voltage driving node, and the gate of the second ferroelectric transistor is a second write voltage driving node; the first signal input node and the second signal input node are used to input the signal input voltage; the first write voltage driving node and the second write voltage driving node are used to input the write voltage.

[0018] In one embodiment, the computation output node is located between the first pole of the first ferroelectric transistor and the first pole of the second ferroelectric transistor.

[0019] In one embodiment, the pre-charge circuit includes a third transistor whose source is connected to a second voltage source for outputting the target voltage, the drain of the third transistor being connected to the compute output node, and the gate of the third transistor for receiving a pulse signal to adjust the compute output node to the target voltage based on the pulse signal.

[0020] In one embodiment, the computing circuit further includes a word line WL; the gate of the third transistor in the pre-charge circuit of each computing unit is connected to the WL; the WL is used to output the pulse signal to the gate of the third transistor in the pre-charge circuit of each computing unit.

[0021] In one embodiment, the word line WL includes a first word line WL and a second word line WL; the gates of the third transistors in the pre-charge circuits of the first computing unit and the second computing unit are both connected to the first word line WL; and the gates of the third transistors in the pre-charge circuits of the third computing unit and the fourth computing unit are both connected to the second word line WL.

[0022] The aforementioned computing circuit includes multiple computing units of different types arranged in an array. Each computing unit includes a multiplication calculation circuit, a pre-charge circuit, and a calculation result output circuit. The calculation result output circuits differ for different types of computing units. The multiplication calculation circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charge circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first and second ferroelectric transistors. The first and second ferroelectric transistors are used to enter a target resistive state under the drive of a write voltage to characterize the initial neural network weight values. The pre-charge circuit is used to adjust the computing output node to the target voltage. The first and second ferroelectric transistors are used for... After the calculation output node is adjusted to the target voltage, it receives the signal input voltage. The calculation result output circuit includes N output paths and is used to turn off M of the N output paths according to the first target voltage signal. After receiving the signal input voltage, under the control of the voltage of the calculation output node, it performs charging or discharging operations according to the NM output paths respectively, so as to obtain the calculation result calculated by the multiplication calculation circuit of the calculation unit through NM charging or discharging operations. The calculation result is the calculation result calculated by the calculation unit according to the signal input voltage and the first neural network weight value. The first neural network weight value is obtained according to the initial neural network weight value and the number of charging or discharging operations NM, where N and M are positive integers. The computing circuit provided in this application includes a computing result output circuit with N output paths, which can be used to turn off M of the N output paths according to a first target voltage signal. Based on the computing result output circuit, weight reconfigurability can be realized. The computing circuit provided in this application can realize the calculation of a weight reconfigurable neural network. Compared with the prior art, the computing circuit of this application uses fewer components. Therefore, the computing circuit provided in this application can effectively reduce power consumption and improve integration. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the computing circuit in one embodiment;

[0024] Figure 2 This is a schematic diagram of the IV characteristics of the first ferroelectric transistor and the second ferroelectric transistor in one embodiment;

[0025] Figure 3 This is a timing diagram of the process of writing initial neural network weight values ​​to a computing unit in one embodiment;

[0026] Figure 4 This is a timing diagram for the case where the computation unit writes a weight value of 0 in one embodiment;

[0027] Figure 5 This is a timing diagram for a computing unit writing a weight value of 1 in one embodiment;

[0028] Figure 6 The timing diagram for the computation unit writing a weight value of -1 in one embodiment is shown below.

[0029] Figure 7 This is a schematic diagram of another computing circuit in one embodiment. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0031] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0032] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0034] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0035] Reconfigurable Neural Network Array Circuits (RNNA) are a type of neural network architecture that allows weights to be modified at runtime to adapt to different tasks and application scenarios.

[0036] In existing technologies, most weight-reconfigurable neural networks are implemented based on static random-access memory (SRAM).

[0037] However, this SRAM-based weighted reconfigurable neural network has high power consumption and low integration density.

[0038] In view of this, this application provides a computing circuit with low power consumption and high integration.

[0039] In one embodiment, such as Figure 1 As shown, the computing circuit includes multiple computing units 100 of different types arranged in an array. Each computing unit 100 includes a multiplication computing circuit 101, a pre-charging circuit 102, and a calculation result output circuit 103. The calculation result output circuit 103 is different for different types of computing units 100.

[0040] The multiplication calculation circuit 101 includes a first ferroelectric transistor 201 and a second ferroelectric transistor 202 connected to each other. The pre-charging circuit 102 and the calculation result output circuit 103 are both connected to the calculation output node 203 located between the first ferroelectric transistor 201 and the second ferroelectric transistor 202. Figure 1 Point A in the diagram is electrically connected.

[0041] The first ferroelectric transistor 201 and the second ferroelectric transistor 202 are used to enter the target resistive state under the drive of the write voltage to characterize the initial neural network weight values.

[0042] In an optional embodiment of this application, such as Figure 1 As shown, the first terminal of the first ferroelectric transistor 201 and the first terminal of the second ferroelectric transistor 202 are connected, and the second terminal of the first ferroelectric transistor 201 is the first signal input node. Figure 1 Vin1), the second electrode of the second ferroelectric transistor 202 is the second signal input node (in the second polarity). Figure 1 Vin2 in the first ferroelectric transistor 201 has its gate as the first write voltage drive node. Figure 1 In the second ferroelectric transistor 202, the gate of the second ferroelectric transistor 202 is the second write voltage drive node (Vwrite1). Figure 1 Vwrite2 in (the text is incomplete and cannot be translated).

[0043] Optionally, the first signal input node and the second signal input node are used to input the signal input voltage, and the first write voltage driving node and the second write voltage driving node are used to input the write voltage.

[0044] In one possible implementation, such as Figure 2 As shown, Figure 2 The diagram shows the IV characteristics of the first ferroelectric transistor 201 and the second ferroelectric transistor 202. Figure 2 In the figure, -Vc and Vc are the threshold voltages of the first ferroelectric transistor 201 and the second ferroelectric transistor 202 in the positive and negative polarization states, respectively. They are also the coercivity voltages of the ferroelectric transistors. For the first ferroelectric transistor 201 and the second ferroelectric transistor 202, when the applied positive gate-source voltage is greater than Vc, the first ferroelectric transistor 201 and the second ferroelectric transistor 202 will enter the positive polarization state, which is the low resistance state. When the applied negative gate-source voltage is greater than Vc, the first ferroelectric transistor 201 and the second ferroelectric transistor 202 will enter the negative polarization state, which is the high resistance state.

[0045] Optionally, assuming the write voltage is Vwrite, the value range of Vwrite is related to the value of Vc. Specifically, Vwrite > Vc > Vwrite / 2.

[0046] In one possible implementation, assuming the initial neural network weight value to be written to the computing unit 100 is 1, two stages are required. In the first stage, Vwrite is input to the first write voltage driving node, and the second write voltage driving node is grounded. Both the first and second signal input nodes are input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the first ferroelectric transistor, causing the first ferroelectric transistor to enter or remain in a low-resistance state. In the second stage, Vwrite is still input to the first write voltage driving node, and the second write voltage driving node is still grounded. The first signal input node and the second signal input node are both input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the first ferroelectric transistor, causing the first ferroelectric transistor to enter or remain in a low-resistance state. Both the input node and the second signal input node input Vwrite. At this time, it is equivalent to inputting a negative gate-source voltage greater than Vc into the second ferroelectric transistor. The second ferroelectric transistor will enter or remain in a high-resistivity state. The high-resistivity state and the low-resistivity state are the target states mentioned above. The target state is used to characterize the initial neural network weight value corresponding to the computing unit 100. That is, the first ferroelectric transistor is in a low-resistivity state and the second ferroelectric transistor is in a high-resistivity state. This can be used to characterize the initial neural network weight value corresponding to the computing unit 100 as 1. The above process is the process of writing the initial neural network weight value 1 into the computing unit 100.

[0047] In another possible implementation, assuming the initial neural network weight value to be written to the computing unit 100 is -1, two stages are required. In the first stage, Vwrite is input to the second write voltage drive node, and the first write voltage drive node is grounded. Both the first and second signal input nodes are input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the second ferroelectric transistor, causing the second ferroelectric transistor to enter or remain in a low-resistance state. In the second stage, Vwrite is still input to the second write voltage drive node, and the first write voltage drive node is still grounded. The first signal input node and the second signal input node are both input with 0. Both the input node and the second signal input node input Vwrite. At this time, it is equivalent to inputting a negative gate-source voltage greater than Vc to the first ferroelectric transistor. The first ferroelectric transistor will enter or remain in a high-resistivity state. The high-resistivity state and the low-resistivity state are the target states mentioned above. The target state is used to characterize the initial neural network weight value corresponding to the computing unit 100. That is, the second ferroelectric transistor is in a low-resistivity state, and the first ferroelectric transistor is in a high-resistivity state. This can be used to characterize the initial neural network weight value corresponding to the computing unit 100 as -1. The above process is the process of writing the initial neural network weight value -1 to the computing unit 100.

[0048] In another possible implementation, assuming the initial neural network weights to be written to the computing unit 100 are 0, two stages are required. In the first stage, both the first write voltage driving node and the second write voltage driving node are grounded, and both the first signal input node and the second signal input node are input with a value of 0. In this first stage, the resistive states of the first ferroelectric transistor and the second ferroelectric transistor remain unchanged. In the second stage, both the first write voltage driving node and the second write voltage driving node are grounded, and both the first signal input node and the second signal input node are input with a value of Vwri. At this point, it is equivalent to inputting a negative gate-source voltage greater than Vc to both the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor will enter a high-resistivity state, which is the target state mentioned above. This target state characterizes the initial neural network weight value corresponding to the computing unit 100. That is, the fact that both the first ferroelectric transistor and the second ferroelectric transistor are in a high-resistivity state can be used to characterize that the initial neural network weight value corresponding to the computing unit 100 is 0. The above process is the process of writing the initial neural network weight value of 0 to the computing unit 100.

[0049] As described above, this is the process of writing initial neural network weight values ​​into the computing unit 100, such as... Figure 3 The diagram shown is the timing diagram for this process. The specific operation of this process can be found in Table 1. In Table 1, Vin1 (non-write row) and Vin2 (non-write row) refer to Vin1 and Vin2 of other calculation units in the calculation circuit that do not perform the write weight value calculation.

[0050] Table 1

[0051]

[0052] In one possible implementation, the inputs of Vin1 (non-write row) and Vin2 (non-write row) can be kept at Vwrite / 2. This ensures that during the weight writing process, the gate-source voltages of the first and second ferroelectric transistors in the computing units 100 corresponding to Vin1 (non-write row) and Vin2 (non-write row) will not exceed Vwrite / 2, thus ensuring that the first and second ferroelectric transistors in the computing units 100 corresponding to Vin1 (non-write row) and Vin2 (non-write row) will not undergo polarization reversal.

[0053] The pre-charge circuit 102 is used to adjust the calculation output node 203 to the target voltage.

[0054] In an optional embodiment of this application, such as Figure 1As shown, the calculation output node 203 is located between the first terminal of the first ferroelectric transistor 201 and the first terminal of the second ferroelectric transistor 202. Figure 1 Point A in the calculation is the output node 203.

[0055] In an optional embodiment of this application, such as Figure 1 As shown, the pre-charge circuit 102 includes a third transistor 1021, the source of which is connected to a second voltage source ( Figure 1 The second voltage source is connected to the Vprecharge in the third transistor 1021, which is used to output the target voltage. The drain of the third transistor 1021 is connected to the calculation output node 203, and the gate of the third transistor 1021 is used to receive a pulse signal to adjust the calculation output node 203 to the target voltage based on the pulse signal.

[0056] Optionally, the third transistor 1021 can be an NMOS transistor, and the voltage of the second voltage source is constant at V. DD / 2.

[0057] In an optional embodiment of this application, such as Figure 1 As shown, the computing circuit also includes word line WL104.

[0058] In each of the computing units 100, the gate of the third transistor 1021 in the pre-charge circuit 102 is connected to the WL104; the WL104 is used to output the pulse signal to the gate of the third transistor 1021 in the pre-charge circuit 102 of each computing unit 100.

[0059] Optional, such as Figure 4 , Figure 5 as well as Figure 6 As shown, Figure 4 The timing diagram shows the pre-charging circuit performing the pre-charging process and the inputting different input values ​​after the pre-charging process, given that the initial neural network weights are 0 in the computing unit 100. Figure 6 Given that the initial neural network weight value is 1, the timing diagram shows the pre-charging circuit performing the pre-charging process and the inputting different input values ​​after the pre-charging process. Figure 7When the initial neural network weight value is written to the computing unit 100 as -1, the timing diagram of the pre-charging circuit executing the pre-charging process and inputting different input values ​​after executing the pre-charging process is as follows: After the first ferroelectric transistor 201 and the second ferroelectric transistor 202 enter the target resistive state, that is, after the operation of writing the weight value to the computing unit 100 has been completed, the computing unit 100 needs to perform a multiplication operation based on the written initial neural network weight value. Before performing the multiplication operation, the computing output node 203 needs to be adjusted to the target voltage based on the pre-charging circuit 102.

[0060] In one possible implementation, when the initial neural network weights written to the computing unit 100 are 0, a positive pulse with a large amplitude can be applied to WL104 so that the computing output node 203 is charged to V by the first voltage source. DD / 2, when the applied pulse ends, the voltage on WL104 will return to 0 and remain at 0, at which point the connection between the first voltage source and the calculation output node 203 will be cut off.

[0061] In another possible implementation, when the initial neural network weight value written to the computing unit 100 is 1, a positive pulse with a large amplitude is applied to WL104. At this time, under the combined action of the first signal input node and the first voltage source, the voltage of the computing output node is set to V. DD / 2.

[0062] In another possible implementation, when the initial neural network weight value written to the computing unit 100 is -1, a positive pulse with a large amplitude is applied to WL104. At this time, under the combined action of the second signal input node and the first voltage source, the voltage of the computing output node is set to V. DD / 2.

[0063] The first ferroelectric transistor 201 and the second ferroelectric transistor 202 are used to receive the signal input voltage after the calculation output node 203 is adjusted to the target voltage.

[0064] Optionally, the signal input voltage is used to characterize the input value.

[0065] In one possible implementation, if the voltage input to the first signal input node is V DD If the voltage input to the second signal input node is 0, then the input value can be determined to be 1.

[0066] In another possible implementation, if the voltage input to the first signal input node is V DD / 2, the voltage input to the second signal input node is V DDIf we use / 2, then we can determine that the input value is 0.

[0067] In another possible implementation, if the voltage input to the first signal input node is 0, the voltage input to the second signal input node is V. DD Then the input value can be determined to be -1.

[0068] The calculation result output circuit 103 includes N output paths and is used to turn off M of the N output paths according to the first target voltage signal. After receiving the signal input voltage, under the control of the voltage of the calculation output node 203, a charging operation or a discharging operation is performed according to the NM output paths respectively, so as to obtain the calculation result calculated by the multiplication calculation circuit of the calculation unit 100 through NM charging operations or discharging operations.

[0069] Optionally, the calculation result is the result calculated by the calculation unit 100 based on the signal input voltage and the first neural network weight value. The first neural network weight value is obtained based on the initial neural network weight value and the number of charging operations or discharging operations NM, where N and M are positive integers.

[0070] In an optional embodiment of this application, the calculation result output circuit 103 includes N sub-output circuits 1031, wherein each sub-output circuit 1031 is used to perform the charging operation or the discharging operation through different output paths.

[0071] In an optional embodiment of this application, such as Figure 1 As shown, the sub-output circuit 103 includes a first transistor 301 and a second transistor 302, and the gates of the first transistor 301 and the second transistor 302 are both connected to the computing output node 203.

[0072] In an optional embodiment of this application, the calculation result output circuit 103 is used to adjust the voltage of the first electrode of the first transistor 301 and the second transistor 302 in the M output paths according to the first target voltage signal, so as to turn off the M output paths.

[0073] In one possible implementation, if M is 0, meaning there are no disconnected output paths in the N sub-output circuits 1031, then in this case, the voltage at the first terminal of the first transistor 301 in each sub-output circuit 1031 is V. DD The voltage at the first terminal of the second transistor 302 in each sub-output circuit is 0.

[0074] In another possible implementation, if M is 1, meaning there is one shut-off output path among the N sub-output circuits, then the calculation result output circuit 103 will adjust the voltage of the first transistor 301 and the first electrode of the second transistor 302 in one output path according to the first target voltage signal. Specifically, the voltage of the first transistor 301 in the output path will be adjusted to 0, and the voltage of the second transistor 302 in the output path will be adjusted to V. DD .

[0075] As described above, the calculation result output circuit 103 is used to turn off M of the N output paths according to the first target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node 203, a charging operation or a discharging operation is performed on each of the NM output paths, so as to obtain the calculation result calculated by the multiplication calculation circuit of the calculation unit 100 through NM charging operations or discharging operations.

[0076] Optional, with Figure 1 Taking the computing circuit shown as an example, the computing circuit includes two computing units 100, namely a first part and a second part. The first part includes a sub-output circuit 1031, and the initial neural network weight value of the first part is (-1, 0, 1). The second part includes two sub-output circuits 1031, and the initial neural network weight value of the second part is also (-1, 0, 1). For the second part, N is 2. If M is 0, then both sub-output circuits of the second part are in the on state, and the first neural network weight value of the second part is (-2, 0, 2). If M is 1, then one of the sub-output circuits of the second part will be in the off state, and the first neural network weight value of the second part is (-1, 0, 1).

[0077] In one possible implementation, the first part and the second part are regarded as two independent computational units, with M being 0 for the first part and M being 1 for the second part. In this case, the first part and the second part are two independent 3-weighted computational units with weight values ​​of (-1, 0, 1).

[0078] In another possible implementation, the first part and the second part can be regarded as a whole, with M of the first part being 0 and M of the second part being 1. Then the first part and the second part are a calculation circuit with a weight value of 5, with the weight value being (-2, -1, 0, 1, 2).

[0079] In another possible implementation, the first part and the second part can be regarded as two independent computational units, with M being 0 for the first part and M being 0 for the second part. Then the first part and the second part are two independent 3-weighted value computational units with weights of (-1, 0, 1) and (-2, 0, 2), respectively.

[0080] In another possible implementation, the first part and the second part can be regarded as a whole, with M of the first part being 0 and M of the second part being 1. Then the first part and the second part are a calculation circuit with 7 weight values, with weight values ​​of (-3, -2, -1, 0, 1, 2, 3).

[0081] The above-mentioned output circuit based on the calculation result is used to turn off M of the N output paths according to the first target voltage signal to change the initial neural network weight value of the calculation unit. It can be understood that due to the turning off and turning on of the output paths, the number of times the output paths in the calculation unit perform charging or discharging operations changes, thereby changing the calculation result corresponding to the calculation unit.

[0082] In an optional embodiment of this application, the calculation result output circuit 103 is further configured to adjust the voltage of the first terminal of the first transistor 301 and the second transistor 302 in the N output paths according to the second target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node 203, the charging operation or discharging operation is performed according to the N output paths respectively. The second target voltage signal is used to adjust the charging current or discharging current when the N output paths perform the charging operation or the discharging operation to the target charging current or the target discharging current. The target charging current is half of the charging current, and the target discharging current is half of the discharging current, so that the calculation result calculated by the multiplication calculation circuit of the calculation unit 100 is obtained by performing N charging operations or discharging operations through the N output paths. The calculation result is the calculation result calculated by the calculation unit 100 according to the signal input voltage and the second neural network weight value, where the second neural network weight value is half of the initial neural network weight value.

[0083] In one possible implementation, assuming the initial neural network weight value of a certain computing unit is (-1, 0, 1), and the output circuit of the computing unit adjusts the voltage of the first pole of the first transistor and the second transistor in the N output paths according to the second target voltage signal, then the second neural network weight value of the computing unit is (-1 / 2, 0, 1 / 2).

[0084] The above-mentioned adjustment of the charging current or discharging current when the N output paths perform the charging operation or the discharging operation to the target charging current or the target discharging current, in order to change the initial neural network weight value, can be understood as the change in the current of the charging operation or the discharging operation altering the calculation result corresponding to the calculation unit.

[0085] In an optional embodiment of this application, such as Figure 1 As shown, the computing circuit also includes a first bit line RBL501 and a second bit line RBL502. The second terminal of the first transistor 301 is connected to the first bit line RBL501, and the second terminal of the second transistor 302 is connected to the second bit line RBL502.

[0086] Optionally, the first transistor 301 and the second transistor 302 are used to perform charging or discharging operations on the first bit line RBL501 and the second bit line RBL502 respectively, under the control of the voltage of the calculation output node 203.

[0087] Optionally, the first transistor 301 may be a PMOS transistor, and the second transistor 302 may be an NMOS transistor.

[0088] In one optional embodiment of this application, before the multiplication calculation circuit 101 performs calculations based on the signal input voltage, it is necessary to discharge and leave the first bit line RBL501 and the second bit line RBL502 floating based on the transistor.

[0089] In an optional embodiment of this application, such as Figure 1 As shown, the first bit line RBL501 and the second bit line RBL502 are connected through the calculation result processing circuit 106. The calculation result processing circuit 106 includes a first switch 601, a second switch 602, a third switch 603, a fourth switch connection 604, a first capacitor 605, and a second capacitor 606.

[0090] The calculation result processing circuit 106 is used to average the voltages of the first bit line RBL501 and the second bit line RBL502 to obtain the calculation results of the plurality of calculation units 100.

[0091] In one possible implementation, during the multiplication calculation circuit 101's calculation based on the signal input voltage, the first switch 601 and the second switch 602 remain closed, while the third switch 603 and the fourth switch 604 remain open.

[0092] In one embodiment, such as Figure 7As shown, the calculation circuit includes multiple first calculation groups 100, and each first calculation group 100 includes four calculation units, namely a first calculation unit 101, a second calculation unit 102, a third calculation unit 103 and a fourth calculation unit 104. The calculation result output circuits of the first calculation unit 101 and the third calculation unit 103 each include one output path, and the calculation result output circuits of the second calculation unit 102 and the fourth calculation unit 104 each include two output paths.

[0093] The first and second ferroelectric transistors of the four computing units are used to receive different signal input voltages after the computing output node is adjusted to the target voltage; the calculation result output circuits of the second computing unit 102 and the fourth computing unit 104 are used to turn off one of the two output paths according to the first target voltage signal, so that after receiving the signal input voltage, the charging operation or the discharging operation is performed according to one of the output paths under the control of the voltage of the computing output node; the calculation result output circuits of the first computing unit 101 and the third computing unit 103 are used to perform the charging operation or the discharging operation according to one of the output paths under the control of the voltage of the computing output node after receiving the signal input voltage.

[0094] In one possible implementation, as described above, the initial neural network weight values ​​of the four computational units are all (-1, 0, 1), and the first neural network weight values ​​of the four computational units are all (-1, 0, 1), that is, the first computational group includes four computational units with a weight value of 3.

[0095] In one embodiment, such as Figure 7 As shown, the calculation circuit includes multiple second calculation groups 100, and each second calculation group 100 includes four calculation units, namely a first calculation unit 101, a second calculation unit 102, a third calculation unit 103 and a fourth calculation unit 104. The calculation result output circuits of the first calculation unit 101 and the third calculation unit 103 each include one output path, and the calculation result output circuits of the second calculation unit 102 and the fourth calculation unit 104 each include two output paths.

[0096] The first ferroelectric transistor and the second ferroelectric transistor of the first computing unit 101 and the second computing unit 102 are used to receive a first signal input voltage after the computing output node is adjusted to the target voltage. The first ferroelectric transistor and the second ferroelectric transistor of the third computing unit 103 and the fourth computing unit 104 are used to receive a second signal input voltage after the computing output node is adjusted to the target voltage. The calculation result output circuit of the second computing unit 102 and the fourth computing unit 104 is used to perform the charging operation or the discharging operation according to the two output paths under the control of the voltage of the computing output node after receiving the first signal input voltage and the second signal input voltage. The calculation result output circuit of the first computing unit 101 and the third computing unit 103 is used to perform the charging operation or the discharging operation according to the one output path under the control of the voltage of the computing output node after receiving the first signal input voltage and the second signal input voltage.

[0097] In one possible implementation, as described above, the initial neural network weight values ​​of the four computing units are all (-1, 0, 1). The first neural network weight values ​​of the first computing unit 101 and the third computing unit 103 are all (-1, 0, 1), and the first neural network weight values ​​of the second computing unit 102 and the fourth computing unit 104 are all (-2, 0, 2). The first computing unit 101 and the second computing unit 102 are considered as a whole, and the third computing unit 103 and the fourth computing unit 104 are considered as a whole. That is, the second computing group includes two computing units with a weight of 7.

[0098] In one embodiment, such as Figure 7 As shown, the calculation circuit includes multiple third calculation groups 100, and each third calculation group 100 includes four calculation units, namely a first calculation unit 101, a second calculation unit 102, a third calculation unit 103 and a fourth calculation unit 104. The calculation result output circuits of the first calculation unit 101 and the third calculation unit 103 each include one output path, and the calculation result output circuits of the second calculation unit 102 and the fourth calculation unit 104 each include two output paths.

[0099] The first and second ferroelectric transistors of the four computing units are used to receive the same signal input voltage after the computing output node is adjusted to the target voltage; the calculation result output circuit of the first computing unit 101 is used to perform the charging operation or the discharging operation according to one output path under the control of the voltage of the computing output node after receiving the signal input voltage; the calculation result output circuit of the second computing unit 102 is used to perform the charging operation or the discharging operation according to two output paths under the control of the voltage of the computing output node after receiving the signal input voltage; the calculation result output of the third computing unit 103... The circuit is used to adjust the voltage of the first transistor and the first electrode of the second transistor in one of the output paths according to the second target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or the discharging operation is performed according to one of the output paths; the calculation result output circuit of the fourth calculation unit 104 is used to adjust the voltage of the first transistor and the first electrode of the second transistor in two of the output paths according to the second target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or the discharging operation is performed according to two of the output paths.

[0100] In an optional embodiment of this application, the calculation result output circuit of the fourth calculation unit 104 is further configured to turn off one of the two output paths according to the first target voltage signal, so that after receiving the signal input voltage, the charging operation or the discharging operation is performed according to one of the output paths under the control of the voltage of the calculation output node.

[0101] In one possible implementation, as described above, the initial neural network weight values ​​of the four computing units are all (-1, 0, 1). The first neural network weight value of the first computing unit 101 is (-1, 0, 1), the first neural network weight value of the second computing unit 102 is (-2, 0, 2), the second neural network weight value of the third computing unit 103 is (-1 / 2, 0, 1 / 2), and the second neural network weight value of the fourth computing unit 104 is (-1, 0, 1). These four computing units are considered as a whole, that is, the third computing group includes one computing unit with 19 weights.

[0102] The above method uses lower weight precision, which improves the inference efficiency of DNN and reduces power consumption by reducing the accuracy of inference. It is suitable for scenarios with high power consumption requirements, such as edge inference computing. The neural network array with adjustable weight precision can adjust the weight values ​​in different usage scenarios, which is conducive to achieving a better trade-off between efficiency and accuracy.

[0103] In one embodiment, such as Figure 7 As shown, the calculation circuit also includes a first bit line RBL and a second bit line RBL. The first bit line RBL includes a first sub-bit line RBL11051 and a first sub-bit line RBL21052, and the second bit line RBL includes a second sub-bit line RBL11061 and a second sub-bit line RBL21062. The second terminals of the first transistors in the calculation result output circuits of the first calculation unit 101 and the second calculation unit 102 are all connected to the first sub-bit line RBL11051, and the second terminals of the second transistors in the calculation result output circuits of the first calculation unit 101 and the second calculation unit 102 are all connected to the second sub-bit line RBL11061. The second terminals of the first transistors in the calculation result output circuits of the third calculation unit 103 and the fourth calculation unit 104 are all connected to the first sub-bit line RBL21052, and the second terminals of the second transistors in the calculation result output circuits of the third calculation unit 103 and the fourth calculation unit 104 are all connected to the second sub-bit line RBL21062.

[0104] In one embodiment, such as Figure 7 As shown, the first sub-line RBL11051 and the second sub-line RBL11061 are connected through the first calculation result processing circuit 107, and the first sub-line RBL21052 and the second sub-line RBL21062 are connected through the second calculation result processing circuit 108. Both the first calculation result processing circuit 107 and the second calculation result processing circuit 108 include a first switch 701, a second switch 702, a third switch 703, a fourth switch connection 704, a first capacitor 705, and a second capacitor 706. The calculation result processing circuit is used to average the voltage of the first sub-line RBL and the second sub-line RBL to obtain the calculation results of the multiple calculation units.

[0105] In one embodiment, such as Figure 7 As shown, the computing circuit also includes word lines WL, which include a first word line WL1091 and a second word line WL1092; the gates of the third transistors in the pre-charge circuits of the first computing unit 101 and the second computing unit 102 are all connected to the first word line WL1091; the gates of the third transistors in the pre-charge circuits of the third computing unit 103 and the fourth computing unit 104 are all connected to the second word line WL1092.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A computing circuit, characterized in that, The computing circuit includes multiple computing units of different types arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charging circuit, and a calculation result output circuit. The calculation result output circuits of different types of computing units are different. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charging circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter the target resistive state under the drive of the write voltage to characterize the initial neural network weight values; The pre-charging circuit is used to adjust the calculation output node to the target voltage; The first ferroelectric transistor and the second ferroelectric transistor are used to receive the signal input voltage after the calculation output node is adjusted to the target voltage; The calculation result output circuit includes N output paths and is used to turn off M of the N output paths according to the first target voltage signal. After receiving the signal input voltage, under the control of the calculation output node voltage, it performs charging or discharging operations according to the NM output paths respectively, so as to obtain the calculation result calculated by the multiplication calculation circuit of the calculation unit through NM charging or discharging operations. The calculation result is the calculation result calculated by the calculation unit according to the signal input voltage and the first neural network weight value. The first neural network weight value is obtained according to the initial neural network weight value and the number of charging or discharging operations NM, where N and M are positive integers.

2. The computing circuit according to claim 1, characterized in that, The calculation result output circuit includes N sub-output circuits, wherein each sub-output circuit is used to perform the charging operation or the discharging operation through different output paths.

3. The computing circuit according to claim 2, characterized in that, The sub-output circuit includes a first transistor and a second transistor, the gates of the first transistor and the second transistor being connected to the computing output node.

4. The computing circuit according to claim 3, characterized in that, The calculation result output circuit is used to adjust the voltage of the first transistor and the first electrode of the second transistor in the M output paths according to the first target voltage signal, so as to shut down the M output paths.

5. The computing circuit according to claim 3, characterized in that, The calculation result output circuit is further configured to adjust the voltage of the first transistor and the first electrode of the second transistor in the N output paths according to the second target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or discharging operation is performed according to the N output paths respectively. The second target voltage signal is used to adjust the charging current or discharging current when the N output paths perform the charging operation or the discharging operation to the target charging current or the target discharging current. The target charging current is half of the charging current, and the target discharging current is half of the discharging current, so that the calculation result calculated by the multiplication calculation circuit of the calculation unit is obtained by performing N charging operations or discharging operations through the N output paths. The calculation result is the result calculated by the calculation unit based on the signal input voltage and the weight value of the second neural network, where the weight value of the second neural network is half of the weight value of the initial neural network.

6. The computing circuit according to claim 1, characterized in that, The computing circuit includes multiple first computing groups, and each first computing group includes four computing units, namely a first computing unit, a second computing unit, a third computing unit and a fourth computing unit. The computing result output circuits of the first computing unit and the third computing unit each include one output path, and the computing result output circuits of the second computing unit and the fourth computing unit each include two output paths. The first ferroelectric transistor and the second ferroelectric transistor of the four computing units are used to receive different signal input voltages after the computing output node is adjusted to the target voltage; The calculation result output circuit of the second calculation unit and the fourth calculation unit is used to turn off one of the two output paths according to the first target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or the discharging operation is performed according to one of the output paths. The calculation result output circuit of the first calculation unit and the third calculation unit is used to perform the charging operation or the discharging operation according to the one output path under the control of the voltage of the calculation output node after receiving the signal input voltage.

7. The computing circuit according to claim 1, characterized in that, The computing circuit includes multiple second computing groups, and each second computing group includes four computing units, namely a first computing unit, a second computing unit, a third computing unit and a fourth computing unit. The computing result output circuits of the first computing unit and the third computing unit each include one output path, and the computing result output circuits of the second computing unit and the fourth computing unit each include two output paths. The first ferroelectric transistor and the second ferroelectric transistor of the first computing unit and the second computing unit are used to receive a first signal input voltage after the computing output node is adjusted to the target voltage. The first ferroelectric transistor and the second ferroelectric transistor of the third computing unit and the fourth computing unit are used to receive a second signal input voltage after the computing output node is adjusted to the target voltage. The calculation result output circuit of the second calculation unit and the fourth calculation unit is used to perform the charging operation or the discharging operation according to the two output paths under the control of the voltage of the calculation output node after receiving the first signal input voltage and the second signal input voltage; The calculation result output circuit of the first calculation unit and the third calculation unit is used to perform the charging operation or the discharging operation according to the one output path under the control of the voltage of the calculation output node after receiving the first signal input voltage and the second signal input voltage.

8. The computing circuit according to claim 1, characterized in that, The computing circuit includes multiple third computing groups, and each third computing group includes four computing units, namely a first computing unit, a second computing unit, a third computing unit and a fourth computing unit. The calculation result output circuits of the first computing unit and the third computing unit each include one output path, and the calculation result output circuits of the second computing unit and the fourth computing unit each include two output paths. The first ferroelectric transistor and the second ferroelectric transistor of the four computing units are used to receive the same signal input voltage after the computing output node is adjusted to the target voltage; The calculation result output circuit of the first calculation unit is used to perform the charging operation or the discharging operation according to the one output path under the control of the voltage of the calculation output node after receiving the signal input voltage; The calculation result output circuit of the second calculation unit is used to perform the charging operation or the discharging operation according to the two output paths under the control of the voltage of the calculation output node after receiving the signal input voltage; The calculation result output circuit of the third calculation unit is used to adjust the voltage of the first terminal of the first transistor and the second transistor in one of the output paths according to the first target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or the discharging operation is performed according to one of the output paths. The calculation result output circuit of the fourth calculation unit is used to adjust the voltage of the first transistor and the first electrode of the second transistor in the two output paths according to the second target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or the discharging operation is performed according to the two output paths.

9. The computing circuit according to claim 8, characterized in that, The calculation result output circuit of the fourth calculation unit is also used to turn off one of the two output paths according to the first target voltage signal, so that after receiving the signal input voltage, under the control of the voltage of the calculation output node, the charging operation or the discharging operation is performed according to one of the output paths.

10. The computing circuit according to claim 6, characterized in that, The computing circuit also includes a first bit line RBL and a second bit line RBL. The first bit line RBL includes a first sub-bit line RBL1 and a first sub-bit line RBL2, and the second bit line RBL includes a second sub-bit line RBL1 and a second sub-bit line RBL2. The second terminal of the first transistor in the calculation result output circuit of the first calculation unit and the second calculation unit is connected to the first sub-bit line RBL1, and the second terminal of the second transistor in the calculation result output circuit of the first calculation unit and the second calculation unit is connected to the second sub-bit line RBL1. The second terminal of the first transistor in the calculation result output circuit of the third calculation unit and the fourth calculation unit is connected to the first sub-bit line RBL2, and the second terminal of the second transistor in the calculation result output circuit of the third calculation unit and the fourth calculation unit is connected to the second sub-bit line RBL2.

11. The computing circuit according to claim 10, characterized in that, The first sub-bit line RBL1 and the second sub-bit line RBL1 are connected through a first calculation result processing circuit, and the first sub-bit line RBL2 and the second sub-bit line RBL2 are connected through a second calculation result processing circuit. Both the first calculation result processing circuit and the second calculation result processing circuit include a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor. The calculation result processing circuit is used to average the voltages of the first sub-bit line RBL and the second sub-bit line RBL to obtain the calculation results of multiple calculation units.

12. The computing circuit according to claim 6, characterized in that, The first terminal of the first ferroelectric transistor and the first terminal of the second ferroelectric transistor are connected. The second terminal of the first ferroelectric transistor is a first signal input node, and the second terminal of the second ferroelectric transistor is a second signal input node. The gate of the first ferroelectric transistor is a first write voltage driving node, and the gate of the second ferroelectric transistor is a second write voltage driving node. The first signal input node and the second signal input node are used to input the signal input voltage; The first write voltage driving node and the second write voltage driving node are used to input the write voltage.

13. The computing circuit according to claim 12, characterized in that, The computational output node is located between the first electrode of the first ferroelectric transistor and the first electrode of the second ferroelectric transistor.

14. The computing circuit according to claim 13, characterized in that, The pre-charge circuit includes a third transistor, the source of which is connected to a second voltage source for outputting the target voltage, the drain of which is connected to the computation output node, and the gate of which is used to receive a pulse signal to adjust the computation output node to the target voltage based on the pulse signal.

15. The computing circuit according to claim 14, characterized in that, The computing circuit also includes a word line WL; The gate of the third transistor in the pre-charge circuit of each computing unit is connected to the WL; the WL is used to output the pulse signal to the gate of the third transistor in the pre-charge circuit of each computing unit.

16. The computing circuit according to claim 15, characterized in that, The word line WL includes a first word line WL and a second word line WL; The gates of the third transistors in the pre-charge circuits of both the first and second computing units are connected to the first word line WL. The gates of the third transistors in the pre-charge circuits of both the third and fourth computing units are connected to the second word line WL.

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