A new display method

Abstract

The present application relates to display technical field, provide a kind of new display method, comprising the following steps: S1, the number of discharge transistor is same with the number of data line;The number of switch transistor is same with the number of scanning line;S2, in first lower brush black time, first lower brush black signal line, second lower brush black signal line and third lower brush black signal line are all transmission VGH signal;S3, in second lower brush black time, first lower brush black signal line, second lower brush black signal line are all transmission VGL signal, and third lower brush black signal line is transmission VGH signal;S4, in third lower brush black time, first lower brush black signal line, second lower brush black signal line and third lower brush black signal line are all transmission VGL signal.The present application has the advantages that: in lower brush black stage, all pixel transistors are discharged simultaneously, improve discharge efficiency, effectively release residual charge existing in pixel TFT.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, in particular to a novel display method. BACKGROUND

[0002] The display of a liquid crystal display panel is accomplished by controlling the pixel TFTs in the in-plane display area, specifically, the gate signals are transmitted by the horizontally arranged scan lines to control the opening and closing of the TFTs, and the source signals are transmitted by the vertically arranged data lines to write the desired display voltage. The pixel TFTs are arranged in a matrix, each of the scan lines is connected to the gate of each row of the pixel transistors one by one, and each of the data lines is connected to the source of each column of the pixel transistors one by one.

[0003] The horizontal gate signals are generated by the gate driving circuit on both sides of the panel, which is referred to as GIP (Gate In Panel) driving circuit. The vertical source signals are provided by the IC according to the desired display. The design and driving of the GIP driving circuit have a great impact on the reliability and display quality of the panel. For example, when the GIP driving circuit is normally driven, the in-plane charges move directionally under the action of the driving voltage and do not escape from the control. However, when the GIP driving circuit stops working, there are a large number of parasitic capacitances in the pixel TFTs themselves in the panel. If there is no good driving at this time, a large number of uncontrolled charges in the panel will be stored in the parasitic capacitances of the pixel TFTs, which will affect the stability of the pixel TFTs and the display effect of the liquid crystal panel. For example, when the display is turned on for display next time, some horizontal stripe-shaped (mura) defects or flash screen defects will occur.

[0004] Referring to Figure 1 , the architecture of the traditional GIP driving circuit, the pre-charge unit, the pull-down unit and the CK signal line are the input part of the GIP driving circuit, and Gout is the output signal of the GIP driving circuit output stage, which is connected to the scan line and used to control the opening and closing of the pixel TFTs.

[0005] Usually in a-Si thin film field effect transistor LCD, when the display is completed, the power-down stage is prepared, the GIP driving circuit opens the pixel TFTs step by step, and the IC outputs 0V signal to the in-plane display area through the data lines S1-Sn for discharging the pixel TFTs, as shown in Figure 2 , the signal timing diagram of the output of each stage of the traditional GIP driving circuit when the display is powered down. In the figure, Gn is the output signal of the nth stage of the GIP driving circuit. As shown in Figure 3 , the connection diagram of the traditional GIP driving circuit and the pixel TFTs in the in-plane display area.

[0006] The thin film field effect transistor made of metal oxide has excellent electron migration rate, which is 20-30 times of a-Si thin film field effect transistor. The thin film field effect transistor made of metal oxide has good storage charge effect, that is, when the thin film field effect transistor is in the off state, the electron is difficult to discharge from the device, which can make the pixel TFT have better charging effect. However, the charge in the pixel TFT of the in-plane display area is difficult to discharge when the TFT is off, and the charge stored in the parasitic capacitor of the pixel TFT can affect the performance of the panel.

[0007] Due to the extremely low leakage characteristics of metal oxide, the pixel TFT is opened by the GIP driving circuit to discharge step by step when the lower brush black signal timing shown in the figure. Figure 2 The discharge efficiency is low, and in the case of short brush black time, the residual charge in the pixel TFT of the in-plane display area will affect the display performance of the metal oxide display panel, such as screen flicker.

[0008] Therefore, how to improve the discharge efficiency and effectively release the residual charge existing in the pixel TFT is a technical problem to be solved in the field at present. SUMMARY

[0009] The technical problem to be solved by the present application is to provide a new display method to improve the discharge efficiency and effectively release the residual charge existing in the pixel TFT.

[0010] The present application is realized as follows: a new display method, comprising the following steps:

[0011] S1, the in-plane display area has transversely arranged scan lines, longitudinally arranged data lines and matrix distributed pixel transistors, each scan line is connected with the gate of each row of pixel transistors one by one, and each data line is connected with the source of each column of pixel transistors one by one;

[0012] The discharge transistor is arranged transversely, the number of the discharge transistor is the same as the number of the data line, the source of the discharge transistor is connected with the data line one by one, the drain of the discharge transistor is connected with the GND signal line, and the gate of the discharge transistor is connected with the first lower brush black signal line;

[0013] The switch transistor is arranged longitudinally, the number of the switch transistor is the same as the number of the scan line, the source of the switch transistor is connected with the scan line one by one, the drain of the switch transistor is connected with the second lower brush black signal line, and the gate of the switch transistor is connected with the third lower brush black signal line;

[0014] S2, in the first lower brush black time, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line are all transmitting VGH signal;

[0015] S3, in the second lower brush black time, the first lower brush black signal line and the second lower brush black signal line are all transmitting VGL signal, and the third lower brush black signal line is transmitting VGH signal;

[0016] S4, in the third lower brush black time, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line are all transmitting VGL signal.

[0017] Further, in the S1, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line are all connected with IC, and in the normal display time, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line are all transmitting VGL signal.

[0018] Further, in the S1, the scan line is connected with GIP driving circuit, and the data line is connected with IC.

[0019] Further, in the S2, the duration of the first lower brush black time is greater than the duration of high level of CK signal.

[0020] Further, in the S1, the pad area of the display panel is reserved with GND pad, and the GND signal line is connected with the GND pad through flexible circuit board.

[0021] Further, the pixel transistor, the discharging transistor and the switch transistor are all TFT (Thin Film Transistor).

[0022] Further, the pixel transistor, the discharging transistor and the switch transistor are all fixedly arranged in the LCD panel.

[0023] The present application has the advantages that: the discharging transistor and the switch transistor are added, and the lower brush black operation is effectively performed after the normal display is ended by cooperating with the corresponding driving signal sequence; compared with the background art, in the lower brush black stage, the voltage signals of all data lines are pulled down to GND, and the voltage signals of all scan lines are pulled up to VGH, all pixel transistors are discharged at the same time, the discharging efficiency is improved, the residual charge existing in the pixel TFT is effectively released, and the display defect caused by the residual charge of the pixel TFT is eliminated. BRIEF DESCRIPTION OF DRAWINGS

[0024] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0025] Figure 1is a schematic diagram of a traditional GIP driving circuit in the background art.

[0026] Figure 2 is a schematic diagram of the signal timing of the output of each stage of the traditional GIP driving circuit in the background art when displaying power-off.

[0027] Figure 3 is a schematic diagram of the connection of the traditional GIP driving circuit and the pixel TFT of the in-plane display area in the background art.

[0028] Figure 4 is a schematic diagram of the connection of the pixel transistor, the discharging transistor and the switch transistor in the present application.

[0029] Figure 5 is a schematic diagram of the signal timing of the first, second and third lower black erasing signal lines in the present application. DETAILED DESCRIPTION

[0030] The present application provides a novel display method, which overcomes the shortcomings of the background art, i.e. when displaying power-off, the pixel TFT is opened by the GIP driving circuit step by step for discharging, the discharging efficiency is low, and in the case of short black erasing time, the residual charge will remain in the pixel TFT of the in-plane display area, which affects the display performance of the metal oxide display panel. The present application realizes the simultaneous discharging of all pixel transistors, improves the discharging efficiency, effectively releases the residual charge existing in the pixel TFT, and thus eliminates the display defects caused by the residual charge of the pixel TFT.

[0031] The general idea of the technical solution of the present application is as follows:

[0032] In the black erasing stage, the voltage signals of all data lines are pulled down to GND through the discharging transistor, the GND signal line and the first lower black erasing signal line; the voltage signals of all scan lines are pulled up to VGH through the switch transistor, the second lower black erasing signal line and the third lower black erasing signal line, so as to simultaneously open all pixel transistors, make all pixel transistors discharge at the same time, improve the discharging efficiency, and then simultaneously close all pixel transistors to end the power-off.

[0033] The signals of the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line are provided by an IC, the time length of the lower signals of the three signal lines is independent of the CK signal, the time length of the first lower brush black time is set to be greater than the time length of the high level of the CK signal, the discharge time of the pixel transistor is increased, and the residual charge of the pixel transistor is more beneficial to be released. In the background art, the output stage of the GIP driving circuit transmits signals related to the CK signal, in normal display, the pixel transistor needs to be quickly opened, data is written into the pixel transistor, and then the pixel transistor is closed, and the display is displayed in stage transmission; but in the lower brush black stage, the brush black time is short. In the present application, adjusting the time of the lower brush black does not affect the CK signal, ensures the normal stage transmission of the display, and increases the discharge time of the pixel transistor in the lower brush black, which is more beneficial to release the residual charge existing in the pixel TFT.

[0034] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings of the specification and specific embodiments.

[0035] Reference Figures 1 to 5 , preferred embodiments of the present application.

[0036] A novel display method, comprising the following steps:

[0037] S1, the in-plane display area has transversely arranged scan lines, longitudinally arranged data lines and matrix distributed pixel transistors, each of the scan lines is connected with the gate of each row of the pixel transistors one by one, and each of the data lines is connected with the source of each column of the pixel transistors one by one; in the figure, the scan lines are G1 to Gn respectively; the data lines are S1 to Sn respectively; and the pixel transistors are T11 to Tnn respectively.

[0038] Transversely arranged discharge transistors, the number of the discharge transistors is the same as the number of the data lines, the source of each of the discharge transistors is connected with one of the data lines, the drain of each of the discharge transistors is connected with the GND signal line, and the gate of each of the discharge transistors is connected with the first lower brush black signal line; in the figure, the discharge transistors are Tg1 to Tgn respectively; the source of the nth discharge transistor is connected with the nth data line.

[0039] A plurality of switch transistors are arranged longitudinally, the number of the switch transistors is the same as the number of the scan lines, the source of the switch transistor is connected to the scan line one by one, the drain of the switch transistor is connected to the second lower brush black signal line, and the gate of the switch transistor is connected to the third lower brush black signal line. In the figure, the switch transistors are T01 to T0n respectively; the source of the nth switch transistor is connected to the nth scan line. The first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line are P1, P2 and P3 respectively.

[0040] The first lower brush black signal line P1, the second lower brush black signal line P2 and the third lower brush black signal line P3 are connected to the IC, and during normal display time, the first lower brush black signal line P1, the second lower brush black signal line P2 and the third lower brush black signal line P3 all transmit VGL signals. At this time, the discharge transistor (Tg1 to Tgn) and the switch transistor (T01 to T0n) are both in the off state.

[0041] The scan lines (G1 to Gn) are connected to the GIP drive circuit, and the data lines (S1 to Sn) are connected to the IC. During normal display time, the GIP drive circuit outputs a gate signal to control the opening and closing of the pixel transistor (T11 to Tnn); the IC outputs a source signal to write the desired display data voltage to the pixel transistor (T11 to Tnn), and the display level is transmitted for display.

[0042] S2, during the first lower brush black time, the first lower brush black signal line P1, the second lower brush black signal line P2 and the third lower brush black signal line P3 all transmit VGH signals;

[0043] At this time, the discharge transistor (Tg1 to Tgn) and the switch transistor (T01 to T0n) are both in the on state, the voltage signals of all data lines (S1 to Sn) are pulled down to GND, and the voltage signals of all scan lines (G1 to Gn) are pulled up to VGH, all pixel transistors (T11 to Tnn) are discharged at the same time, and the discharge efficiency is improved.

[0044] The duration of the first lower brush black time is greater than the duration of the high level of the CK signal. Adjusting the time of the lower brush black does not affect the CK signal, ensuring normal level transmission display of the display, and increasing the discharge time of the pixel transistor during the lower brush black, which is more conducive to releasing the residual charge existing in the pixel transistor.

[0045] S3, during the second lower brush black time, the first lower brush black signal line P1 and the second lower brush black signal line P2 both transmit VGL signals, and the third lower brush black signal line P3 transmits VGH signals;

[0046] At this time, all the discharge transistors (Tg1 to Tgn) are in the off state, all the switch transistors (T01 to T0n) are in the on state, all the scan lines (G1 to Gn) are connected to the VGL signal, so that all the pixel transistors (T11 to Tnn) are in the off state, and the pixel transistors complete the discharge.

[0047] S4, at the third lower brush black time, the first lower brush black signal line P1, the second lower brush black signal line P2 and the third lower brush black signal line P3 all transmit the VGL signal.

[0048] At this time, all the discharge transistors (Tg1 to Tgn) and the switch transistors (T01 to T0n) are in the off state. The lower brush black operation is completed.

[0049] In the embodiment, the pad area of the display panel is reserved with a GND pad, and the GND signal line is connected to the GND pad through a flexible circuit board. By introducing the GND level into the in-plane display area, better discharge of the pixel transistors in the in-plane display area is achieved. The method of introducing the GND into the in-plane display area can reserve the GND in the pad area when the layout of the display panel is made, and then introduce the GND level into the in-plane display area through the FPC (flexible circuit board).

[0050] The pixel transistors, the discharge transistors and the switch transistors are metal oxide TFT thin film transistors.

[0051] The pixel transistors, the discharge transistors and the switch transistors are fixedly arranged in the LCD panel.

[0052] The novel display method of the present application, in the lower brush black stage, first the first lower brush black signal line P1, the second lower brush black signal line P2, the third lower brush black signal line P3 are all high level VGH, at this time the pixel transistors (T11~Tnn) of the in-plane display area are all in the open state, through the discharge transistor (Tg1~Tgn) discharges the capacitance of the pixel transistors (T11~Tnn) of the in-plane display area, makes its level GND, releases the in-plane charge. Next, the first lower brush black signal line P1 and the second lower brush black signal line P2 become VGL level, the third lower brush black signal line P3 is still VGH level, the switch transistor (T01~T0n) is opened, at this time because the second lower brush black signal line P2 is VGL level, all the scan lines (G1~Gn) can be pulled down to VGL level, at the same time the pixel transistors (T11~Tnn) of the in-plane display area are all in the closed state, finally the first lower brush black signal line P1, the second lower brush black signal line P2, the third lower brush black signal line P3 are all low level VGL, thus the lower brush black discharge process ends. The present application adopts the mode that all the scan lines are pulled up to VGH, increases the discharge time, improves the discharge efficiency, effectively releases the excess charge existing in the pixel TFT transistor, increases the brush black efficiency, eliminates the display defects caused by the residual charge of the in-plane pixel TFT transistor.

[0053] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific examples described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A novel display method, characterized by, The method comprises the following steps: S1, the in-plane display area has transversely arranged scan lines, longitudinally arranged data lines and matrix distributed pixel transistors, each scan line is connected with the gate of each row of pixel transistors one by one, and each data line is connected with the source of each column of pixel transistors one by one; Transversely arranged discharge transistors, the number of discharge transistors is the same as the number of data lines, the source of the discharge transistor is connected with the data line one by one, the drain of the discharge transistor is connected with the GND signal line, and the gate of the discharge transistor is connected with the first lower brush black signal line; Longitudinally arranged switch transistors, the number of switch transistors is the same as the number of scan lines, the source of the switch transistor is connected with the scan line one by one, the drain of the switch transistor is connected with the second lower brush black signal line, and the gate of the switch transistor is connected with the third lower brush black signal line; S2, at the first lower brush black time, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line all transmit VGH signals; S3, at the second lower brush black time, the first lower brush black signal line and the second lower brush black signal line transmit VGL signals, and the third lower brush black signal line transmits VGH signals; S4, at the third lower brush black time, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line all transmit VGL signals.

2. A novel display method according to claim 1, characterized in that, In the S1, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line are connected with IC, and at the normal display time, the first lower brush black signal line, the second lower brush black signal line and the third lower brush black signal line all transmit VGL signals.

3. The novel display method according to claim 1, characterized in that, In the S1, the scan line is connected with the GIP driving circuit, and the data line is connected with IC.

4. A novel display method according to claim 3, characterized in that, In the S2, the duration of the first lower brush black time is greater than the duration of the high level of the CK signal.

5. The novel display method according to claim 1, characterized in that, In the S1, the pad area of the display panel reserves a GND pad, and the GND signal line is connected with the GND pad through a flexible circuit board.

6. The novel display method according to claim 1, characterized in that, The pixel transistor, the discharge transistor and the switch transistor are all metal oxide TFT thin film transistors.

7. The novel display method according to claim 1, characterized in that, The pixel transistor, the discharge transistor and the switch transistor are all fixedly arranged on the LCD panel.

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