Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising: a substrate substrate; a pixel circuit arranged on the substrate substrate and comprising a driving transistor and a storage capacitor; the display substrate further comprising a first conductive layer, a second conductive layer and a first semiconductor layer, wherein the first conductive layer comprises a first connection structure, the first connection structure comprises opposite first and second ends, the first end is connected with the first semiconductor layer, and the second end is electrically connected with the gate of the driving transistor and the first plate of the storage capacitor; the first conductive layer is on the side of the first semiconductor layer away from the substrate substrate, the second conductive layer is on the side of the first conductive layer away from the substrate substrate, and the orthogonal projection of the second conductive layer on the substrate substrate and the orthogonal projection of at least part of the first connection structure on the substrate substrate overlap.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices. They possess advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost, thus demonstrating high development prospects. With the continuous development of display technology, flexible display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. As display technology continues to advance, optimizing display effects has become an inevitable trend. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate and a display device. The display substrate uses a first electrode adapter line or a first power signal line located on a second conductive layer (SD2) to shield the N1 node. Since a stable signal is connected to the second conductive layer (SD2) and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1), the influence of nearby data signals on the N1 node can be reduced, that is, the influence of data signals on the N1 node is shielded. This can improve the problem that the display panel cannot display normally due to the voltage of the N1 node being affected by the data signal jump.

[0004] At least one embodiment of this disclosure provides a display substrate, the display substrate comprising: a substrate; a pixel circuit disposed on the substrate, including a driving transistor and a storage capacitor; the display substrate further comprising a first conductive layer, a second conductive layer and a first semiconductor layer, wherein the first conductive layer includes a first connection structure, the first connection structure including a first end and a second end opposite to each other, the first end being connected to the first semiconductor layer, and the second end being electrically connected to the gate of the driving transistor and a first plate of the storage capacitor; the first conductive layer is on the side of the first semiconductor layer away from the substrate, the second conductive layer is on the side of the first conductive layer away from the substrate, and the orthographic projection of the second conductive layer on the substrate overlaps with the orthographic projection of at least a portion of the first connection structure on the substrate.

[0005] For example, the display substrate provided in at least one embodiment of this disclosure further includes a plurality of sub-pixels, wherein each sub-pixel includes the pixel circuit and the light-emitting element, the first conductive layer is between the first electrode of the light-emitting element and the first semiconductor layer, and the second conductive layer is between the first conductive layer and the first electrode of the light-emitting element.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, the second conductive layer includes mutually spaced data lines, a first electrode adapter line, and a first power signal line. The first electrode adapter line is connected to the first electrode of the light-emitting element, and the orthographic projection of the first electrode adapter line on the substrate overlaps with the orthographic projection of a portion of the first connection structure on the substrate.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the first connection structure includes a portion that overlaps with the first electrode adapter line and a portion that does not overlap with the first electrode adapter line, and the non-overlapping portion is further away from the data line closest to it relative to the overlapping portion.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the extension direction of the data line is a first direction, and the direction perpendicular or substantially perpendicular to the extension direction of the data line is a second direction; the first conductive layer further includes a power signal connection line, the power signal connection line includes a main body portion and a branch portion, the extension direction of the main body portion of the power signal connection line is parallel to the second direction, and the extension direction of the branch portion is parallel to the first direction; the first power signal line includes a block portion and a strip portion that extends generally along the first direction, the strip portion connects adjacent block portions, and the main body portion of the power signal connection line and the first power signal line are connected to form a grid.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, the strip portion includes a first strip portion and a second strip portion disposed opposite to each other, and a third strip portion connecting the first strip portion and the second strip portion, wherein the extending directions of the first strip portion and the second strip portion are parallel to the first direction, and the third strip portion connects the middle region of the first strip portion and the second strip portion.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the strip portion includes a hollow structure.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the width of the block portion in the second direction is greater than the overall width of the strip portion in the second direction.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the first electrode adapter line extends along the first direction, and the first electrode adapter line blocks a portion of the first connection structure at its end position near the first connection structure.

[0013] For example, in at least one embodiment of the display substrate provided in this disclosure, the pixel circuit further includes a first transistor, a second transistor, a sixth transistor, and a seventh transistor; the first terminal of the first transistor is connected to the gate of the driving transistor, the second terminal of the first transistor is connected to a first initial signal line, the first terminal of the second transistor is connected to the gate of the driving transistor, the second terminal of the second transistor is connected to the second terminal of the driving transistor, the first terminal of the sixth transistor is connected to the second terminal of the driving transistor, the first terminal of the seventh transistor is connected to the second terminal of the sixth transistor, and the second terminal of the seventh transistor is connected to the second initial signal line; the display substrate further includes: a first active layer between the substrate and the second conductive layer, the first active layer including a third active portion and a sixth active portion. The system comprises a third active portion, a sixth active portion, a seventh active portion, a tenth active portion, and an eleventh active portion. The third active portion forms the channel region of the driving transistor. The sixth active portion forms the channel region of the sixth transistor. The seventh active portion forms the channel region of the seventh transistor. The tenth active portion is connected between the seventh active portion and the sixth active portion. The eleventh active portion is connected between the sixth active portion and the third active portion. A second active layer is located between the first active layer and the second conductive layer. The second active layer includes a first active portion, a second active portion, and a twelfth active portion. The first active portion forms the channel region of the first transistor. The second active portion is connected to the first active portion to form the channel region of the second transistor. The twelfth active portion is connected to the end of the second active portion away from the first active portion.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the display substrate includes a plurality of repeating units distributed along the first direction and the second direction. Each repeating unit includes two pixel circuits, and the two pixel circuits include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are arranged in a mirror-symmetrical manner. Each pixel circuit also includes a fourth transistor and a fifth transistor. The first electrode of the fourth transistor is connected to the data line, the second electrode of the fourth transistor is connected to the first electrode of the driving transistor, the first electrode of the fifth transistor is connected to the first power signal line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor. The first active layer further includes: a fourth active portion connected to one side of the third active portion and forming the channel region of the fourth transistor; a fifth active portion forming the channel region of the fifth transistor; an eighth active portion connected to the side of the fifth active portion away from the third active portion; and a ninth active portion connected between two eighth active portions in the same repeating unit.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the first conductive layer includes: a plurality of third connection structures, wherein the plurality of third connection structures are disposed in a one-to-one correspondence with the plurality of repeating units, and the third connection structures are connected to the ninth active unit through a first via connection portion.

[0016] For example, at least one embodiment of the display substrate provided in this disclosure further includes a third conductive layer, wherein the third conductive layer includes: a second gate line, whose orthographic projection on the substrate extends along the second direction and overlaps with the orthographic projection of the fourth active portion on the substrate, a portion of the structure of the second gate line being used to form the gate of the fourth transistor; a light emission control signal line, whose orthographic projection on the substrate extends along the second direction and overlaps with the orthographic projection of the sixth active portion on the substrate, a portion of the structure of the light emission control signal line being used to form the gate of the sixth transistor; and a second reset signal line, whose orthographic projection on the substrate extends along the second direction and overlaps with the orthographic projection of the seventh active portion on the substrate, a portion of the structure of the second reset ... The second gate line in the pixel circuit is configured to form the gate of the seventh transistor, and the second gate line in the pixel circuit of the same row is multiplexed as the second reset signal line in the pixel circuit of the adjacent row; the second conductive portion overlaps with the orthographic projection of the third active portion on the substrate, and the second conductive portion forms the gate of the driving transistor and the first plate of the storage capacitor; wherein, in the same pixel circuit, the orthographic projection of the second conductive portion on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the light emission control signal line on the substrate; the orthographic projection of the second reset signal line on the substrate is located on the side of the orthographic projection of the light emission control line on the substrate away from the orthographic projection of the second conductive portion on the substrate.

[0017] For example, at least one embodiment of the display substrate provided in this disclosure further includes a fourth conductive layer, wherein the fourth conductive layer is located between the second active layer and the second conductive layer, and the fourth conductive layer includes: a first reset signal line whose orthographic projection on the substrate overlaps with the orthographic projection of the first active portion on the substrate, and a portion of the structure of the first reset signal line forms the top gate of the first transistor; a first gate line whose orthographic projection on the substrate overlaps with the orthographic projection of the second active portion on the substrate, and a portion of the structure of the first gate line forms the top gate of the second transistor; in the same pixel circuit, the orthographic projection of the first gate line on the substrate lies between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the second gate line on the substrate, and the orthographic projection of the first reset signal line on the substrate lies on the side of the orthographic projection of the second gate line on the substrate away from the orthographic projection of the second conductive portion on the substrate.

[0018] For example, at least one embodiment of the display substrate provided in this disclosure further includes: a conductive film layer between the third conductive layer and the fourth conductive layer, wherein the conductive film layer includes: a first initial signal line, the orthographic projection of which on the substrate is on the side away from the orthographic projection of the second conductive portion on the substrate; a third reset signal line, connected to the first reset signal line through a via, the orthographic projection of which on the substrate overlaps with the orthographic projection of the first active portion on the substrate, a portion of the structure of which is used to form the bottom gate of the first transistor; a third gate line, the orthographic projection of which on the substrate overlaps with the orthographic projection of the second active portion on the substrate, a portion of the structure of which is used to form the bottom gate of the second transistor; a first conductive portion, including a main body portion, wherein the storage capacitor includes a second electrode plate opposite to the first electrode plate, and the main body portion corresponds to two second electrode plates.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the first conductive portion further includes a bridging portion that connects two second electrode plates, and the first conductive portion includes a notch between the two second electrode plates.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the second conductive layer includes a data line and a first power signal line, wherein the orthographic projection of the first power signal line on the substrate covers more than 50% of the orthographic projection of the first connection structure on the substrate.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit further includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the gate of the first transistor is connected to a reset control signal line, the first electrode of the first transistor is connected to a first initial signal line, and the second electrode of the first transistor is connected to the first electrode of the eighth transistor and the first electrode of the second transistor; the gate of the second transistor is connected to a first scan signal line, and the second electrode of the second transistor is connected to the second electrode of the driving transistor and the first electrode of the sixth transistor; the gate of the driving transistor is connected to the second electrode of the eighth transistor and the first electrode of the storage capacitor, the first electrode of the driving transistor is connected to the second electrode of the fourth transistor and the second electrode of the fifth transistor, and the second electrode of the driving transistor is connected to the second electrode of the second transistor and the first electrode of the sixth transistor; the gate of the fourth transistor is connected to the first scan signal line, the first electrode of the fourth transistor is connected to the data line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor and the second electrode of the fifth transistor; the gate of the fifth transistor is connected to a first light emission control signal line. The fifth transistor is connected in a line connection. The first terminal of the fifth transistor is connected to the first power signal line and the second plate of the storage capacitor. The second terminal of the fifth transistor is connected to the second terminal of the fourth transistor and the first terminal of the driving transistor. The gate of the sixth transistor is connected to the first light-emitting control signal line. The first terminal of the sixth transistor is connected to the second terminal of the driving transistor and the second terminal of the second transistor. The second terminal of the sixth transistor is connected to the first terminal of the light-emitting element and the second terminal of the seventh transistor. The gate of the seventh transistor is connected to the first scan signal line or the reset control signal line. The first terminal of the seventh transistor is connected to the second initial signal line. The second terminal of the seventh transistor is connected to the second terminal of the sixth transistor and the first terminal of the light-emitting element. The gate of the eighth transistor is connected to the second scan signal line. The first terminal of the eighth transistor is connected to the second terminal of the first transistor and the first terminal of the second transistor. The second terminal of the eighth transistor is connected to the gate of the driving transistor and the first plate of the storage capacitor. The first plate of the storage capacitor is connected to the gate of the driving transistor and the second terminal of the eighth transistor. The second plate of the storage capacitor is connected to the first power signal line.

[0022] For example, at least one embodiment of the display substrate provided in this disclosure further includes: a first active layer between the substrate and the second conductive layer, the first active layer including a first active portion, a second active portion, a third active portion, a fourth active portion, a fifth active portion, a sixth active portion and a seventh active portion, wherein the first active portion forms the channel region of the first transistor, the second active portion forms the channel region of the second transistor, the third active portion forms the channel region of the driving transistor, the fourth active portion forms the channel region of the fourth transistor, the fifth active portion forms the channel region of the fifth transistor, the sixth active portion forms the channel region of the sixth transistor, and the seventh active portion forms the channel region of the seventh transistor; and a second active layer between the first active layer and the second conductive layer, the second active layer including an eighth active portion, the eighth active portion forming the channel region of the eighth transistor.

[0023] For example, at least one embodiment of the display substrate provided in this disclosure further includes a third conductive layer, wherein the third conductive layer includes: a first scan signal line, whose orthogonal projection on the substrate extends along a second direction, and a portion of the structure of the first scan signal line is used to form the gates of the second transistor and the fourth transistor; a reset control signal line, whose orthogonal projection on the substrate extends along the first direction, and a portion of the structure of the reset control signal line is used to form the gates of the seventh transistor and the first transistor; a first light emission control signal line, whose orthogonal projection on the substrate extends along the first direction, and a portion of the structure of the first light emission control signal line is used to form the gates of the sixth transistor and the fifth transistor; and a third conductive portion, forming the gate of the driving transistor and the first electrode of the storage capacitor; wherein, in the same pixel circuit, the orthogonal projection of the third conductive portion on the substrate is located between the orthogonal projection of the first scan signal line on the substrate and the orthogonal projection of the first light emission control signal line on the substrate; and the orthogonal projection of the reset control signal line on the substrate is on the side of the orthogonal projection of the first light emission control signal line on the substrate away from the orthogonal projection of the third conductive portion on the substrate.

[0024] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a conductive film layer between the third conductive layer and the second conductive layer, wherein the conductive film layer includes: a second scan signal line, and a portion of the structure of the second scan signal line is used to form the bottom gate of the eighth transistor; a first conductive portion including the second plates of two adjacent storage capacitors in the second direction; and a fifth conductive portion electrically connected to the first conductive layer.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, the first conductive portion further includes a bridging portion that connects two second electrode plates, and the first conductive portion includes a notch between the two second electrode plates.

[0026] For example, at least one embodiment of the display substrate provided in this disclosure further includes a fourth conductive layer, wherein the fourth conductive layer is located between the conductive film layer and the second conductive layer, the fourth conductive layer includes the first initial signal line and the fourth scan signal line, and a portion of the structure of the fourth scan signal line forms the top gate of the eighth transistor.

[0027] For example, in a display substrate provided in at least one embodiment of this disclosure, the extension direction of the data line is a first direction, and the direction perpendicular or substantially perpendicular to the extension direction of the data line is a second direction. The first connection structure is inverted "L" shape, and the end of the inverted "L" shape along the second direction that is furthest from the data line closest to it is connected to the second electrode of the eighth transistor.

[0028] For example, in a display substrate provided in at least one embodiment of this disclosure, the inverted "L"-shaped portion along the first direction is electrically connected to the fifth conductive portion of the conductive film layer; the first scan signal line includes a protrusion extending along the first direction and a portion extending along the second direction, and the fifth conductive portion overlaps with the protrusion of the first scan signal line extending along the first direction.

[0029] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels; two second sub-pixels constitute a second sub-pixel pair, and the two second sub-pixels in a second sub-pixel pair are respectively a first pixel block and a second pixel block, and the first pixel block and the second pixel block are alternately arranged along the first direction or the second direction; the plurality of sub-pixels includes a plurality of minimum repeating units, and one minimum repeating unit includes a first sub-pixel, a first pixel block, a second pixel block, and a third sub-pixel.

[0030] For example, at least one embodiment of the display substrate provided in this disclosure further includes a first electrode layer, wherein the first electrode layer is on the side of the second conductive layer away from the substrate, the first electrode layer includes a plurality of electrode portions, each electrode portion including a body portion and an extension portion connected to each other, the orthographic projection of the extension portion on the substrate at least partially overlaps with the orthographic projection of the first electrode adapter line on the substrate, and each electrode portion corresponds to one of the first sub-pixel, the first pixel block, the second pixel block and the third sub-pixel.

[0031] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of electrode portions include a first electrode portion, a second electrode portion, and a third electrode portion of three different colors. The first electrode portion corresponds to the first sub-pixel, the second electrode portion corresponds to either the first pixel block or the second pixel block, and the third electrode portion corresponds to the third sub-pixel. The overlapping area of ​​the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the first power signal line on the substrate is greater than the overlapping area of ​​the orthographic projection of the second electrode portion on the substrate and the orthographic projection of the first power signal line on the substrate, and is also greater than the overlapping area of ​​the orthographic projection of the third electrode portion on the substrate and the orthographic projection of the first power signal line on the substrate. The overlapping area of ​​the orthographic projection of the third electrode portion on the substrate and the orthographic projection of the first power signal line on the substrate is greater than the overlapping area of ​​the orthographic projection of the second electrode portion on the substrate and the orthographic projection of the first power signal line on the substrate.

[0032] For example, in a display substrate provided in at least one embodiment of this disclosure, the first electrode portion corresponds to a blue sub-pixel that emits blue light, the second electrode portion corresponds to a green sub-pixel that emits green light, and the third electrode portion corresponds to a red sub-pixel that emits red light.

[0033] For example, in a display substrate provided in at least one embodiment of this disclosure, the second conductive layer further includes a plurality of first electrode adapter lines, the plurality of first electrode adapter lines being disposed in a one-to-one correspondence with a plurality of electrode portions, and the electrode portions being connected to the first electrode adapter lines disposed therewith through vias.

[0034] For example, in a display substrate provided in at least one embodiment of this disclosure, the sub-pixel further includes a light-shielding layer on the side of the active semiconductor pattern of the driving transistor near the substrate, wherein the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active semiconductor pattern of the driving transistor on the substrate.

[0035] For example, at least one embodiment of this disclosure also provides a display device including the display substrate described in any of the above claims. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0037] Figure 1This is a layout for reducing the impact of data signal transitions on the N1 node in an LTPS pixel circuit by forming 3D capacitors.

[0038] Figure 2 This is a layout where the anode blocks the N1 node.

[0039] Figure 3 This is a schematic diagram of the circuit structure of a pixel circuit provided in one embodiment of the present disclosure.

[0040] Figure 4 for Figure 3 Timing diagram of each node in a driving method for a mid-pixel circuit.

[0041] Figure 5A This is a structural layout of a display substrate provided for at least one embodiment of the present disclosure.

[0042] Figure 5B This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure.

[0043] Figure 6 for Figure 5B The structural layout of the second conductive layer.

[0044] Figure 7 for Figure 5B The structural layout of the first conductive layer.

[0045] Figure 8 for Figure 5B The structural layout of the first and second conductive layers stacked together.

[0046] Figure 9 for Figure 5B The diagram shows a partial structural schematic of the first active layer in the display substrate.

[0047] Figure 10 for Figure 5B The diagram shows a partial structural schematic of the third conductive layer in the display substrate.

[0048] Figure 11 for Figure 5B The diagram shows a partial structural schematic of the conductive film layer in the display substrate.

[0049] Figure 12 for Figure 5B The diagram shows a partial structural schematic of the second active layer in the display substrate.

[0050] Figure 13 for Figure 5B The diagram shows a partial structural schematic of the fourth conductive layer in the display substrate.

[0051] Figure 14This is a schematic diagram of a partial pixel arrangement structure on a display substrate according to an embodiment of the present disclosure.

[0052] Figure 15A for Figure 5B A layout of the pixel circuit and the first electrode stack of the light-emitting element in a chip.

[0053] Figure 15B for Figure 5B Another layout of the pixel circuit and the first electrode stack of the light-emitting element.

[0054] Figure 16 This is a schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure.

[0055] Figure 17 for Figure 5B and Figure 15B The diagram shows a partial structural schematic of the light-shielding layer in the display substrate.

[0056] Figure 18 This is a layout of a stack of a light-shielding layer and a first active layer provided in an embodiment of the present disclosure.

[0057] Figure 19 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present disclosure.

[0058] Figure 20 for Figure 19 Timing diagram of each node in a driving method for a mid-pixel circuit.

[0059] Figure 21A This is a structural layout of another display substrate provided in an embodiment of the present disclosure.

[0060] Figure 21B This is a structural layout of another display substrate provided in an embodiment of the present disclosure.

[0061] Figure 22 for Figure 21B The structural layout of the second conductive layer.

[0062] Figure 23 for Figure 21B The structural layout of the first conductive layer.

[0063] Figure 24 for Figure 21B The structural layout of the first and second conductive layers stacked together.

[0064] Figure 25 for Figure 19 The diagram shows a partial structural schematic of the first active layer in the display substrate.

[0065] Figure 26 for Figure 19The diagram shows a partial structural schematic of the third conductive layer in the display substrate.

[0066] Figure 27 for Figure 19 The diagram shows a partial structural schematic of the conductive film layer in the display substrate.

[0067] Figure 28 for Figure 19 The diagram shows a partial structural schematic of the second active layer in the display substrate.

[0068] Figure 29 for Figure 19 The diagram shows a partial structural schematic of the fourth conductive layer in the display substrate.

[0069] Figure 30 This is a schematic diagram of a partial pixel arrangement structure on a display substrate according to an embodiment of the present disclosure.

[0070] Figure 31A for Figure 19 A layout of the pixel circuit and the first electrode stack of the light-emitting element in a chip.

[0071] Figure 31B for Figure 19 Another layout of the pixel circuit and the first electrode stack of the light-emitting element.

[0072] Figure 32 This is a schematic cross-sectional view of a display substrate provided in at least one embodiment of the present disclosure.

[0073] Figure 33 This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure.

[0074] Figure 34 This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure.

[0075] Figure 35 This is a structural layout of another display substrate provided for at least one embodiment of the present disclosure.

[0076] Figure 36 This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0078] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0079] The characteristics such as "perpendicular" and "identical" used in this disclosure include "perpendicular" and "identical" in a strict sense, as well as "approximately perpendicular" and "approximately identical," which include a certain degree of error. Taking into account the measurement and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The term "center" in this disclosure can include a position strictly located at the geometric center as well as a position approximately at the center within a small area surrounding the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0080] Low-Temperature Polycrystalline Oxide (LTPO) technology can be applied to light-emitting diode (LED) displays, thereby reducing power consumption. Display power consumption includes both drive power and emission power. LTPO-based displays have lower drive power than LTPS-based displays. While LTPS-based displays require 60 Hz to display still images, LTPO-based displays can achieve as low as 1 Hz, significantly reducing drive power.

[0081] Based on LTPO technology, some transistors in the display panel are oxide transistors (e.g., N-type oxide transistors). Oxide transistors have less leakage current, allowing the capacitor voltage (charge) to be maintained for one second, achieving a refresh rate of 1Hz. LTPS transistors have much greater leakage current, requiring 60Hz even to drive stationary pixels; otherwise, brightness would be significantly reduced. Therefore, LTPO technology has been widely used in display substrates.

[0082] For example, Figure 1This is a layout for reducing the impact of data signal transitions on the N1 node in an LTPS pixel circuit by forming a 3D capacitor. For example, the N1 node is located at the connection point between the lower plate of the storage capacitor and the gate of the driving transistor. Figure 1 As shown, in the LTPS pixel circuit design, to prevent the N1 node from being affected by the data signal, a second gate layer 02 connected to the power signal is added to the right of the N1 node. This power signal is generated by the power signal line 04, meaning the second gate layer 02 and the power signal line 04 are electrically connected. A capacitor can be formed between the second gate layer 02 and the N1 node, thus blocking the influence of data signal transitions generated by the data line 03 on the N1 node. However, this structural design does not directly overlap the second gate layer 02 and the N1 node; the resulting capacitor does not overlap on the plane, forming a spatial 3D capacitor. This spatial 3D capacitor is too small, resulting in insufficient shielding for the N1 node, and therefore cannot effectively prevent the data signal from affecting the N1 node.

[0083] For example, Figure 2 This is a layout where the anode shades the N1 node, such as... Figure 2 As shown, anode 05 covers node N1. Specifically, as... Figure 2 As shown, the anode 05R of the red sub-pixel covers the N1 node, and the additional portion of the anode 05R of the red sub-pixel crosses the data line 03 to the right of the anode 05R. The anode 05B of the blue sub-pixel covers the N1 node. To avoid differences in pixel brightness and ensure uniformity of display brightness, only the anodes 05R of the red sub-pixel and 05B of the blue sub-pixel cover the N1 node; the anodes 05G of the green sub-pixel do not obscure the N1 node.

[0084] Due to the advantages of LTPO technology, such as high charge mobility, high pixel response speed, and low power consumption, LTPO display products have many performance specifications. The inventors of this disclosure have noted that these performance specifications of LTPO display products are closely related to the circuit design of the product's backplane. For example, the N1 node can be shielded using an anode adapter line located on the second conductive layer (SD2). Since a stable signal is connected to the second conductive layer (SD2), and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1), the influence of nearby data signals on the N1 node can be reduced, i.e., the influence of data signals on the N1 node is shielded. This improves the problem of the display panel failing to display properly due to the voltage of the N1 node being affected by data signal fluctuations. Furthermore, this design can be used to shield the N1 node for red, green, and blue sub-pixels, thereby improving the problem of poor light emission uniformity of the display panel caused by transistor process variations.

[0085] The inventors of this disclosure also noted that a horizontal power signal line (horizontal VDD) can be designed on the first conductive layer (SD1), and a vertical power signal line (vertical VDD) can be designed on the second conductive layer (SD2). The horizontal and vertical power signal lines intersect to form a mesh of power signal lines, thereby making the signal on the power signal line more stable and also saving design space.

[0086] For example, at least one embodiment of this disclosure provides a display substrate, the display substrate comprising: a substrate, a pixel circuit disposed on the substrate, the pixel circuit including a driving transistor and a storage capacitor, the display substrate further comprising a first conductive layer, a second conductive layer and a first semiconductor layer, wherein the first conductive layer includes a first connection structure, the first connection structure including a first end and a second end opposite to each other, the first end being connected to the first semiconductor layer, and the second end being electrically connected to the gate of the driving transistor and the first plate of the storage capacitor; the first conductive layer is located on the side of the first semiconductor layer away from the substrate, the second conductive layer is located on the side of the first conductive layer away from the substrate, and the orthographic projection of the second conductive layer on the substrate and at least a portion of the first connection structure on the substrate are also orthographic projections of the second conductive layer onto the substrate. The projection overlaps the first electrode connection line in the second conductive layer (SD2) by overlapping the orthographic projection of the second conductive layer on the substrate with the orthographic projection of at least part of the first connection structure on the substrate. This allows at least part of the N1 node to be blocked. Since the second conductive layer (SD2) is connected to a stable signal and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1), and a capacitor is formed between the N1 node and the data line closest to it, the data signal has little impact on the capacitor. This reduces the impact of nearby data signals on the N1 node, i.e., shields the impact of data signals on the N1 node. This improves the problem of the display panel failing to display properly due to the voltage of the N1 node being affected by data signal jumps.

[0087] For example, Figure 3 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the pixel circuit 110 includes: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C.

[0088] For example, such as Figure 3 As shown, the first transistor T1 is the first reset transistor T1, the second transistor T2 is the threshold compensation transistor T2, the fourth transistor T4 is the data writing transistor T4, the fifth transistor T5 is the second light-emitting control transistor T5, the sixth transistor T6 is the first light-emitting control transistor T6, and the seventh transistor T7 is the second reset control transistor T7.

[0089] For example, the first terminal of the first transistor T1 is connected to node N1, which is electrically connected to the gate of the driving transistor T3. The second terminal of the first transistor T1 is connected to the first initial signal terminal Vinit1, which is electrically connected to the first reset signal line to receive the reset signal. The gate of the first transistor T1 is connected to the first reset signal terminal Re1, which is electrically connected to the reset control signal line to receive the reset control signal. The first terminal of the second transistor T2, which is also the threshold compensation transistor, is connected to node N1, which is electrically connected to the gate of the driving transistor T3. The second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3. The gate of the second transistor T2 is connected to the first gate drive signal terminal G1 to receive the compensation control signal. The gate of the driving transistor T3 is connected to node N1 to connect to the first plate of the storage capacitor C, the first terminal of the first transistor T1, and the first terminal of the second transistor T2. The first terminal of the fourth transistor T4, which is also the data write transistor, is connected to the data signal terminal Data to receive the data signal. The second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3. The gate of the fourth transistor T4 is connected to the second gate. The drive signal terminal G2 receives the scan signal; the first terminal of the fifth transistor T5, which is also the second light-emitting control transistor, is connected to the first power supply terminal VDD to receive the first power supply signal, the second terminal of the fifth transistor T5 is connected to the first terminal of the drive transistor T3, and the gate of the fifth transistor T5 is connected to the light-emitting control signal terminal EM to receive the light-emitting control signal; the first terminal of the sixth transistor T6, which is also the first light-emitting control transistor, is connected to the second terminal of the drive transistor T3, the second terminal of the sixth transistor T6 is connected to the first terminal of the seventh transistor T7, and the gate of the sixth transistor T6 is connected to the light-emitting control signal terminal EM to receive the light-emitting control signal; the second terminal of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, which is electrically connected to the second reset power supply signal line to receive the reset signal Vinit, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2, which is electrically connected to the reset control signal line to receive the reset control signal; the first plate of the storage capacitor C is connected to node N1 and electrically connected to the gate of the drive transistor T3, and the second plate of the storage capacitor C is connected to the first power supply terminal VDD, which is connected to the first power supply signal line. The pixel circuit can be connected to the light-emitting element 120, which can be an organic light-emitting diode (OLED). The pixel circuit is used to drive the light-emitting element 120 to emit light. The light-emitting element 120 can be connected between the second terminal of the sixth transistor T6 and the second power supply terminal VSS, that is, connected to the second power supply signal line.

[0090] For example, the first power signal line mentioned above refers to the signal line for the output voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal. The second power signal line mentioned above refers to the signal line for the output voltage signal VSS, which can be connected to a voltage source to output a constant voltage signal, such as a negative voltage signal.

[0091] For example, the scan signal and the compensation control signal can be the same; that is, the gate of the data write transistor T4 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. Alternatively, the gate of the data write transistor T4 and the gate of the threshold compensation transistor T2 can be electrically connected to different signal lines; that is, the gate of the data write transistor T4 is electrically connected to the second scan signal line (second gate line), and the gate of the threshold compensation transistor T2 is electrically connected to the first scan signal line (first gate line). The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thus allowing the gates of the data write transistor T4 and the threshold compensation transistor T2 to be controlled separately, thereby increasing the flexibility of the pixel circuit control.

[0092] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically connected to different light-emitting control signal lines. In this case, the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0093] For example, the reset control signals input to the second reset transistor T7 and the first reset transistor T1 can be the same; that is, the gates of the second reset transistor T7 and the first reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the second reset transistor T7 and the first reset transistor T1 can be electrically connected to different reset control signal lines, in which case the signals on the different reset control signal lines can be the same or different.

[0094] For example, the first transistor T1 and the second transistor T2 can be N-type transistors. For example, the first transistor T1 and the second transistor T2 can be N-type metal-oxide transistors. N-type metal-oxide transistors have smaller leakage current, thus avoiding leakage current through the N1 node during the light-emitting stage. Meanwhile, the driving transistors T3, T4, T5, T6, and T7 can be P-type transistors. For example, the driving transistors T3, T4, T5, T6, and T7 can be P-type low-temperature polysilicon transistors. P-type low-temperature polysilicon transistors have higher carrier mobility, which is beneficial for achieving display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals depending on the actual situation.

[0095] For example, Figure 4 for Figure 3 The timing diagram of each node in a driving method for a pixel circuit is shown. G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the light emission control signal terminal EM, and Data represents the timing of the data signal terminal Data. The driving method for this pixel circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light emission stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to node N1. During the compensation phase t2: the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and simultaneously the data signal terminal Data outputs a drive signal to write a voltage Vdata+Vth (i.e., the sum of voltages Vdata and Vth) to node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3. During the second reset phase t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second terminal of the sixth transistor T6. During the light emission phase t4: the light emission control signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the drive transistor T3 emits light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0096] It should be noted that, in the embodiments of this disclosure, each pixel circuit can, in addition to being able to... Figure 3In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 7T2C, 6T1C, 6T2C, 8T1C, or 9T2C structures. This disclosure does not limit the specific number of transistors in the embodiments.

[0097] For example, the display substrate includes a plurality of repeating units distributed along intersecting first and second directions. Each repeating unit includes two pixel circuits, which include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are arranged in a substantially mirror-symmetrical manner. The pixel circuit described below is described using one of the first pixel circuit and the second pixel circuit.

[0098] For example, embodiments of this disclosure provide a display substrate, Figure 5A This is a structural layout of a display substrate provided in at least one embodiment of the present disclosure. Figure 5B This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure. Figure 6 for Figure 5B Layout of the second conductive layer. Figure 7 for Figure 5B The structural layout of the first conductive layer in the middle. Figure 8 for Figure 5B The structural layout of the first and second conductive layers stacked together. Figures 5A to 7 The schematic diagram only shows a partial stacked structure or a single-layer structure of the film layers in the display substrate. Other film layers may include the film layer containing the gate lines, the film layer containing the light-shielding layer, etc. Figure 5B Compared to Figure 5A It has an additional light-shielding layer, but the other structural settings are the same.

[0099] For example, combining Figure 3 and Figure 5BAs shown, the display substrate 100 includes: a substrate 101, a pixel circuit 110 disposed on the substrate 101, the pixel circuit 110 including a driving transistor T3 and a storage capacitor C, the display substrate 100 further including a first conductive layer 102, a second conductive layer 103 and a first semiconductor layer 104, wherein the first conductive layer 102 includes a first connection structure 1021, the first connection structure 1021 including a first end 1021a and a second end 1021b opposite to each other, the first end 1021a being connected to the first semiconductor layer 104, and the second end 1021b being connected to the gate of the driving transistor T3 and the storage capacitor C. The first electrode Cst1 of the storage capacitor C is electrically connected; the first conductive layer 102 is on the side of the first semiconductor layer 104 away from the substrate 101, and the second conductive layer 103 is on the side of the first conductive layer 102 away from the substrate 101, and the orthographic projection of the second conductive layer 103 on the substrate 101 overlaps with the orthographic projection of at least a portion of the first connection structure 1021 on the substrate 101. The display substrate 100 achieves this by making the orthographic projection of the second conductive layer 103 on the substrate 101 overlap with the orthographic projection of at least a portion of the first connection structure 1021 on the substrate 101, thus making the second conductive layer... 103 (also known as SD2) can block at least part of the first connection structure 1021 (also known as the N1 node), thereby causing the second conductive layer 103 and the first connection structure 1021 located on the first conductive layer 102 to directly form a capacitor, that is, a capacitor is directly formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also known as SD1), thereby forming a capacitor between the N1 node and the nearest data line data. Since the light emission control signal line EM and the second initial signal line Vinit2 both transmit stable DC signals, the second conductive layer 103 (SD2) is connected to a stable DC signal. The signal changes only once within a frame. This design allows the second conductive layer 103 (SD2) to directly form a capacitor with the first conductive layer 102 (also called SD1) at the N1 node during normal operation. The second conductive layer 103 (SD2, the upper plate) is connected to a stable signal. Due to the inherent characteristics of a capacitor, the voltage across it cannot change abruptly. After a stable DC signal is connected to the upper plate, the signal on the lower plate, i.e., the first conductive layer 102 (SD1) at the N1 node, also remains stable. This reduces the impact of frequently changing data signals on the N1 node within a frame. The data signal has a smaller impact on the capacitor, thus reducing the influence of nearby data signals on the N1 node, effectively shielding the N1 node from the impact of data signal changes. This improves the problem of the display panel failing to display properly due to the voltage fluctuations of the N1 node caused by data signal changes.

[0100] For example, such as Figure 5BAs shown, the first semiconductor layer 104 includes active semiconductor patterns of the first transistor T1 and the second transistor T2, which will be mentioned later. The material of the first semiconductor layer 104 is a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO). The first plate Cst1 of the storage capacitor C can be used as the gate of the driving transistor T3.

[0101] For example, combining Figure 3 and Figure 5B The first end 1021a of the first connection structure 1021 is also electrically connected to the first pole of the first transistor T1 (first reset transistor) and the first pole of the second transistor T2 (threshold compensation transistor).

[0102] For example, such as Figure 5A , Figure 5B , Figure 6 and Figure 8 As shown, the second conductive layer 103 includes mutually spaced data lines 1031, a first electrode adapter line 1032, and a first power signal line 1033. The first electrode adapter line 1032 is elongated and extends entirely along the extension direction of the data line 1031 to which it is closest. The extension direction of the data line 1031 is a first direction Y, and the direction perpendicular or substantially perpendicular to the extension direction of the data line 1031 is a second direction X. (Combined with...) Figure 3 , Figure 5B , Figure 6 and Figure 8 The first electrode adapter wire 1032 is connected to the first electrode of the light-emitting element 120, which will be described later, via a via. For example, as Figure 5B , Figure 6 and Figure 8 As shown, the orthographic projection of the data line 1031 onto the substrate 101 extends along the first direction Y. In the same repeating unit, the orthographic projections of the two data lines 1031 onto the substrate 101 are located between the orthographic projections of the two first power signal lines 1033 onto the substrate 101.

[0103] For example, in Figure 7 In the structural layout of the first conductive layer 102 shown, the first conductive layer 102 further includes a second initial signal line 1022, combined with... Figure 3 and Figure 7The second initial signal line 1022 is electrically connected to the first electrode of the seventh transistor T7 (the first reset transistor) to provide a reset signal. For example, the second initial signal line 1022 can be a first reset signal line electrically connected to the first electrode of the seventh transistor T7. The display substrate 110 also includes a second reset power signal line (not shown in the figure). The first portion of the second reset power signal line is located between the first conductive layer 102 and the film layer containing the gate of the seventh transistor T7, and is configured to be electrically connected to the first electrode of the first transistor T1 to provide a reset signal.

[0104] For example, such as Figure 7 and Figure 8 As shown, the first conductive layer 102 further includes power signal connection lines 1023 extending along the second direction X, and the second conductive layer 103 includes data lines and first power signal lines 1033 extending along the first direction Y. Each power signal connection line 1023 is electrically connected to a plurality of first power signal lines 1033 arranged along the second direction X to form a grid. The first power signal lines 1033 can be used to provide... Figure 3 The first power supply terminal, data cable 1031, can be used to provide... Figure 3 The data signal terminal in the middle. For example, such as Figure 7 and Figure 8 As shown, the main body 1023a of the power signal connection line 1023 is shaped like a zigzag with a protrusion, and a connecting block 1023b is provided in the middle of the protrusion. The overall extension direction of the power signal connection line 1023 is parallel to the second direction X, and the extension direction of the connecting block 1023b is parallel to the first direction Y. Multiple connecting blocks 1023b are present on the power signal connection line 1023, and the power signal connection line 1023 is connected to multiple first power signal lines 1033 on the second conductive layer 103 through these multiple connecting blocks 1023b.

[0105] For example, such as Figure 3 Figure 5 and Figure 7 As shown, the first conductive layer 102 also includes a first connection portion 1024 electrically connected to a first portion of the second reset power signal line.

[0106] For example, such as Figure 3 Figure 5 and Figure 7 As shown, the first conductive layer 102 also includes a second connection portion 1025, through which the first electrode of the data writing transistor T4 is electrically connected to the data line 1031 to receive data signals.

[0107] For example, such as Figure 3 Figure 5 Figure 7 and Figure 8As shown, the first conductive layer 102 also includes a third connection structure 1027, through which the first terminal of the sixth transistor T6 (first light-emitting control transistor) is electrically connected to the second terminal of the second transistor T2 (threshold compensation transistor). For example, the third connection structure 1027 is a branch portion of the power signal connection line 1023.

[0108] For example, such as Figure 5B , Figure 6 , Figure 7 and Figure 8 As shown, the orthographic projection of the first electrode adapter line 1032 on the substrate 101 overlaps with the orthographic projection of a portion of the first connection structure 1021 on the substrate 101. The first connection structure 1021 is a zigzag line extending as a whole away from the data line 1031 closest to it. The first connection structure 1021 includes a portion that overlaps with the first electrode adapter line 1032 and a portion that does not overlap with the first electrode adapter line 1032, and the non-overlapping portion is further away from the data line 1031 closest to it than the overlapping portion.

[0109] For example, such as Figure 5B , Figure 6 , Figure 7 and Figure 8 As shown, the first power signal line 1033 includes a block-shaped portion 1033a and a strip-shaped portion 1033b extending generally along the first direction Y. The strip-shaped portion 1033b connects adjacent block-shaped portions 1033a along the first direction Y. The main body portion 1023a of the power signal connection line 1023 and the first power signal line 1033 are connected to form a grid. For example, the main body portion 1023a of the power signal connection line 1023 and the strip-shaped portion 1033b of the first power signal line 1033 are connected to form a grid. This grid-like arrangement can electrically connect the first power signal lines 1033 of each pixel, which helps to reduce the voltage drop of the first power signal lines 1033, thereby improving the uniformity of the display panel when the display substrate is used as a display panel.

[0110] For example, such as Figure 5B , Figure 6 and Figure 7 As shown, the block portion 1033a overlaps with the light-emitting area of ​​at least one of the first and third sub-pixels mentioned later.

[0111] For example, such as Figure 5B , Figure 6 and Figure 7 As shown, the second conductive layer 103 also includes a portion overlapping with the light-emitting area of ​​the second sub-pixel (e.g., a portion of the data line 1031).

[0112] For example, such as Figure 6 As shown, the width W1 of the block portion 1033a in the second direction X is greater than the overall width W2 of the strip portion 1033b in the second direction X, thereby further reducing the area of ​​the second conductive layer 103 to save space.

[0113] For example, such as Figure 5B , Figure 6 , Figure 7 and Figure 8 As shown, the first electrode adapter line 1032 extends along the first direction Y, and the first electrode adapter line 1032 partially blocks the first connection structure 1021 at its end position near the first connection structure 1021. That is, the orthographic projection of the end of the first electrode adapter line 1032 near the first connection structure 1021 on the substrate 101 overlaps with the orthographic projection of part of the first connection structure 1021 on the substrate 101.

[0114] For example, such as Figure 6 and Figure 8 As shown, the strip portion 1033b includes a first strip portion 1033b1 and a second strip portion 1033b2 disposed opposite to each other, and a third strip portion 1033b3 connecting the first strip portion 1033b1 and the second strip portion 1033b2. The extending directions of the first strip portion 1033b1 and the second strip portion 1033b2 are parallel to the first direction Y, and the third strip portion 1033b3 connects the middle region of the first strip portion 1033b1 and the second strip portion 1033b2. For example, the extending direction of the third strip portion 1033b3 may be parallel to the second direction X, or it may not be parallel to the second direction X, but may intersect with the second direction X.

[0115] For example, in one example, the planar shape of the first strip portion 1033b1, the second strip portion 1033b2, and the third strip portion 1033b3 can be H-shaped.

[0116] For example, in one example, the strip portion 1033b includes a hollow structure, which can reduce the area of ​​the second conductive layer 103, thereby saving space.

[0117] For example, such as Figure 3 , Figure 5B , Figure 6 , Figure 7 and Figure 8 As shown, the first conductive layer 102 also includes a third connection portion 1026, and the second electrode of the sixth transistor T6 (first light-emitting control transistor) is electrically connected to the first electrode of the light-emitting element through the third connection portion 1026 and the first electrode adapter wire 1032.

[0118] For example, Figure 9for Figure 5B The diagram shows a partial structural illustration of the first active layer in the display substrate, for example, as shown below. Figures 5B to 9 As shown, the pixel circuit 110 includes a first active layer 105, which includes a channel region 1051 and a source / drain region 1052 for each transistor. For example, the source / drain region 1052 may include a source region 1052a and a drain region 1052b.

[0119] For example, Figure 9 The diagram schematically illustrates the formation of a first active layer 105 using a patterned semiconductor material. The first active layer 105 can be used to fabricate the active layers of the aforementioned driving transistor T3, fourth transistor T4 (data write transistor), fifth transistor T5 (second light-emitting control transistor), sixth transistor T6 (first light-emitting control transistor), and seventh transistor T7 (second reset control transistor) to form the channel regions of these transistors. The first active layer 105 includes the active layer pattern (channel region) and doped region pattern (source / drain region) of the aforementioned transistors in each sub-pixel, and the active layer pattern and doped region pattern of the aforementioned transistors in the same pixel circuit are integrally formed.

[0120] For example, Figure 9 The dashed rectangles in the diagram illustrate the overlapping portions of the aforementioned metal layer and the first active layer 105, which respectively serve as the channel regions for driving transistors T3, T4, T5, T6, and T7. The portions of the first active layer on both sides of each channel region 1051 are conductiveized through processes such as ion doping to serve as the first and second electrodes of each transistor, i.e., the aforementioned source / drain regions 1052. The source and drain electrodes of the aforementioned transistors can be structurally symmetrical, so their physical structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the transistors, except for the gate which serves as the control electrode, one electrode is directly described as the first electrode and the other as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0121] For example, such as Figure 9As shown, the first active layer 105 includes a third active portion 23, a fourth active portion 24, a fifth active portion 25, a sixth active portion 26, a seventh active portion 27, an eighth active portion 28, a ninth active portion 29, a tenth active portion 210, and an eleventh active portion 211. The third active portion 23 is used to form the channel region of the driving transistor T3; the fourth active portion 24 is used to form the channel region of the fourth transistor T4; the fifth active portion 25 is used to form the channel region of the fifth transistor T5; the sixth active portion 26 is used to form the channel region of the sixth transistor T6; the seventh active portion 27 is used to form the channel region of the seventh transistor T7; the eighth active portion 28 is connected to the side of the fifth active portion 25 away from the third active portion 23; and the ninth active portion 29 is connected between the eighth active portion 28 in the first pixel circuit P1 and the eighth active portion 28 in the second pixel circuit P2. The tenth active portion 210 is connected between the sixth active portion 26 and the seventh active portion 27, and the eleventh active portion 211 is connected between the sixth active portion 26 and the third active portion 23. The eighth active portion 28 can be used to form the first electrode of the fifth transistor T5. For example, in an embodiment of this disclosure, by connecting the eighth active portion 28 in two adjacent pixel circuits through the ninth active portion 29, the voltage difference at the first power supply terminal in the adjacent pixel circuits can be reduced.

[0122] For example, such as Figure 9 As shown, the first active layer 105 can be fabricated using amorphous silicon, polycrystalline silicon, etc. It should be noted that the source and drain regions mentioned above can be regions doped with n-type or p-type impurities. For example, in one example, the first active layer can be formed of polycrystalline silicon material, and correspondingly, the driving transistors T3, T4, T5, T6, and T7 can be p-type low-temperature polycrystalline silicon thin-film transistors.

[0123] For example, a metal layer is provided on the side of the first active layer 105 away from the substrate 101. The metal layer includes the scan signal line, reset control signal line, light emission control signal line, and the gates of the driving transistors T3, T4, T5, T6, and T7.

[0124] For example, the display substrate also includes a third conductive layer, for example, Figure 10 for Figure 5B The diagram shown is a partial structural schematic of the third conductive layer in the display substrate. Figure 5B and Figure 10 As shown, the third conductive layer 106 includes: a second gate line 1061, a light emission control signal line 1062, a second reset signal line 1063, and a second conductive portion 1064.

[0125] For example, combining Figure 5B , Figure 9 and Figure 10 The orthographic projection of the second gate line 1061 onto the substrate 101 extends along the second direction X and overlaps with the orthographic projection of the fourth active portion 24 onto the substrate 101. A portion of the structure of the second gate line 1061 is used to form the gate of the fourth transistor T4. The second gate line 1061 can be used to provide... Figure 3 The second gate drive signal terminal G2.

[0126] For example, combining Figure 5B , Figure 9 and Figure 10 The orthographic projection of the light-emitting control signal line 1062 onto the substrate 101 extends along the second direction X and overlaps with the orthographic projection of the sixth active portion 26 onto the substrate 101. A portion of the structure of this light-emitting control signal line 1062 is used to form the gate of the sixth transistor T6. This light-emitting control signal line 1062 can be used to provide... Figure 3 The light-emitting control signal terminal EM. For example, the orthogonal projection of the light-emitting control signal line 1062 on the substrate 101 can overlap with the orthogonal projection of the fifth active part 25 on the substrate 101, and part of the structure of the light-emitting control signal line 1062 is used to form the gate of the fifth transistor T5.

[0127] For example, combining Figure 5B , Figure 9 and Figure 10 The orthographic projection of the second reset signal line 1063 on the substrate 101 extends along the second direction X and overlaps with the orthographic projection of the seventh active portion 27 on the substrate 101. A portion of the structure of the second reset signal line 1063 is used to form the gate of the seventh transistor T7, and the second gate line 1061 in the current row pixel circuit 110 is multiplexed as the second reset signal line 1063 in the adjacent row pixel circuit 110. The second reset signal line 1063 can be used to provide... Figure 3 The second reset signal terminal Re2. For example, this setting can improve the integration of pixel circuits and reduce the layout area of ​​pixel circuits.

[0128] For example, combining Figure 5B and Figure 10 The orthographic projections of the second gate line 1061, the light-emitting control signal line 1062, and the second reset signal line 1063 on the substrate 101 all extend along the second direction X and are substantially parallel to each other. It should be noted that the orthographic projection of a structure on the substrate extending along a certain direction can be understood as the structure extending in a straight line or bending along that direction; the embodiments disclosed herein do not limit this.

[0129] For example, combining Figure 5B , Figure 9 and Figure 10 The orthographic projection of the second conductive portion 1064 on the substrate 101 overlaps with the orthographic projection of the third active portion 23 on the substrate 101. The second conductive portion 1064 forms the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor C. For example, in the same pixel circuit 110, the orthographic projection of the second conductive portion 1064 on the substrate 101 is located between the orthographic projection of the second gate line 1061 on the substrate 101 and the orthographic projection of the light emission control signal line 1062 on the substrate 101. The orthographic projection of the second reset signal line 1063 on the substrate 101 is located on the side of the orthographic projection of the light emission control signal line 1062 on the substrate 101 that is away from the orthographic projection of the second conductive portion 1064 on the substrate 101.

[0130] For example, the display substrate can use the third conductive layer 106 as a mask to perform a conductor treatment on the first active layer 105, that is, the area of ​​the first active layer 105 covered by the third conductive layer 106 can form the channel region of each transistor, and the area of ​​the first active layer 105 not covered by the third conductive layer 106 forms a conductor structure.

[0131] For example, the display substrate also includes a conductive film layer, for example, Figure 11 for Figure 5B The diagram shown is a partial structural schematic of the conductive film layer in the display substrate, combined with... Figure 5B and Figure 11 As shown, the conductive film layer 107 is located between the third conductive layer 106 and the second conductive layer 103. The conductive film layer 107 includes a first initial signal line 1071, a third reset signal line 1072, a third gate line 1073, and a first conductive portion 1074.

[0132] For example, such as Figure 11 As shown, the first initial signal line 1071 is used to provide Figure 3 The first initial signal terminal and the third reset signal line 1072 are used to provide Figure 3 The first reset signal terminal in the middle, the third gate line 1073 is used to provide Figure 3 The first gate drive signal terminal G1. The orthographic projection of the first initial signal line 1071 on the substrate 101, the orthographic projection of the third reset signal line 1072 on the substrate 101, and the orthographic projection of the third gate line 1073 on the substrate 101 can all extend along the second direction X.

[0133] For example, combining Figure 3 and Figure 11 The orthographic projection of the first initial signal line 1071 onto the substrate 101 is onto the first reset signal line (described in the text). Figure 3(As mentioned at the time) The side of the orthogonal projection of the second conductive part 1064 on the substrate 101 that is away from the orthogonal projection of the second conductive part 1064 on the substrate 101.

[0134] For example, combining Figure 3 , Figure 5B and Figure 11 The third reset signal line 1072 is connected to the first reset signal line through a via. The orthographic projection of the third reset signal line 1072 on the substrate 101 overlaps with the orthographic projection of the first active portion (included in the subsequent fourth conductive layer) on the substrate 101. A portion of the structure of the third reset signal line 1072 is used to form the bottom gate of the first transistor T1. The orthographic projection of the third gate line 1073 on the substrate 101 overlaps with the orthographic projection of the second active portion (included in the subsequent fourth conductive layer) on the substrate 101. A portion of the structure of the third gate line 1073 is used to form the bottom gate of the second transistor T2.

[0135] For example, combining Figure 3 , Figure 5B and Figure 11 The first conductive portion 1074 includes a main body portion 1074a, and the storage capacitor C also includes a second electrode plate Cst2 opposite to the first electrode plate Cst1. The main body portion 1074a corresponds to two second electrode plates Cst2. For example, the first conductive portion 1074 also includes a bridging portion 1074b, which connects two adjacent main body portions 1074a in the second direction X, that is, connects two adjacent second electrode plates Cst2. The first conductive portion 1074 also includes a notch 1074c between the two second electrode plates Cst2.

[0136] For example, combining Figure 3 , Figure 5B and Figure 11 The orthographic projection of the first conductive layer 102 on the substrate 101 does not overlap with the orthographic projection of the notch 1074c on the substrate 101, and the orthographic projection of the second conductive layer 103 on the substrate 101 does not overlap with the orthographic projection of the notch 1074c on the substrate 101. This ensures that the notch 1074c is not blocked by the first conductive layer 102 and the second conductive layer 103, thereby improving pixel transmittance. It should also be noted that the notch 1074c is not blocked by any other film layer with a light-shielding function.

[0137] For example, combining Figure 3 , Figure 5B and Figure 11An opening 1074d is also formed on the first conductive portion 1074. The orthographic projection of the via connecting the gate of the driving transistor T3 and the first connection structure 1021 on the substrate 101 is within the orthographic projection of the opening 1074d on the substrate 101, so that the conductive structure in the via is insulated from the first conductive portion 1074.

[0138] For example, the display substrate further includes a second active layer, for example, Figure 12 for Figure 5B The diagram shown is a partial structural schematic of the second active layer in the display substrate, combined with... Figure 5B and Figure 12 As shown, the second active layer 108 is located between the first active layer 105 and the second conductive layer 103. The second active layer 108 may include a first active portion 311, a second active portion 312, and a twelfth active portion 313 connected to each other. The first active portion 311 forms the channel region of the first transistor T1; the second active portion 312 forms the channel region of the second transistor T2; the twelfth active portion 313 is connected to the end of the second active portion 312 away from the first active portion 311, and the first semiconductor layer includes the second active layer 108.

[0139] For example, in one example, such as Figure 12 As shown, the second active layer 108 can be formed of indium gallium zinc oxide, and correspondingly, the first transistor T1 and the second transistor T2 can be N-type metal oxide thin film transistors.

[0140] For example, the first semiconductor layer forming the channel region of the first transistor T1 and the second transistor T2 in the pixel circuit 110 can be located on the side away from the substrate 101 of the active semiconductor pattern layer of the driving transistor T3. This first semiconductor layer may include an oxide semiconductor material. For example, when the active layer in the first transistor T1 and the second transistor T2 of the pixel circuit is made of oxide semiconductor, since the transistors using oxide semiconductor have good hysteresis characteristics, low leakage current, and low mobility, the transistors using oxide semiconductor can replace the low-temperature polysilicon material in the transistor to form a low-temperature polysilicon-oxide (LTPO) pixel circuit, achieving low leakage current and improving the stability of the transistor's gate voltage.

[0141] Of course, the embodiments of this disclosure are not limited to the second active layer of the pixel circuit being... Figure 12In the structure shown, in other examples, the first semiconductor layer of the channel region of the first transistor T1 and the second transistor T2 may also be located on the same layer as the semiconductor layer of the channel region of the other transistors. That is, the first active layer may also include the channel regions of the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0142] For example, combining Figure 5B , Figure 11 and Figure 12 The orthogonal projection of the third gate line 1073 on the substrate 101 can cover the orthogonal projection of the second active portion 312 on the substrate 101, and a portion of the structure of the third gate line 1073 can be used to form the bottom gate of the second transistor T2. The orthogonal projection of the third reset signal line 1072 on the substrate 101 can cover the orthogonal projection of the first active portion 311 on the substrate 101, and a portion of the structure of the third reset signal line 1072 can be used to form the bottom gate of the first transistor T1.

[0143] For example, the display substrate also includes a fourth conductive layer, for example, Figure 13 for Figure 5B The diagram shown is a partial structural schematic of the fourth conductive layer in the display substrate. Figure 5B and Figure 13 As shown, the fourth conductive layer 109 is located between the second active layer 108 and the second conductive layer 103. The fourth conductive layer 109 includes a first reset signal line 1091 and a first gate line 1092.

[0144] For example, combining Figure 3 , Figure 5B , Figure 12 and Figure 13 The orthographic projection of the first reset signal line 1091 onto the substrate 101 and the orthographic projection of the first gate line 1092 onto the substrate 101 can both extend along the second direction X. The first reset signal line 1091 can be used to provide Figure 3 The first reset signal terminal in the display substrate has its orthographic projection on the substrate 101 overlapping with the orthographic projection of the first active portion 311 on the substrate 101. A portion of the structure of the first reset signal line 1091 is configured to form the top gate of the first transistor T1. Simultaneously, the first reset signal line 1091 can be connected to the third reset signal 1072 via a via located in the edge trace area of ​​the display substrate.

[0145] For example, combining Figure 3 , Figure 5B , Figure 11 , Figure 12 and Figure 13 The first gate line 1092 can be used to provide Figure 3The first gate drive signal terminal in the first gate line 1092 can cover the orthogonal projection of the second active part 312 on the substrate 101. Part of the structure of the first gate line 1092 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 1092 can be connected to the third gate line 1073 through a via located in the edge wiring area of ​​the display substrate.

[0146] For example, combining Figure 5B , Figure 10 and Figure 13 In the same pixel circuit, the orthographic projection of the first gate line 1092 on the substrate 101 is between the orthographic projection of the second conductive part 1064 on the substrate 101 and the orthographic projection of the second gate line 1061 on the substrate 101, and the orthographic projection of the first reset signal line 1091 on the substrate 101 is on the side away from the orthographic projection of the second conductive part 1064 on the substrate 101 of the second gate line 1061 on the substrate 101.

[0147] For example, combining Figure 5B , Figure 10 and Figure 13 In the same pixel circuit, the orthographic projection of the second conductive portion 1064 on the substrate 101 can be located between the orthographic projection of the first gate line 1092 on the substrate 101 and the orthographic projection of the light emission control signal line 1062 on the substrate 101. The orthographic projection of the first reset signal line 1091 on the substrate 101 can be located on the side of the first gate line 1092 on the substrate 101 away from the orthographic projection of the second conductive portion 1064 on the substrate 101.

[0148] For example, combining Figure 5B , Figure 10 and Figure 13 In the same pixel circuit, the orthographic projection of the second gate line 1061 on the substrate 101 can be located between the orthographic projection of the first gate line 1092 on the substrate 101 and the orthographic projection of the first reset signal line 1091 on the substrate 101. The orthographic projection of the second reset signal line 1063 on the substrate 101 can be located on the side away from the orthographic projection of the second conductive portion 1064 on the substrate 101 of the orthographic projection of the light emission control signal line 1062 on the substrate 101.

[0149] For example, combining Figure 3 , Figure 5B , Figure 7 and Figure 11The first conductive layer 102 includes a plurality of third connection structures 1027, which are correspondingly disposed one-to-one with the plurality of repeating units. Each third connection structure 1027 is connected to the ninth active portion 29 of the first active layer 105 via a first via connection portion H1, and is connected to the bridging portion 1074b (a part of the first conductive portion 1074) of the conductive film layer 107 via a second via connection portion H2, thereby connecting the first electrode of the fifth transistor T5 and the second electrode plate Cst2 of the capacitor C. That is, the third connection structure 1027 includes a first via connection portion H1 for connecting the ninth active portion 29. It should be noted that only some vias are labeled in the embodiments of this disclosure.

[0150] For example, combined with the diagram Figure 5B , Figure 7 and Figure 8 The sixth connection structure 1028 included in the first conductive layer 102 and the first electrode adapter wire 1032 included in the second conductive layer 103 are connected through the third through-hole connection portion H3.

[0151] For example, combining Figure 3 , Figure 5B , Figure 7 , Figure 8 , Figure 9 and Figure 12 The third connection part 1026 is connected to the eleventh active part 211 through the fourth via connection part H4, and the third connection part 1026 is connected to the twelfth active part 313 through the fifth via connection part H5, so as to connect the second terminal of the second transistor T2, the first terminal of the sixth transistor T6 and the second terminal of the driving transistor T3.

[0152] For example, combining Figure 3 , Figure 5B , Figure 7 , Figure 8 and Figure 12 The first connection structure 1021 connects the portion of the second active layer 108 between the first active portion 311 and the second active portion 312 through the sixth via connection portion H6. The first connection structure 1021 connects the second conductive portion 1064 through the seventh via connection portion H7 to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3.

[0153] For example, combining Figure 5B , Figure 10 and Figure 11 An opening 1074d is formed on the first conductive portion 1074. The orthographic projection of the seventh via connection portion H7, which connects the second conductive portion 1064 and the first connection structure 1021, on the substrate 101 is located within the orthographic projection of the opening 1074d on the substrate 101, so that the conductive structure in the seventh via connection portion H7 is insulated from the first conductive portion 1074.

[0154] For example, combining Figure 3 , Figure 5B , Figure 7 , Figure 8 , Figure 11 and Figure 12 The first connection portion 1024 can be connected to the portion of the second active layer of the first active portion 311 away from the second active portion 312 via the eighth via connection portion H8. The first connection portion 1024 can be connected to the first initial signal line 1071 via the ninth via connection portion H9 to connect the second electrode of the first transistor T1 and the first initial signal terminal. For example, in two adjacent repeating units in the second direction X, the two adjacent pixel circuits can share the same first connection portion 1024.

[0155] For example, combining Figure 3 , Figure 5B , Figure 7 and Figure 9 The second connection portion 1025 can be connected to the portion of the first active layer 105 located on the side of the fourth active portion 24 away from the third active portion 23 through the tenth via connection portion H10, so as to connect the first electrode of the fourth transistor T4.

[0156] For example, combining Figure 3 , Figure 5B , Figure 7 , Figure 8 and Figure 9 The second initial signal line 1022 can be used to provide Figure 3 The second initial signal terminal in the first active layer 105, the second initial signal line 1022 can be connected to the portion of the first active layer 105 located on the side away from the sixth active portion 26 of the seventh active portion 27 through the eleventh via connection portion H11, so as to connect the second pole of the seventh transistor T7 and the second initial signal terminal Vinit2.

[0157] For example, the display substrate also includes a plurality of sub-pixels, each sub-pixel including the pixel circuit 110 and light-emitting element as described in any of the examples above. Figure 14 This is a schematic diagram of a partial pixel arrangement structure on a display substrate according to an embodiment of the present disclosure. Figure 15A for Figure 5B A layout of the pixel circuit and the first electrode stack of the light-emitting element in a [structure / process]. Figure 15B for Figure 5B Another layout of the pixel circuit and the first electrode stack of the light-emitting element. Figure 15B Compared to Figure 15A An additional light-shielding layer has been added; all other structural details remain the same. For example, as... Figure 14 and Figure 15BAs shown, the plurality of sub-pixels 40 includes a plurality of first sub-pixels 401, a plurality of second sub-pixels 402, and a plurality of third sub-pixels 403. For example, one of the first sub-pixels 401 and the third sub-pixels 403 is a red sub-pixel that emits red light, the other of the first sub-pixels 401 and the third sub-pixels 403 is a blue sub-pixel that emits blue light, and the second sub-pixels 402 is a green sub-pixel that emits green light.

[0158] For example, in one example, the first sub-pixel 401 is a red sub-pixel, the third sub-pixel 403 is a blue sub-pixel, and the second sub-pixel 402 is a green sub-pixel. The area of ​​the light-emitting region of the blue sub-pixel is larger than the area of ​​the light-emitting region of the red sub-pixel, and the area of ​​the light-emitting region of the red sub-pixel is larger than the area of ​​the light-emitting region of the green sub-pixel.

[0159] For example, the names of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be interchanged. For instance, the first sub-pixel can be a green sub-pixel, the second sub-pixel can be a blue sub-pixel, and the third sub-pixel can be a red sub-pixel; or, the first sub-pixel can be a blue sub-pixel, the second sub-pixel can be a red sub-pixel, and the third sub-pixel can be a green sub-pixel, etc. The embodiments disclosed herein do not limit this.

[0160] For example, such as Figure 14 As shown, multiple first sub-pixels 401 and multiple third sub-pixels 403 are alternately arranged along the second direction X and the first direction Y to form multiple first pixel rows R1 and multiple first pixel columns C1. Multiple second sub-pixels 402 are arrayed along the second direction X and the first direction Y to form multiple second pixel rows R2 and multiple second pixel columns C2. The multiple first pixel rows R1 and multiple second pixel rows R2 are alternately arranged along the first direction Y and staggered from each other in the second direction X. The multiple first pixel columns C1 and multiple second pixel columns C2 are alternately arranged along the second direction X and staggered from each other in the first direction Y. The second direction X and the first direction Y intersect. For example, the second direction X and the first direction Y can be perpendicular. For example, the second direction X and the first direction Y can be interchanged.

[0161] For example, such as Figure 14 As shown, a second pixel row R2 includes a plurality of second sub-pixel pairs 4020 arranged along a second direction X. Two second sub-pixels 402 in a second sub-pixel pair 4020 are respectively a first pixel block 4020a and a second pixel block 4020b, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, in a second pixel column C2, the first pixel block 4020a and the second pixel block 4020b are alternately arranged along a first direction Y.

[0162] For example, such as Figure 14As shown, at least two second pixel rows R2 include a plurality of second sub-pixel pairs 4020 arranged along a second direction X. Two second sub-pixels 402 in each of the at least two second sub-pixel pairs 4020 are respectively a first pixel block 4020a and a second pixel block 4020b, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, the first pixel block 4020a and the second pixel block 4020b in at least two second pixel columns C2 are alternately arranged along a first direction Y.

[0163] For example, such as Figure 14 As shown, each second pixel row R2 includes a plurality of second sub-pixel pairs 4020 arranged along the second direction X. The two second sub-pixels 402 in each second sub-pixel pair 4020 are respectively a first pixel block 4020a and a second pixel block 4020b, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, the first pixel block 4020a and the second pixel block 4020b in each second pixel column C2 are alternately arranged along the first direction Y.

[0164] For example, such as Figure 14 As shown, the plurality of sub-pixels 40 include a plurality of minimum repeating units A. Each minimum repeating unit A includes a first sub-pixel 401, a first pixel block 4020a, a second pixel block 4020b, and a third sub-pixel 403. For example, at least two minimum repeating units A include a first sub-pixel 401, a first pixel block 4020a, a second pixel block 4020b, and a third sub-pixel 403. For example, each minimum repeating unit A includes a first sub-pixel 401, a first pixel block 4020a, a second pixel block 4020b, and a third sub-pixel 403. For example, each minimum repeating unit A includes two rows and four columns of sub-pixels 40.

[0165] For example, such as Figure 14 As shown, in a minimum repeating unit A, the first pixel block 4020a and the first sub-pixel 401 constitute the first pixel unit A1, and the second pixel block 4020b and the third sub-pixel 403 constitute the second pixel unit A2. For example, in at least two minimum repeating units A, the first pixel block 4020a and the first sub-pixel 401 constitute the first pixel unit A1, and the second pixel block 4020b and the third sub-pixel 403 constitute the second pixel unit A2. For example, in each minimum repeating unit A, the first pixel block 4020a and the first sub-pixel 401 constitute the first pixel unit A1, and the second pixel block 4020b and the third sub-pixel 403 constitute the second pixel unit A2.

[0166] The first pixel unit A1 and the second pixel unit A2 mentioned above are not pixels in the strict sense, that is, a pixel defined by a complete first sub-pixel, a second sub-pixel, and a third sub-pixel. The minimum repeating unit here refers to the minimum repeating unit that can be included in the pixel arrangement structure.

[0167] For example, Figure 16 This is a schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure, as shown below. Figures 14-16 As shown, the display substrate 100 includes a substrate 101 and a plurality of sub-pixels 40 located on the substrate 101. At least some of the sub-pixels 40 include light-emitting elements 120 and pixel circuits 110. The light-emitting element 120 includes a light-emitting functional layer 122 and a first electrode 121 and a second electrode 123 located on both sides of the light-emitting functional layer 122 along a direction perpendicular to the substrate 101. The first electrode 121 is located between the light-emitting functional layer 122 and the substrate 101.

[0168] For example, such as Figure 16 As shown, the display substrate 100 also includes a pixel defining pattern 50, with the direction perpendicular to the main surface of the substrate 101 as the third direction Z. The third direction Z is the direction perpendicular to the plane containing the first direction Y and the second direction X. The pixel defining pattern 50 is located on the side of the first electrode 121 of the light-emitting element 120 away from the substrate 101, and the pixel defining pattern 50 includes a plurality of pixel openings 51 and a defining portion 52 surrounding the plurality of pixel openings 51. The plurality of light-emitting elements 120 are at least partially located in the plurality of pixel openings 51. Figure 16 The schematic diagram shows that a structural layer 011 is provided on the side of the first electrode 121 of the light-emitting element 120 away from the second electrode 123. The structural layer 011 may include a substrate 101, a layer containing the active semiconductor pattern, a layer containing the gate line, a layer containing the data line, and multiple insulating layers.

[0169] For example, the limiting portion 52 is a structure that defines the pixel opening 51. For example, the material of the limiting portion 52 may include polyimide, acrylic, or polyethylene terephthalate, etc.

[0170] For example, the pixel opening 51 of the pixel defining pattern 50 is configured to define the light-emitting area 124 of the light-emitting element 120. For example, the light-emitting elements 120 of the plurality of sub-pixels 40 may be provided in a one-to-one correspondence with the plurality of pixel openings 51. For example, the light-emitting element 120 may include a portion located in the pixel opening 51, and a portion that overlaps with the defining portion 52 in a direction perpendicular to the substrate 101.

[0171] For example, the opening 51 of the pixel defining pattern 50 is configured to expose the first electrode 121 of the light-emitting element 120, and the exposed first electrode 121 is at least partially in contact with the light-emitting functional layer 122 in the light-emitting element 120. For example, at least a portion of the first electrode 121 is located between the defining portion 52 and the substrate 101. For example, when the light-emitting functional layer 122 is located in the pixel opening 51 of the pixel defining pattern 50, the first electrode 121 and the second electrode 123 located on both sides of the light-emitting functional layer 122 can drive the light-emitting functional layer 122 in the pixel opening 51 of the pixel defining pattern 50 to emit light. For example, the light-emitting area 124 can refer to the area of ​​effective light emission of the light-emitting element 120, and the shape of the light-emitting area 124 refers to a two-dimensional shape. For example, the shape of the light-emitting area 124 can be the same as the shape of the pixel opening 51 of the pixel defining pattern 50. For example, the pixel opening 51 of the pixel defining pattern 50 can be a shape with a smaller size on the side closer to the substrate 101 and a larger size on the side farther from the substrate 101. For example, the shape of the light-emitting area 124 can be approximately the same in size and shape as the pixel opening 51 of the pixel definition pattern 50 on the side near the substrate 101.

[0172] For example, the first electrode 121 can be an anode, and the second electrode 123 can be a cathode. For example, the cathode can be formed of a material with high conductivity and low work function; for example, the cathode can be made of a metallic material. For example, the anode can be formed of a conductive material with a high work function.

[0173] For example, with the arrow pointing upwards in the first direction Y and the arrow pointing to the right in the second direction X, the first pixel block 4020a in the first pixel unit A1 is located to the lower right of the first sub-pixel 401, and the second pixel block 4020b in the second pixel unit A2 is located to the lower right of the third sub-pixel 403. In the first pixel unit and the second pixel unit of the display substrate provided in this embodiment, the pixel space and design are optimized by changing the first sub-pixel and the third sub-pixel to borrow second sub-pixels at different positions, thereby improving the flatness of the first electrode of the light-emitting element and optimizing the pixel space structure, and thus reducing the bottom bezel.

[0174] For example, combining Figures 14-16As shown, the first sub-pixel 401 can form a first pixel unit with the second sub-pixel 402 located to its upper right or to its lower right; similarly, the third sub-pixel 403 can form a second pixel unit with the second sub-pixel 402 located to its upper right or to its lower right. In this embodiment, the fifth transistor T5 is located in the light-emitting area in the first sub-pixel 401. By forming a first pixel unit with the second sub-pixel 402 located to its upper right, the first sub-pixel 401 can facilitate pixel circuit design, reduce the probability of affecting pixel flatness by changing the shape of the pad that plays a planarization role in the second conductive layer, and help prevent color shift. In addition, it can also reduce the impact on the capacitance of the node corresponding to the first electrode of the light-emitting element, such as preventing the impact on the image quality of low grayscale. If the capacitance here is large, the capacitance of the node corresponding to the first electrode of the light-emitting element needs to be fully charged before the low grayscale, resulting in a decrease in the charging voltage of the node at the low grayscale. This will make the pixel lighting time longer (response time), thus affecting the image quality. Similarly, in the third sub-pixel 403, the fifth transistor T5 is located in the light-emitting area. This third sub-pixel 403 forms a second pixel unit with the second sub-pixel 402 located to its upper right, which facilitates pixel circuit design.

[0175] For example, such as Figure 5A Figure 5B As shown in Figure 15, along the second direction X, two data lines 1031 are provided on each side of the first sub-pixel 401. For example, two data lines 1031 are provided between adjacent first sub-pixels 401 and third sub-pixels 403 arranged in the second direction X.

[0176] For example, Figure 14The layer structure shown can also be a first electrode layer 501 included in the display substrate. The first electrode layer 501 is located on the side of the second conductive layer 103 away from the substrate 101. The first electrode layer 501 includes a plurality of electrode portions 502. Each electrode portion 502 includes a body portion 5021 and an extension portion 5022 connected to each other. The orthographic projection of the extension portion 5022 on the substrate 101 at least partially overlaps with the orthographic projection of the first electrode adapter line 1032 on the substrate 101. Each electrode portion 502 corresponds to one of the first sub-pixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third sub-pixel 403. An additional portion 5022 is provided on the electrode portion 502 to increase the overlap area between the electrode portion 502 and the second conductive layer 103, thereby increasing the self-capacitance of the electrode portion of the light-emitting unit and extending the charging time before the light-emitting unit emits light. In the embodiments of this disclosure, the period when the current output of the driving transistor T3 is unstable can be completely or at least partially located in the charging period of the light-emitting unit. That is, this setting can reduce the duration of the light-emitting unit emitting light during the period when the current output of the driving transistor T3 is unstable, thereby improving the flicker problem when the display substrate is working.

[0177] For example, such as Figure 14 As shown, the plurality of electrode portions 502 include a first electrode portion 502a, a second electrode portion 502b, and a third electrode portion 502c of three different colors. The first electrode portion 502a corresponds to the first sub-pixel 401, the second electrode portion 502b corresponds to either the first pixel block 4020a or the second pixel block 4020b, and the third electrode portion 502c corresponds to the third sub-pixel 403.

[0178] For example, combining Figure 14 and Figure 15B In the first direction Y, the first electrode portion 502a and the third electrode portion 502c cover the block portion 1033a of the first power signal line 1033, and the second electrode portion 502b covers part of the data line 1031 and part of the first electrode adapter line 1032. The orthographic projection of the second electrode portion 502b on the substrate 101 is defined between the orthographic projections of two adjacent first electrode adapter lines 1032 on the substrate 101. Therefore, the orthographic projection of the second electrode portion 502b on the substrate 101 and the orthographic projection of the first power signal line 1033 on the substrate 101 do not overlap. The overlapping area of ​​the orthographic projection of the first electrode portion 502a on the substrate 101 and the orthographic projection of the first power signal line 1033 on the substrate 101 is greater than the overlapping area of ​​the orthographic projection of the second electrode portion 502b on the substrate 101 and the orthographic projection of the first power signal line 1033 on the substrate 101, and is also greater than the overlapping area of ​​the orthographic projection of the third electrode portion 502c on the substrate 101 and the orthographic projection of the first power signal line 1033 on the substrate 101.

[0179] For example, combining Figure 14 and Figure 15B The overlapping area of ​​the orthographic projection of the third electrode portion 502c on the substrate 101 and the orthographic projection of the first power signal line 1033 on the substrate 101 is also greater than the overlapping area of ​​the orthographic projection of the second electrode portion 502b on the substrate 101 and the orthographic projection of the first power signal line 1033 on the substrate 101.

[0180] For example, combining Figure 14 and Figure 15B The orthographic projections of the additional portions 5022 of each electrode portion 502 on the substrate 101 and the orthographic projections of the second conductive layer 103 on the substrate 101 at least partially overlap, and are electrically connected to the second conductive layer 103 through corresponding vias. For example, the additional portion 5022a of the first electrode portion 502a is connected to the first electrode adapter line 1032 through the first via V1; the additional portion 5022b of the second electrode portion 502b is connected to the first electrode adapter line 1032 through the second via V2; and the additional portion 5022c of the third electrode portion 502c is connected to the first electrode adapter line 1032 through the third via V3.

[0181] For example, combining Figure 14 and Figure 15B The first electrode portion 502a corresponds to the blue sub-pixel that emits blue light, the second electrode portion 502b corresponds to the green sub-pixel that emits green light, and the third electrode portion 502c corresponds to the red sub-pixel that emits red light.

[0182] For example, the display substrate also includes a light-shielding layer, for example, Figure 17 for Figure 5B and Figure 15B The diagram shows a partial structural schematic of the light-shielding layer in the display substrate, as shown below. Figure 17 As shown, the light-shielding layer 111 may include a plurality of light-shielding portions 111a distributed in the second direction X and the first direction Y. Adjacent light-shielding portions 111a in the second direction X are interconnected, and the connecting line connecting adjacent light-shielding portions 111a is on the same straight line. The extension direction of the connecting line is parallel or approximately parallel to the second direction X. Two adjacent light-shielding portions 111a in the first direction Y are also interconnected. The light-shielding layer 111 can be a conductive structure; for example, the light-shielding layer 111 can be a light-shielding metal layer.

[0183] For example, combining Figure 3 , Figure 5B , Figure 15B and Figure 17 As shown, the light-shielding layer 111 can be connected to a stable power supply terminal. For example, the light-shielding layer 111 can be connected to... Figure 3The first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc., in the light-shielding layer 111 can play a voltage stabilizing role for the second conductive part 1064, thereby reducing the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting stage.

[0184] For example, Figure 18 This is a layout of the stacked layer of the light-shielding layer and the first active layer provided in an embodiment of the present disclosure, such as... Figure 18 As shown, the orthogonal projection of the light-shielding layer 111 on the substrate 101 can cover the orthogonal projection of the third active part 23 on the substrate 101, and the light-shielding layer 111 can reduce the influence of light on the characteristics of the driving transistor T3.

[0185] For example, Figure 19 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present disclosure, as shown below. Figure 19 As shown, the pixel circuit 610 includes: a first transistor T1, a second transistor T2, a third transistor (driving transistor) T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor C. That is, the pixel circuit 610 may include eight transistors (first transistor T1 to eighth transistor T8), one storage capacitor C, and multiple signal lines (data signal line Data, first scan signal line Gate, second scan signal line GateN, reset control signal line Reset, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, second power supply line VSS, and light emission control signal line EM).

[0186] For example, such as Figure 19As shown, the gate of the first transistor T1 is connected to the reset control signal line Reset, the first terminal of the first transistor T1 is connected to the first initial signal line Vinit1, and the second terminal of the first transistor T1 is connected to node N5. The gate of the second transistor T2 is connected to the first scan signal line Gate, the first terminal of the second transistor T2 is connected to node N5, and the second terminal of the second transistor T2 is connected to node N3. The gate of the driving transistor T3 is connected to node N1, the first terminal of the driving transistor T3 is connected to node N2, and the second terminal of the driving transistor T3 is connected to node N3. The gate of the fourth transistor T4 is connected to the first scan signal line Gate, the first terminal of the fourth transistor T4 is connected to the data signal line Data, and the second terminal of the fourth transistor T4 is connected to node N2. The gate of the fifth transistor T5 is connected to the light emission control signal line EM, the first terminal of the fifth transistor T5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is connected to node N2. The gate of the sixth transistor T6 is connected to the light-emitting control signal line EM, the first terminal of the sixth transistor T6 is connected to node N3, and the second terminal of the sixth transistor T6 is connected to node N4 (i.e., the first terminal of the light-emitting element). The gate of the seventh transistor T7 is connected to the first scan signal line Gate or the reset control signal line Reset, the first terminal of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second terminal of the seventh transistor T7 is connected to node N4. The gate of the eighth transistor T8 is connected to the second scan signal line GateN, the first terminal of the eighth transistor T8 is connected to node N5, and the second terminal of the eighth transistor T8 is connected to node N1. The first terminal of the storage capacitor C is connected to the first power supply line VDD, and the second terminal of the storage capacitor C is connected to node N1.

[0187] Specifically, the gate of the first transistor T1 is connected to the reset control signal line, the first terminal of the first transistor T1 is connected to the first initial signal line, and the second terminal of the first transistor T1 is connected to the first terminal of the eighth transistor T8 and the first terminal of the second transistor T2; the gate of the second transistor T2 is connected to the first scan signal line, and the second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3 and the first terminal of the sixth transistor T6; the gate of the driving transistor T3 is connected to the second terminal of the eighth transistor T8 and the first plate Cst1 of the storage capacitor C, the first terminal of the driving transistor T3 is connected to the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5, and the second terminal of the driving transistor T3 is connected to the second terminal of the second transistor T2 and the first terminal of the sixth transistor T6; the gate of the fourth transistor T4 is connected to the first scan signal line, the first terminal of the fourth transistor T4 is connected to the data line Data, and the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3 and the second terminal of the fifth transistor T5; the gate of the fifth transistor T5 is connected to the first light emission control signal line, and the first terminal of the fifth transistor is connected to the first power supply signal line and the second plate Cst1 of the storage capacitor C. The second terminal of the fifth transistor T5 is connected to the second terminal of the fourth transistor T4 and the first terminal of the driving transistor T3; the gate of the sixth transistor T6 is connected to the first light-emitting control signal line, the first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T3 and the second terminal of the second transistor T2, the second terminal of the sixth transistor T6 is connected to the first terminal of the light-emitting element and the second terminal of the seventh transistor T7; the gate of the seventh transistor T7 is connected to the first scan signal line or the reset control signal line, the first terminal of the seventh transistor T7 is connected to the second initial signal line, and the second terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6 and the first terminal of the light-emitting element; the gate of the eighth transistor T8 is connected to the second scan signal line, the first terminal of the eighth transistor T8 is connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2, the second terminal of the eighth transistor T8 is connected to the gate of the driving transistor T3 and the first terminal Cst1 of the storage capacitor C; the first terminal Cst1 of the storage capacitor C is connected to the gate of the driving transistor T3 and the second terminal of the eighth transistor T8, and the second terminal Cst2 of the storage capacitor C is connected to the first power supply signal line.

[0188] For example, in some exemplary embodiments, the first transistor T1 to the seventh transistor T7 may be N-type thin-film transistors and the eighth transistor T8 may be P-type thin-film transistors; or, the first transistor T1 to the seventh transistor T7 may be P-type thin-film transistors and the eighth transistor T8 may be N-type thin-film transistors.

[0189] For example, in some exemplary embodiments, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon (LTPS) thin film transistor (TFT), and the eighth transistor T8 may be an indium gallium zinc oxide (IGZO) thin film transistor.

[0190] For example, indium gallium zinc oxide (IZO) thin-film transistors (TFTs) generate less leakage current compared to low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS). Therefore, using an IZO TFT as the eighth transistor T8 can significantly reduce leakage current, thereby improving the low-frequency, low-brightness flicker problem of the display substrate. The first transistor T1 and the second transistor T2 do not need to be IZO TFTs. Since LTPS thin-film transistors are generally smaller than IZO TFTs, the pixel circuit in this embodiment occupies less space, which is beneficial for improving the resolution of the subsequently formed display panel.

[0191] For example, Figure 19 The pixel circuit shown combines the excellent switching characteristics of LTPS-TFT with the low leakage characteristics of Oxide-TFT, enabling low-frequency driving (1Hz~60Hz) and significantly reducing the power consumption of the display substrate.

[0192] For example, the display substrate also includes a light-emitting element EL. The second electrode of the light-emitting element EL is connected to a second power line VSS. The signal of the second power line VSS is a continuously low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The signal of the first scan signal line Gate is the scan signal in the pixel circuit of this display row, and the signal of the reset control signal line Reset is the scan signal in the pixel circuit of the previous display row. That is, for the nth display row, the first scan signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n-1). The signal of the reset control signal line Reset of this display row and the signal of the first scan signal line Gate in the pixel circuit of the previous display row can be the same signal to reduce the number of signal lines on the display substrate and achieve a narrow bezel on the display substrate.

[0193] For example, in some exemplary embodiments, the first scan signal line Gate, the second scan signal line GateN, the reset control signal line Reset, the light emission control signal line EM, the first initial signal line Vinit1, and the second initial signal line Vinit2 all extend in the horizontal direction, while the second power line VSS, the first power line VDD, and the data signal line Data all extend in the vertical direction.

[0194] For example, in some exemplary embodiments, the light-emitting element 620 may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0195] For example, Figure 20 for Figure 19 Timing diagrams of each node in a driving method for a mid-pixel circuit. The following is a breakdown of the timing diagrams. Figure 20 The operation of the example pixel circuit illustrates an exemplary embodiment of this disclosure. Figure 19 The pixel circuit in the image includes eight transistors (transistor T1 to transistor T8) and one storage capacitor C. The example is given with transistors T1 to T7 being P-type transistors, transistor T8 being an N-type transistor, and the gate of transistor T7 being connected to the first scan signal line Gate.

[0196] For example, combining Figure 19 and Figure 20 The operation of this pixel circuit can include:

[0197] In the first stage, t1, called the reset stage, the signals of the first scan signal line Gate, the reset control signal line Reset, the second scan signal line GateN, and the light-emitting control signal line EM are all high-level signals, while the signal of the reset control signal line Reset is low-level. The high-level signal of the light-emitting control signal line EM turns off the fifth transistor T5 and the sixth transistor T6, the high-level signal of the second scan signal line GateN turns on the eighth transistor T8, and the low-level signal of the reset control signal line Reset turns on the first transistor T1. Therefore, the voltage of node N1 is reset to the first initial voltage Vinit1 provided by the first initial signal line Vinit1. Then, the voltage of the reset control signal line Reset goes high, and the first transistor T1 turns off. Since the fifth transistor T5 and the sixth transistor T6 are off, the light-emitting element EL does not emit light in this stage.

[0198] In the second stage, t2, known as the data writing stage, the first scan signal line Gate is at a low level. Transistors T4, T2, and T7 are turned on, and the data signal line Data outputs a data voltage. The voltage at node N4 is reset to the second initial voltage Vinit2 provided by the second initial signal line Vinit2, completing initialization. During this stage, since node N1 is at a low level, transistor T3 is turned on. The turn-on of transistors T4 and T2 allows the data voltage output from the data signal line Data to be supplied to node N1 via the turned-on transistor T4, node N2, the turned-on transistor T3, node N3, the turned-on transistor T2, node N5, and the eighth transistor T8. The sum of the data voltage output from the data signal line Data and the threshold voltage of transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of storage capacitor C (node ​​N1) is Vdata + Vth, where Vdata is the data voltage output from the data signal line Data, and Vth is the threshold voltage of the driving transistor T3. When the light-emitting control signal line EM is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned off, ensuring that the light-emitting element EL does not emit light.

[0199] The third stage, t3, is called the light-emitting stage. During this stage, the first scan signal line (Gate) and the reset control signal line (Reset) are both high-level signals, while the light-emitting control signal line (EM) and the second scan signal line (GateN) are both low-level signals. The high-level signal on the reset control signal line (Reset) turns off the seventh transistor (T7), and the low-level signal on the light-emitting control signal line (EM) turns on the fifth transistor (T5) and the sixth transistor (T6). The power supply voltage output from the first power supply line (VDD) provides a driving voltage to the first terminal (node ​​N4) of the light-emitting element (EL) through the conducting fifth transistor (T5), third transistor (T3), and sixth transistor (T6), driving the light-emitting element (EL) to emit light.

[0200] For example, in Figure 19 In the pixel circuit shown, by initializing node N4 to the signal of the second initial signal line Vinit2 and node N5 to the signal of the first initial signal line Vinit1, the reset voltage of the light-emitting element EL and the reset voltage of node N1 can be adjusted respectively, thereby achieving better display effect and improving problems such as low-frequency flicker.

[0201] It should be noted that, in the embodiments of this disclosure, each pixel circuit can, in addition to being able to... Figure 19 In addition to the 8T1C (i.e., 8 transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 7T2C, 6T1C, 6T2C, 7T1C, or 9T2C structures. This disclosure does not limit the specific number of transistors in the embodiments.

[0202] For example, the display substrate includes a plurality of repeating units distributed along intersecting first and second directions. Each repeating unit includes two pixel circuits, which include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are arranged in a substantially mirror-symmetrical manner. The pixel circuit described below is described using one of the first pixel circuit and the second pixel circuit.

[0203] For example, embodiments of this disclosure provide a display substrate, Figure 21A This is a structural layout of another display substrate provided in one embodiment of the present disclosure. Figure 21B This is a structural layout of another display substrate provided in one embodiment of the present disclosure. Figure 22 for Figure 21B Layout of the second conductive layer. Figure 23 for Figure 21B The structural layout of the first conductive layer in the middle. Figure 24 for Figure 21B The structural layout of the first and second conductive layers stacked together. Figures 21A to 24 The schematic diagram only shows a partial stacked structure or a single-layer structure of the film layers in the display substrate. Other film layers may include the film layer containing the gate lines, the film layer containing the light-shielding layer, etc. Figure 21B Compared to Figure 21A It has an additional light-shielding layer, but the other structural settings are the same.

[0204] For example, combining Figure 19 and Figure 21BAs shown, the display substrate 600 includes: a substrate 601, a pixel circuit 610 disposed on the substrate 601, the pixel circuit 610 including a driving transistor T3 and a storage capacitor C, the display substrate 600 further including a first conductive layer 602, a second conductive layer 603 and a first semiconductor layer 604, wherein the first conductive layer 602 includes a first connection structure 6021, the first connection structure 6021 including a first end 6021a and a second end 6021b opposite to each other, the first end 6021a is connected to the first semiconductor layer 604, and the second end 6021b is electrically connected to the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor C; the first conductive layer 602 is on the side of the first semiconductor layer 604 away from the substrate 601, the second conductive layer 603 is on the side of the first conductive layer 602 away from the substrate 601, and the orthographic projection of the first power signal line 6033 on the second conductive layer 603 onto the substrate 601 is the same as the first connection. The orthographic projections of the entire structure 6021 onto the substrate 601 overlap. By making the orthographic projections of the second conductive layer 603 onto the substrate 601 overlap with the orthographic projections of the entire first connection structure 6021 onto the substrate 601, the first power signal line 6033 in the second conductive layer 603 (also called SD2) can completely cover the first connection structure 6021 (also called the N1 node). Since the second conductive layer 603 (SD2) is connected to a stable signal, and a capacitor is formed between the second conductive layer 603 (SD2) and the first conductive layer 602 (also called SD1), a capacitor is formed between the N1 node and the data line data closest to it. The data signal has little influence on the capacitor, thereby reducing the influence of the nearby data signal on the N1 node, that is, shielding the influence of the data signal on the N1 node, and thus improving the problem that the display panel cannot display normally due to the voltage of the N1 node being affected by the data signal jump.

[0205] For example, such as Figure 19 As shown in Figure 21, the first semiconductor layer 604 includes the semiconductor pattern of the eighth transistor T8, which will be mentioned later. The material of the first semiconductor layer 604 is a metal-oxide semiconductor, such as indium gallium zinc oxide (IGZO). The first plate Cst1 of the storage capacitor C can be used as the gate of the driving transistor T3.

[0206] For example, combining Figure 21B and 22The second conductive layer 603 includes a data line 6031 and a first power signal line 6033. The second conductive layer 603 can be a second source / drain metal layer (SD2). The orthographic projection of the first power signal line 6033 onto the substrate 601 covers more than 50% of the orthographic projection of the first connection structure 6021 onto the substrate 601. That is, the first power signal line 6033 can completely cover the first connection structure 6021, or it can partially cover the first connection structure 6021. When the first power signal line 6033 completely covers the first connection structure 6021, the orthographic projection of the first power signal line 6033 onto the substrate 601 covers the entire orthographic projection of the first connection structure onto the substrate 601.

[0207] For example, combining Figure 21B and 22 The second conductive layer 603 also includes a first electrode adapter wire 6032. For example, the planar shape of the first electrode adapter wire 6032 can be rectangular. The plurality of first electrode adapter wires 6032 are provided one-to-one with a plurality of electrode parts (not shown in the figure), and the electrode parts are connected to the corresponding first electrode adapter wires 6032 through vias.

[0208] For example, combining Figure 21B and 22 The first power signal line 6033 includes a block portion 6033a and a strip portion 6033b that connects two adjacent block portions 6033a in the first direction Y. The strip portion 6033b connects the adjacent block portions 6033a at the edge of the block portion 6033a, so that the strip portion 6033b and the block portion 6033a form a receiving space, and the first electrode adapter line 6032 is formed in the receiving space.

[0209] For example, combining Figure 21B and 22 The orthographic projection of the data line 6031 onto the substrate 601 extends along the first direction Y. In the same repeating unit, the orthographic projections of the two data lines 6031 onto the substrate 601 are located between the orthographic projections of the two first power signal lines 6033 onto the substrate 601.

[0210] For example, in the first direction Y, the second conductive layer 603 of any two adjacent columns of sub-pixels has a mirror-symmetric structure. In other exemplary embodiments, the second conductive layer 603 of any two adjacent columns of sub-pixels in the first direction Y may not have a mirror-symmetric structure.

[0211] For example, such as Figure 23As shown, the first conductive layer 602 includes at least: a second initial signal line Vinit2, a first connecting electrode 6021, a second connecting electrode 6022, a third connecting electrode 6023, a fourth connecting electrode 6024, a fifth connecting electrode 6025, and a sixth connecting electrode 6026, as follows. Figure 23 As shown. In some exemplary embodiments, the first conductive layer 602 may be referred to as the first source / drain metal (SD1) layer.

[0212] For example, combining Figure 21B , Figure 22 and Figure 23 The data line 6031 extends in the first direction Y, and the direction perpendicular or substantially perpendicular to the extension direction of the data line 6031 is the second direction X. The first connection structure 6021 is in the shape of an inverted "L", and the part of the inverted "L" along the second direction X extends away from the data line 6031 closest to it. The end M1 of the part of the inverted "L" along the second direction X that is away from the data line 6031 closest to it is connected to the second electrode of the eighth transistor T8.

[0213] For example, such as Figure 24 As shown, the orthographic projection of the block-shaped portion 6033a of the first power signal line 6033 onto the substrate 601 completely covers the orthographic projections of the first connection structure 6021 and the third connection electrode 6023 onto the substrate 601. The orthographic projection of the first electrode adapter 6032 onto the substrate 601 overlaps with at least a portion of the orthographic projection of the fourth connection electrode 6024 onto the substrate 601. The orthographic projection of the strip-shaped portion 6033b of the first power signal line 6033 onto the substrate 601 overlaps with at least a portion of the orthographic projections of the fifth connection electrode 6025 and the sixth connection electrode 6026 onto the substrate 601. The orthographic projection of the data line 6031 onto the substrate 601 and the orthographic projection of the second connection electrode 6022 onto the substrate 601 at least partially overlap.

[0214] For example, Figure 25 for Figure 19 The diagram shows a partial structural illustration of the first active layer in the display substrate, for example, as shown below. Figure 25 As shown, the pixel circuit 610 includes a first active layer 605, which includes a channel region and a source / drain region for each transistor. For example, the source / drain region may include a source region and a drain region.

[0215] For example, Figure 25schematically shows that the first active layer 605 is formed by patterning a semiconductor material. The first active layer 605 can be used to fabricate the active layers of the aforementioned first transistor T1, second transistor T2, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7, so as to form the channel regions of the aforementioned transistors. The first active layer 605 includes the active layer patterns (channel regions) and doped region patterns (source and drain regions) of the aforementioned transistors of each sub-pixel, and the active layer patterns and doped region patterns of the aforementioned transistors in the same pixel circuit are integrally formed.

[0216] For example, Figure 25 each dashed rectangular frame in the drawing shows the respective portions where the aforementioned metal layer overlaps with the first active layer 605, namely the first active portion 21, second active portion 22, third active portion 23, fourth active portion 24, fifth active portion 25, sixth active portion 26, and seventh active portion 27, which respectively serve as the channel regions of the first transistor T1, second transistor T2, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7. The portions of the first active layer 605 on both sides of each channel region are made conductive through processes such as ion doping to serve as the first electrode and the second electrode of each transistor, i.e., the aforementioned source and drain regions. The aforementioned first active layer 605 may be an integral structure. The source electrode and drain electrode of each of the aforementioned transistors may be structurally symmetric, so the source electrode and the drain electrode may have no difference in physical structure. In the embodiments of the present disclosure, to distinguish the transistors, apart from the gate electrode serving as the control electrode, one electrode is directly described as the first electrode and the other as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed.

[0217] For example, as shown in Figure 25 , the shape of the channel region 23 of the driving transistor T3 may be in a "several" shape, and the shapes of the channel region 21 of the first transistor T1, the channel region 22 of the second transistor T2, the channel region 24 of the fourth transistor T4, the channel region 25 of the fifth transistor T5, the channel region 26 of the sixth transistor T6, and the channel region 27 of the seventh transistor T7 are all in a "1" shape.

[0218] For example, in some exemplary implementations, the active structure of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0219] For example, in some exemplary implementations, the first active layer 605 may adopt polysilicon (p-Si), that is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be LTPS thin film transistors.

[0220] For example, Figure 26 for Figure 19 The diagram shows a partial structural schematic of the third conductive layer in the display substrate, for example, as shown below. Figure 26 As shown, the pixel circuit 610 includes a third conductive layer 606, which at least includes: a first scan signal line 6061 (Gate_P), a reset control signal line 6062 (Reset_P), an emissive control signal line 6063 (EM_P), and a first electrode Cst1 of the storage capacitor C, as shown. Figure 26 As shown. In some exemplary embodiments, the third conductive layer 606 may be referred to as the first gate metal layer. The first scan signal line 6061 may also be used as the gate of the second transistor T2 and the gate of the fourth transistor T4; the reset control signal line 6062 may also be used as the gate of the first transistor T1 and the gate of the seventh transistor T7; the reset control signal line 6062 may also be used as the gate of the fifth transistor T5 and the gate of the sixth transistor T6; the first plate Cst1 of the storage capacitor C may be used as the gate of the driving transistor T3.

[0221] For example, such as Figure 26 As shown, in the first direction Y, the third conductive layer 606 of any two adjacent columns of sub-pixels has a mirror-symmetric structure.

[0222] For example, such as Figure 26 As shown, the first scan signal line 6061, the reset control signal line 6062, and the light emission control signal line 6063 all extend along the second direction X. Within each sub-pixel, the reset control signal line 6062 is located on the side of the first scan signal line 6061 away from the light emission control signal line 6063, and the first plate Cst1 of the storage capacitor is disposed between the first scan signal line 6061 and the light emission control signal line 6063.

[0223] For example, such as Figure 25 and 26 As shown, the first electrode plate Cst1 has a rectangular planar shape, and at least one corner of the rectangle may be chamfered. The orthographic projection of the first electrode plate Cst1 on the substrate 601 overlaps with the orthographic projection of the channel region 23 of the third transistor T3 on the substrate 601. The region of the first active layer 605 that overlaps with the first electrode plate Cst1 serves as the channel region 23 of the third transistor T3. One end of the channel region 23 of the third transistor T3 is connected to the first region of the active region of the third transistor T3, and the other end is connected to the second region of the active region of the third transistor T3.

[0224] For example, in some exemplary embodiments, the region of the reset control signal line 6062 (Reset_P) that overlaps with the first active region of the first transistor T1 serves as the gate of the first transistor T1; the region of the first scan signal line 6061 (Gate_P) that overlaps with the second active region of the second transistor T2 serves as the gate of the second transistor T2; the region of the first scan signal line 6061 (Gate_P) that overlaps with the fourth active region of the fourth transistor T4 serves as the gate of the fourth transistor T4; the region of the light emission control signal line 6063 (EM_P) that overlaps with the fifth active region of the fifth transistor T5 serves as the gate of the fifth transistor T5; and the region of the light emission control signal line 6063 (EM_P) that overlaps with the sixth active region of the sixth transistor T6 serves as the gate of the sixth transistor T6. In the next row of sub-pixels, the region of the reset control signal line Reset_P (which has the same signal as the first scan signal line Gate_P in the current row of sub-pixels) that overlaps with the seventh active region of the seventh transistor T7 in the current row of sub-pixels serves as the gate of the seventh transistor T7.

[0225] For example, Figure 27 for Figure 19 The diagram shows a partial structural illustration of the conductive film layer in the display substrate, for example, as shown below. Figure 27 As shown, the pixel circuit 610 includes a conductive film layer 607 located between the third conductive layer 606 and the second conductive layer 603. The conductive film layer 607 includes a second scan signal line 6071, a first conductive portion 6072, and a fifth conductive portion 6073. A portion of the structure of the second scan signal line 6071 is used to form the bottom gate of the eighth transistor T8. The first conductive portion 6072 includes the second plates Cst2 of two adjacent storage capacitors C in the first direction Y. The fifth conductive portion 6073 is electrically connected to the first conductive layer 602. This conductive film layer 607 can be referred to as the second gate metal layer (Gate 2).

[0226] For example, such as Figure 27 As shown, the first conductive portion 6072 includes a main body portion 6072a, and the storage capacitor C also includes a second electrode plate Cst2 opposite to the first electrode plate Cst1. The main body portion 6072a corresponds to two second electrode plates Cst2. For example, the first conductive portion 6072 also includes a bridging portion 6072b, which connects two adjacent main body portions 6072a in the second direction X, i.e., two adjacent second electrode plates Cst2. The first conductive portion 6072 also includes a notch 6072c between the two second electrode plates Cst2.

[0227] For example, combining Figure 19 , Figure 23 and Figure 27The orthographic projection of the first conductive layer 602 on the substrate 601 does not overlap with the orthographic projection of the notch 6072c on the substrate 601, and the orthographic projection of the second conductive layer 603 on the substrate 601 does not overlap with the orthographic projection of the notch 6072c on the substrate 601. This ensures that the notch 6072c is not blocked by the first conductive layer 602 and the second conductive layer 603, thereby improving pixel transmittance. It should also be noted that the notch 6072c is not blocked by any other light-shielding film layer.

[0228] For example, combining Figure 19 , Figure 23 and Figure 27 An opening 6072d is also formed on the first conductive portion 6072. The orthographic projection of the via connecting the gate of the driving transistor T3 and the first connection structure 6021 on the substrate 601 is within the orthographic projection of the opening 6072d on the substrate 601, so that the conductive structure in the via is insulated from the first conductive portion 6072.

[0229] For example, the display substrate further includes a second active layer, for example, Figure 28 for Figure 19 The diagram shown is a partial structural schematic of the second active layer in the display substrate, combined with... Figure 19 and Figure 28 As shown, the second active layer 608 is located between the first active layer 605 and the second conductive layer 603. The second active layer 608 may include an eighth active portion 38, which forms the channel region of the eighth transistor T8. A first region 381 and a second region 382 of the eighth transistor T8 are formed at both ends of the eighth active portion 38. The first region 381 of the eighth transistor T8 is adjacent to the channel region of the first transistor T1, and the second region 382 of the eighth transistor T8 is adjacent to the storage capacitor C. The first semiconductor layer 604 includes the second active layer 608.

[0230] For example, such as Figure 19 and Figure 28 As shown, the second active layer 608 can be formed of indium gallium zinc oxide, and correspondingly, the eighth transistor T8 can be an N-type metal oxide thin film transistor. The entire first region 381 and the second region 382 of the eighth active portion 38 and the eighth transistor T8 extend along the first direction Y, and the overall shape of the entire first region 381 and the second region 382 of the eighth active portion 38 and the eighth transistor T8 can be dumbbell-shaped.

[0231] For example, the first semiconductor layer forming the channel region of the eighth transistor T8 in the pixel circuit can be located on the side of the active semiconductor pattern layer of the driving transistor T3 away from the substrate 601. This first semiconductor layer may include an oxide semiconductor material. For example, when the active layer in the eighth transistor T8 of the pixel circuit is made of oxide semiconductor, since the transistor using oxide semiconductor has good hysteresis characteristics, low leakage current, and low mobility, the oxide semiconductor transistor can be used instead of the low-temperature polysilicon material in the transistor to form a low-temperature polysilicon-oxide (LTPO) pixel circuit, achieving low leakage current and improving the stability of the transistor's gate voltage.

[0232] Of course, the embodiments of this disclosure are not limited to the second active layer of the pixel circuit being... Figure 28 In the structure shown, in other examples, the first semiconductor layer including the channel region of the eighth transistor T8 may also be located on the same layer as the semiconductor layers of the channel regions of other transistors. That is, the first active layer may also include the channel regions of the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0233] For example, Figure 29 for Figure 19 The diagram shows a partial structural schematic of the fourth conductive layer in the display substrate, for example, as shown below. Figure 29 As shown, the pixel circuit 610 also includes a fourth conductive layer 609, which is located between the conductive film layer 607 and the second conductive layer 603. The fourth conductive layer 609 includes a first initial signal line Vinit1 and a fourth scan signal line 6091. A portion of the structure of the fourth scan signal line 6091 is configured to form the top gate of the eighth transistor T8.

[0234] For example, combining Figures 21A to 29 The first conductive layer 602 includes a second initial signal line Vinit2 that extends along the second direction X. The second initial signal line Vinit2 is connected to the first region of the seventh transistor T7 through a third via V3, so that the first electrode of the seventh transistor T7 and the second initial signal line Vinit2 have the same potential.

[0235] For example, combining Figures 21A to 29The first scan signal line 6061 includes a protrusion 6061a extending along a first direction Y and a portion extending along a second direction X. The first end 6021a of the first connection structure 6021 is connected to the first region of the eighth transistor T8 through a fourth via V4. The second end 6021b of the first connection structure 6021 is electrically connected to the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor C through a fifth via V5. The orthographic projection of the third end 6021c of the first connection structure 6021 onto the substrate 601 overlaps with the orthographic projection of the protrusion 6061a of the first scan signal line 6061 onto the substrate 601, thereby forming a coupling capacitor between the third end 6021c of the first connection structure 6021 and the protrusion 6061a of the first scan signal line 6061. For example, the first end 6021a of the first connection structure 6021 can serve as the second electrode of the eighth transistor T8.

[0236] For example, the inverted "L"-shaped portion of the first connection structure 6021 along the first direction Y is electrically connected to the fifth conductive portion 6073 of the conductive film layer 607; the fifth conductive portion 6073 overlaps with the protrusion 6061a of the first scan signal line extending along the first direction Y.

[0237] For example, combining Figures 21A to 29 The second connection electrode 6022 is connected to the first region of the fourth transistor T4 through the sixth via V6. In some exemplary embodiments, the second connection electrode 6022 can serve as the first electrode of the fourth transistor T4.

[0238] For example, combining Figures 21A to 29 One end of the third connection electrode 6023 is connected to the first region of the second transistor T2 (which is also the second region of the first transistor T1) through the seventh via V7, and the other end is connected to the first region of the eighth transistor T8 through the eighth via V8. In some exemplary embodiments, the third connection electrode 6023 can serve as the first electrode of the eighth transistor T8, the first electrode of the second transistor T2, and the second electrode of the first transistor T1.

[0239] For example, combining Figures 21A to 29 The fourth connection electrode 6024 is connected to the second region of the sixth transistor T6 (which is also the second region of the seventh transistor T7) through the ninth via V9. In some exemplary embodiments, the fourth connection electrode 6024 can simultaneously serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7.

[0240] For example, combining Figures 21A to 29The fifth connecting electrode 6025 is connected to the second electrode plate Cst2 through the tenth via V10 on one hand, and to the first region of the fifth transistor T5 through the eleventh via V11 on the other hand. The fifth connecting electrode 6025 is also configured to be connected to the first power signal line formed subsequently.

[0241] For example, combining Figures 21A to 29 One end of the sixth connecting electrode 6026 is connected to the first region of the first transistor T1 through the twelfth via V12, and the other end is connected to the first initial signal line, so that the first electrode of the first transistor T1 and the first initial signal line have the same potential.

[0242] For example, in the first direction Y, the first conductive layer 602 of any two adjacent columns of sub-pixels has a mirror-symmetric structure.

[0243] For example, the display substrate 100 also includes a plurality of sub-pixels, each sub-pixel including the pixel circuit 610 and light-emitting element as described in any of the above examples. Figure 30 This is a schematic diagram of a partial pixel arrangement structure on a display substrate according to an embodiment of the present disclosure. Figure 31A for Figure 19 A layout of the pixel circuit and the first electrode stack of the light-emitting element in a [structure / process]. Figure 31B for Figure 19 Another layout of the pixel circuit and the first electrode stack of the light-emitting element. Figure 31B Compared to Figure 31A It has an additional light-shielding layer, but the other structural settings are the same.

[0244] For example, the design of this local pixel arrangement structure and each electrode portion 502 on the first electrode layer 501 can be found in the above description. Figure 14 , Figure 15A and Figure 15B The relevant descriptions will not be repeated here.

[0245] For example, combining Figure 30 and Figure 31A and Figure 31B Each electrode portion 502 on the first electrode layer 501 is connected to the first electrode adapter line 6032.

[0246] For example, the display substrate 610 may also include a light-shielding layer, the details of which can be found in the documentation. Figure 17 The relevant descriptions will not be repeated here.

[0247] For example, in some exemplary embodiments, the display substrate may further include an encapsulation layer, which may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to ensure that external moisture cannot enter the light-emitting structure layer.

[0248] For example, Figure 32 This is a cross-sectional structural schematic diagram of a display substrate provided in at least one embodiment of the present disclosure, and is described based on the above-described 7T1C pixel circuit structure. For example, a first buffer layer 125 is provided on the substrate 101, a first active layer 105 is provided on the first buffer layer 125, a first insulating layer 126 is provided on the first active layer 105, a third conductive layer 106 is provided on the first insulating layer 126, a second insulating layer 127 is provided on the third conductive layer 106, a conductive film layer 107 is provided on the second insulating layer 127, a third insulating layer 128 is provided on the conductive film layer 107, and a fourth insulating layer 129 is provided on the third insulating layer 128. A second active layer 108 is disposed on the insulating layer 129. A fifth insulating layer 130 is disposed on the second active layer 108. A fourth conductive layer 109 is disposed on the fifth insulating layer 130. A sixth insulating layer 131 is disposed on the fourth conductive layer 109. A first conductive layer 102 is disposed on the sixth insulating layer 131. The first conductive layer 102 is electrically connected to the first active layer 105, the third conductive layer 106, and the conductive film layer 107 through vias, respectively. A seventh insulating layer 132 is disposed on the first conductive layer 102. A second conductive layer 103 is disposed on the seventh insulating layer 132. The second conductive layer 103 is electrically connected to the first conductive layer 102 through a via penetrating the seventh insulating layer 132. A second planarization layer 133 is disposed on the second conductive layer 103. A first electrode layer 501 is disposed on the second planarization layer 133. The first electrode layer 501 is electrically connected to the second conductive layer 103 through a via penetrating the second planarization layer 133.

[0249] For example, the first buffer layer (BUF1) 125, the first insulating layer 126, the second insulating layer 127, the third insulating layer 128, the fourth insulating layer 129, the fifth insulating layer 130, and the sixth insulating layer 131 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first buffer (BUF1) layer can be used to improve the water and oxygen resistance of the substrate 101. The first insulating layer 126 is called the first gate insulating (GI1) layer, the second insulating layer 127 is called the second gate insulating (GI2) layer, the third insulating layer 128 is called the first interlayer insulating (ILD1) layer, the fourth insulating layer 129 is called the second buffer (BUF2) layer, and the fifth insulating layer 130 is called the third gate insulating (GI3) layer.

[0250] For example, the first planarization layer 132 and the second planarization layer 133 can be made of organic materials, and the transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO). The first active layer can be made of polycrystalline silicon (p-Si), and the second active layer can be made of metal oxide.

[0251] For example, in some exemplary embodiments, the substrate 101 / 601 can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some exemplary embodiments, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0252] For example, in some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the conductive film layer, and the light-shielding layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0253] Figure 32The structure of the display substrate shown is merely an illustrative example. In some exemplary embodiments, the corresponding structure can be modified according to actual needs, and the embodiments disclosed herein are not limited in this regard. The structure of the above-described display substrate is based on... Figure 3 The pixel circuit shown is used as an example for illustration. In other exemplary embodiments, the pixel circuit may also be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 8T1C structure, etc. The embodiments disclosed herein do not limit this.

[0254] For example, Figure 33 This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure. Figure 33 The explanation will take the 7T1C pixel circuit as an example. Figure 33 As shown, the structure of the first conductive layer 102 can be found in the above description. Figure 6 The structure of the second conductive layer 103 can be found in the above description. Figure 7 The relevant descriptions will not be repeated here. Combined with... Figure 3 and Figure 33As shown, the first conductive layer 102 includes a first connection structure 1021. The orthographic projection of the first electrode adapter line 1032 on the second conductive layer 103 onto the substrate 101 overlaps with the orthographic projection of at least a portion of the first connection structure 1021 onto the substrate 101, so that the second conductive layer 103 (also referred to as SD2) can block at least a portion of the first connection structure 1021 (also referred to as the N1 node), thereby causing the second conductive layer 103 and the first connection structure 1021 located on the first conductive layer 102 to directly form a capacitor, that is, a capacitor is formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also referred to as SD1), thereby forming a capacitor between the N1 node and the data line closest to it, due to the light emission control signal. Both the EM line and the second initial signal line Vinit2 transmit stable DC signals. The second conductive layer 103 (SD2) is connected to the stable signal, and the signal changes only once within one frame. This design allows the second conductive layer 103 (SD2) to directly form a capacitor with the first conductive layer 102 (also called SD1) at the N1 node when the N1 node is working normally. The second conductive layer 103 (SD2, the upper plate) is connected to the stable signal. Due to the inherent characteristics of a capacitor, the voltage across the capacitor cannot change abruptly. After the upper plate is connected to the stable DC signal, the signal on the lower plate, i.e., the first conductive layer 102 (SD1) at the N1 node, can also remain stable. This reduces the impact of data signals that frequently jump within one frame on the N1 node. The data signal has a relatively small impact on the capacitor, thereby reducing the impact of nearby data signals on the N1 node, i.e., shielding the N1 node from the influence of data signals. This improves the problem of the display panel failing to display properly due to the voltage of the N1 node being affected by data signal jumps.

[0255] For example, in Figure 33 In the illustrated structure, exemplarily, each first conductive portion 1074 includes only two main portions 1074a, and the storage capacitor C includes two second plates Cst2, with the main portion 1074a corresponding to the two second plates Cst2. For example, the first conductive portion 1074 does not include other structures.

[0256] For example, Figure 33 For the settings of other structures, please refer to the descriptions of the corresponding sections above, which will not be repeated here.

[0257] For example, Figure 34 This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure. Figure 34 The explanation will take an 8T1C pixel circuit as an example. Figure 34 As shown, the structure of the first conductive layer 602 can be found in the above description. Figure 23 The structure of the second conductive layer 603 can be found in the above description. Figure 22 The relevant descriptions will not be repeated here. Combined with... Figure 19 and Figure 34 As shown, the first conductive layer 602 includes a first connection structure 6021. The orthographic projection of the first power signal line 6033 on the substrate 601 on the second conductive layer 603 overlaps with the orthographic projection of the entire first connection structure 6021 on the substrate 601, so that the second conductive layer 603 (also called SD2) can completely cover the first connection structure 6021 (also called the N1 node). This allows the second conductive layer 603 and the first power signal line 6033 located on the first conductive layer 602 to directly form a capacitor, that is, a capacitor is formed between the second conductive layer 603 (SD2) and the first conductive layer 602 (also called SD1). Thus, a capacitor is formed between the N1 node and the nearest data line data. Due to the light emission control signal line... Both EM and the second initial signal line Vinit2 transmit stable DC signals. The second conductive layer 603 (SD2) is connected to the stable signal, and the signal changes only once within one frame. This design allows the second conductive layer 603 (SD2) to directly form a capacitor with the first conductive layer 602 (also called SD1) at the N1 node when the N1 node is working normally. The second conductive layer 603 (SD2, the upper plate) is connected to the stable signal. Due to the inherent characteristics of a capacitor, the voltage across the capacitor cannot change abruptly. After the upper plate is connected to the stable DC signal, the signal on the lower plate, i.e., the first conductive layer 602 (SD1) at the N1 node, can also remain stable. This reduces the impact of data signals that frequently jump within one frame on the N1 node. The data signal has a relatively small impact on the capacitor, thereby reducing the impact of nearby data signals on the N1 node, i.e., shielding the N1 node from the influence of data signals. This improves the problem of the display panel failing to display properly due to the voltage of the N1 node being affected by data signal jumps.

[0258] For example, in Figure 34 In the illustrated structure, exemplarily, each first conductive portion 6074 includes only two main portions 6074a, and the storage capacitor C includes two second plates Cst2, with the main portion 6074a corresponding to the two second plates Cst2. For example, the first conductive portion 6074 does not include other structures.

[0259] For example, Figure 34 For the settings of other structures, please refer to the descriptions of the corresponding sections above, which will not be repeated here.

[0260] For example, Figure 35 This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure. Figure 35 The explanation will take the 7T1C pixel circuit as an example. Figure 35As shown, the structure of the first conductive layer 102 can be found in the above description. Figure 6 The structure of the second conductive layer 103 can be found in the above description. Figure 22 The relevant descriptions will not be repeated here. Combined with... Figure 3 and Figure 35 As shown, the first conductive layer 102 includes a first connection structure 1021. The orthographic projection of the first power signal line 1033 on the substrate 101 on the second conductive layer 103 overlaps with the orthographic projection of more than 50% of the area of ​​the first connection structure 1021 on the substrate 101, so that the second conductive layer 103 (also called SD2) can completely cover the first connection structure 1021 (also called the N1 node), thereby directly forming a capacitor between the second conductive layer 103 and the first power signal line 1033 located on the first conductive layer 102, that is, a capacitor is formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also called SD1), thereby forming a capacitor between the N1 node and the data line data closest to it. Due to the light emission control Both signal line EM and the second initial signal line Vinit2 transmit stable DC signals. The second conductive layer 103 (SD2) is connected to the stable signal, and the signal changes only once within one frame. This design allows the second conductive layer 103 (SD2) to directly form a capacitor with the first conductive layer 102 (also called SD1) at the N1 node when the N1 node is working normally. The second conductive layer 103 (SD2, upper plate) is connected to the stable signal. Due to the inherent characteristics of a capacitor, the voltage across the capacitor cannot change abruptly. After the upper plate is connected to the stable DC signal, the signal on the lower plate, i.e., the first conductive layer 102 (SD1) at the N1 node, can also remain stable. This reduces the impact of data signals that frequently jump within one frame on the N1 node. The data signal has a relatively small impact on the capacitor, thereby reducing the impact of nearby data signals on the N1 node, i.e., shielding the N1 node from the influence of data signals. This improves the problem of the display panel failing to display properly due to the voltage of the N1 node being affected by data signal jumps.

[0261] For example, in Figure 35 In the illustrated structure, exemplarily, each first conductive portion 6074 includes only two main portions 6074a, and the storage capacitor C includes two second plates Cst2, with the main portion 6074a corresponding to the two second plates Cst2. For example, the first conductive portion 6074 does not include other structures.

[0262] For example, such as Figure 35 As shown, the first electrode adapter wire 1032 and the first connection structure 1021 do not overlap.

[0263] For example, Figure 35For the settings of other structures, please refer to the descriptions of the corresponding sections above, which will not be repeated here.

[0264] For example, Figure 36 This is a structural layout of another display substrate provided in at least one embodiment of the present disclosure. Figure 36 The layer structure shown can also be a display substrate including a first electrode layer 501, which is located on the side of the second conductive layer 103 away from the substrate 101. This arrangement can make the area below the first electrode (anode) in the pixel unit flat and can also maintain capacitance balance. Figure 36 As shown, the first electrode layer 501 includes a plurality of electrode portions 502. Each electrode portion 502 includes a body portion 5021 and an extension portion 5022 connected to each other. Each electrode portion 502 corresponds to one of the first sub-pixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third sub-pixel 403. For example, the first electrodes (anodes) corresponding to the first sub-pixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third sub-pixel 403 are preferably disposed above the first power signal line 1033 of the second conductive layer 103.

[0265] For example, providing an extension portion 5022 on the electrode portion 502 can increase the overlap area between the electrode portion 502 and the second conductive layer 103. For example, the extension portion 5022 of the electrode portion 502 corresponding to the first pixel block 4020a and the second pixel block 4020b can cover the elongated position of the edge of the first power signal line 1033, and the extension portion 5022 of the electrode portion 502 corresponding to the first sub-pixel 401 and the third sub-pixel 403 can cover the block-shaped portion of the first power signal line 1033, thereby further increasing the overlap area between the electrode portion 502 and the second conductive layer 103.

[0266] At least one embodiment of this disclosure also provides a display device, which includes any of the display substrates described above. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; however, this embodiment is not limited to this. The following points need to be noted:

[0267] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0268] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0269] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; A pixel circuit is disposed on the substrate and includes a driving transistor and a storage capacitor; The display substrate further includes a first conductive layer, a second conductive layer, and a first semiconductor layer, wherein... The first conductive layer includes a first connection structure, the first connection structure includes a first end and a second end opposite to each other, the first end is connected to the first semiconductor layer, and the second end is electrically connected to the gate of the driving transistor and the first plate of the storage capacitor; The first conductive layer is on the side of the first semiconductor layer away from the substrate, the second conductive layer is on the side of the first conductive layer away from the substrate, and the orthographic projection of the second conductive layer on the substrate overlaps with the orthographic projection of at least a portion of the first connection structure on the substrate. The second conductive layer includes mutually spaced data lines, a first electrode adapter line, and a first power signal line, wherein the first electrode adapter line is connected to the first electrode of the light-emitting element; The extension direction of the data line is the first direction, and the direction perpendicular or substantially perpendicular to the extension direction of the data line is the second direction. The first conductive layer further includes a power signal connection line, which includes a main body and a branch body. The main body of the power signal connection line extends in a direction parallel to the second direction, and the branch body extends in a direction parallel to the first direction. The first power signal line includes a block portion and a strip portion that extends generally along the first direction, the strip portion connecting adjacent block portions, and the main body portion of the power signal connection line connecting to the first power signal line.

2. The display substrate according to claim 1 further includes a plurality of sub-pixels, wherein, Each sub-pixel includes the pixel circuit and the light-emitting element, the first conductive layer is between the first electrode of the light-emitting element and the first semiconductor layer, and the second conductive layer is between the first conductive layer and the first electrode of the light-emitting element.

3. The display substrate according to claim 2, wherein, The orthographic projection of the first electrode adapter line on the substrate overlaps with the orthographic projection of part of the first connection structure on the substrate.

4. The display substrate according to claim 3, wherein, The first connection structure includes a portion that overlaps with the first electrode adapter wire and a portion that does not overlap with the first electrode adapter wire, and the non-overlapping portion is further away from the data line closest to it relative to the overlapping portion.

5. The display substrate according to claim 1, wherein, The strip portion includes a first strip portion and a second strip portion disposed opposite to each other, and a third strip portion connecting the first strip portion and the second strip portion. The extending directions of the first strip portion and the second strip portion are parallel to the first direction, and the third strip portion connects the middle region of the first strip portion and the second strip portion.

6. The display substrate according to claim 5, wherein, The strip-shaped portion includes a hollow structure.

7. The display substrate according to claim 1, wherein, The width of the block-shaped portion in the second direction is greater than the overall width of the strip-shaped portion in the second direction.

8. The display substrate according to claim 1, wherein, The first electrode adapter wire extends along the first direction, and the first electrode adapter wire partially blocks the first connection structure at its end position near the first connection structure.

9. The display substrate according to claim 1, wherein, The pixel circuit also includes a first transistor, a second transistor, a sixth transistor, and a seventh transistor; The first terminal of the first transistor is connected to the gate of the driving transistor, the second terminal of the first transistor is connected to the first initial signal line, the first terminal of the second transistor is connected to the gate of the driving transistor, the second terminal of the second transistor is connected to the second terminal of the driving transistor, the first terminal of the sixth transistor is connected to the second terminal of the driving transistor, the first terminal of the seventh transistor is connected to the second terminal of the sixth transistor, and the second terminal of the seventh transistor is connected to the second initial signal line; The display substrate further includes: A first active layer is located between the substrate and the second conductive layer. The first active layer includes a third active portion, a sixth active portion, a seventh active portion, a tenth active portion, and an eleventh active portion. The third active portion forms the channel region of the driving transistor, the sixth active portion forms the channel region of the sixth transistor, the seventh active portion forms the channel region of the seventh transistor, the tenth active portion is connected between the seventh active portion and the sixth active portion, and the eleventh active portion is connected between the sixth active portion and the third active portion. The second active layer is located between the first active layer and the second conductive layer. The second active layer includes a first active portion, a second active portion, and a twelfth active portion. The first active portion forms the channel region of the first transistor. The second active portion is connected to the first active portion to form the channel region of the second transistor. The twelfth active portion is connected to the end of the second active portion away from the first active portion.

10. The display substrate according to claim 9, wherein, The display substrate includes a plurality of repeating units distributed along the first direction and the second direction. Each repeating unit includes two pixel circuits. The two pixel circuits include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are arranged in a mirror symmetrical manner. Each pixel circuit further includes a fourth transistor and a fifth transistor, wherein the first terminal of the fourth transistor is connected to the data line, the second terminal of the fourth transistor is connected to the first terminal of the driving transistor, the first terminal of the fifth transistor is connected to the first power signal line, and the second terminal of the fifth transistor is connected to the first terminal of the driving transistor; The first active layer further includes: The fourth active part is connected to one side of the third active part and forms the channel region of the fourth transistor; The fifth active part forms the channel region of the fifth transistor; The eighth active unit is connected to the side of the fifth active unit that is away from the third active unit; The ninth active unit is connected between the two eighth active units in the same repeating unit.

11. The display substrate according to claim 10, wherein, The first conductive layer includes: a plurality of third connection structures, wherein the plurality of third connection structures are disposed in a one-to-one correspondence with the plurality of repeating units, and the third connection structures are connected to the ninth active unit through a first via connection portion.

12. The display substrate according to claim 11, further comprising a third conductive layer, wherein, The third conductive layer includes: The second gate line extends along the second direction in the orthographic projection on the substrate and overlaps with the orthographic projection of the fourth active portion on the substrate. A portion of the structure of the second gate line is used to form the gate of the fourth transistor. A light-emitting control signal line extends along the second direction in its orthogonal projection on the substrate and overlaps with the orthogonal projection of the sixth active portion on the substrate. A portion of the structure of the light-emitting control signal line is used to form the gate of the sixth transistor. The second reset signal line extends along the second direction in the orthographic projection on the substrate and overlaps with the orthographic projection of the seventh active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, and the second gate line in the pixel circuit of this row is multiplexed as the second reset signal line in the pixel circuit of the adjacent row. The second conductive portion overlaps with the orthographic projection of the third active portion on the substrate, and the second conductive portion forms the gate of the driving transistor and the first plate of the storage capacitor. In the same pixel circuit, the orthographic projection of the second conductive portion on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the light emission control signal line on the substrate. The orthographic projection of the second reset signal line on the substrate is located on the side away from the orthographic projection of the second conductive part on the substrate.

13. The display substrate according to claim 12, further comprising a fourth conductive layer, wherein, The fourth conductive layer is located between the second active layer and the second conductive layer, and the fourth conductive layer includes: The first reset signal line has its orthographic projection on the substrate overlapping with the orthographic projection of the first active part on the substrate, and a portion of the structure of the first reset signal line forms the top gate of the first transistor. The first gate line, whose orthogonal projection on the substrate overlaps with the orthogonal projection of the second active portion on the substrate, forms the top gate of the second transistor in part of the structure of the first gate line; In the same pixel circuit, the orthographic projection of the first gate line on the substrate lies between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the second gate line on the substrate, and the orthographic projection of the first reset signal line on the substrate lies on the side of the orthographic projection of the second gate line on the substrate that is away from the orthographic projection of the second conductive portion on the substrate.

14. The display substrate according to claim 13, further comprising: A conductive film layer between the third conductive layer and the fourth conductive layer, wherein the conductive film layer comprises: The orthographic projection of the first initial signal line on the substrate is on the side of the orthographic projection of the first reset signal line on the substrate that is away from the orthographic projection of the second conductive portion on the substrate. The third reset signal line is connected to the first reset signal line through a via. Its orthographic projection on the substrate overlaps with the orthographic projection of the first active part on the substrate. A portion of the structure of the third reset signal line is used to form the bottom gate of the first transistor. The third gate line has its orthographic projection on the substrate overlapping with the orthographic projection of the second active portion on the substrate, and a portion of the structure of the third gate line is used to form the bottom gate of the second transistor. The first conductive portion includes a main body portion, and the storage capacitor includes a second electrode plate opposite to the first electrode plate, with the main body portion corresponding to two second electrode plates.

15. The display substrate according to claim 14, wherein, The first conductive portion further includes a bridging portion that connects two second electrode plates, and the first conductive portion includes a notch between the two second electrode plates.

16. The display substrate according to claim 2, wherein, The orthographic projection of the first power signal line on the substrate covers more than 50% of the orthographic projection of the first connection structure on the substrate.

17. The display substrate according to claim 2, wherein, The pixel circuit also includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The gate of the first transistor is connected to the reset control signal line, the first terminal of the first transistor is connected to the first initial signal line, and the second terminal of the first transistor is connected to the first terminal of the eighth transistor and the first terminal of the second transistor. The gate of the second transistor is connected to the first scan signal line, and the second terminal of the second transistor is connected to the second terminal of the driving transistor and the first terminal of the sixth transistor; The gate of the driving transistor is connected to the second terminal of the eighth transistor and the first plate of the storage capacitor; the first terminal of the driving transistor is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor; and the second terminal of the driving transistor is connected to the second terminal of the second transistor and the first terminal of the sixth transistor. The gate of the fourth transistor is connected to the first scan signal line, the first terminal of the fourth transistor is connected to the data line, and the second terminal of the fourth transistor is connected to the first terminal of the driving transistor and the second terminal of the fifth transistor. The gate of the fifth transistor is connected to the first light-emitting control signal line, the first terminal of the fifth transistor is connected to the first power supply signal line and the second plate of the storage capacitor, and the second terminal of the fifth transistor is connected to the second terminal of the fourth transistor and the first terminal of the driving transistor. The gate of the sixth transistor is connected to the first light-emitting control signal line, the first terminal of the sixth transistor is connected to the second terminal of the driving transistor and the second terminal of the second transistor, and the second terminal of the sixth transistor is connected to the first terminal of the light-emitting element and the second terminal of the seventh transistor; The gate of the seventh transistor is connected to the first scan signal line or the reset control signal line, the first terminal of the seventh transistor is connected to the second initial signal line, and the second terminal of the seventh transistor and the second terminal of the sixth transistor are connected to the first terminal of the light-emitting element. The gate of the eighth transistor is connected to the second scan signal line, the first terminal of the eighth transistor is connected to the second terminal of the first transistor and the first terminal of the second transistor, and the second terminal of the eighth transistor is connected to the gate of the driving transistor and the first plate of the storage capacitor. The first plate of the storage capacitor is connected to the gate of the driving transistor and the second plate of the eighth transistor, and the second plate of the storage capacitor is connected to the first power signal line.

18. The display substrate according to claim 17, further comprising: A first active layer is located between the substrate and the second conductive layer. The first active layer includes a first active portion, a second active portion, a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion. The first active portion forms the channel region of the first transistor, the second active portion forms the channel region of the second transistor, the third active portion forms the channel region of the driving transistor, the fourth active portion forms the channel region of the fourth transistor, the fifth active portion forms the channel region of the fifth transistor, the sixth active portion forms the channel region of the sixth transistor, and the seventh active portion forms the channel region of the seventh transistor. A second active layer is located between the first active layer and the second conductive layer. The second active layer includes an eighth active portion, which forms the channel region of the eighth transistor.

19. The display substrate according to claim 17 or 18, further comprising a third conductive layer, wherein, The third conductive layer includes: The first scan signal line extends along the second direction in its orthogonal projection on the substrate, and a portion of the structure of the first scan signal line is used to form the gates of the second transistor and the fourth transistor; The reset control signal line extends along the first direction in its orthogonal projection on the substrate, and a portion of the structure of the reset control signal line is used to form the gates of the seventh transistor and the first transistor. The first light-emitting control signal line extends along the first direction in its orthogonal projection on the substrate, and a portion of the structure of the first light-emitting control signal line is used to form the gates of the sixth transistor and the fifth transistor; The third conductive portion forms the gate of the driving transistor and the first plate of the storage capacitor; In the same pixel circuit, the orthographic projection of the third conductive part on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the first light emission control signal line on the substrate. The orthographic projection of the reset control signal line on the substrate is on the side away from the orthographic projection of the third conductive part on the substrate.

20. The display substrate according to claim 19, further comprising: A conductive film layer between the third conductive layer and the second conductive layer, wherein the conductive film layer comprises: The second scan signal line, and a portion of the structure of the second scan signal line is used to form the bottom gate of the eighth transistor; The first conductive portion includes the second plates of two adjacent storage capacitors in the second direction; The fifth conductive part is electrically connected to the first conductive layer.

21. The display substrate according to claim 20, wherein, The first conductive portion further includes a bridging portion that connects two second electrode plates, and the first conductive portion includes a notch between the two second electrode plates.

22. The display substrate according to claim 20 or 21, further comprising a fourth conductive layer, wherein, The fourth conductive layer is located between the conductive film layer and the second conductive layer. The fourth conductive layer includes the first initial signal line and the fourth scan signal line. A portion of the structure of the fourth scan signal line forms the top gate of the eighth transistor.

23. The display substrate according to claim 20 or 21, wherein, The extension direction of the data line is a first direction, and the direction perpendicular or substantially perpendicular to the extension direction of the data line is a second direction. The first connection structure is in the shape of an inverted "L". The end of the inverted "L" shape along the second direction that is furthest from the data line is connected to the second electrode of the eighth transistor.

24. The display substrate according to claim 23, wherein, The inverted "L"-shaped portion along the first direction is electrically connected to the fifth conductive portion of the conductive film layer; the first scan signal line includes a protrusion extending along the first direction and a portion extending along the second direction, and the fifth conductive portion overlaps with the protrusion of the first scan signal line extending along the first direction.

25. The display substrate according to claim 2, wherein, The plurality of sub-pixels includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels; Two second sub-pixels constitute a second sub-pixel pair. The two second sub-pixels in a second sub-pixel pair are a first pixel block and a second pixel block, respectively, and the first pixel block and the second pixel block are alternately arranged along the first direction or the second direction. The plurality of sub-pixels includes a plurality of minimum repeating units, and each minimum repeating unit includes a first sub-pixel, a first pixel block, a second pixel block, and a third sub-pixel.

26. The display substrate according to claim 25, further comprising a first electrode layer, wherein, The first electrode layer is located on the side of the second conductive layer away from the substrate. The first electrode layer includes a plurality of electrode portions, each of which includes a body portion and an extension portion connected to each other. The orthographic projection of the extension portion on the substrate overlaps at least partially with the orthographic projection of the first electrode adapter line on the substrate. Each electrode portion corresponds to one of the first sub-pixel, the first pixel block, the second pixel block, and the third sub-pixel.

27. A display device comprising a display substrate according to any one of claims 1 to 26.

Images