Fixed charge control method, method for manufacturing thin film transistor, and thin film transistor

Abstract

A fixed charge control method, a method for manufacturing a thin film transistor, and a thin film transistor. The fixed charge control method is a method for controlling fixed charges in an insulating film used in a semiconductor element. In the method, a metal film is formed on the surface of the insulating film, and ions are implanted into the insulating film through the metal film, thereby showing fixed charges in the insulating film.

Description

Technical Field

[0001] The invention relates to a fixed charge control method, a method for manufacturing a thin film transistor and a thin film transistor. Background Art

[0002] In recent years, development of thin film transistors (TFTs) using oxide semiconductors such as In-Ga-Zn-O (indium gallium zinc oxide (IGZO)) for channel layers has been actively pursued.

[0003] As such a thin film transistor, for example, Patent Document 1 discloses a thin film transistor having a low film density (2.70 g / cm 3 ~2.79g / cm 3 ) as an insulating film constituting a gate insulating layer or a channel protection layer in contact with a channel layer. It is also described that: in the thin film transistor, by using such aluminum oxide with a low film density as an insulating film, the negative fixed charge density of the insulating film can be increased, thereby shifting the threshold voltage of the thin film transistor in a positive direction, thereby improving reliability.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2011-222767 Summary of the invention

[0007] Problems to be solved by the invention

[0008] However, in the thin film transistor disclosed in Patent Document 1, since the necessary fixed charge is developed by reducing the film density, in other words, by deteriorating the film quality, there is a possibility that reliability may be reduced due to an increase in leakage current or environmental changes.

[0009] The present invention has been made in view of such problems, and a main object of the present invention is to efficiently generate necessary fixed charges in an insulating film used in a semiconductor element while suppressing degradation of film quality.

[0010] Technical means of solving problems

[0011] As a result of intensive studies to solve the above problems, the present inventors noticed that defects caused by atomic collisions generated in a film by ion implantation are distributed in a region shallower than the distribution of implanted ions, and conceived the present invention.

[0012] That is, the fixed charge control method of the present invention is a method for controlling fixed charges within an insulating film used in a semiconductor element, and the method is characterized in that a metal film is formed on the surface of the insulating film, and ions are implanted into the insulating film through the metal film, thereby expressing fixed charges in the insulating film.

[0013] If such a structure is used, since the ions are implanted into the insulating film through the metal film, the defects generated by the ion implantation are not distributed entirely in the insulating film but also in the metal film, thereby reducing the degradation of the film quality caused by the defects in the insulating film. In addition, by adjusting the thickness of the metal film or the range of the ions during ion implantation, the fixed charge density in the insulating film can be easily adjusted. For example, by thinning the metal film or increasing the depth of ion implantation so that most of the defects are distributed in the metal film, negative fixed charges can be efficiently displayed in the insulating film. On the other hand, by thinning the metal film or increasing the depth of ion implantation so that the distribution of defects formed in the insulating film is increased, positive fixed charges can also be efficiently displayed. In addition, since the film quality of the entire insulating film is not changed but only the film quality of the surface layer is changed by ion implantation, partial functions can be added while basically maintaining the original insulating properties of the insulating film.

[0014] Preferably, in the fixed charge control method, the thickness of the metal film is approximately the same as the average range of ions based on the ion implantation, and the sum of the thickness of the metal film and the thickness of the insulating film is greater than the sum of the average range of ions based on the ion implantation and its standard deviation.

[0015] In this way, by making the thickness of the metal film and the average range of the ions substantially the same, most of the implanted ions can be implanted into the lower insulating film, while most of the defects generated by atomic collisions can be retained in the upper metal film, so that negative fixed charges can be efficiently generated in the insulating film. In addition, since the sum of the thickness of the metal film and the thickness of the insulating film is made larger than the sum of the average range of the ions and the standard deviation thereof, the distribution of the implanted ions passing through the entire insulating film can be reduced, and the influence on the material in contact with the back side of the insulating film can be reduced.

[0016] As a specific form of the insulating film that significantly exhibits the effect of the fixed charge control method, an insulating film composed of an oxide film, a nitride film, or an oxynitride film can be cited.

[0017] Specific forms of the metal film that significantly demonstrate the effect of the fixed charge control method include metal films made of aluminum, aluminum alloys, molybdenum, molybdenum alloys, titanium, or titanium alloys.

[0018] As specific forms of ion types injected by the ion implantation that significantly exert the effect of the fixed charge control method, one or more of atomic ions such as O, N, C, molecular ions such as O2, N2, C2, or rare gas ions such as Ar can be listed.

[0019] In addition, the manufacturing method of the thin film transistor of the present invention is a method for manufacturing a top-gate thin film transistor, and the manufacturing method of the thin film transistor is characterized in that it includes: a channel layer forming step, forming a channel layer including an oxide semiconductor material on the surface of an insulating substrate; a gate insulating layer forming step, forming a gate insulating layer on the surface of the channel layer; a first gate electrode forming step, forming a first gate electrode layer including a metal material on the surface of the gate insulating layer; and a first ion implantation step, implanting ions into the gate insulating layer via the first gate electrode layer.

[0020] If this is a method for manufacturing a thin film transistor, the same effect as the fixed charge control method can be achieved. That is, for example, by ion implanting the gate insulating layer through the first gate electrode layer containing a metal material, the defects caused by the ion implantation are retained in the upper first gate electrode layer, and the implanted ions are mostly distributed near the interface between the gate insulating layer and the first gate electrode layer, so that the necessary fixed charge can be manifested. Thus, electrical characteristics can be controlled by fixed charges, and thin film transistors with high mobility and easy to operate at a positive threshold voltage can be manufactured.

[0021] In addition, preferably, the method for manufacturing the thin film transistor further includes: a second gate electrode forming step of forming a second gate electrode layer including a metal material having a thickness greater than that of the first gate electrode layer on a surface of the first gate electrode layer after the first ion implantation step.

[0022] In the first ion implantation step, the thickness of the first gate electrode through which ions pass needs to be reduced to the same extent as the range of the ions. By forming a thicker second gate electrode after the first ion implantation step, the gate electrode can be reliably functioned.

[0023] In addition, preferably, the manufacturing method of the thin film transistor further includes: an etching process, after a patterned anti-etching agent is stacked on the surface of the second gate electrode, the first gate electrode and the second gate electrode are patterned by etching, and in the etching process, a portion of the surface layer of the gate insulating layer that has been ion-implanted is removed.

[0024] In the upper layer of the gate insulating layer after the first ion implantation step, the region outside the gate electrode in the layer direction becomes the region connected to the source electrode and the drain electrode in the final structure of the thin film transistor. Therefore, by removing a portion of the surface layer of the gate insulating layer after ion implantation, leakage of current between the gate electrode and the source electrode and the drain electrode through the gate insulating layer can be prevented.

[0025] Preferably, the method further includes: a second ion implantation step of implanting ions into the channel layer through the gate insulating layer using the patterned first gate electrode layer, the second gate electrode layer, and the resist as masks after the etching step.

[0026] Thus, the final thin film transistor can be set as a self-aligned structure, which can reduce the parasitic capacitance between the first gate electrode layer and the second gate electrode layer and the source region and the drain region formed by ion implantation into the channel layer, and can suppress the deviation of the parasitic capacitance within the substrate surface, thereby enabling high-speed switching.

[0027] Preferably, heat treatment is performed after the first ion implantation step in order to further reduce the fixed charge of the gate insulating layer.

[0028] In addition, the thin film transistor of the present invention is a top-gate thin film transistor in which a channel layer including an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in sequence on a substrate, and the thin film transistor is characterized in that elements added by ion implantation are distributed near the interface between the gate insulating layer and the gate electrode layer.

[0029] If this thin film transistor is used, the same effects as those of the fixed charge control method and the method for manufacturing a thin film transistor can be achieved.

[0030] Effects of the Invention

[0031] According to the present invention thus constituted, necessary fixed charges can be efficiently generated in an insulating film used in a semiconductor element while suppressing degradation of film quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a cross-sectional view schematically showing the structure of a thin film transistor manufactured using the fixed charge control method of this embodiment.

[0033] Figure 2 This is a diagram for explaining the distribution of implanted ions and the distribution of defects by ion implantation.

[0034] Figure 3 It is a cross-sectional view schematically showing a manufacturing process of the thin film transistor according to the embodiment.

[0035] Figure 4 It is a figure which shows schematically the structure of the evaluation sample used in an Example.

[0036] Figure 5 It is a diagram showing the simulation results in Example 1 and is a diagram showing the relationship between the energy of implanted ions and the implantation depth.

[0037] Figure 6 It is a graph showing the measurement results in Example 1 and is a graph showing the relationship between the ion implantation amount and the fixed charge density.

[0038] Figure 7 It is a graph showing the measurement results in Example 2 and is a graph showing the relationship between the heat treatment after ion implantation and the fixed charge density.

[0039] [Explanation of Symbols]

[0040] 1: Thin Film Transistor

[0041] 2: Substrate

[0042] 3: Channel layer

[0043] 4: Gate insulation layer

[0044] 5: Gate electrode layer

[0045] 6: Insulation layer

[0046] 7: Source electrode

[0047] 8: Drain electrode DETAILED DESCRIPTION

[0048] Hereinafter, one embodiment of a thin film transistor 1 manufactured by the fixed charge control method of the present invention and a method for manufacturing the same will be described.

[0049] <1. Thin-film transistor>

[0050] The thin film transistor 1 of this embodiment is a so-called top-gate TFT, and is a thin film transistor using an oxide semiconductor in a channel. Figure 1 As shown, it has a substrate 2, a channel layer (active layer) 3, a gate insulating layer (equivalent to the insulating film of the claims) 4, a gate electrode layer 5, an insulating layer 6, a source electrode 7 and a drain electrode 8, and is formed in sequence from the substrate 2 side. Hereinafter, each part will be described in detail.

[0051] (1)Substrate

[0052] The substrate 2 includes any material that can transmit light, and may include, for example, plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic, polyimide, or glass.

[0053] (2) Channel layer

[0054] The channel layer 3 is a channel layer that forms a channel between the source electrode 7 and the drain electrode 8 by applying a gate voltage, so that current passes through. The channel layer 3 includes an oxide semiconductor, for example, an oxide of at least one element selected from In, Ga, Zn, Sn, Al, Ti, etc. as a main component. As specific examples of materials constituting the channel layer 3, for example, oxide materials with In2O3 as the main component, In-Ga-Zn-O (IGZO), In-Al-Mg-O, In-Al-Zn-O or In-Hf-Zn-O, etc. can be cited. The channel layer 3, for example, includes an amorphous (amorphous) oxide semiconductor film. The channel layer 3 of this embodiment is a single-layer structure, but is not limited to this, and can also be a stacked structure composed of multiple layers with different compositions or crystallinity overlapping.

[0055] The channel layer 3 is formed in a manner covering a portion of the surface of the substrate 2. In addition, a source region layer S and a drain region layer D are formed on the surface of the substrate 2 in a manner sandwiching the channel layer 3 from both sides and electrically connected to the channel layer 3. The source region layer S and the drain region layer D are electrically connected to the source electrode 7 and the drain electrode 8, respectively, via a contact hole H formed along the stacking direction. In addition, the contact hole H is filled with a metal such as molybdenum.

[0056] (3) Gate insulation layer

[0057] The gate insulating layer 4 is formed to cover the surface of the channel layer 3, the source region layer S, and the drain region layer D. The gate insulating layer 4 includes any insulating material such as an oxide film, a nitride film, or a nitride oxide film having high insulating properties. The gate insulating layer 4 may include, for example, a material selected from SiO x 、SiN x The gate insulating layer 4 may be an insulating film of one or more oxides of SiON, Al2O3, Y2O3, Ta2O5, Hf2, etc. The gate insulating layer 4 may be a gate insulating layer having these conductive films as a single layer structure or a stacked structure of two or more layers.

[0058] (4) Gate electrode layer

[0059] The gate electrode layer 5 is a gate electrode layer for controlling the carrier density in the channel layer 3 by applying a gate voltage to the thin film transistor 1. The gate electrode layer 5 is formed on the surface of the gate insulating layer 4 in a manner of being located directly above the channel layer 3. More specifically, the gate electrode layer 5 is formed in a manner in which the positions of its two end faces along the intralayer direction (direction orthogonal to the stacking direction) coincide with the positions of the two end faces of the channel layer 3. The gate electrode layer 5 includes any metal material having high conductivity, for example, it may include one or more metals selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, etc., and may also include alloys such as Al alloys, Ag alloys, Mo alloys, and Ti alloys.

[0060] The gate electrode layer 5 of this embodiment includes a stacked structure of two or more layers with different thicknesses, and includes, in order from the gate insulating layer 4 side, a first gate electrode layer (equivalent to the metal film of the claims) 51, and a second gate electrode layer 52 with a thickness greater than the first gate electrode layer 51. In addition, the first gate electrode layer 51 and the second gate electrode layer 52 may include the same metal material or different metal materials.

[0061] (5) Insulation layer

[0062] The insulating layer 6 insulates the gate electrode layer 5 from the source electrode 7 and the drain electrode 8 and includes, for example, a silicon oxide film containing fluorine. The insulating layer 6 is formed to cover the entire surface (upper surface and side surfaces) of the gate electrode layer 5 and the surface of the gate insulating layer 4.

[0063] (6) Source electrode, drain electrode

[0064] The source electrode 7 and the drain electrode 8 are formed separately from each other in a manner that partially covers the surface of the channel layer 3. The source electrode 7 and the drain electrode 8, like the gate electrode layer 5, contain a material having high conductivity so as to function as an electrode. The source electrode 7 and the drain electrode 8 may be a single-layer structure containing a single material, or a stacked structure in which a plurality of layers containing different materials are stacked. The source electrode 7 and the drain electrode 8 are electrically connected to the source region layer S and the drain region layer D, respectively, via a contact hole H that penetrates the insulating layer 6 and the gate insulating layer 4 along the stacking direction.

[0065] (7) Fixed charge in the gate insulating layer

[0066] Furthermore, in the thin film transistor 1 of the present embodiment, negative fixed charges formed (appeared) by ion implantation exist in the gate insulating layer 4 near the interface with the gate electrode layer 5 .

[0067] In the thin film transistor 1 of this embodiment, by adjusting the thickness d of the first gate electrode layer 51 M, the thickness d of the gate insulating layer 4 i , the average range R of the implanted ions (e.g., atomic ions such as O, N, C, molecular ions such as O2, N2, C2, and rare gas ions such as Ar) p , and its standard deviation ΔR p By adjusting the relationship between the gate insulating layer 4 and the gate insulating layer 4, most of the injected ions (for example, atomic ions such as O, N, and C, molecular ions such as O2, N2, and C2, and rare gas ions such as Ar) are retained in the gate insulating layer 4, and the lattice defects caused by the ion injection in the gate insulating layer 4 are reduced. Specifically, in the thin film transistor 1 of the present embodiment, it is constructed in a manner that satisfies both the following conditions (A) and (B).

[0068] (A) Thickness d of the first gate electrode layer 51 M Compared with the average range R of ions based on ion implantation p Roughly the same (d M ≒R p )

[0069] (B) Thickness d of the first gate electrode layer 51 M The thickness d of the gate insulating layer 4 i The sum is greater than the average range R of the ions based on ion implantation p Its standard deviation ΔR p The sum (d M +d i >R p +ΔR p )

[0070] In addition, the so-called average range of ions R p , is the depth position of the maximum value of the probability distribution of the ion implanted ions in the film along the depth direction (stacking direction), and the standard deviation ΔR at this time p It is an index showing the spread of the distribution toward the inner side (intra-layer direction side).

[0071] Furthermore, both the first gate electrode layer 51 and the gate insulating layer 4 have implanted ions and defects caused by ion implantation distributed in the layers. Figure 2 As shown, the implanted ions have the highest density near the interface between the first gate electrode layer 51 and the gate insulating layer 4, and are more distributed in the gate insulating layer 4 than in the first gate electrode layer 51. On the other hand, the defects caused by ion implantation have the highest density in the first gate electrode layer 51, and are more distributed in the first gate electrode layer 51 than in the gate insulating layer 4. In addition, the second gate electrode layer 52 formed on the first gate electrode layer 51 does not form implanted ions and lattice defects caused by ion implantation.

[0072] In addition, from the perspective of element distribution, in the thin film transistor 1 of this embodiment, the element added by ion implantation is distributed near the interface between the gate insulating layer 4 and the first gate electrode layer 51. Furthermore, the element added by ion implantation is also distributed near the interface between the first gate electrode layer 51 and the gate insulating layer 4.

[0073] <2. Method for manufacturing thin film transistor>

[0074] Next, refer to Figure 3 The manufacturing method of the thin film transistor 1 of the above structure is described. The manufacturing method of the thin film transistor 1 of the present embodiment includes a channel layer forming step, a gate insulating layer forming step, a gate electrode forming step, a source region / drain region forming step, an insulating layer forming step, and a source electrode / drain electrode forming step. Each step is described below.

[0075] (1) Channel layer formation process

[0076] First, a channel layer 3 is formed on a substrate 2. The channel layer 3 can be formed by a known method. For example, the channel layer 3 can be formed by sputtering a conductive oxide sintered body such as InGaZnO as a target using plasma to cover the entire surface of the substrate 2. In addition, the present invention is not limited to this, and the channel layer 3 including an oxide semiconductor can also be formed by other methods.

[0077] (2) Gate Insulation Layer Formation Step

[0078] Next, a gate insulating layer 4 made of any insulating material such as an oxide film, a nitride film, or a nitride oxide film is formed on the channel layer 3. Here, the gate insulating layer 4 is formed to cover the entire surface of the channel layer 3 by a known method such as plasma chemical vapor deposition (CVD).

[0079] (3) Gate Electrode Formation Step

[0080] Next, the gate electrode layer 5 is formed on the gate insulating layer 4. The above process includes a first gate electrode forming process, a first ion implantation process, and a second gate electrode forming process in sequence.

[0081] (3-1) First Gate Electrode Forming Step

[0082] First, a first gate electrode layer 51 made of a metal material such as a metal or an alloy is formed on the gate insulating layer 4 by a known method such as vacuum evaporation. The first gate electrode layer 51 can be formed to cover the entire surface of the gate insulating layer 4. Here, the thickness of the formed first gate electrode layer 51 satisfies the above condition (A). M≒R p and condition (B)d M +d i >R p +ΔR p .

[0083] (3-2) First ion implantation step

[0084] Then, if Figure 3 As shown in (a), ions are implanted into the gate insulating layer 4 through the formed first gate electrode layer 51. The ion implantation can be performed by a known ion implantation method. The ion implantation process is performed by implanting ions into the entire surface of the gate insulating layer 4 when viewed from the stacking direction. The types of ions implanted are, for example, atomic ions such as O, N, and C, molecular ions such as O2, N2, and C2, and rare gas ions such as Ar, but are not limited to these. The ion energy is, for example, 5keV to 30keV, but is not limited to this. In addition, the ion implantation amount (dose) is, for example, 1×10 13 ions / cm 2 ~1×10 15 ions / cm 2 , but not limited to this. The ion energy and ion injection amount are based on the average range R of the ions. p The above-mentioned conditions (A) and (B) are set so as to be satisfied. Thus, negative fixed charges are formed in the vicinity of the interface between the gate insulating layer 4 and the first gate electrode layer 51 .

[0085] (3-3) Second Gate Electrode Forming Step

[0086] After the first ion implantation step, Figure 3 As shown in (b), the second gate electrode layer 52 is formed on the first gate electrode layer 51. The second gate electrode layer 52 can be formed in a manner that covers the entire surface of the first gate electrode layer 51. The second gate electrode layer 52 is formed by a known method such as a vacuum evaporation method in a manner that its thickness is greater than that of the first gate electrode layer 51.

[0087] (4) Source Region / Drain Region Formation Step

[0088] Then, if Figure 3 As shown in (c), the source region layer S and the drain region layer D are formed so as to sandwich the channel layer 3. The above steps include a resist patterning step, an etching step, and a second ion implantation step.

[0089] (4-1) Resist Patterning Step

[0090] First, a photoresist R is applied on the gate electrode layer 5 (specifically, the second gate electrode layer 52 ), and then exposed and developed. The photoresist R is selectively applied only on the gate electrode layer 5 directly above the portion that will eventually become the channel layer 3 .

[0091] (4-2) Etching process

[0092] Next, the portion of the gate electrode layer 5 not coated with the photoresist R is removed by etching, and the first gate electrode layer 51 and the second gate electrode layer 52 are patterned. In the etching step, the region near the interface with the gate electrode layer 5 in the gate insulating layer 4 (i.e., the surface region where ions were implanted in the first ion implantation step) is removed.

[0093] (4-3) Second ion implantation step

[0094] Next, ion implantation is performed into the region outside the gate electrode layer 5 in the channel layer 3 through the etched gate insulating layer 4, thereby forming a source region layer S and a drain region layer D on both sides of the channel layer 3. In the ion implantation step, the stacked photoresist R and the gate electrode layer 5 are used as masks. In addition, the ion implantation in the step can be performed by any known method.

[0095] (5) Insulation layer forming process

[0096] After the second ion implantation step, Figure 3 As shown in (d), the photoresist R is removed to form an insulating layer 6. The insulating layer 6 is formed to cover the entire surface of the gate insulating layer 4 and the gate electrode layer 5. The insulating layer 6 can be formed by any method such as a plasma CVD method.

[0097] (6) Source Electrode / Drain Electrode Formation Process

[0098] Then, if Figure 3 As shown in (e), a source electrode 7 and a drain electrode 8 are formed on the gate insulating layer 4. The source electrode 7 and the drain electrode 8 can be formed by a known method such as radio frequency (RF) magnetron sputtering. The source electrode 7 and the drain electrode 8 are respectively connected to the source region layer S and the drain region layer D via a contact hole H formed along the stacking direction by etching or the like.

[0099] (7) Heat treatment process

[0100] In addition, as needed, after the first ion implantation step and / or the second ion implantation step, heat treatment may be performed in an environment containing oxygen under atmospheric pressure. The fixed charge formed in the gate insulating layer 4 can be further reduced by performing the heat treatment step, and the interface defects of the gate insulating layer 4 / oxide semiconductor layer 3 can be reduced. The furnace temperature during the heat treatment is not particularly limited, for example, it is 150° C. or more and 300° C. or less. In addition, the heat treatment time is not particularly limited, for example, it is 1 hour to 3 hours.

[0101] Through the above operations, the thin film transistor 1 of this embodiment can be obtained.

[0102] <3. Effects of the present embodiment>

[0103] According to the manufacturing method of the thin film transistor 1 of the present embodiment, by performing ion implantation into the gate insulating layer 4 via the first gate electrode layer 51 containing a metal material, defects caused by the ion implantation are retained in the upper first gate electrode layer 51, and the implanted ions are mostly distributed near the interface with the first gate electrode layer 51 in the gate insulating layer 4, so that necessary fixed charges can be manifested. In addition, by adjusting the thickness of the first gate electrode layer 51 during ion implantation or the range of ions caused by ion implantation, the negative fixed charge density in the gate insulating layer 4 can be efficiently adjusted. Thus, electrical characteristics can be controlled by fixed charges, and a thin film transistor 1 with high mobility and easy to operate at a positive threshold voltage can be manufactured.

[0104] In addition, the fixed charge control method of the present invention is not limited to the above-described embodiment.

[0105] For example, in the above embodiment, the method for manufacturing the thin film transistor 1 is described as an example of the fixed charge control method, but the present invention is not limited thereto. In other embodiments, the fixed charge control method of the present invention can be used in methods for manufacturing semiconductor elements other than thin film transistors.

[0106] In addition, in the manufacturing method of the embodiment, negative fixed charges are displayed in the insulating film (gate insulating layer 4) on the front channel side of the thin film transistor 1, but the present invention is not limited thereto. In other embodiments, an insulating layer may be formed on the back channel side of the thin film transistor 1, and positive fixed charges are displayed in the insulating layer.

[0107] In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, it can be understood by those skilled in the art that the above-described multiple exemplary embodiments are specific examples of the following forms.

[0108] (Form 1) A fixed charge control method is a method for controlling fixed charges within an insulating film used in a semiconductor element, wherein a metal film is formed on the surface of the insulating film, and ions are implanted into the insulating film through the metal film, thereby causing fixed charges to appear in the insulating film.

[0109] (Form 2) A fixed charge control method according to Form 1, wherein the thickness of the metal film is approximately the same as the average range of ions based on the ion injection, and the sum of the thickness of the metal film and the thickness of the insulating film is greater than the sum of the average range of ions based on the ion injection and its standard deviation.

[0110] (Form 3) The fixed charge control method according to Form 1 or 2, wherein the insulating film is composed of an oxide film, a nitride film, or a nitride oxide film.

[0111] (Form 4) The fixed charge control method according to any one of Forms 1 to 3, wherein the metal film includes aluminum, an aluminum alloy, molybdenum, a molybdenum alloy, titanium, or a titanium alloy.

[0112] (Form 5) A fixed charge control method according to any one of Forms 1 to 4, wherein the type of ions injected by the ion injection is one or more selected from atomic ions such as O, N, C, molecular ions such as O2, N2, C2, or rare gas ions such as Ar.

[0113] (Form 6) A method for manufacturing a thin film transistor, which is a method for manufacturing a top-gate thin film transistor, the method for manufacturing a thin film transistor comprising: a channel layer forming step, forming a channel layer comprising an oxide semiconductor material on the surface of an insulating substrate; a gate insulating layer forming step, forming a gate insulating layer on the surface of the channel layer; a first gate electrode forming step, forming a first gate electrode layer comprising a metal material on the surface of the gate insulating layer; and a first ion implantation step, implanting ions into the gate insulating layer via the first gate electrode layer.

[0114] (Form 7) The method for manufacturing a thin film transistor according to Form 6 further includes: a second gate electrode formation step, after the first ion implantation step, forming a second gate electrode layer on the surface of the first gate electrode layer, which includes a metal material having a thickness greater than that of the first gate electrode layer.

[0115] (Form 8) The method for manufacturing a thin film transistor according to Form 7 further includes: an etching step, wherein after a patterned resist is stacked on the surface of the second gate electrode, the first gate electrode and the second gate electrode are patterned by etching, and in the etching step, a portion of the surface layer of the gate insulating layer into which ions have been implanted is removed.

[0116] (Form 9) The method for manufacturing a thin film transistor according to Form 8 further includes: a second ion implantation process, after the etching process, using the patterned first gate electrode layer, the second gate electrode layer and the resist as masks to implant ions into the channel layer through the gate insulating layer.

[0117] (Form 10) The method for manufacturing a thin film transistor according to any one of Forms 6 to 9, wherein heat treatment is performed after the first ion implantation step.

[0118] (Form 11) A thin film transistor is a top-gate thin film transistor in which a channel layer including an oxide semiconductor, a gate insulating layer, and a gate electrode layer are stacked in sequence on a substrate, and elements added by ion implantation are distributed near the interface between the gate insulating layer and the gate electrode layer.

[0119] Example

[0120] The present invention is not limited to the following examples, and can be implemented by appropriately adding modifications within the scope of the above and the following gist, and all of these are included in the technical scope of the present invention.

[0121] <Example 1. Relationship between the presence or absence of a metal layer and the amount of ion implantation and fixed charge density>

[0122] The presence or absence of a metal layer during ion implantation and the relationship between the ion implantation amount and the fixed charge density were evaluated.

[0123] (1) Evaluation samples

[0124] In the described embodiment, Figure 4 As shown in the figure, two types of evaluation samples were prepared, namely, a plurality of samples in which a thermal silicon oxide film and a metal layer were stacked on a silicon substrate (samples with a metal layer), and a plurality of samples in which only a thermal silicon oxide film was stacked on a silicon substrate (samples without a metal layer). In each evaluation sample, an n-type silicon substrate with a resistivity of 1Ωcm to 10Ωcm was used. In addition, in each evaluation sample, the film thickness of the thermal silicon oxide film was set to 100nm. In addition, in the sample with a metal layer, an Al-Si alloy film with a film thickness of about 10nm was formed as the metal layer.

[0125] (2) Ion implantation

[0126] Then, ion implantation was performed on each of the prepared evaluation samples by changing the ion implantation amount and the type of ions to be implanted. The ion implantation amount (dose amount) was set to 1×10 13 ions / cm 2 ~1×10 15ions / cm 2 In addition, the implanted ion species is set to N + , O + ,Ar + In addition, for all evaluation samples, the implanted ion energy was set to 10 keV. In addition, the implanted ions (N + , O + ,Ar + The relationship between the ion energy and the implantation depth is shown in Figure 5 In the above simulation, the target of ion implantation was a silicon oxide film (film thickness: 100 nm) on a Si substrate, and the energy of the implanted ions was 5 keV to 30 keV.

[0127] (3) Evaluation of fixed charge density

[0128] Then, the fixed charge density of the thermal silicon oxide film in each evaluation sample after ion implantation was measured by the capacitance-voltage (CV) method. In addition, for samples without a metal layer, an electrode in contact with the thermal silicon oxide film was formed. The results are shown in Figure 6 middle.

[0129] like Figure 6 As shown in the figure, compared with the fixed charge density of the thermal oxide film measured before ion implantation (about 3×10 11 / cm 2 ), an increase in positive fixed charge can be seen in the sample without a metal layer after ion implantation. Since defects in silicon oxide are generally known to exhibit positive fixed charge, it is believed that in the ion implantation of the sample without a metal layer, the positive charge increases due to the defects generated during the ion implantation.

[0130] On the other hand, in the sample with a metal layer in which ion implantation was performed via the metal layer (Al-Si), a decrease in positive fixed charge was observed. It is known that in the ion implantation via the metal layer, negative charge can be generated to the extent that the original charge amount can be almost eliminated. According to the above results, in the ion implantation via the metal layer, the defects caused by the ion implantation can be confined within the metal layer, so that negative fixed charge can be manifested near the interface between the silicon oxide film and the metal layer where the implanted ions are distributed.

[0131] In addition, according to Figure 5 As shown in the depth distribution of implanted ions, light elements penetrate deeper than heavy elements, and according to N + , O + ,Ar +Therefore, when the thickness of the metal layer of the evaluation sample having a metal layer is the same, it is easier to generate injection defects in the silicon oxide film by injecting light elements as injection ions than by injecting heavy elements. Figure 6 It is considered that the reason is that the fixed charge density of the silicon oxide film is different depending on the type of ions implanted.

[0132] Based on the above results, it can be confirmed that the negative fixed charge density (or charge amount) formed in the silicon oxide film can be controlled by the type of ions injected and the amount of ion injection. In addition, it can be confirmed that by making the thickness of the silicon oxide film sufficiently smaller than the ion injection depth, additional functions can be added without damaging the function as an insulating film.

[0133] <Example 2. Relationship between heat treatment after ion implantation and fixed charge density>

[0134] Next, the relationship between the heat treatment after ion implantation and the fixed charge density was evaluated.

[0135] (1) Evaluation samples

[0136] In the example, a plurality of samples having a metal layer were prepared under the same conditions as in the first example.

[0137] (2) Ion implantation

[0138] Then, for each sample having a metal layer, ion implantation was performed by changing the ion implantation amount and the type of ions implanted. The conditions for ion implantation were the same as those in the first embodiment. In addition, in the embodiment, the implantation ion type was set to N + , O + .

[0139] (3) Heat treatment

[0140] Then, each sample having a metal layer after ion implantation was subjected to heat treatment. The heat treatment was performed for 2 hours in an atmosphere (200° C.) containing oxygen under atmospheric pressure.

[0141] (4) Evaluation of fixed charge density

[0142] Then, the fixed charge density of the thermally oxidized silicon film in each evaluation sample after the heat treatment was measured by the CV method. In addition, in the above-mentioned embodiment, the fixed charge density of each evaluation sample before the heat treatment was also measured in advance by the CV method. The results are shown in Figure 7 middle.

[0143] like Figure 7As shown, it can be confirmed that in the embodiment, when ion implantation is performed via the metal layer, the positive fixed charge density can be reduced regardless of the subsequent heat treatment. In addition, it can be confirmed that the positive fixed charge density is further uniformly reduced by performing heat treatment after ion implantation. It is believed that the reason is that in ion implantation via the metal layer, the defect distribution (positive charge) generated by crossing the metal layer is reduced by heat treatment, and the negative increase caused by the implanted ions is more significantly manifested.

[0144] Industrial Applicability

[0145] According to the fixed charge control method of the present invention, necessary fixed charges can be efficiently generated in an insulating film used in a semiconductor element while suppressing degradation of the film quality.

Claims

1. A fixed charge control method, which is a method for controlling fixed charges in an insulating film used in a semiconductor element, wherein: A metal film is formed on the surface of the insulating film, and ions are implanted into the insulating film through the metal film so that the implanted ions are distributed in the insulating film near the interface with the metal film, thereby generating fixed charges in the insulating film, wherein The thickness of the metal film is equal to the average range of ions by the ion implantation, so that most of the defects generated by atomic collisions remain in the metal film.

2. The fixed charge control method according to claim 1, wherein: A sum of a thickness of the metal film and a thickness of the insulating film is greater than a sum of an average range of ions based on the ion implantation and a standard deviation thereof.

3. The fixed charge control method according to claim 1, wherein: The insulating film is composed of an oxide film, a nitride film, or a nitride oxide film.

4. The fixed charge control method according to claim 1, wherein: The metal film includes aluminum, aluminum alloy, molybdenum, molybdenum alloy, titanium or titanium alloy.

5. The fixed charge control method according to claim 1, wherein: The type of ions implanted in the ion implantation is selected from one or more of O atomic ions, N atomic ions, C atomic ions, O2 molecular ions, N2 molecular ions, or Ar ions.

6. A method for manufacturing a thin film transistor, which is a method for manufacturing a top-gate thin film transistor, the method for manufacturing a thin film transistor comprising: a channel layer forming step of forming a channel layer including an oxide semiconductor material on a surface of an insulating substrate; A gate insulating layer forming step, forming a gate insulating layer on the surface of the channel layer; A first gate electrode forming step of forming a first gate electrode layer including a metal material on a surface of the gate insulating layer; as well as In the first ion implantation process, ions are implanted into the gate insulating layer via the first gate electrode layer, so that the implanted ions are distributed in the gate insulating layer near the interface with the first gate electrode layer, wherein the thickness of the first gate electrode layer is the same as the average range of the ions based on the ion implantation, so that most of the defects generated by atomic collisions remain in the first gate electrode layer.

7. The method for manufacturing a thin film transistor according to claim 6 further comprises: a second gate electrode forming step, after the first ion implantation step, forming a second gate electrode layer containing a metal material having a thickness greater than that of the first gate electrode layer on a surface of the first gate electrode layer.

8. The method for manufacturing a thin film transistor according to claim 7, further comprising: an etching step of patterning the first gate electrode and the second gate electrode by etching after a patterned resist is stacked on a surface of the second gate electrode; In the etching step, a portion of the surface layer of the gate insulating layer into which the ions have been implanted is removed. 9 . The method for manufacturing a thin film transistor according to claim 8 , further comprising: after the etching step, a second ion implantation step of implanting ions into the channel layer through the gate insulating layer using the patterned first gate electrode layer, the second gate electrode layer and the resist as masks.

10. The method for manufacturing a thin film transistor according to claim 6, wherein: After the first ion implantation step, heat treatment is performed.

11. A thin film transistor, which is a top-gate thin film transistor in which a channel layer including an oxide semiconductor, a gate insulating layer, and a gate electrode layer are sequentially stacked on a substrate, The elements added by ion implantation are distributed near the interface between the gate insulating layer and the gate electrode layer, and the elements added by ion implantation are also distributed near the interface between the gate electrode layer and the gate insulating layer, wherein the thickness of the gate electrode layer is the same as the average range of ions based on the ion implantation, so that most of the defects generated by atomic collisions remain in the gate electrode layer.

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