Method for measuring contact resistance of field effect transistor

Abstract

A field effect transistor comprises a gate, an insulating layer, a source, a drain and a channel layer, the insulating layer is on the surface of the gate, the channel layer is on the surface of the insulating layer away from the gate, the source and the drain are arranged on the surface of the channel layer away from the insulating layer; the source and the drain are one-dimensional structures. The application further provides a preparation method of the field effect transistor and a method for measuring the contact resistance of the field effect transistor.

Description

Technical Field

[0001] This invention relates to a method for measuring the contact resistance of a field-effect transistor. Background Technology

[0002] The ultimate miniaturization of transistors is a relentless pursuit of the integrated circuit industry. Reducing channel length and contact length is essential for minimizing the overall device size. Two-dimensional semiconductors show great potential in reducing channel length because their ultra-thin atomic structure effectively suppresses short-channel effects. Therefore, field-effect transistors (FETs) with shorter gate lengths can be developed using two-dimensional semiconductors. Shortening the contact length increases contact resistance and degrades the conductivity of the contact material itself. For traditional three-dimensional metals, when the contact length is reduced to below 10 nm, severe domaining occurs in the metal lines, significantly increasing resistivity. For two-dimensional semi-metals such as graphene, reducing the contact length to below 10 nm leads to additional quantization and severe edge scattering. These limitations degrade the contact performance of FETs. Therefore, achieving ultra-short contact lengths and low contact resistance in high-performance two-dimensional FETs remains a significant challenge. Furthermore, methods for measuring the contact resistance of FETs with ultra-short contact lengths and low contact resistance also present a considerable challenge. Summary of the Invention

[0003] In view of this, it is indeed necessary to provide a method for measuring the contact resistance of field-effect transistors with ultra-short contact length and low contact resistance.

[0004] A method for measuring the contact resistance of a field-effect transistor, comprising the following steps:

[0005] A field-effect transistor is provided, comprising a gate, an insulating layer, a source, a drain, and a channel layer. The insulating layer is located on the surface of the gate, and the channel layer is located on the surface of the insulating layer away from the gate. The source and the drain are spaced apart on the surface of the channel layer away from the insulating layer. Both the source and the drain are metallic single-walled carbon nanotubes. The channel layer is made of molybdenum disulfide, and multiple electrodes are disposed on the metallic single-walled carbon nanotubes and the channel layer, respectively. The insulating layer is made of silicon dioxide.

[0006] Formula I is provided: Among them, R tot It is the resistance between two metallic single-walled carbon nanotubes. It is the interfacial contact resistance between the metallic single-walled carbon nanotube and the electrode. It is a quantum resistance of metallic SWCNT. The resistivity, L, of metallic single-walled carbon nanotubes on silicon dioxide. inIt is the distance from the electrode to the channel layer. r c D represents the interfacial resistivity between the metallic single-walled carbon nanotube and the channel layer. CNT It is the diameter of the metallic single-walled carbon nanotube. L is the sheet resistance of the channel layer, and L is the length of the channel layer between the source and the drain. is the resistivity of the metallic single-walled carbon nanotubes on the molybdenum disulfide, and W is the width of the channel layer. The interfacial resistivity r between the metallic single-walled carbon nanotube and the channel layer is calculated using Formula I. c ;as well as

[0007] The contact resistance R between the metallic single-walled carbon nanotube and the channel layer c Satisfying formula R c =r c / lc, where l C The diameter of the metallic single-walled carbon nanotube is used to obtain the contact resistance between the metallic single-walled carbon nanotube and the channel layer.

[0008] Furthermore, a pseudocolor scanning electron microscope (SEM) image of the field-effect transistor is formed. In the pseudocolor SEM image, the first line represents the metallic single-walled carbon nanotube as the source, and the second line represents the metallic single-walled carbon nanotube as the drain. Point A is defined on the first line, and point B is defined on the second line. The electrode is disposed at both points A and B, and the line connecting points A and B is parallel to the length direction of the channel layer.

[0009] Furthermore, R tot It is the resistance between the electrodes at points A and B.

[0010] Furthermore, the resistivity of metallic single-walled carbon nanotubes on silica was obtained based on the transfer length method. Resistivity of metallic single-walled carbon nanotubes on molybdenum disulfide and the interfacial contact resistance between the metallic single-walled carbon nanotube and the electrode.

[0011] Furthermore, the length L from the electrode to the channel layer is measured using a scanning electron microscope or an atomic force microscope. in The diameter D of the metallic single-walled carbon nanotube CNT The length L and width W of the channel layer between the source and the drain.

[0012] Furthermore, the resistance R between the two metallic single-walled carbon nanotubes was measured using a power meter.tot Furthermore, the sheet resistance of the channel layer was obtained using the four-probe method.

[0013] Furthermore, the quantum resistance of the metallic single-walled carbon nanotubes... It is 6.5 kΩ. Furthermore, the interfacial resistivity r between the metallic single-walled carbon nanotube and the channel layer... c 10 -6 Ω·cm 2 The contact resistance between the metallic single-walled carbon nanotube and the channel layer is 50 kΩ·μm.

[0014] Furthermore, the method for measuring the interface resistance between the drain and the channel layer is the same as the method for measuring the interface resistance between the source and the channel layer.

[0015] Compared with existing technologies, this invention achieves one-dimensional half-metal contact by setting two SWCNTs with the same chirality on a two-dimensional semiconductor, successfully reducing the contact length of the field-effect transistor to 2nm, thus enabling the field-effect transistor to have an ultra-short contact length. This invention proposes a "longitudinal transmission line model," providing the two-terminal resistance of the field-effect transistor with an extremely short metallic SWCNT contact. Based on this, and combining the four-probe method and the transfer length method to extract relevant position parameters, the contact resistance of the field-effect transistor can be calculated, i.e., the interface resistance between the source (or drain) and the channel layer in the field-effect transistor. Moreover, in the ohmic contact mode, the resistivity (i.e., contact resistivity) and contact resistance of the interface contact between the metallic SWCNT and the channel layer are 10... -6 Ω·cm 2 With a resistance of 50 kΩ·μm, the field-effect transistor has a low contact resistance. Attached Figure Description

[0016] Figure 1 A schematic diagram of the structure of the field-effect transistor provided by the present invention.

[0017] Figure 2 A flowchart illustrating the fabrication method of the field-effect transistor provided by this invention.

[0018] Figure 3 This is a schematic diagram of the carbon nanotube preparation apparatus provided by the present invention.

[0019] Figure 4 A schematic diagram of the structure of carbon nanotubes horizontally falling on a substrate with multiple grooves, provided by the present invention.

[0020] Figure 5The image provided for this invention is a transmission electron microscopy (TEM) image of the cross-section of the source and drain electrodes disposed on the channel layer.

[0021] Figure 6 The present invention provides an overall electron energy loss spectroscopy (EELS) of the source and drain electrodes formed on the channel layer.

[0022] Figure 7 The Raman spectrum of the entire structure formed by the source and drain electrodes disposed on the channel layer, as provided in this invention.

[0023] Figure 8 The image provided by this invention is a false-colored scanning electron microscope (false-colored SEM) image of the field-effect transistor.

[0024] Figure 9 for Figure 8 The transfer characteristics between points A and B.

[0025] Figure 10 for Figure 8 Barrier heights at the interface between the metallic SWCNT and MoS2 and between the Au / Ti electrode and MoS2 at different gate voltages.

[0026] Figure 11 for Figure 8 The energy band diagram of the contact between points A and B and the contact between points 1 and 2.

[0027] Figure 12 for Figure 1 The interfacial contact resistivity-gate voltage diagram between the metallic SWCNT and the MoS2 film in the field-effect transistor described in the paper.

[0028] Figure 13 The results are obtained by analyzing multiple groups of CNT devices using the transfer length method.

[0029] Figure 14 For measurement Figure 1 The longitudinal transmission line model of the interface resistance between the source, drain and channel layers in the field-effect transistor described in the paper.

[0030] Figure 15 Resistivity-voltage curves for metallic SWCNTs on silicon dioxide and metallic SWCNTs on MoS2 film.

[0031] Figure 16The sheet resistance-voltage curve of the MoS2 film is shown.

[0032] Figure 17 The results show the measurement of each feature length using an atomic force microscope.

[0033] Explanation of main component symbols

[0034] Field-effect transistor 100

[0035] Gate 102

[0036] Insulation layer 104

[0037] Channel layer 106

[0038] Source 108

[0039] Drain 110

[0040] Growth device 30

[0041] Heating Furnace 302

[0042] Reaction chamber 304

[0043] 306 air intake

[0044] 308 air outlet

[0045] Fixed Platform 310

[0046] Rotary platform 312

[0047] Growth substrate 316

[0048] Catalyst layer 318

[0049] Matrix 10

[0050] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0051] The method for measuring the contact resistance of a field-effect transistor provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] Please see Figure 1 A first embodiment of the present invention provides a field-effect transistor 100, which includes a gate 102, an insulating layer 104, a source 108, a drain 110, and a channel layer 106. The insulating layer 104 is located on the surface of the gate 102, and the channel layer 106 is located on the surface of the insulating layer 104 away from the gate 102. The source 108 and the drain 110 are spaced apart on the surface of the channel layer 106 away from the insulating layer 104.

[0053] The gate 102 is made of a material with good conductivity. Specifically, the gate 102 can be made of conductive materials such as metals, alloys, indium tin oxide (ITO), antimony tin oxide (ATO), conductive silver paste, conductive polymers, and carbon nanotube films. The metal or alloy can be aluminum, copper, tungsten, molybdenum, gold, or alloys thereof. Specifically, the thickness of the gate 102 is 0.5 nanometers to 100 micrometers. In this embodiment, the gate 102 is highly doped silicon (highly doped silicon is conductive).

[0054] The insulating layer 104 can be made of rigid materials such as silicon nitride and silicon oxide, or flexible materials such as benzocyclobutene (BCB), polyester, or acrylic resin. Depending on the material of the insulating layer 104, different methods can be used to form it. Specifically, when the material of the insulating layer 104 is silicon nitride or silicon oxide, it can be formed by deposition. When the material of the insulating layer 104 is benzocyclobutene (BCB), polyester, or acrylic resin, it can be formed by printing and coating. The thickness of the insulating layer 104 is 0.5 nanometers to 100 micrometers. In this embodiment, the surface of the highly doped silicon wafer has a 300 nm thick oxide layer, the material of which is SiO2 (silicon dioxide), and this oxide layer is the insulating layer 104.

[0055] The channel layer 106 is a two-dimensional semiconductor structure, such as a molybdenum disulfide (MoS2) film, a tungsten disulfide (WS2) film, or a tungsten diselenide (WSe2) film, etc.

[0056] The source electrode 108 and drain electrode 110 should be made of materials with good conductivity, and the source electrode 108 and drain electrode 110 should be one-dimensional structures. Specifically, the materials of the source electrode 108 and drain electrode 110 can be conductive materials such as metals, alloys, ITO, ATO, conductive silver paste, conductive polymers, and metallic carbon nanotubes. Specifically, when the materials of the source electrode 108 and drain electrode 110 are metals, alloys, ITO, or ATO, the source electrode 108 and drain electrode 110 can be formed by methods such as evaporation, sputtering, deposition, masking, and etching. When the materials of the source electrode 108 and drain electrode 110 are conductive silver paste, conductive polymers, or carbon nanotubes, the conductive silver paste or carbon nanotubes can be coated or adhered to the surface of the insulating layer 104 away from the gate electrode 102 by printing or direct adhesion methods to form the source electrode 108 and drain electrode 110. The thickness of the source electrode 108 and the drain electrode 110 is 0.5 nanometers to 100 micrometers, and the distance between the source electrode 108 and the drain electrode 110 is 10 nanometers to 800 nanometers. In this embodiment, both the source electrode 108 and the drain electrode 110 are single metallic single-walled carbon nanotubes (SWCNTs), and the distance between the source electrode 108 and the drain electrode 110 is 150 nanometers.

[0057] Furthermore, the field-effect transistor 100 may further include an insulating substrate that supports the gate 102, meaning the insulating layer 104 is located on the surface of the gate 102 away from the insulating substrate. The insulating substrate can be made of rigid materials such as glass, quartz, ceramic, diamond, or silicon wafers, or flexible materials such as plastics or resins. In one specific embodiment, the insulating substrate is made of glass. The insulating substrate can also be a substrate used in large-scale integrated circuits, and multiple back-gate field-effect transistors 100 can be integrated onto the same insulating substrate according to a predetermined pattern or design.

[0058] Furthermore, the field-effect transistor 100 includes multiple electrodes, which are respectively disposed on the channel layer 106, the source 108, and the drain 110. The multiple electrodes are spaced apart, and the distance between adjacent electrodes is not equal. All electrodes are composed of conductive materials, which can be metals, ITO, ATO, conductive silver paste, conductive polymers, and conductive carbon nanotubes, etc. The metal material can be aluminum, copper, tungsten, molybdenum, gold, titanium, palladium, or any combination of alloys. The electrode can also be a conductive thin film with a thickness of 0.01 micrometers to 10 micrometers. In this embodiment, the electrode is an Au / Ti (gold / titanium, 50nm / 5nm thickness) electrode, which is formed by stacking a 50nm thick gold layer and a 5nm thick titanium layer. The Au layer is disposed on the upper surface of the Ti layer, with the Ti layer serving as an adhesion layer and the Au layer as a conductive layer. The electrode can be deposited by methods such as evaporation, sputtering, deposition, masking, etching, printing coating, or direct adhesion.

[0059] Please see Figure 2 The first embodiment of the present invention further provides a method for fabricating the field-effect transistor 100, which includes the following steps:

[0060] S1, forming the insulating layer 104 on the surface of the gate 102;

[0061] S2, forming the channel layer 106 on the surface of the insulating layer 104 away from the gate 102;

[0062] S3, two conductive one-dimensional structures are spaced apart on the surface of the channel layer 106 away from the insulating layer 104; and

[0063] S4, multiple electrodes are disposed on the one-dimensional structure and multiple electrodes are disposed on the channel layer 106. The multiple electrodes are disposed at intervals and the distance between adjacent electrodes is not equal.

[0064] Furthermore, the method for fabricating the field-effect transistor 100 may further include the step of disposing the gate 102 on the insulating substrate. The insulating substrate may be a substrate used in large-scale integrated circuits.

[0065] In step S1, the insulating layer 104 can be formed on the surface of the gate 102 by sputtering, vapor deposition, direct deposition, or other methods.

[0066] In step S2, the channel layer 106 can be formed on the surface of the insulating layer 104 away from the gate 102 by methods such as sputtering, evaporation, or direct deposition. In a specific embodiment, the two-dimensional semiconductor material is directly deposited on the surface of the insulating layer 104 away from the gate 102.

[0067] In step S3, the conductive one-dimensional structure serves as the source 108 and the drain 110, respectively. The material of the conductive one-dimensional structure is the same as that of the source 108 and drain 110 described in the first embodiment, and will not be described again here.

[0068] In one specific embodiment, the conductive one-dimensional structure is a single metallic SWCNT, and the preparation method of the single metallic SWCNT includes the following steps:

[0069] S31, growing CNTs (carbon nanotubes);

[0070] S32, the CNT is placed in sulfur vapor, and sulfur vapor forms sulfur particles on the CNT. The sparser the distribution of sulfur particles, the smaller the diameter of the CNT, thereby selecting SWCNT from the CNT.

[0071] S33, determine the conductivity of the selected SWCNT, and thus select the metallic SWCNT; and

[0072] S34, annealing treatment to remove sulfur particles from CNTs.

[0073] In step S31, the method for growing CNTs is not limited, such as chemical vapor deposition. The following only uses the "kite-flying method" as an example to explain in detail the process of horizontally growing CNTs on a growth substrate, but it is not limited to this.

[0074] Please see Figure 3 The method of growing CNTs using the "kite-flying method" includes the following steps:

[0075] S311, provides a growth apparatus 30;

[0076] S312, a growth substrate 316 and a substrate 10 are provided, wherein a monodisperse catalyst layer 318 is formed on the surface of the growth substrate 316.

[0077] In S313, the growth substrate 316 is placed on the fixed platform 310, and the substrate 10 is placed on the rotating platform 312;

[0078] S314, introducing carbon source gas, growing CNTs along the direction of gas flow; and

[0079] S315, the carbon source gas is stopped, and CNTs are formed parallel and spaced on the surface of the substrate 10.

[0080] In step S311, the growth apparatus 30 includes a heating furnace 302, a reaction chamber 304, a rotatable platform 312, and a fixed platform 310 corresponding to the rotatable platform 312. The rotatable platform 312 and the fixed platform 310 are spaced apart within the reaction chamber 304. The reaction chamber 304 includes an air inlet 306 and an air outlet 308. The fixed platform 310 is located near the air inlet 306, and the rotatable platform 312 is located near the air outlet 308. The distance between the rotatable platform 312 and the fixed platform 310 is less than 1 cm, and the rotatable platform 312 is slightly lower than the fixed platform 310. The rotatable platform 312 can rotate at any angle in the horizontal direction.

[0081] In step S312, when an alloy of iron, cobalt, nickel, or any combination thereof is used to prepare the monodisperse catalyst layer 318, thin film technology can be used to deposit the catalyst material onto the surface of the growth substrate 316. When a metal salt is used to prepare the monodisperse catalyst layer 318, a monodisperse solution of the metal salt or a monodisperse solution of the metal is coated onto the growth substrate 316 to form the monodisperse catalyst layer 318. In this embodiment, the monodisperse solution of the metal salt used as the catalyst material is preferably a monodisperse aqueous solution or a monodisperse ethanol solution of ferric nitrate (Fe(NO3)3), copper chloride (CuCl2), or ferric chloride (FeCl3). The monodisperse solution of the metal used as the catalyst material is preferably a monodisperse solution of iron / molybdenum (Fe-Mo), iron / cobalt (Fe-Co), or iron / ruthenium (Fe-Ru) in n-octane, ethanol, or n-hexane. Using a monodisperse solution to prepare the catalyst layer 318 is beneficial to prevent the agglomeration of catalyst materials and form a monodisperse catalyst layer 318, that is, the catalyst layer 318 includes multiple monodisperse catalyst particles.

[0082] In step S313, the growth substrate 316 is placed on the fixed platform 310, ensuring that the side of the growth substrate 316 with the catalyst layer 318 deposited faces upwards. The growth substrate 316 and the substrate 10 are a high-temperature resistant substrate, and its material is not limited, as long as its melting point is higher than the growth temperature of the carbon nanotubes. In this embodiment, the growth substrate 316 is preferably a strip-shaped silicon wafer with a length of 10 cm and a width of 0.5 mm. It can be understood that in this embodiment, the catalyst material can be deposited on a large area of ​​silicon wafer surface first, and then the silicon wafer can be cut into multiple growth substrates 316 of predetermined sizes.

[0083] In step S314, the specific process of introducing carbon source gas and growing CNTs along the direction of gas flow is as follows:

[0084] First, a protective gas is introduced to purge the air from the reaction chamber 304. The protective gas is nitrogen or an inert gas; in this embodiment, argon is preferred.

[0085] Next, the reaction chamber 304 is heated to the CNT growth temperature under a protective gas environment and maintained at a constant temperature. The CNT growth temperature is 800℃ to 1000℃. It is understood that the CNT growth temperature varies depending on the carbon source gas. In this embodiment, when ethanol is used as the carbon source gas, the preferred CNT growth temperature is 850℃ to 950℃. When methane is used as the carbon source gas, the preferred CNT growth temperature is 950℃ to 1000℃.

[0086] Next, a carbon source gas is introduced to grow CNTs. The carbon source gas can be a chemically reactive hydrocarbon such as ethanol, acetylene, ethylene, or methane; in this embodiment, ethanol or methane is preferred. The flow rate of the carbon source gas is 5 sccm (mL / min at standard conditions) to 100 sccm. A certain amount of hydrogen is mixed into the carbon source gas as a carrier gas, and the flow ratio of carbon source gas to carrier gas is 1:1 to 1:3.

[0087] When carbon source gas is introduced, CNTs begin to grow under the action of catalyst particles on the surface of the growth substrate 316. One end of the CNT is fixed to the growth substrate 316, while the other end continues to grow. Because the catalyst layer 318 includes multiple monodisperse catalyst particles, the grown CNTs are not very dense, allowing some CNTs to grow into SWCNTs. Since the growth substrate 316 on the fixed platform 310 is located close to the air inlet 306 of the reaction chamber 304, the growing CNTs float above the substrate 10 along with the carbon source gas as it is continuously introduced. This growth mechanism is called the "kite-flying mechanism". The growth time of the CNTs is related to the CNTs to be prepared. In this embodiment, preferably, the growth time is 10 minutes. The CNTs grown by this method are longer than 1 cm, and can even reach more than 30 cm.

[0088] In step S315, CNT growth ceases after the carbon source gas is stopped. Heating is also stopped, and the temperature is lowered. However, a protective gas continues to be supplied until the temperature of the reaction chamber 304 drops to room temperature to prevent the grown CNTs from being oxidized. When the carbon source gas is stopped, CNT growth ceases, and they are formed parallel and spaced on the substrate 10, with a distance greater than 20 micrometers between adjacent CNTs. To facilitate the removal of CNTs from the substrate 10, multiple spaced trenches can be pre-etched into the substrate 10. When the CNTs fall onto the substrate 10, they are suspended in the trenches, as shown below. Figure 4 As shown. In one specific embodiment, the substrate 10 is composed of silicon and silicon nitride.

[0089] In step S32, in this embodiment, sulfur powder is heated to 150°C to form sulfur vapor. Then, the substrate 10 with CNTs placed in step S11 is placed in the sulfur vapor for a period of time. Many sulfur particles will form on the outer surface of the CNTs, that is, sulfur particles are distributed on the outer surface of the CNTs. The condensation morphology of sulfur vapor on the CNTs depends on the diameter of the CNTs. The sparser the distribution of sulfur particles, the smaller the diameter of the CNTs. Under an optical microscope, the CNT with the sparsest distribution of sulfur particles is selected, and this CNT is the single-walled carbon nanotube (SWCNT).

[0090] In step S33, metallic SWCNTs are selected by detecting their conductivity. Specifically, if the current of an SWCNT is greater than or equal to 1 nA at a voltage of 1V, then the SWCNT is a metallic SWCNT.

[0091] In step S34, the annealing temperature is 300°C to 400°C to remove sulfur particles from the CNTs. Preferably, the annealing temperature is 300°C to 350°C.

[0092] The following specific embodiment illustrates the fabrication method of the field-effect transistor 100, but is not limited thereto.

[0093] The first step is to place a MoS2 film (as a channel layer 106) onto the highly doped silicon wafer (as a gate 102), the surface of which has a 300nm thick SiO2 layer (as an insulating layer 104) located between the MoS2 film and the highly doped silicon wafer.

[0094] The second step involves growing ultralong CNTs using a chemical vapor deposition (CVD) method employing a "kite-flying" technique: a 0.2 nm ferroelectron beam is deposited onto a silicon substrate. The reactor temperature is then set to 970 °C, and H2 and C2H4 at flow rates of 200 sccm and 1 sccm, respectively, are selected as reducing gases and carbon sources to grow the CNTs. The substrate 10 used to collect the suspended CNTs is a Si / SiNx substrate with seven 200 μm wide trenches.

[0095] Step 3: Selection of Metallic SWCNTs: Sulfur powder is evaporated by heating to 150°C using a hot plate. Then, ultralong CNTs placed on a trench Si / SiN substrate are treated in a sulfur atmosphere for 10 seconds. Sulfur vapor deposits on the CNT surface, forming sulfur particles, which are effectively tracked using an optical microscope. The condensation morphology of sulfur vapor on the CNT depends on the CNT diameter; the sparser the sulfur particle distribution, the smaller the CNT diameter. Under the optical microscope, the CNT with the sparsest sulfur particle distribution is selected; this CNT is the single-walled carbon nanotube (SWCNT). A power meter (e.g., the tungsten tip of a Keithley 2900 high-precision source meter) is then connected to determine the conductivity of the SWCNT. If the current is greater than or equal to 1 nanoamp at 1V, then the SWCNT is metallic, also known as a metallic SWCNT.

[0096] Step 4: The two metallic SWCNTs selected in Step 3 are spaced apart on the surface of the MoS2 film away from the highly doped silicon wafer.

[0097] Step 5: Perform annealing treatment at a temperature of 350℃ to remove sulfur particles from the surface of metallic CNTs.

[0098] Step 6: Patterned Ti / Au (5nm / 50nm) electrodes were fabricated through electron beam lithography, electron beam evaporation, and lift-off. The Ti / Au (5nm / 50nm) electrodes are composite structures of titanium and gold. Specifically, Au is laminated onto the surface of Ti, with a Ti thickness of 5nm and an Au thickness of 50nm. The Ti / Au (5nm / 50nm) electrodes are respectively disposed at opposite ends of the MoS2 film and at opposite ends of the metallic SWCNTs.

[0099] The performance of the field-effect transistor 100 prepared in this specific embodiment is characterized below.

[0100] Figure 5 A transmission electron microscopy (TEM) image of the overall cross-section of the source electrode 108 and drain electrode 110 formed on the channel layer 106. Figure 6 The electron energy loss spectroscopy (EELS) is the overall electron energy loss spectrum formed by the source 108 and drain 110 disposed on the channel layer 106. Figure 5 A layered structure can be observed, with a MoS2 film at the bottom and a metallic SWCNT layer on top, thus proving that the channel layer 106 is a MoS2 film, and the source 108 and drain 110 are both metallic SWCNTs. Figure 6It can be seen that the source 108 and drain 110 formed on the channel layer 106 contain three elements: carbon (C), molybdenum (Mo), and oxygen (O). This further proves that the channel layer 106 is a MoS2 film, and both the source 108 and drain 110 are metallic SWCNTs.

[0101] Figure 7 The image shows the overall Raman spectrum of the source electrode 108 and drain electrode 110 formed on the channel layer 106. Figure 7 It can be seen that the Raman spectra of the source 108 and the drain 110 show typical SWCNT peaks, indicating that the source 108 and the drain 110 are SWCNTs with the same chirality; the channel layer 106 shows typical MoS2 peaks, indicating that the material of the channel layer 106 is MoS2.

[0102] Figure 8 The image shows a false-colored scanning electron microscope (false-colored SEM) image of the field-effect transistor 100. Figure 8 In the diagram, the bright-colored bands represent electrodes disposed on the channel layer 106, source 108, and drain 110. Figure 8 The transfer characteristics between two metallic SWCNTs (i.e.) Figure 8 The test of the transfer characteristics between points A and B, and the test of... Figure 8 Transfer characteristics between Au / Ti electrodes (i.e.) Figure 8 (Transfer characteristics between points 1 and 2) test. Figure 9 for Figure 8 The transfer characteristics between points A and B. (From...) Figure 9 It can be seen that a metallic SWCNT contact with a contact length of 2nm has a larger on-state current than an Au / Ti electrode contact with a length of 3 micrometers. Here, the 2nm contact length refers to the diameter of the metallic SWCNT being 2nm, that is, the contact length is the diameter of the metallic SWCNT. Figure 10 for Figure 8 Barrier heights at the interfaces of metallic SWCNT and MoS2, and Au / Ti electrodes and MoS2, under different gate voltages. Figure 10 It can be seen that the interfacial barrier between SWCNT and MoS2 film is adjustable over a wider range (550 meV to 0), where meV is megaelectronvolt.

[0103] Figure 11 for Figure 8 Comparison of band diagrams between the metallic SWCNT contact between points A and B and the Au / Ti contact between points 1 and 2. Figure 11It can be understood that the field-effect transistor 100 can switch between Schottky contact and ohmic contact under the action of gate voltage.

[0104] Figure 12 This is a diagram showing the interfacial resistivity-gate voltage between the metallic SWCNT and the MoS2 film in the field-effect transistor 100. Figure 12 It can be seen that the ohmic contact resistivity between metallic SWCNTs and MoS2 films can be as low as 10. -6 Ω·cm 2 .

[0105] Compared with the prior art, the field-effect transistor 100 and its fabrication method have the following advantages: First, the present invention proposes a one-dimensional half-metal contact by setting two SWCNTs with the same chirality on a two-dimensional semiconductor, successfully reducing the contact length of the field-effect transistor 100 to 2nm, thereby enabling the field-effect transistor 100 to have an ultra-short contact length; Second, the field-effect transistor 100 can switch between Schottky contact and ohmic contact by adjusting the potential of the gate 102; Third, in ohmic contact mode, the resistivity and contact resistance of the interface contact between the SWCNT and the channel layer 106 are 10 Ω·cm and 10 Ω·cm, respectively. -6 Ω·cm 2 With a contact resistance of 50 kΩ·μm, the field-effect transistor 100 has a low contact resistance.

[0106] The second embodiment of the present invention provides a method for measuring the contact resistance of a field-effect transistor 100, that is, a method for measuring the interface resistance between the source 108 (or drain 110) and the channel layer 106 in the field-effect transistor 100, which includes the following steps:

[0107] S21, the field-effect transistor 100 is provided, wherein the source 108 and drain 110 are respectively the metallic SWCNT, and the channel layer 106 is a two-dimensional semiconductor material such as molybdenum disulfide (MoS2) film, tungsten disulfide (WS2) film, or tungsten diselenide (WSe2) film; a plurality of Au / Ti electrodes are respectively disposed on the single metallic SWCNT and the channel layer 106;

[0108] S22, forming a false-colored scanning electron microscope (false-colored SEM) image of the field-effect transistor 100, such as... Figure 8 As shown; Figure 8 In the diagram, the bright colored bands A to I and 1 to 4 represent the Au / Ti electrodes, and the dashed box area b represents the channel layer 106. Figure 8The two parallel white bright lines a and a' represent the metallic SWCNT. Figure 8 A to I can be understood as electrode A to electrode I, or as the Au / Ti electrode being set at point A to point I; 1 to 4 can be understood as electrode 1 to electrode 4 (or can be represented by first electrode, second electrode, third electrode and fourth electrode respectively), or as the Au / Ti electrode being set at point 1 to point 4;

[0109] S23, the resistivity of metallic SWCNTs on silicon dioxide (the highly doped silicon wafer has a layer of silicon dioxide on its surface) is obtained based on the transfer length method. Resistivity of metallic SWCNTs on MoS2 films and the contact resistance at the interface between metallic SWCNT and Ti / Au electrode

[0110] S24, The sheet resistance of the channel layer 106 is obtained based on the four-probe method.

[0111] S25, the length from the Ti / Au electrode to the edge of the channel layer 106 is measured using a scanning electron microscope or an atomic force microscope (in this embodiment). Figure 8 (Length L from the Ti / Au electrode at point A to the lower edge of the 106 channel layer) in The diameter D of the metallic SWCNT CNT The length L and width W (μm) of the channel layer 106 between the source 108 and the drain 110;

[0112] S26, Substitute the above measurement results into Formula I,

[0113]

[0114] Among them, R tot Electrodes are respectively disposed on the two metallic SWCNTs (serving as source 108 and drain 110, respectively), and the resistance between these two electrodes is such that the line connecting these two electrodes is parallel to the length direction of the channel layer 106 (i.e., R). tot yes Figure 8 The resistance between the electrodes at points A and B can be directly obtained by measuring the resistance R using a power meter (such as the Keithley 2912 high-precision power meter). tot ; It is the interfacial contact resistance between the metallic SWCNT and the Ti / Au electrode, which can be obtained by the transfer length method; This is the quantum resistance of metallic SWCNTs; The resistivity of metallic SWCNTs on silicon dioxide can be obtained using the transfer length method; Lin It is the distance from the Ti / Au electrode to the channel layer 106 (i.e. Figure 8 The length from the Ti / Au electrode at point A to the lower edge of the 106 channel layer can be measured using a scanning electron microscope or an atomic force microscope. r c D represents the interfacial contact resistivity between the metallic SWCNT and the channel layer 106. CNT It is the diameter of the metallic SWCNT. L is the sheet resistance of the channel layer 106 (which can be obtained by the four-probe method), and L is the length of the channel layer 106 between the source 108 and the drain 110 (which can be measured by scanning electron microscopy or atomic force microscopy). is the resistivity of the metallic SWCNTs on the MoS2 film (which can be obtained by the transfer length method); W is the width of the channel layer 106 (which can be measured by scanning electron microscopy or atomic force microscopy).

[0115] In formula I, r c The unknown variable is SWCNT, while the other values ​​can be obtained through steps S23 to S25, thus finally calculating the interfacial contact resistivity r between SWCNT and channel layer 106. c (Ω·μm 2 );as well as

[0116] S27, the contact resistance R between the metallic SWCNT and the channel layer 106 c Satisfying formula R c =r c / lc(Ω·μm), where l C The diameter of the metallic SWCNT is used to obtain the contact resistance R between the metallic SWCNT and the channel layer 106. c The contact resistance between the metallic SWCNT and the channel layer 106 is the interface resistance between the source 108 (or drain 110) and the channel layer 106 in the field-effect transistor 100.

[0117] In step S23, in this embodiment, The resistivity of metallic SWCNTs that are in direct contact with silicon dioxide. The resistivity of metallic SWCNTs that are in direct contact with the MoS2 film.

[0118] The transfer length method obtains the channel resistance and the contact resistance between the electrode and the channel by linearly fitting the resistance of devices with different channel lengths. For a long-channel CNT transistor, the total resistance between the source 108 and the drain 110 can be expressed as:

[0119]

[0120] in, The resistivity of the metallic SWCNT in direct contact with silicon dioxide is represented by L, where L represents the length of the channel layer 106 between the source 108 and the drain 110. This indicates the contact resistance at the interface between the Au / Ti electrode and the metallic SWCNT due to structural defects. The quantum resistance of metallic SWCNTs,

[0121] In step S23, the transfer characteristic curves of multiple sets of CNT devices (the CNT devices are devices composed of electrodes EF, DE, CD, AG, GH, and HI) are measured. Figure 13 The results of analyzing the multiple groups of CNT devices are presented using the transfer length method. The horizontal axis represents the channel length of the device, and the vertical axis represents the resistance of the device. Different colored dots and lines represent the measurement results of the device under different gate voltages. The slope of the fitted line represents... The intercept with respect to the vertical axis (x=0) represents

[0122] The resistivity of metallic SWCNTs on SiO2 was obtained based on the transfer length method. Contact resistance between metal Au / Ti and metal SWCNT Here, it is assumed that the contact resistance between the metallic SWCNT and each Au / Ti electrode is the same. The transfer characteristic curve between electrodes AC is measured. Subtracting the contact resistance between Au / Ti and the metallic SWCNT, the quantum resistance of the metallic SWCNT, and the resistance of the metallic SWCNT on SiO2, the resistance of the metallic SWCNT on molybdenum disulfide is obtained. Dividing this by the length of the metallic SWCNT on MoS2 yields...

[0123] In step S24, the four-probe method is a commonly used method for measuring the sheet resistance of thin films. For example... Figure 8 Electrodes 1, 2, 3, and 4 are provided. A constant current I is applied to electrodes 1 and 4. 14 Then read the voltage V between electrode 2 and electrode 3. 23 Thus, the channel resistance of the two-dimensional material (molybdenum disulfide in this embodiment) between electrode 2 and electrode 3 can be expressed as R. 23 =V 23 / I 12 The corresponding sheet resistance

[0124]

[0125] Figure 14 This is a longitudinal transmission line model used to measure the interface resistance between the source 108 (or drain 110) and the channel layer 106 in the field-effect transistor 100. Figure 14 It can be seen that when the field-effect transistor 100 uses ultra-short contacts, considering the self-resistance of the contact material and the contact resistance, the potential and current distribution in the channel layer may be uneven. The longitudinal transmission line model has been used to model and analyze this situation, and an analytical expression for the equivalent resistance of the field-effect transistor 100 under the condition of uneven potential and current distribution is given, which is Equation I in step S26.

[0126] Therefore, by measuring the interface resistance between the source 108 (or drain 110) and the channel layer 106 in the field-effect transistor 100 described above, the interface resistance between the source 108 and the channel layer 106, and the interface resistance between the drain 110 and the channel layer 106, can be obtained. Since both the source 108 and the drain 110 use metallic SWCNTs in the above method, the interface resistance between the metallic SWCNT and the channel layer 106 can also be obtained.

[0127] The following specific embodiment illustrates the method for measuring the interface resistance between the source 108 (or drain 110) and the channel layer 106 in the field-effect transistor 100, but is not limited thereto.

[0128] In this specific embodiment, the experimentally measured and like Figure 15 and 16 As shown. Combined with Figure 17 The interfacial contact resistivity r between metallic SWCNT and MoS2 can be calculated using formula I based on the measurement results of various characteristic lengths obtained by atomic force microscopy (AFM). c =10 -6 Ω·cm 2 ,like Figure 12 As shown. Therefore, the contact resistance R between the metallic SWCNT and MoS2 is... c =r c / D CNT =50kΩ·μm.

[0129] The method for measuring the interface resistance between the source 108 (or drain 110) and the channel layer 106 in the field-effect transistor 100 has the following advantages: When the field-effect transistor 100 uses extremely short SWCNT contacts, the resistance of the contact and interconnect portions cannot be ignored, and the potential and current in the channel layer 106 exhibit a non-uniform distribution trend. Traditional four-probe methods and transfer length methods are not suitable for measuring and extracting the interface resistance (i.e., contact resistance) between the source 108 (or drain 110) and the channel layer 106 under these conditions. Therefore, this invention proposes a "longitudinal transmission line model" to provide the two-terminal resistance (i.e., contact resistance) of the field-effect transistor 100 with extremely short SWCNT contacts. Figure 8 The resistance between the electrodes at point A and point B is calculated. Based on this, by combining the four-probe method and the transfer length method to extract relevant position parameters, the contact resistance of the field-effect transistor 100 can be calculated, which is the interface resistance between the source 108 (or drain 110) and the channel layer 106 in the field-effect transistor 100.

[0130] Furthermore, those skilled in the art may make other changes within the spirit of this invention. Of course, all such changes made in accordance with the spirit of this invention should be included within the scope of protection claimed by this invention.

Claims

1. A method for measuring the contact resistance of a field-effect transistor, comprising the following steps: A field-effect transistor is provided, comprising a gate, an insulating layer, a source, a drain, and a channel layer. The insulating layer is located on the surface of the gate, and the channel layer is located on the surface of the insulating layer away from the gate. The source and the drain are spaced apart on the surface of the channel layer away from the insulating layer. Both the source and the drain are metallic single-walled carbon nanotubes. The channel layer is made of molybdenum disulfide, and multiple electrodes are disposed on the metallic single-walled carbon nanotubes and the channel layer, respectively. The insulating layer is made of silicon dioxide. Formula I is provided: Among them, R tot It is the resistance between two metallic single-walled carbon nanotubes. It is the interfacial contact resistance between the metallic single-walled carbon nanotube and the electrode. It is a quantum resistance of metallic SWCNT. The resistivity, L, of metallic single-walled carbon nanotubes on silicon dioxide. in It is the distance from the electrode to the channel layer. r c D represents the interfacial resistivity between the metallic single-walled carbon nanotube and the channel layer. CNT It is the diameter of the metallic single-walled carbon nanotube. L is the sheet resistance of the channel layer, and L is the length of the channel layer between the source and the drain. is the resistivity of the metallic single-walled carbon nanotubes on the molybdenum disulfide, and W is the width of the channel layer. The interfacial resistivity r between the metallic single-walled carbon nanotube and the channel layer is calculated using Formula I. c ;as well as The contact resistance R between the metallic single-walled carbon nanotube and the channel layer c Satisfying formula R c =r c / lc, where l C The diameter of the metallic single-walled carbon nanotube is used to obtain the contact resistance between the metallic single-walled carbon nanotube and the channel layer.

2. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The method further includes the step of forming a pseudocolor scanning electron microscope image of the field-effect transistor, wherein in the pseudocolor scanning electron microscope image, the first line represents a metallic single-walled carbon nanotube as the source, the second line represents a metallic single-walled carbon nanotube as the drain, point A is defined on the first line, point B is defined on the second line, the electrode is disposed at both points A and B, and the line connecting points A and B is parallel to the length direction of the channel layer.

3. The method for measuring the contact resistance of a field-effect transistor as described in claim 2, characterized in that, R tot It is the resistance between the electrodes at points A and B.

4. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The resistivity of metallic single-walled carbon nanotubes on silica was obtained based on the transfer length method. Resistivity of metallic single-walled carbon nanotubes on molybdenum disulfide and the interfacial contact resistance between the metallic single-walled carbon nanotube and the electrode.

5. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The length L from the electrode to the channel layer was measured using a scanning electron microscope or an atomic force microscope. in The diameter D of the metallic single-walled carbon nanotube CNT The length L and width W of the channel layer between the source and the drain.

6. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The resistance R between the two metallic single-walled carbon nanotubes was measured using a power meter. tot .

7. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The sheet resistance of the channel layer was obtained using the four-probe method.

8. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The quantum resistance of the metallic single-walled carbon nanotubes It is 6.5kΩ.

9. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The interfacial resistivity r between the metallic single-walled carbon nanotube and the channel layer c 10 -6 Ω·cm 2 The contact resistance between the metallic single-walled carbon nanotube and the channel layer is 50 kΩ·μm.

10. The method for measuring the contact resistance of a field-effect transistor as described in claim 1, characterized in that, The method for measuring the interface resistance between the drain and the channel layer is the same as the method for measuring the interface resistance between the source and the channel layer.

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