Chip and method and apparatus for counting interface information thereof

Abstract

The embodiment of the present application provides a chip and an interface information statistical method and device, the method comprises the following steps: connecting each interface in the chip to an internally arranged statistical bus; a controller of the statistical bus acquires the value of a data item corresponding to a target statistical item of a target interface by interacting with each interface according to a transmission protocol and a bus cycle of the statistical bus; and the controller updates statistical information according to the acquired value of the data item. The technical scheme of the embodiment of the present application connects multiple interfaces to the statistical bus, realizes statistics and collection by one instance, and only needs to set the position of the statistical item in the controller, thereby avoiding using the registers and customized RAM of the interfaces and reducing the chip area.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, in particular to a chip and a method and device for counting interface information of the chip. BACKGROUND

[0002] The interfaces are multiple, and the counting types of the interfaces are also multiple, and 64, 128 or more bits can be needed for each counting type to store. The interfaces can be understood as network ports of a switch, and the counting types can be understood as message types, message lengths, unicast messages, multicast messages, etc., and the number of bits needed depends on the possible size of the counting value, for example, the byte counting of the message can be large, and the number of bits needed is large, while the error message does not often occur, and the number of bits needed is small.

[0003] Currently, the following methods are used for the design of counting information: 1) multiple types of counting information are written in a module, and are stored in the form of a register; 2) multiple types of counting information are written in a module, and are stored in the form of a RAM; and 3) multiple interfaces and multiple types of counting information are realized by instantiating the above module.

[0004] The disadvantages are as follows: 1) when there are many types of counting information, more resources need to be allocated, and the use of a register can result in a huge area consumption; 2) the use of a RAM can result in the need to consider the customization of the RAM, such as the width and the depth, and if the customization does not completely match, resource waste can be caused; and 3) when multiple interfaces are counted, multiple instances of the above module need to be used, and the resource consumption can be multiplied. SUMMARY

[0005] Therefore, the embodiments of the present application provide a chip and a method and device for counting interface information of the chip. The technical scheme of the embodiments of the present application realizes counting and summarization through the hanging of multiple interfaces on a counting bus, and only needs to set the positions of the counting items in a controller, avoids the use of registers of the interfaces and customized RAMs, and reduces the chip area.

[0006] In a first aspect, the embodiments of the present application provide a method for counting interface information of a chip, which includes the following steps: hanging each interface in the chip on an internally set counting bus; a controller of the counting bus interacts with each interface according to a bus cycle and a set transmission protocol to acquire the value of a data item corresponding to a target counting item of a target interface; and the controller updates counting information according to the acquired value of the data item.

[0007] According to the above, when counting the information of the interface module in the chip interface or the chip design code, a plurality of interfaces are cascaded through a group of buses, and the counting information is stored in the bus controller, thereby avoiding the problem of too many registers caused by the registers of each interface, reducing the chip area, avoiding the resource waste caused by the use of customized RAM by each interface, and separating the counting and storage, so that the counting can be realized by different engineers, and after the counting information is summarized, the access mode is more friendly to users.

[0008] In a possible implementation of the first aspect, in the transmission protocol, the bus data at least includes an input indication, wherein when the input indication is valid, the bus data further includes an identification of the accessed interface and an identification of the accessed data item, and when the input indication is invalid, the bus data further includes a value of the accessed data item in the accessed interface.

[0009] According to the above, the input indication bit of the bus is counted to distinguish the read data and the write data of the interface from the bus, so that the bus wiring is reduced.

[0010] In a possible implementation of the first aspect, each bus cycle includes 2 beats, and each beat is one system beat, wherein in the first beat, the input indication is valid, and in the second beat, the input indication is invalid; the method for counting the information of the chip interface further includes: when any interface determines, according to the identification of the accessed interface in the received bus data, that the received bus data is the value of one data item of the interface in the first beat of any bus cycle, the value of the data item is sent to the counting bus in the second beat of the bus cycle.

[0011] According to the above, the read and the write of one bus cycle are completed on one wiring through the 2-beat bus cycle, and the resource consumption of the bus is reduced.

[0012] In a possible implementation of the first aspect, the value of each statistical item of each interface fed back by the controller is at least the statistical result of the corresponding data item after a set number of times.

[0013] According to the above, the statistical accuracy is improved through the set number of times of statistics.

[0014] In a possible implementation of the first aspect, when the controller receives a request for the value of any statistical item of any interface, the value of the statistical item is fed back to the requester.

[0015] According to the above, the controller saves and refreshes the statistical information, and feeds back according to the demand, so that the statistical party can obtain the latest statistical information.

[0016] In a possible implementation of the first aspect, the method further includes that the controller cyclically accesses the data item corresponding to each statistical item of each interface; or the controller accesses the data item corresponding to any statistical item of any interface according to the command of the requester.

[0017] According to the above, the data item corresponding to each statistical item of each interface is accessed by the controller according to the controller cycle of the set period or the command of the requester, so as to match various scenarios.

[0018] In a possible implementation of the first aspect, the method further includes that interface information of each interface is obtained, and the interface information at least includes one of the following: the number of interfaces of the chip, the number of statistical items and width information of each interface, and width information of the data item corresponding to each statistical item; and the address bit width and the data bit width of the statistical bus are determined according to the interface information.

[0019] According to the above, the statistical bus interface is designed according to the detailed chip interface information, so as to reduce the number of registers.

[0020] In a possible implementation of the first aspect, the statistical information is stored in the RAM of the controller, and the method further includes that the width and the depth of the RAM are determined according to the interface information.

[0021] According to the above, the RAM in the controller is designed according to the chip interface information, so as to save the RAM.

[0022] In a possible implementation of the first aspect, the method further includes that when the controller obtains the statistical items of all interfaces within a set time, the number of statistical buses and the number of ports on each statistical bus are determined according to the system clock of the chip and the interface information.

[0023] According to the above, the statistical items of all interfaces are completed within a set time by using multiple statistical buses.

[0024] In the second aspect, an embodiment of the present application provides a chip interface information statistical device, which includes: an interface hanging module, configured to hang each interface in a chip to a statistical bus arranged internally; a data obtaining module, configured to enable a controller of the statistical bus to interact with each interface according to a bus cycle and a set transmission protocol to obtain the value of the data item corresponding to the target statistical item of the target interface; and a statistical updating module, configured to enable the controller to update statistical information according to the value of the obtained data item.

[0025] According to the above, when the information of the interface module in the chip or the interface module in the chip design code is counted, a plurality of interfaces are cascaded through a group of buses, and the counting information is collected and stored, so as to avoid the problem of too many registers caused by the registers of each interface, reduce the chip area, avoid the resource waste caused by the use of customized RAM of each interface, and separate the counting and storage, so that the counting information can be realized by different engineers, and the access mode of the counting information is more friendly to users after the counting information is collected.

[0026] In a possible implementation of the second aspect, in the transmission protocol, the bus data at least includes an input indication, wherein when the input indication is valid, the bus data further includes an identification of the accessed interface and an identification of the accessed data item, and when the input indication is invalid, the bus data further includes a value of the accessed data item in the accessed interface.

[0027] According to the above, the input indication bit of the bus is counted to distinguish the read data and the write data of the interface from the bus, so that the bus wiring is reduced.

[0028] In a possible implementation of the second aspect, each bus cycle includes two beats, each beat is one system beat, in the first beat, the input indication is valid, and in the second beat, the input indication is invalid; when any interface judges that the received bus data is the value of one data item of the interface according to the identification of the accessed interface in the received bus data in the first beat of any bus cycle, the value of the data item is sent to the counting bus in the second beat of the bus cycle.

[0029] According to the above, the read and the write of one bus cycle are completed on one wiring through the bus cycle of two beats, so that the resource consumption of the bus is reduced.

[0030] In a possible implementation of the second aspect, the value of each counting item of each interface fed back by the controller is at least the statistical result of the corresponding data item for a set number of times.

[0031] According to the above, the statistical accuracy is improved through the set number of times of counting.

[0032] In a possible implementation of the second aspect, the method further includes: a counting feedback module, configured to feed back the value of any counting item of any interface to a requester when the controller receives a request to acquire the value of the counting item.

[0033] According to the above, the controller saves and refreshes the counting information, and feeds back according to the demand, so that the counting party can obtain the latest counting information.

[0034] In a possible implementation of the second aspect, the controller cyclically accesses the data item corresponding to each statistical item of each interface; or the controller accesses the data item corresponding to any statistical item of any interface according to a command of the requester.

[0035] According to the above, the data item corresponding to each statistical item of each interface is accessed by the controller according to the controller cycle of the set period or the command of the requester, so as to match various scenarios.

[0036] In a possible implementation of the second aspect, the statistical device of the interface information of the chip further includes an information obtaining module, configured to obtain the interface information to be counted, wherein the interface information at least includes one of the following: the number of interfaces of the chip, the number of statistical items of each interface and the width information, and the width information of the data item corresponding to each statistical item.

[0037] According to the above, the detailed interface information of the chip is obtained, so as to provide a reference for the design of the statistical bus interface and the RAM, thereby saving the registers and the RAM.

[0038] In a possible implementation of the second aspect, the statistical device of the interface information of the chip further includes a line width design module, configured to obtain the address bit width and the data bit width of the statistical bus according to the interface information, wherein the address bit width at least includes one of the following: the width of the interface identifier and the width of the data item identifier.

[0039] According to the above, the statistical bus interface is designed according to the interface information of the chip, so as to reduce the number of registers.

[0040] In a possible implementation of the second aspect, the statistical device of the interface information of the chip further includes a RAM design module, configured to determine the width and the depth of the RAM according to the interface information.

[0041] According to the above, the RAM in the controller is designed according to the interface information of the chip, so as to save the RAM.

[0042] In a possible implementation of the second aspect, the statistical device of the interface information of the chip further includes a number of strips design module, configured to, when the controller obtains the statistical items of all interfaces within a set time, determine the number of strips of the statistical bus and the number of ports on each strip of the statistical bus according to the system clock of the chip and the interface information.

[0043] According to the above, the statistical bus is used to complete the statistics of the statistical items of all interfaces within a set time.

[0044] In a third aspect, an embodiment of the present application provides a chip, and the interface information of the chip is counted by using any of the embodiments of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1A Figure 1 is a flowchart of a chip interface information statistical method according to an embodiment of the present application;

[0046] Figure 1B Figure 2 is a structure diagram of serially connecting interfaces to a statistical bus according to an embodiment of the present application;

[0047] Figure 2A Figure 3 is a flowchart of a bus design method according to an embodiment of the present application;

[0048] Figure 2B Figure 4 is a timing structure diagram according to an embodiment of the present application;

[0049] Figure 3 Figure 5 is a flowchart of a data statistical method according to an embodiment of the present application;

[0050] Figure 4 Figure 6 is a structure diagram of a chip interface information device according to an embodiment of the present application;

[0051] Figure 5 Figure 7 is a structure diagram of a bus design device according to an embodiment of the present application;

[0052] Figure 6 Figure 8 is a structure diagram of a data statistical device according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0054] In the following description, the terms "first\second\third, etc." or module A, module B, module C, etc. are used only to distinguish similar objects or to distinguish different embodiments, and do not represent a specific order of the objects. It can be understood that the specific order or sequence can be interchanged as permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0055] In the following description, the labels indicating steps such as S110, S120, etc. do not necessarily mean that the steps are executed in this order, and the order of the steps can be interchanged or executed simultaneously as permitted.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to be limiting of this application.

[0057] The embodiment of the present application provides a chip and a method and device for counting interface information of the chip, the method comprising: connecting each interface in the chip to a counting bus arranged internally; connecting each interface in the chip to the counting bus arranged internally; a controller of the counting bus acquires the value of a data item corresponding to a target counting item of a target interface by interacting with each interface according to a transmission protocol set by the counting bus in a bus cycle; and the controller updates counting information according to the value of the data item acquired.

[0058] The technical solution of the embodiment of the present application is used for counting information of interfaces in a chip or interface modules in a chip design code, a plurality of interfaces are connected to an internal counting bus, counting information is collected and stored in a counting bus controller, the problem of too many registers caused by registers of each interface is avoided, chip area is reduced, resource waste caused by use of customized RAM by each interface is avoided, counting and storage are separated, and counting information can be realized by different engineers, and the access mode of the counting information is more user-friendly after the counting information is collected.

[0059] The embodiments of the present application will be described below with reference to the accompanying drawings. First, a chip interface information counting method embodiment one of the present application is described with reference to Figure 1A and Figure 1B A chip interface information counting method embodiment one of the present application is described.

[0060] Figure 1A A flow of a chip interface information counting method embodiment one is shown, comprising steps S110 to S130.

[0061] In step S110, each interface in the chip is connected to a counting bus arranged internally in the chip.

[0062] The interface can be a network port, a serial port, a parallel port, and various interfaces. The counting bus is controlled and managed by a bus controller arranged internally in the chip, and the bus controller directly accesses each interface.

[0063] In some embodiments, the counting bus is a ring bus, and the starting point and the ending point of the counting bus are both the controller of the counting bus. The signals of the counting bus pass through each interface in series, and the series is that the counting bus starts from the controller, passes through each interface in turn, and returns to the controller. In other embodiments, the counting bus is a chain bus or a star bus.

[0064] Figure 1B A structure diagram of series connection of each interface to the counting bus in the embodiments of the present application is shown.

[0065] For example, four interfaces are serially connected to the statistic bus in the figure, and any number of interfaces can be included in the actual scenario. The signals of the statistic bus are sent from the controller of the statistic bus, pass through interface 0, interface 1, interface 2 and interface 3 in turn, and then return to the controller. Each interface judges whether the signal on the statistic bus is input to itself or whether it needs to output a signal.

[0066] In some embodiments, the interface information of the chip is obtained in advance, and the interface information at least includes one of the following: the number of interfaces of the chip, the number of data items of each interface and the width information of each data item; the address bit width and the data bit width of the statistic bus are determined according to the interface information of the chip, and the address bit width at least includes one of the following: the width of the interface identifier and the width of the data item identifier. According to the above, the address bit width and the data bit width of the statistic bus are obtained according to the interface information of the chip, so that the data structure of the statistic bus is determined, and more registers are avoided.

[0067] In other embodiments, when the controller obtains the statistical items of all interfaces within a set time, the number of the statistic buses and the number of ports on each statistic bus are determined according to the system clock of the chip and the interface information. For example, when the switch chip obtains the statistical data of all FE, GE and NPI interfaces in a scheduling period, a plurality of statistic buses can be designed, each statistic bus is connected to a corresponding interface, and each statistic bus works in parallel.

[0068] In step S120, the controller of the statistic bus interacts with each interface through the statistic bus according to a set transmission protocol and a bus cycle to obtain the value of the data item corresponding to the target statistical item of the target interface.

[0069] Each statistical item of each interface is statistical information of different angles of the interface. For example, when the interface is a network port, the statistical items can be the number of various messages, the average length of message bytes and the number of collisions, wherein the types of messages include unicast, multicast, broadcast, IPV4, IPV6, ARP and flow control frames. For example, when the statistical item is the number of various messages, the corresponding data item is the type of the message; when the statistical item is the average length of message bytes, the data item is the byte length of the current message; and when the statistical item is the number of collisions, the data item is whether a collision occurs.

[0070] The refreshing method is obtained according to the statistical method of the data item. For example, the summation statistical method directly takes out the value in the RAM, adds the value sent from the bus, and then stores it in the corresponding position of the RAM.

[0071] The bus controller is built in the chip, and sends bus data to the statistic bus to acquire a data item of an interface, the bus data being data received by each interface, and when an interface judges that the controller acquires the value of a data item, the bus data including the value of the data item is output to the statistic bus and received by the controller.

[0072] In some embodiments, the controller accesses the data item corresponding to each statistic item of each interface in a set period of controller cycle, for example, in a switch chip, each statistic item of each interface is accessed in each scheduling cycle to obtain the statistic result of the scheduling cycle, and scheduling is performed in the next cycle; in other embodiments, the controller accesses the data item corresponding to each statistic item of each interface according to the request of the statistic item.

[0073] In some embodiments, in the transmission protocol of the statistic bus, the address and data of the statistic bus share a set of physical buses, and the bus data at least includes an input indication, wherein when the input indication is valid, the bus data is input data of the interface, and further includes the identification of the accessed interface and the identification of the accessed data item, and when the input indication is invalid, the bus data is output data of the interface, and further includes the value of the accessed data item in the accessed interface. From the above, the direction of the data of the statistic bus is distinguished by setting the input indication of the statistic bus, so as to facilitate the operation of the interface. In other embodiments, the statistic bus also has only one set of physical buses, and the width of the statistic bus is equal to the sum of the address bit width and the data bit width. In other embodiments, the statistic bus has two sets of physical buses, and the address and data use one set of physical buses of the statistic bus respectively.

[0074] In some embodiments, each bus cycle includes two beats, each beat being one system beat, in the first beat, the input indication is valid, and in the second beat, the input indication is invalid; when any interface judges that the received bus data is the value of a data item of the interface according to the identification of the accessed interface in the received bus data in the first beat of any bus cycle, the value of the data item is sent to the statistic bus in the second beat of the bus cycle. From the above, the two beats in the statistic bus cycle are distinguished by the input indication, in the first beat, each interface accurately acquires the number of the accessed interface and the type of the accessed data item, and in the second beat, the number of the accessed interface is written into the current value of the accessed data item.

[0075] In some embodiments, when a plurality of statistic buses are arranged in the chip, each statistic bus works in parallel under the management of the same controller.

[0076] In some embodiments, the interface information to be counted is obtained in advance, and the interface information includes at least one of the following: the number of interfaces of the chip, the number of counting items of each interface, and the width information of each counting item; the width and depth of the RAM in which the controller stores the counting items are determined according to the interface information of the chip. The information of each counting item of each interface is stored in a piece of RAM, thereby saving the RAM and reducing the chip area.

[0077] In some embodiments, a position in the RAM is reserved for each counting item of each interface to fill in the counting information. In other embodiments, the idle address in the current RAM is indicated in the form of a RAM address pointer or a linked list, so as to be used by the newly added counting item, thereby further saving the RAM.

[0078] In step S130, the controller updates the counting information according to the value of the obtained data item.

[0079] In some embodiments, when the controller receives a request for obtaining the value of any counting item of any interface, the controller feeds back the counting item to the requester, so that the request method can obtain the latest counting information.

[0080] In some embodiments, the requester requests to obtain the value of the counting item of all interfaces at a time, and in other embodiments, the requester requests to obtain the value of all or specified counting items of a specified interface.

[0081] In some embodiments, the value of each counting item fed back to the requester is at least the statistical result of the corresponding data item for a set number of times, so as to improve the accuracy of the statistics.

[0082] In some embodiments, the requester is a CPU, and other modules in the chip obtain the value of each counting item of each interface through the CPU.

[0083] In some embodiments, the controller cyclically updates the data of the counting items of each interface, and clears 0 after reaching a cycle period. When receiving a reading command of a counting item of an interface from the requester, the controller temporarily stores the command. The controller determines whether the value of the counting item has been counted for a set number of times since the last clearing 0. When the value of the counting item meets the counting for the set number of times, the controller feeds back to the CPU, otherwise, the controller continues to update. In other embodiments, when receiving a reading command of a counting item of an interface from the requester, the controller temporarily stores the command, starts to access the data item corresponding to the counting item of the interface according to the bus period (the data of multiple interfaces and multiple counting items can be accessed in parallel), and updates the counting item according to the access result. The controller determines whether the value of the counting item has been counted for a set number of times. When the value of the counting item has been counted for the set number of times, the controller feeds back to the CPU, otherwise, the controller continues to update.

[0084] In summary, the statistical method of chip interface information embodiment one is used for information statistics of interface in chip or interface module in chip design code, a plurality of interfaces are cascaded through a group of statistical buses, each interface is accessed by a statistical bus controller and information is counted and stored, the use of more distributed registers and customized RAM is avoided, the chip area is reduced, the statistics and storage are separated, and different engineers can independently implement the statistics, and the access mode of the statistical information is more friendly to users after the statistical information is summarized.

[0085] The statistical method of chip interface information embodiment two will be introduced below. Figure 2A 、 Figure 2B and Figure 3 The statistical method of chip interface information embodiment two will be introduced below.

[0086] The statistical method of chip interface information embodiment two inherits the method of the statistical method of chip interface information embodiment one, has all the advantages thereof, and increases the design method of the statistical bus. The flow includes a bus design method and a data statistical method.

[0087] Figure 2A The bus design method of the statistical method of chip interface information embodiment two is shown in a flow, including steps S210 to S240.

[0088] In step S210, interface information of a chip is obtained.

[0089] The interface information at least includes one of the following: the number of interfaces of the chip, the number of statistical items of each interface and the width of each statistical item, the data item corresponding to each statistical item and the width information.

[0090] The interfaces can be various types of interfaces, such as network ports, serial ports, etc. Even if it is a network port, it includes a hundred-megabit port, a gigabit port, etc.

[0091] The interface can be an interface module in the corresponding chip implementation code or a real chip interface.

[0092] In step S220, the address bit width and the data bit width of the statistical bus are determined according to the interface information, so as to determine the bus width.

[0093] The width of the interface identifier is determined according to the number of interfaces, and the width of the data item identifier is determined according to the number of data items. The address bit width at least includes the sum of the width of the interface identifier and the width of the data item identifier, and the data bit width is the width of the maximum value of each data item. The bus width is at least 1 larger than the larger one of the address bit width and the data bit width, and the 1 is used for input indication.

[0094] When a data item is too wide, it can be split into two data items to prevent a too-wide data item from causing the statistical bus width to be too wide.

[0095] The speed of the statistics bus is determined according to the speed of the interfaces, and when the speed of the interfaces is high, the speed of the statistics bus is also high.

[0096] Each bus cycle of the statistics bus includes two beats, the first beat is that each interface reads data from the statistics bus, and the second beat is that each interface writes data to the statistics bus.

[0097] Figure 2B The timing structure of the embodiment is shown.

[0098] For example, the interface bus is named as CSC (Classification Statistics Center), and the CSC is an array, and each group of data is 11 bits, and bit 10 is a csc_vld signal, which is an input indication, and when the csc_vld is 1, it indicates that the input is valid.

[0099] In the first beat of each statistics bus cycle, the csc_vld is 1, the first beat bits 4-9 cnt_id represent the data item identifier to be written, and bits 0-3 bits csc_port_num represent the interface identifier to be written; the second beat bits 0-9 are statistics values, and the csc_vld is 0.

[0100] In step S230, when the statistics items of each interface are obtained within the set time, the number of statistics bus strips and the number of interfaces on each strip are determined according to the chip clock period and the interface information.

[0101] The number of statistics bus strips is determined as follows: first, the number of chip clock periods included in the set time is obtained according to the chip clock period and the set time; then, the number of chip clock periods required to obtain all statistics items of an interface is determined according to the maximum number of statistics items in each interface; the second number of chip clock periods is divided by the first number of chip clock periods to obtain the number of statistics bus strips; then, the interfaces to be connected to each statistics bus strip are designed.

[0102] The statistics bus strips work in parallel and are managed by the same controller.

[0103] In step S240, the width and depth of the RAM used for statistics in the controller are obtained according to the interface information.

[0104] In some embodiments, the width of the RAM is the number of bits of the widest statistics item in each statistics item of each interface in the interface information, and the depth is the sum of each statistics item of each interface, so that each statistics item has a position.

[0105] In some other embodiments, when the bus controller completes a round of statistics of each statistical item of each interface, the statistics are saved in the RAM of the controller for the data requester to acquire, and a new round of statistics is started, the new statistics being intermediate statistics, not yet completed, saved in the RAM at a location, when the new round of statistics is completed, the statistics are saved to the saved location of the last round in the RAM, so that the requester can always acquire the latest statistics, and the depth of the RAM is twice the sum of each statistical item of each interface.

[0106] Figure 3 A flow of the data statistics method of the second embodiment of the chip interface information statistics method is shown, including steps S310 to S360.

[0107] For ease of description, the bus controller is taken as an example to cyclically acquire the value of each statistical item of each interface.

[0108] In step S310, each interface in the chip is connected to a ring-shaped statistics bus, and the starting point and the ending point of the statistics bus are both the controller of the statistics bus.

[0109] When there are multiple statistics buses, a corresponding number of interfaces are connected to each bus, so that the statistics of each interface can be completed within a set time.

[0110] In step S320, the controller cyclically and sequentially sends bus data to the statistics bus to access a data item of an interface in the first beat of each statistics bus cycle.

[0111] The loop iterates through each data item of each interface. For example, when there is only one statistics bus, the number of bus cycles in each round of loop is the product of the number of interfaces and the number of data items. When there are multiple statistics buses, the statistics buses run in parallel, and each statistics bus is separately iterated through. In each round of loop, the number of bus cycles is the product of the number of interfaces connected to each bus and the number of data items.

[0112] For ease of description, this step and step S330 are taken as an example in which the controller accesses the data item p of the interface m in the qth statistics bus cycle.

[0113] In the first beat of the qth statistics bus cycle, the controller sends bus data to access the data item p of the interface m. The bus data is a CSC data structure, the values of CSC.bit0-bit3 of which are m, i.e., the interface identifier is m, the values of CSC.bit4-bit9 of the first beat are p, i.e., the data item identifier is p, and the value of CSC.bit10 is 1, i.e., the input request vld (input indication) is valid. The interface identifier width is 4, the data item identifier width is 6, the address bit width is 10, and the bus width is 11.

[0114] In step S330, when the interface judges that the received statistical bus signal is the value of a data item of the interface in the first beat of the current statistical bus cycle, the first beat of the current statistical bus cycle sends the current value of the data item to the statistical bus.

[0115] In the qth statistical bus cycle, interface 0 judges that the current bus data is not the data item of the interface, and transmits the bus signal downward until the bus signal reaches interface m.

[0116] In the qth statistical bus cycle, when interface m judges that the value of CSC.bit10 in the current bus data is 1, and the values of CSC.bit0-bit3 are m and the values of CSC.bit4-bit9 are p, it judges that the current value of the data item p of the interface is obtained, and in the second beat of the qth statistical bus cycle, the value of CSC.bit10 is set to 0, and the values of CSC.bit0-bit9 are set to the current value of the data item p, to generate the bus data of the second beat of the qth statistical bus cycle, and send the bus data to the statistical bus, which is received by the controller.

[0117] In each round of loop, each interface runs the step for the same number of times as the number of data items of the interface. For example, the total number of times the step is run by each interface is the product of the number of interfaces and the number of data items.

[0118] In step S340, the controller obtains the current value of each data item of each interface from the statistical bus, and refreshes the value of the statistical item corresponding to the data item of the interface in the RAM according to the current value.

[0119] In the second beat of each bus cycle, the controller receives the statistical data from the statistical bus. For the bus data of the CSC structure, the value of CSC.bit10 of the received bus data is set to 0, and the values of CSC.bit0-bit9 are set to the current value of the data item of the interface in the bus data of the first beat of the current statistical cycle.

[0120] The refreshing method is obtained according to the statistical method of the data item. For example, for the summation statistical method, the value in the RAM is directly taken out and added to the value sent from the bus, and then stored in the corresponding position of the RAM.

[0121] For example, in each round of loop, the total number of times the step is run by each interface is the product of the number of interfaces and the number of data items.

[0122] In step S350, the controller judges whether each statistical item has been counted for a set number of times.

[0123] If the statistical item has been counted for a set number of times, step S360 is run, otherwise step S320 is executed.

[0124] In step S360, the controller feeds back to the requester of the interface statistical information the value of each statistical item of each interface saved in the RAM.

[0125] In summary, the second embodiment of the chip interface information statistical method is based on the first embodiment of the chip interface information statistical method, and adds the design method of the statistical bus, designs the signal data structure of the statistical bus and the RAM structure of the controller based on the chip port information, further avoids using more distributed registers and customized RAMs of different specifications, reduces the chip area, and reduces resource waste.

[0126] The chip interface information statistical method and the chip interface information statistical device will be described in detail below. Figure 4 The first embodiment of the chip interface information statistical device of the application is introduced.

[0127] The first embodiment of the chip interface information statistical device executes the method of the first embodiment of the chip interface information statistical method, and has all the advantages thereof.

[0128] Figure 4 The structure of the first embodiment of the chip interface information device is shown, which comprises an interface hanging module 410, a data obtaining module 420, and a statistical updating module 430.

[0129] The interface hanging module 410 is used for hanging each interface in the chip to the statistical bus arranged inside the chip. Its working principle and advantages are described with reference to step S110 of the first embodiment of the chip interface information statistical method.

[0130] The data obtaining module 420 is used for the controller of the statistical bus to interact with each interface through the statistical bus according to the transmission protocol set by the bus cycle, and obtain the value of the data item corresponding to the target statistical item of the target interface. Its working principle and advantages are described with reference to step S120 of the first embodiment of the chip interface information statistical method.

[0131] The statistical updating module 430 is used for the controller to update the statistical information according to the value of the obtained data item. Its working principle and advantages are described with reference to step S130 of the first embodiment of the chip interface information statistical method.

[0132] The chip interface information statistical method and the chip interface information statistical device will be described in detail below. Figure 5 and Figure 6 The second embodiment of the chip interface information statistical device of the application is introduced.

[0133] The second embodiment of the chip interface information statistical device executes the method of the second embodiment of the chip interface information statistical method, and has all the advantages thereof.

[0134] Figure 5The chip interface information device implements a structure of a bus design device in the second embodiment, which is located in a computing device and includes an information obtaining module 510, a line width design module 520, a number of strips design module 530, and a RAM design module 540.

[0135] The information obtaining module 510 is configured to obtain interface information to be counted, which includes at least one of the following: the number of interfaces to be counted, the number of data items to be counted for each interface, and the width information of each data item. The working principle and advantages thereof can refer to step S210 of the bus design method of the second embodiment of the chip interface information counting method.

[0136] The line width design module 520 is configured to obtain the address bit width and the data bit width of the bus according to the interface information to determine the bus width. The working principle and advantages thereof can refer to step S220 of the bus design method of the second embodiment of the chip interface information counting method.

[0137] The number of strips design module 530 is configured to determine the number of strips of the bus and the number of interfaces on each strip according to the chip clock period and the interface information when obtaining the counting items of each interface within a set time. The working principle and advantages thereof can refer to step S230 of the bus design method of the second embodiment of the chip interface information counting method.

[0138] The RAM design module 540 is configured to obtain the width and the depth of the RAM in the controller for counting according to the interface information. The working principle and advantages thereof can refer to step S240 of the bus design method of the second embodiment of the chip interface information counting method.

[0139] Figure 6 The chip interface information device implements a structure of a data counting device in the second embodiment, which is located in a chip or a module of chip code and includes an interface hanging module 610, an interface access module 620, a data obtaining module 630, a counting updating module 640, a number of times judging module 650, and a counting obtaining module 660.

[0140] For ease of description, the CPU obtains the information of the counting item m of the interface n as an example, and the counting item m corresponds to a data item p.

[0141] The interface hanging module 610 is configured to hang each interface in the chip to a ring-shaped counting bus, and the starting point and the ending point of the counting bus are both the controller of the counting bus. The working principle and advantages thereof can refer to step S310 of the data counting method of the second embodiment of the chip interface information counting method.

[0142] The interface access module 620 is configured to control the controller to sequentially send bus data of accessing a data item of each interface to the statistical bus in the first beat of each statistical bus cycle. The working principle and advantages of the interface access module 620 can refer to step S320 of the data statistics method of the second embodiment of the chip interface information statistics method.

[0143] The data obtaining module 630 is configured to, when the interface judges that the received statistical bus signal is to obtain the value of a data item of the interface in the first beat of the current statistical bus cycle, send the current value of the data item to the statistical bus in the first beat of the current statistical bus cycle. The working principle and advantages of the data obtaining module 630 can refer to step S330 of the data statistics method of the second embodiment of the chip interface information statistics method.

[0144] The statistics updating module 640 is configured to control the controller to obtain the current value of each data item of each interface from the statistical bus, and refresh the value of the statistical item corresponding to the data item of the interface in the RAM according to the current value. The working principle and advantages of the statistics updating module 640 can refer to step S340 of the data statistics method of the second embodiment of the chip interface information statistics method.

[0145] The times judging module 650 is configured to control the controller to judge whether each statistical item is counted for a set number of times. The working principle and advantages of the times judging module 650 can refer to step S350 of the data statistics method of the second embodiment of the chip interface information statistics method.

[0146] The statistics obtaining module 660 is configured to control the controller to feed back the value of each statistical item of each interface saved in the RAM to the requester of the interface statistics. The working principle and advantages of the statistics obtaining module 660 can refer to step S360 of the data statistics method of the second embodiment of the chip interface information statistics method.

[0147] The embodiment of the present application further provides a chip, which uses the method of the first embodiment of the chip interface information statistics method or the method of the second embodiment of the chip interface information statistics method to count the interface information of the chip.

[0148] It is noted that the above only describes the preferred embodiments of the present application and the applied technical principles. Those skilled in the art can understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments and replacements without departing from the protection scope of the present application. Therefore, although the present application is described in detail through the above embodiments, the present application is not limited to the above embodiments, and more other equivalent embodiments can be included without departing from the concept of the present application, and all belong to the protection scope of the present application.

Claims

1. A method of counting chip interface information, characterized by, The chip comprises: each interface in the chip is connected to a statistical bus arranged inside; a controller of the statistical bus interacts with each interface through the statistical bus according to a transmission protocol set in a bus cycle to obtain a value of a data item corresponding to a target statistical item of a target interface; in the transmission protocol, the bus data at least includes an input indication, when the input indication is valid, the bus data further includes an identification of an accessed interface and an identification of an accessed data item, and when the input indication is invalid, the bus data further includes a value of the accessed data item in the accessed interface; each bus cycle includes two beats, each beat is one system clock, in the first beat, the input indication is valid, and in the second beat, the input indication is invalid; when any interface judges that the received bus data is a value of a data item of the interface in the first beat of any bus cycle, the value of the data item is sent to the statistical bus in the second beat of the bus cycle; the controller updates statistical information according to the obtained value of the data item.

2. The method of claim 1, wherein, The value of each statistical item of each interface fed back by the controller is at least a statistical result of a corresponding data item for a set number of times.

3. The method of claim 1, wherein, When the controller receives a request for a value of any statistical item of any interface, the value of the statistical item is fed back to the requester.

4. The method of claim 3, wherein, The controller cyclically accesses each data item corresponding to each statistical item of each interface; or The controller accesses any data item corresponding to any statistical item of any interface according to a command of the requester.

5. The method of claim 1, wherein, Further comprising: obtaining interface information of each interface, the interface information at least includes one of the following: the number of interfaces of the chip, the number of statistical items and width information of each interface, and width information of each data item corresponding to each statistical item; determining the address bit width and the data bit width of the statistical bus according to the interface information.

6. The method of claim 5, wherein, The statistical information is stored in a RAM of the controller, and further comprising: determining the width and the depth of the RAM according to the interface information.

7. The method of claim 5, wherein, Further comprising: when the controller obtains the statistical items of all interfaces within a set time, determining the number of statistical buses and the number of ports on each statistical bus according to a system clock of the chip and the interface information.

8. A chip interface information statistics device, characterized by comprising: The chip comprises: an interface connection module for connecting each interface in the chip to a statistical bus arranged inside; A data obtaining module is configured to obtain a value of a data item corresponding to a target statistical item of a target interface by a controller of the statistical bus interacting with each interface according to a transmission protocol in a bus cycle through the statistical bus; wherein in the transmission protocol, the bus data at least includes an input indication, when the input indication is valid, the bus data further includes an identification of an accessed interface and an identification of an accessed data item, and when the input indication is invalid, the bus data further includes a value of the accessed data item in the accessed interface; wherein each bus cycle includes two beats, each beat is one system beat, in the first beat, the input indication is valid, and in the second beat, the input indication is invalid; when any interface judges that the received bus data is a value of a data item of the interface in the first beat of any bus cycle, the interface sends the value of the data item to the statistical bus in the second beat of the bus cycle; A statistical updating module is configured to update the statistical information according to the obtained value of the data item.

9. A chip, characterized by The method of any one of claims 1 to 7 is executed to count the interface information.

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