Display driver circuit and display device

Abstract

This application discloses a display driving circuit and a display device. The display driving circuit includes: multiple address input circuits, each of which generates and outputs an address signal based on a clock signal and an encoding signal; a decoder, each of which receives an address signal output from one of the address input circuits at its input terminal, decodes each of the received address signals one by one, and sequentially outputs a trigger signal through its multiple output terminals; and multiple signal latching circuits, each of which receives a trigger signal output from one of the multiple output terminals of the decoder at its input terminal, latches the received trigger signal based on a clock signal, and continuously outputs a trigger signal. Based on the above method, display driving efficiency can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to display driver circuits and display devices. Background Technology

[0002] In the prior art, when refreshing the pixels corresponding to each row or column in the pixel array of a display device, it is usually necessary to send corresponding trigger signals to each row or column of the pixel circuit in the pixel array one by one in order to refresh the screen corresponding to the display device row by row or column by column.

[0003] The drawback of the existing technology is that when the decoder sends the corresponding trigger signal to a row or column of pixel circuits in the pixel array to trigger the refresh of the pixel circuit, it needs to go through two processes: decoding an address signal and continuously sending the trigger signal obtained from the decoding process to the corresponding pixel circuit until the refresh is completed. In other words, the refresh process corresponding to a row or column of pixel circuits needs to include the time of the decoding process and the time of receiving the trigger signal. This makes the refresh time of each row or column of pixel circuits in the pixel array relatively long, which in turn makes the display driving efficiency low. Summary of the Invention

[0004] The main technical problem addressed in this application is how to improve display driver efficiency.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this application is: a display driving circuit, comprising: multiple address input circuits, each address input circuit receiving a clock signal at its first input terminal and an encoding signal at its second input terminal, each address input circuit generating and outputting an address signal based on the clock signal and the encoding signal; a decoder, the decoder including multiple input terminals, each decoder input terminal receiving an address signal output by an address input circuit, the decoder performing decoding processing on each of the received multiple address signals one by one, and sequentially outputting trigger signals through the multiple output terminals of the decoder; multiple signal latching circuits, each signal latching circuit receiving a trigger signal output by one of the multiple output terminals of the decoder, the signal latching circuit latching the received trigger signal based on the clock signal and continuously outputting a trigger signal; wherein, the decoder is used to decode the next address signal among the multiple address signals after the current trigger signal is received by the corresponding signal latching circuit, the current trigger signal being the trigger signal output based on the decoding processing of one of the multiple address signals.

[0006] The display driving circuit also includes a pixel array module, which includes multiple groups of pixel units. Each pixel unit group includes multiple pixel units, and the input of each pixel unit group is connected to the output of the corresponding signal latch circuit. The pixel unit group is used to control the corresponding multiple pixel units to acquire pixel display data when a trigger signal is received. The multiple pixel units update the display based on the pixel display data when a trigger signal is received.

[0007] The display driving circuit also includes a data storage module, which is connected to multiple groups of pixel units. Specifically, when a trigger signal is received, the pixel units control the corresponding multiple pixel units to obtain pixel display data from the data storage module.

[0008] Each signal latching circuit includes a switching module and a latching module. The first input terminal of the switching module receives a clock signal, the second input terminal of the switching module receives a trigger signal output from the corresponding output terminal of the decoder, and the output terminal of the switching module is connected to the input terminal of the latching module. The switching module is used to turn on the second input terminal and the output terminal of the switching module based on the clock signal and output a trigger signal to the latching module. The latching module is used to latch the trigger signal after receiving it and continuously output the trigger signal while latching the trigger signal.

[0009] The switching module is a transmission gate module, which includes an NMOS transistor and a PMOS transistor. The first terminal of the NMOS transistor is connected to the first terminal of the PMOS transistor, and the second terminal of the NMOS transistor is connected to the second terminal of the PMOS transistor. The first terminal of the NMOS transistor is the input terminal of the switching module, and the second terminal of the NMOS transistor is the output terminal of the switching module. The driving terminal of the NMOS transistor receives the clock signal, and the driving terminal of the PMOS transistor receives the complementary signal of the clock signal.

[0010] The latch module includes a first NOT gate, a second NOT gate, and a trigger signal output circuit. The output of the first NOT gate is connected to the input of the second NOT gate, and the output of the second NOT gate is connected to the input of the first NOT gate. The input of the first NOT gate is the input of the latch module, and the output of the first NOT gate is connected to the input of the trigger signal output circuit. The output of the trigger signal output circuit is the output of the latch module. The trigger signal output circuit is used to output a trigger signal based on the signal output by the first NOT gate.

[0011] The first input terminal of the trigger signal output circuit receives a time control signal, and the second input terminal of the trigger signal output circuit receives a signal output by the first NOT gate. The trigger signal output circuit is used to output a trigger signal within a preset output time based on the time control signal and the signal output by the first NOT gate.

[0012] The trigger signal output circuit includes a NOR gate; the first input terminal of the NOR gate receives a time control signal, the second input terminal of the NOR gate receives a signal output by the first NOT gate, and the output terminal of the NOR gate outputs a trigger signal within a preset output time corresponding to the low-level range of the time control signal.

[0013] In this configuration, the switching module is an NMOS transistor, with its first terminal serving as the input and its second terminal as the output. The driving terminal of the NMOS transistor receives a clock signal. Alternatively, the switching module can be a PMOS transistor, with its first terminal serving as the input and its second terminal as the output. The driving terminal of the PMOS transistor receives a complementary signal to the clock signal.

[0014] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: a display device, including the above-mentioned display driving circuit.

[0015] The advantages of this application are as follows: Unlike the prior art, the display driving circuit in the technical solution of this application is equipped with multiple signal latching circuits, which can latch the trigger signal output by the decoder and continuously output it. This allows the decoder to start decoding the next address signal after sending the trigger signal to the corresponding signal latching circuit, without having to maintain the sending of the trigger signal. Based on the above method, the decoder can synchronously decode the next address signal and output the current trigger signal, thereby reducing the refresh time of each row or column of pixel circuit that receives the corresponding trigger signal for refreshing and improving the display driving efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the first embodiment of the display driving circuit of this application;

[0018] Figure 2 This is a timing diagram of one embodiment of the clock signal of this application;

[0019] Figure 3 This is a schematic diagram of the structure of the second embodiment of the display driving circuit of this application;

[0020] Figure 4 This is a schematic diagram of the structure of the third embodiment of the display driving circuit of this application;

[0021] Figure 5 This is a schematic diagram of the structure of the fourth embodiment of the display driving circuit of this application;

[0022] Figure 6 This is a schematic diagram of the structure of the fifth embodiment of the display driving circuit of this application;

[0023] Figure 7 This is a schematic diagram of the structure of the sixth embodiment of the display driving circuit of this application;

[0024] Figure 8 This is a schematic diagram of the structure of one embodiment of the display device of this application. Detailed Implementation

[0025] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] In the description of this application, it is necessary to specify that, unless otherwise expressly stated and limited, the terms "installation," "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or a connection through an intermediate medium. Those skilled in the art will understand the specific meanings of the above terms within the context of this application.

[0028] This application first proposes a display driver circuit, see [link to relevant documentation] Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the display driving circuit of this application, as shown below. Figure 1 As shown, the display driver circuit includes multiple address input circuits 11, a decoder 12, and multiple signal latch circuits 13.

[0029] The first input terminal of each address input circuit 11 is used to receive the clock signal (CLK) provided by the clock circuit, and the second input terminal of each address input circuit 11 is used to receive the corresponding encoding signal. The address input circuit 11 can process the received encoding signal to generate and output the corresponding address signal.

[0030] The decoder 12 includes multiple input terminals, each of which is connected to the output terminal of a corresponding address input circuit 11. This allows the decoder to receive the address signal input by each address input circuit 11 through each input terminal. The decoder 12 can receive multiple address signals simultaneously or sequentially, without limitation. The decoder 12 can decode the received address signals one by one according to a preset order and output the resulting trigger signal.

[0031] Each signal latch circuit 13 has its input terminal connected to one of the multiple output terminals of the decoder 12 to receive the corresponding first trigger signal. Each signal latch circuit 13 also receives a clock signal at its input terminal. After the corresponding decoder 12 outputs the first trigger signal, the connected signal latch circuit 13 can receive the first trigger signal based on the clock signal, latch the received trigger signal, and output a display drive signal based on the latched trigger signal. The display drive signal can be used to control the display device using the display drive circuit to refresh display data.

[0032] Specifically, the decoder 12 is used to decode the next address signal among multiple address signals after the current trigger signal is received by the corresponding signal latch circuit.

[0033] The current trigger signal can be the trigger signal output by the decoder 12 after decoding one of the multiple address signals at the first time, and the next address signal corresponds to the address signal to be decoded by the decoder 12 at the second time, where the second time is the time closest to the first time after the first time. The first time and the second time are two clock cycles that are sequentially adjacent.

[0034] It should be noted that each trigger signal can be used to trigger the refresh display of several pixel units in a row or column of the pixel array. After receiving the trigger signal, the corresponding pixel unit can refresh the display based on the corresponding pixel display data.

[0035] In one application scenario, see Figure 2 , Figure 2 This is a timing diagram of one embodiment of the clock signal of this application, as shown below. Figure 2As shown, the clock signal has three clock cycles over time: the first clock cycle A, the second clock cycle B, and the third clock cycle C. Based on the above display driver circuit, taking the first address signal and the second address signal, which are two adjacent decoding processes, as an example, the decoding process and display driver flow are as follows:

[0036] In the first clock cycle A, the decoder 12 can decode the first address signal to obtain the corresponding first trigger signal.

[0037] During the second clock cycle B, the corresponding signal latch circuit 13 can receive the first trigger signal corresponding to the first address signal, latch the first trigger signal, and continuously output the first display drive signal based on the latched first trigger signal. At the same time, the decoder 12 can stop outputting the first trigger signal and start decoding the second address signal to obtain another corresponding first trigger signal.

[0038] In the third clock cycle C, the corresponding signal latch circuit 13 can receive the first trigger signal corresponding to the second address signal, latch the first trigger signal, and continuously output the second display drive signal based on the latched first trigger signal.

[0039] The above example only illustrates the relevant processes for two address signals and related signals. In practice, based on the above display driver circuit, the decoding process and trigger signal output process corresponding to any address signal can be separated into two clock cycles in the clock signal. This allows the decoding of one address signal and the latching and output of the trigger signal corresponding to another address signal to be performed simultaneously within the same clock cycle. This reduces the output interval time of multiple trigger signals, thereby reducing the total time for refreshing each row / column pixel unit based on multiple trigger signals and improving the efficiency of the display driver.

[0040] Unlike existing technologies, the display driving circuit in this application incorporates multiple signal latching circuits, enabling it to latch and continuously output the trigger signal from the decoder. This allows the decoder to begin decoding the next address signal immediately after sending the trigger signal to the corresponding signal latching circuit, without needing to maintain the transmission of the trigger signal. Based on this approach, the decoder's decoding of the next address signal and the output of the current trigger signal can be synchronized, thereby reducing the refresh time of each row or column of pixel circuits that receive the corresponding trigger signal for refreshing and improving display driving efficiency.

[0041] In one embodiment, see Figure 3 , Figure 3 This is a schematic diagram of the structure of the second embodiment of the display driving circuit of this application, as shown below. Figure 3 As shown, the display driving circuit also includes a pixel array module 14, which includes multiple groups of pixel units 141. Each pixel unit group 141 includes multiple pixel units. The input terminal of each pixel unit group 141 is connected to the output terminal of the corresponding signal latch circuit 13 to receive the corresponding trigger signal.

[0042] Each pixel unit group 141 is used to control the multiple pixel units contained therein to acquire pixel display data when a trigger signal is received. Each pixel unit is used to display based on the acquired pixel display data when a trigger signal is received.

[0043] Specifically, the pixel array module 14 may include a pixel array composed of multiple pixel units, where each pixel unit group 141 may be a number of pixel units corresponding to a row or column in the pixel array. After a number of pixel units in a certain row or column receive a corresponding trigger signal, the number of pixel units in that row or column may respectively obtain the pixel display data to be displayed at the corresponding position from a designated data storage module, so that each pixel unit can refresh the display of the pixel points based on the obtained pixel display data, and then refresh the display sequentially through the pixel units in each row or column, finally completing the overall refresh display of the display screen corresponding to a pixel array.

[0044] Optionally, such as Figure 3 As shown, the display driving circuit also includes a data storage module 15, which is connected to multiple pixel unit groups 141. Specifically, when a trigger signal is received, the pixel unit group 141 controls the multiple pixel units contained therein to obtain pixel display data from the data storage module 15.

[0045] Specifically, there may be one or more data storage modules 15, and each pixel unit group 141 is connected to the data storage module 15 that stores the pixel display data required for the corresponding pixel unit group.

[0046] In one embodiment, see Figure 4 , Figure 4 This is a schematic diagram of the structure of the third embodiment of the display driving circuit of this application, as shown below. Figure 4 As shown, each signal latching circuit 13 includes a switching module 131 and a latching module 132.

[0047] The first input terminal of the switch module 131 receives a clock signal, the second input terminal of the switch module 131 receives a first trigger signal output by the corresponding output terminal of the decoder, and the output terminal of the switch module 131 is connected to the input terminal of the latch module 132.

[0048] The switch module 131 is used to turn on its second input and output terminals based on a clock signal, and output a first trigger signal to the latch module 132. The latch module 132 is used to latch the trigger signal after receiving the first trigger signal, and continuously output a display drive signal based on the latched first trigger signal.

[0049] Specifically, in one example, such as Figure 5 As shown, the switching module 131 includes a transmission gate module, which includes an NMOS transistor 1311 and a PMOS transistor 1312. The first terminal of the NMOS transistor 1311 is connected to the first terminal of the PMOS transistor 1312, and the second terminal of the NMOS transistor 1311 is connected to the second terminal of the PMOS transistor 1312. The first terminal of the NMOS transistor 1311 is the input terminal of the switching module, and the second terminal of the NMOS transistor 1311 is the output terminal of the switching module. The driving terminal of the NMOS transistor 1311 receives a clock signal, and the driving terminal of the PMOS transistor 1312 also receives a clock signal. In a specific embodiment of this application, the clock signals received by the NMOS transistor 1311 and the PMOS transistor 1312 are complementary signals.

[0050] In another example, the switching module 131 can also be a single NMOS transistor, with the first terminal of the NMOS transistor serving as the input terminal of the switching module and the second terminal of the NMOS transistor serving as the output terminal of the switching module. The driving terminal of the NMOS transistor receives a clock signal. Alternatively, the switching module can be a single PMOS transistor, with the first terminal of the PMOS transistor serving as the input terminal of the switching module and the second terminal of the PMOS transistor serving as the output terminal of the switching module. The driving terminal of the PMOS transistor receives a complementary signal to the clock signal.

[0051] Transmission gate modules, compared to ordinary switches such as a single NMOS or a single PMOS transistor, have lower on-resistance and higher off-resistance, resulting in higher data transmission rates.

[0052] Optionally, such as Figure 6 As shown, the latch module 132 includes a first NOT gate 1321, a second NOT gate 1322, and a trigger signal output circuit 1323. The output terminal of the first NOT gate 1321 is connected to the input terminal of the second NOT gate 1322, and the output terminal of the second NOT gate 1322 is connected to the input terminal of the first NOT gate 1321.

[0053] The input terminal of the first NOT gate 1321 is the input terminal of the latch module 132. The output terminal of the first NOT gate 1321 is connected to the input terminal of the trigger signal output circuit 1323. The output terminal of the trigger signal output circuit 1323 is the output terminal of the latch module. The trigger signal output circuit 1323 is used to output a display drive signal based on the signal output by the first NOT gate 1321.

[0054] Specifically, the latch composed of the first NOT gate 1321 and the second NOT gate 1322 can latch the first trigger signal received by the switching module 131 and continuously output it to the trigger signal output circuit 1323, which then outputs the display drive signal. It should be noted that the signal output by the first NOT gate 1321 is a second trigger signal complementary to the first trigger signal. Therefore, the trigger signal output circuit 1323 converts this second complementary signal based on the time control signal to obtain the original first trigger signal, and then outputs the first trigger signal. That is, the display drive signal is the first trigger signal.

[0055] Furthermore, such as Figure 6 As shown, the first input terminal of the trigger signal output circuit 1323 receives the time control signal (tc), and the second input terminal of the trigger signal output circuit 1323 receives the signal output by the first NOT gate. The trigger signal output circuit 1323 is used to output a trigger signal within a preset output time based on the time control signal and the signal output by the first NOT gate.

[0056] Specifically, the trigger signal output circuit 1323 can determine the preset output time through the time control signal, and output the corresponding trigger signal only within the preset output time.

[0057] It should be noted that, through the function of the aforementioned trigger signal output circuit 1323, the total duration of the trigger signal output can be adjusted to reserve the relevant processing time for the corresponding row / column pixel units after receiving the trigger signal, thereby ensuring the normal refresh display of the corresponding display device and improving the reliability of the display driving circuit.

[0058] Furthermore, such as Figure 7 As shown, the trigger signal output circuit 1323 includes a NOR gate.

[0059] The first input of the NOR gate receives the time control signal (tc), the second input of the NOR gate receives the signal output by the first NOT gate 1321, and the output of the NOR gate outputs a trigger signal within a preset output time corresponding to the low level range of the time control signal.

[0060] Specifically, such as Figure 7As shown, assuming the input of the first NOT gate 1321 receives a trigger signal, which is a high-level signal, the output latched by the first NOT gate 1321 will be a low-level signal, meaning the second input of the NOR gate will also receive a low-level signal. In this case, if the first input of the NOR gate receives a low-level signal, the output of the NOR gate will output a high-level signal identical to the trigger signal; conversely, if the first input receives a high-level signal, the output of the NOR gate will output a low-level signal complementary to the trigger signal. Based on this characteristic, the length of the high and low level intervals in the time control signal can be adjusted to achieve the adjustment of the preset output time. This ensures that the NOR gate outputs the trigger signal only within the preset output time, guaranteeing the normal refresh of the display device and improving the reliability of the display driver circuit.

[0061] This application also discloses a display device, see [link to relevant documentation] Figure 8 , Figure 8 This is a schematic diagram of the structure of an embodiment of the display device of this application, as shown below. Figure 8 As shown, the display device 20 includes a display driving circuit 21, which can be the display driving circuit in any of the preceding embodiments, and is not limited here.

[0062] The display device can be any of the following: a television, tablet computer, desktop computer screen, mobile phone, or other type of display device, depending on the specific needs; no limitation is made here. The screen of the display device can be an LCD screen or other types of display screen, depending on the specific needs; no limitation is made here.

[0063] Unlike existing technologies, the display driving circuit in this application incorporates multiple signal latching circuits, enabling it to latch and continuously output the trigger signal from the decoder. This allows the decoder to begin decoding the next address signal immediately after sending the trigger signal to the corresponding signal latching circuit, without needing to maintain the transmission of the trigger signal. Based on this approach, the decoder's decoding of the next address signal and the output of the current trigger signal can be synchronized, thereby reducing the refresh time of each row or column of pixel circuits that receive the corresponding trigger signal for refreshing and improving display driving efficiency.

[0064] In the description of this application, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0066] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0067] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0068] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display driving circuit, characterized in that, include: Multiple address input circuits, each address input circuit receiving a clock signal at its first input terminal and an encoding signal at its second input terminal, each address input circuit generating and outputting an address signal based on the clock signal and the encoding signal; The decoder includes multiple input terminals, each input terminal of which receives an address signal output by an address input circuit. The decoder performs decoding processing on each of the multiple received address signals and sequentially outputs trigger signals through the multiple output terminals of the decoder. Multiple signal latching circuits are provided. The input terminal of each signal latching circuit receives the trigger signal and the clock signal output by one output terminal of the decoder. The signal latching circuit latches the received trigger signal based on the clock signal and continuously outputs the trigger signal. The decoder is used to decode the next address signal among the plurality of address signals after the current trigger signal is received by the corresponding signal latch circuit. The current trigger signal is the trigger signal output based on the decoding of one of the plurality of address signals.

2. The display driving circuit according to claim 1, characterized in that, The display driving circuit further includes a pixel array module, which includes multiple groups of pixel units, each group of pixel units including multiple pixel units, and the input terminal of each group of pixel units is connected to the output terminal of the corresponding signal latch circuit. The pixel unit group is used to control the corresponding plurality of pixel units to acquire pixel display data respectively when the trigger signal is received, and the plurality of pixel units update the display based on the pixel display data respectively when the trigger signal is received.

3. The display driving circuit according to claim 2, characterized in that, The display driving circuit also includes a data storage module, which is connected to multiple groups of pixel units respectively. The pixel unit group is specifically used to control the corresponding multiple pixel units to obtain the pixel display data from the data storage module when the trigger signal is received.

4. The display driving circuit according to any one of claims 1 to 3, characterized in that, Each of the aforementioned signal latching circuits includes a switching module and a latching module; The first input terminal of the switch module receives the clock signal, the second input terminal of the switch module receives the trigger signal output by the corresponding output terminal of the decoder, and the output terminal of the switch module is connected to the input terminal of the latch module. The switching module is used to turn on the second input terminal and the output terminal of the switching module based on the clock signal, and output the trigger signal to the latch module; The latching module is used to latch the trigger signal after receiving the trigger signal, and to continuously output the trigger signal while latching the trigger signal.

5. The display driving circuit according to claim 4, characterized in that, The switching module is a transmission gate module, which includes an NMOS transistor and a PMOS transistor. The first end of the NMOS transistor is connected to the first end of the PMOS transistor, and the second end of the NMOS transistor is connected to the second end of the PMOS transistor. The first end of the NMOS transistor is the input end of the switching module, and the second end of the NMOS transistor is the output end of the switching module. The driving terminal of the NMOS transistor receives the clock signal, and the driving terminal of the PMOS transistor receives the complementary signal of the clock signal.

6. The display driving circuit according to claim 4, characterized in that, The latch module includes a first NOT gate, a second NOT gate, and a trigger signal output circuit. The output terminal of the first NOT gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the input terminal of the first NOT gate. The input terminal of the first NOT gate is the input terminal of the latch module, and the output terminal of the first NOT gate is connected to the input terminal of the trigger signal output circuit. The output terminal of the trigger signal output circuit is the output terminal of the latch module. The trigger signal output circuit is used to output the trigger signal based on the signal output by the first NOT gate.

7. The display driving circuit according to claim 6, characterized in that, The first input terminal of the trigger signal output circuit receives a time control signal, and the second input terminal of the trigger signal output circuit receives the signal output by the first NOT gate. The trigger signal output circuit is used to output the trigger signal within a preset output time based on the time control signal and the signal output by the first NOT gate.

8. The display driving circuit according to claim 7, characterized in that, The trigger signal output circuit includes a NOR gate; The first input terminal of the NOR gate receives a time control signal, the second input terminal of the NOR gate receives the signal output by the first NOT gate, and the output terminal of the NOR gate outputs the trigger signal within a preset output time corresponding to the low-level range of the time control signal.

9. The display driving circuit according to claim 4, characterized in that, The switching module is an NMOS transistor. The first terminal of the NMOS transistor is the input terminal of the switching module, and the second terminal of the NMOS transistor is the output terminal of the switching module. The driving terminal of the NMOS transistor receives the clock signal, or The switching module is a PMOS transistor, with the first terminal of the PMOS transistor serving as the input terminal of the switching module and the second terminal of the PMOS transistor serving as the output terminal of the switching module. The driving terminal of the PMOS transistor receives the complementary signal of the clock signal.

10. A display device, characterized in that, Includes the display driving circuit as described in any one of claims 1 to 9.

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