LCD panel

Abstract

The liquid crystal display panel provided in the present application includes an array substrate, an opposing substrate, and a liquid crystal layer arranged between the array substrate and the opposing substrate. By providing a first pixel sub-unit electrically connected to a first data line and a first scan line on the array substrate and providing a second pixel sub-unit electrically connected to a second data line and a second scan line on the opposing substrate, the second pixel sub-unit and the first pixel sub-unit corresponding in position form a pixel unit, so that the voltage of the first pixel sub-unit and the voltage of the second pixel sub-unit in the same pixel unit can be independently controlled without providing a common electrode on the entire surface of the opposing substrate, thereby achieving independent control of the deflection of liquid crystal molecules in corresponding areas of the liquid crystal layer, thereby improving the problems of flickering and uneven brightness of the display screen of the liquid crystal display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a liquid crystal display panel. Background Art

[0002] Liquid crystal display panels in related technologies charge the liquid crystal layer by adjusting the voltage difference between the pixel electrodes and the common electrode to control the deflection of liquid crystal molecules in the liquid crystal layer. However, the common electrode in traditional LCD panels is designed to be a full-surface common electrode. The common voltage across the entire surface is uneven, and the common voltage of the common electrode is easily affected by other large voltages in the LCD panel, causing it to drift. As a result, the voltage difference between the pixel electrodes and the common electrode in different areas varies, leading to problems such as flicker and uneven brightness (mura) on the LCD display screen. Summary of the Invention

[0003] The present application provides a liquid crystal display panel, which can improve the problem of flickering and uneven brightness of the display screen of the liquid crystal display panel.

[0004] The present application provides a liquid crystal display panel, comprising:

[0005] an array substrate, the array substrate comprising a plurality of first scan lines, a plurality of first data lines, and a plurality of first pixel sub-units, the plurality of first scan lines and the plurality of first data lines defining a plurality of pixel electrode regions, a first pixel sub-unit being disposed in a pixel electrode region, and a first pixel sub-unit being electrically connected to a first scan line and a first data line;

[0006] an opposing substrate disposed opposite to the array substrate, the opposing substrate comprising a plurality of second scan lines, a plurality of second data lines, and a plurality of second pixel sub-units, the plurality of second scan lines and the plurality of second data lines defining a plurality of opposing electrode regions, a second pixel sub-unit being disposed in the opposing electrode region, a second pixel sub-unit being electrically connected to a second scan line and a second data line, a position of the second pixel sub-unit in the opposing substrate corresponding to a position of the first pixel sub-unit in the array substrate, and the second pixel unit and the corresponding first pixel sub-unit forming a pixel unit;

[0007] a liquid crystal layer, the liquid crystal layer being provided between the array substrate and the counter substrate;

[0008] In one of the pixel units, one of the first data signal and the second data signal input to the first pixel sub-unit by the first data line has a first voltage value, and the other of the first data signal and the second data signal input to the second pixel sub-unit by the second data line has a second voltage value.

[0009] In the liquid crystal display panel provided in the present application, the liquid crystal display panel also includes a data driver, the first data line and the second data line are both electrically connected to the data driver, and the data driver is used to transmit one of the first data signal and the second data signal to the first data line, and to transmit the other of the first data signal and the second data signal to the second data line.

[0010] In the liquid crystal display panel provided in the present application, the liquid crystal display panel further includes a timing controller;

[0011] The timing controller is electrically connected to the data driver, and is configured to provide the data driver with display data for generating the first data signal and the second data signal.

[0012] In the liquid crystal display panel provided in the present application, the data driver includes a first data sub-driver and a second data sub-driver;

[0013] The first data sub-driver is electrically connected to the first data line, and the first data sub-driver transmits one of the first data signal and the second data signal;

[0014] The second data sub-driver is electrically connected to the second data line, and the second data sub-driver transmits the other of the first data signal and the second data signal.

[0015] In the liquid crystal display panel provided in the present application, when displaying a picture with a grayscale value of zero, in the same pixel unit, the first voltage value and the second voltage value are the same;

[0016] When displaying an image with a grayscale value greater than zero, in the same pixel unit, the first voltage value and the second voltage value are different.

[0017] In the liquid crystal display panel provided in the present application, in an n-th frame displaying a picture with a grayscale value greater than zero, the first voltage value of the first data signal transmitted by the first data line is greater than the second voltage value of the second data signal transmitted by the second data line;

[0018] In the (n+1)th frame displaying a grayscale value greater than zero, the first voltage value of the first data signal transmitted by the first data line is less than the second voltage value of the second data signal transmitted by the second data line;

[0019] Wherein, n is an integer greater than or equal to 1.

[0020] In the liquid crystal display panel provided in the present application, the first pixel subunit includes a first thin film transistor and a first pixel electrode, the gate of the first thin film transistor is electrically connected to the first scan line, one of the source and the drain of the first thin film transistor is electrically connected to the first data line, and the other of the source and the drain of the first thin film transistor is electrically connected to the first pixel electrode;

[0021] The second pixel subunit includes a second thin film transistor and a second pixel electrode, the gate of the second thin film transistor is electrically connected to the second scan line, one of the source and the drain of the second thin film transistor is electrically connected to the first data line, and the other of the source and the drain of the second thin film transistor is electrically connected to the second pixel electrode.

[0022] In the liquid crystal display panel provided in the present application, in one of the pixel units, the starting moment of the first scanning signal output by the first scanning line to turn on the first thin film transistor is the same as the starting moment of the second scanning signal output by the second scanning line to turn on the second thin film transistor, and the ending moment of the first scanning signal is the same as the ending moment of the second scanning signal.

[0023] In the liquid crystal display panel provided in the present application, in one of the pixel units, the starting moment of the first scanning signal output by the first scanning line to turn on the first thin film transistor is the same as the starting moment of the first data signal output by the first data line to charge the first pixel electrode, and the starting moment of the second scanning signal output by the second scanning line to turn on the second thin film transistor is the same as the starting moment of the second data signal output by the second data line to charge the second pixel electrode.

[0024] In the liquid crystal display panel provided in the present application, the liquid crystal display panel also includes a scan driver, the first scan line and the second scan line are both electrically connected to the scan driver, and the scan driver is used to provide the first scan signal to the first scan line and provide the second scan signal to the second scan line.

[0025] In the liquid crystal display panel provided by the present application, a first pixel subunit electrically connected to the first data line and the first scan line is provided on the array substrate, and a second pixel subunit electrically connected to the second data line and the second scan line is provided on the opposite substrate, so that the second pixel subunit and the first pixel subunit corresponding in position form a pixel unit, and the voltage of the first pixel subunit and the voltage of the second pixel subunit in the same pixel unit are independently controlled without providing a common electrode on the entire surface of the opposite substrate, thereby realizing independent control of the deflection of liquid crystal molecules in corresponding areas of the liquid crystal layer, and improving the problems of flickering and uneven brightness of the display screen of the liquid crystal display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A cross-sectional view of a liquid crystal display panel provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of a structure of an array substrate provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of a structure of an opposing substrate provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of a first structure of a liquid crystal display panel provided in an embodiment of the present application;

[0030] Figure 5 for Figure 4 A schematic diagram of the position of the pixel unit in;

[0031] Figure 6 for Figure 4 A schematic diagram of an equivalent circuit of a pixel unit in FIG.

[0032] Figure 7 for Figure 6 A timing diagram of a first scanning signal and a second scanning signal of an equivalent circuit;

[0033] Figure 8 A schematic diagram of a second structure of a liquid crystal display panel provided in an embodiment of the present application;

[0034] Figure 9 A schematic diagram of a third structure of a liquid crystal display panel provided in an embodiment of the present application;

[0035] Figure 10a for Figure 4 A schematic diagram showing the state of the liquid crystal display panel at the first moment;

[0036] Figure 10b for Figure 4 A schematic diagram showing the state of the liquid crystal display panel at the second moment;

[0037] Figure 10c for Figure 4 FIG. 1 is a schematic diagram showing the state of the liquid crystal display panel at the third moment. DETAILED DESCRIPTION

[0038] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. The described embodiments are only used to explain the ideas created by the present invention and should not be regarded as limiting the scope of protection of this application.

[0039] The embodiment of the present application provides a liquid crystal display panel, such as Figures 1 to 3 As shown, the liquid crystal display panel 1000 includes an array substrate 100 , an opposite substrate 200 and a liquid crystal layer 300 .

[0040] The array substrate 100 includes a plurality of first scan lines G10 , a plurality of first data lines D10 , and a plurality of first pixel sub-units 10 .

[0041] Multiple first scan lines G10 and multiple first data lines D10 define multiple pixel electrode areas P10. A first pixel sub-unit 10 is disposed in a pixel electrode area P10, i.e., multiple first pixel sub-units 10 are disposed in a one-to-one correspondence with multiple pixel electrode areas P10. A first pixel sub-unit 10 disposed in a pixel electrode area P10 is electrically connected to a first scan line G10, and this first pixel sub-unit 10 is also electrically connected to a first data line D10.

[0042] The first scan line G10 is used to control the charging time of the first pixel subunit 10. The first data line D10 is used to provide a charging voltage to the first pixel subunit 10, that is, the first data line D10 is used to control the voltage value of the charging voltage of the first pixel subunit 10.

[0043] Since each first pixel sub-unit 10 is electrically connected to a first scan line G10 and a first data line D10 , the charging time and charging voltage of each first pixel sub-unit 10 can be independently controlled.

[0044] The counter substrate 200 is disposed opposite to the array substrate 100 and includes a plurality of second scan lines G20 , a plurality of second data lines D20 and a plurality of second pixel sub-units 20 .

[0045] Multiple second scan lines G20 and multiple second data lines D20 define multiple opposing electrode areas P20. A second pixel sub-unit 20 is disposed in each opposing electrode area P20, i.e., multiple second pixel sub-units 20 are disposed in a one-to-one correspondence with the multiple opposing electrode areas P20. A second pixel sub-unit 20 disposed in the opposing electrode area P20 is electrically connected to a second scan line G20, and this second pixel sub-unit 20 is also electrically connected to a second data line D20.

[0046] The second scan line G20 is used to control the charging time of the second pixel subunit 20. The second data line D20 is used to provide a charging voltage to the second pixel subunit 20, that is, the second data line D20 is used to control the voltage value of the charging voltage of the second pixel subunit 20.

[0047] Since each second pixel sub-unit 20 is electrically connected to a second scan line G20 and a second data line D20 , the charging time and charging voltage of each second pixel sub-unit 20 can be independently controlled.

[0048] Furthermore, a second pixel subunit 20 is located in the opposite substrate 200 and corresponds to a first pixel subunit 10 in the array substrate 100 . The second pixel subunit 20 and the corresponding first pixel subunit 10 form a pixel unit 01 .

[0049] like Figure 4 As shown, in a pixel unit 01, the position of the second pixel subunit 20 in the opposing substrate 200 corresponds to the position of the first pixel subunit 10 in the array substrate 100, which means that the orthographic projection of the second pixel subunit 20 on the opposing substrate 200 at least partially overlaps with the orthographic projection of the first pixel subunit 10 on the array substrate 100. In a preferred embodiment, the orthographic projection of the second pixel subunit 20 on the opposing substrate 200 completely overlaps with the orthographic projection of the first pixel subunit 10 on the array substrate 100.

[0050] The liquid crystal layer 300 is disposed between the array substrate 100 and the counter substrate 200. The liquid crystal layer 300 includes a plurality of liquid crystal molecules. Under the action of an external voltage, the liquid crystal molecules in the liquid crystal layer 300 are deflected, and linearly polarized light incident on the liquid crystal layer 300 is transmitted or blocked, acting as a liquid crystal shutter.

[0051] In a pixel unit 01, one of the first data signal and the second data signal input to the first pixel sub-unit 10 via the first data line D10 has a first voltage value, and the other of the first data signal and the second data signal input to the second pixel sub-unit 20 via the second data line D20 has a second voltage value. Furthermore, the first voltage value and the second voltage value may be the same or different.

[0052] In this embodiment, the external voltage that causes the liquid crystal molecules of the liquid crystal layer 300 to deflect mainly refers to the voltage of the first pixel subunit 10 after being charged and the voltage of the second pixel subunit 20 after being charged, and the voltage of the first pixel subunit 10 after being charged depends on the first voltage value of one of the first data signal and the second data signal input to the first pixel subunit 10 through the first data line D10, and the voltage of the second pixel subunit 20 after being charged depends on the second voltage value of the other of the first data signal and the second data signal input to the second pixel subunit 20 through the second data line D20.

[0053] When displaying an image with a grayscale value of zero (L0), that is, when displaying an image with the lowest grayscale, the first voltage value and the second voltage value are the same in the same pixel unit 01. Because the first voltage value and the second voltage value are the same in the same pixel unit 01, the first pixel subunit 10 and the second pixel subunit 20 in the same pixel unit 01 are at the same potential, the voltage difference is zero, and the liquid crystal molecules in the corresponding areas of the liquid crystal layer 300 do not deflect, thereby displaying the lowest grayscale.

[0054] When displaying an image with a grayscale value greater than zero, that is, when displaying an image other than the lowest grayscale (L1-L255), the first voltage value and the second voltage value within the same pixel unit 01 are different. Because the first voltage value and the second voltage value within the same pixel unit 01 are different, a non-zero voltage difference is formed between the first pixel subunit 10 and the second pixel subunit 20 within the same pixel unit 01. Liquid crystal molecules in corresponding regions of the liquid crystal layer 300 are charged based on this voltage difference, causing the liquid crystal molecules in the corresponding regions to deflect, thereby displaying the corresponding grayscale.

[0055] In this embodiment, since the charging time and charging voltage of each first pixel sub-unit 10 and the charging time and charging voltage of each second pixel sub-unit 20 can be independently controlled, the first voltage value in each pixel unit 01 and the second voltage value in each pixel unit 01 can be independently controlled. In other words, the voltage difference between the first pixel sub-unit 10 and the second pixel sub-unit 20 in each pixel unit 01 can be independently controlled, thereby independently controlling the liquid crystal molecules in corresponding areas of the liquid crystal layer 300. Since the voltage difference of each pixel unit 01 can be controlled, it is possible to ensure that the pixel units 01 located in different areas of the liquid crystal display panel 1000 have a consistent voltage difference, thereby reducing the possibility of flicker and / or mura in the display image of the liquid crystal display panel 1000 and improving the display quality of the liquid crystal display panel 1000.

[0056] Because the liquid crystal molecules in the liquid crystal layer 300 cannot remain at a fixed voltage for a long time, an AC drive method is required to alternately charge the liquid crystal molecules. This involves alternating between positive and negative voltages. For example, in a related art liquid crystal display panel with a full-surface common electrode, in the nth frame displaying a grayscale value greater than zero (e.g., L255), the first tie-point voltage is 15V and the common voltage of the common electrode is 7.8V. In this case, the liquid crystal layer 300 is charged using a positive voltage with a voltage difference of 7.2V. In the (n+1)th frame displaying a grayscale value greater than zero (e.g., L255), the second tie-point voltage is 0.2V. Since the common voltage of the common electrode remains unchanged, the common voltage remains at 7.8V. Therefore, the liquid crystal layer 300 is charged using a negative voltage with a voltage difference of 7.6V. Specifically, in the related art, using positive and negative voltages to alternately charge the liquid crystal layer 300 to display the same non-zero grayscale image requires two preset tie-point voltages. However, to display a full grayscale image (L0-L255), 14 to 22 preset tie-point voltages are required. Furthermore, even with multiple tie-point voltages, there's no guarantee that the positive and negative voltages are identical. Consequently, the display may flicker or appear inconsistently bright or dark due to the difference in the positive and negative voltages.

[0057] In this embodiment, in the nth frame displaying a grayscale value greater than zero, a first voltage value of a first data signal transmitted by the first data line D10 of the liquid crystal display panel 1000 is greater than a second voltage value of a second data signal transmitted by the second data line D20. In the (n+1)th frame displaying a grayscale value greater than zero, a first voltage value of the first data signal transmitted by the first data line D10 of the liquid crystal display panel 1000 is less than a second voltage value of the second data signal transmitted by the second data line D20. n is an integer greater than or equal to 1.

[0058] In the nth frame displaying a grayscale value greater than zero, for the first pixel subunit 10 and the second pixel subunit 20 in the same pixel unit 01, the first voltage value of the first data signal transmitted from the first data line D10 to the first pixel subunit 10 is greater than the second voltage value of the second data signal transmitted from the second data line D20 to the second pixel subunit 20. For example, the first voltage value of the first data signal transmitted from the first data line D10 to the first pixel subunit 10 is 8 volts (V), and the second voltage value of the second data signal transmitted from the second data line D20 to the second pixel subunit 20 is 1V. Therefore, in the nth frame display, the voltage difference between the first pixel subunit 10 and the second pixel subunit 20 is 7V, and the liquid crystal molecules in the corresponding areas of the liquid crystal layer 300 are charged based on the positive voltage of 7V.

[0059] Similarly, in the (n+1)th frame displaying a grayscale value greater than zero, for the first pixel subunit 10 and the second pixel subunit 20 in the same pixel unit 01, the first voltage value of the first data signal transmitted by the first data line D10 is less than the second voltage value of the second data signal transmitted by the second data line D20. For example, the first voltage value of the first data signal transmitted by the first data line D10 to the first pixel subunit 10 is 1V, and the second voltage value of the second data signal transmitted by the second data line D20 to the second pixel subunit 20 is 8V. Therefore, in the (n+1)th frame displaying the image, the voltage difference between the first pixel subunit 10 and the second pixel subunit 20 is -7V, and the liquid crystal molecules in the corresponding regions of the liquid crystal layer 30 are charged based on the negative voltage of -7V.

[0060] In the adjacent nth frame displaying a grayscale value greater than zero and the n+1th frame displaying a grayscale value greater than zero, the same pixel unit 01 alternately charges the liquid crystal molecules in corresponding regions of the liquid crystal layer 30 using positive and negative voltages of equal magnitude, ensuring that the display image of the liquid crystal display panel 1000 does not exhibit flickering or uneven brightness due to the difference in the magnitude of the positive and negative voltages. Furthermore, because the data voltage input to any second pixel subunit 20 can be independently controlled, only one tie-point voltage needs to be preset to display the same grayscale image. Compared to related technologies, the liquid crystal display panel provided in this embodiment can also reduce the number of tie-point voltages by half.

[0061] like Figure 6 As shown, the first pixel subunit 10 includes a first thin-film transistor T1 and a first pixel electrode c01. The gate of the first thin-film transistor T1 is electrically connected to the first scan line G10, one of the source and drain of the first thin-film transistor T1 is electrically connected to the first data line D10, and the other of the source and drain of the first thin-film transistor T1 is electrically connected to the first pixel electrode c01. The second pixel subunit 20 includes a second thin-film transistor T2 and a second pixel electrode c02. The gate of the second thin-film transistor T2 is electrically connected to the second scan line G20, one of the source and drain of the second thin-film transistor T2 is electrically connected to the second data line D20, and the other of the source and drain of the second thin-film transistor T2 is electrically connected to the second pixel electrode c02.

[0062] In the first pixel subunit 10, the charging start time, charging end time, and charging duration of the first pixel electrode c01 are controlled by controlling the on and off states of the first thin-film transistor T1. Similarly, in the second pixel subunit 20, the charging start time, charging end time, and charging duration of the second pixel electrode c02 are controlled by controlling the on and off states of the second thin-film transistor T2. For the same pixel subunit 01, when the first thin-film transistor T1 is on, it provides one of the first and second data signals transmitted by the first data line D10 to the first pixel electrode c01, charging the first pixel electrode c01. When the second thin-film transistor T2 is on, it provides the other of the first and second data signals transmitted by the second data line D20 to the second pixel electrode c02, charging the second pixel electrode c02. The charging between the first and second pixel electrodes c01 and c02 creates a voltage difference, and the liquid crystal molecules in the corresponding regions deflect based on the voltage difference between the first and second pixel electrodes c01 and c02.

[0063] In the same pixel unit 01, the position of the first pixel electrode c01 on the array substrate 100 corresponds to the position of the second pixel electrode c02 on the opposing substrate 200, that is, the orthographic projection of the first pixel electrode c01 on the array substrate 100 completely overlaps or partially overlaps with the orthographic projection of the second pixel electrode c02 on the opposing substrate 200.

[0064] like Figure 6 as well as Figure 7 As shown, in a pixel unit 01, the start time t11 of the first scan signal Scan1 output by the first scan line G10 to turn on the first thin film transistor T1 is the same as the start time t21 of the second scan signal Scan2 output by the second scan line G20 to turn on the second thin film transistor T2. Furthermore, the end time t12 of the first scan signal Scan1 output by the first scan line G10 to turn on the first thin film transistor T1 is the same as the end time t22 of the second scan signal Scan2 output by the second scan line G20 to turn on the second thin film transistor T2.

[0065] In this embodiment, for the same pixel unit 01, the start-up time of the first thin film transistor T1 and the second thin film transistor T2 are controlled to be the same so as to start charging the first pixel electrode c01 and the second pixel electrode c02 at the same time; the end-up time of the first thin film transistor T1 and the second thin film transistor T2 are controlled to be the same so as to end charging the first pixel electrode c01 and the second pixel electrode c02 at the same time.

[0066] The first thin film transistor T1 and the second thin film transistor T2 can both be N-type thin film transistors, such that the gate of the first thin film transistor T1 is turned on when receiving a high-level first scan signal Scan1, and the gate of the second thin film transistor T2 is turned on when receiving a high-level second scan signal Scan2. The first thin film transistor T1 and the second thin film transistor T2 can both be P-type thin film transistors, such that the gate of the first thin film transistor T1 is turned on when receiving a low-level first scan signal Scan1, and the gate of the second thin film transistor T2 is turned on when receiving a low-level second scan signal Scan2. The first thin film transistor T1 can also be either a P-type thin film transistor or an N-type thin film transistor, and the second thin film transistor T2 can also be the other of a P-type thin film transistor and an N-type thin film transistor.

[0067] In the same pixel unit 01, the start time of the first data signal output by the first data line D10 to charge the first pixel electrode c01 coincides with the start time of the first scan signal output by the first scan line G10 to turn on the first thin-film transistor T1. While the first thin-film transistor T1 is in the on-state based on the first scan signal, one of the source and drain of the first thin-film transistor T1 provides the first data signal to the other of the source and drain of the first thin-film transistor T1, thereby outputting the first data signal to the first pixel electrode c01 and charging the first pixel electrode c01. This prevents leakage in the first thin-film transistor T1 due to long-term operation, which could cause errors in the voltage value of the first pixel electrode c01. The end time of the first data signal output by the first data line D10 to charge the first pixel electrode c01 and the end time of the first scan signal output by the first scan line G10 to turn on the first thin-film transistor T1 can be the same as or different from the end time of the first data signal output by the first data line D10 to charge the first pixel electrode c01.

[0068] In the same pixel unit 01, the start time of the second data signal output by the second data line D20 to charge the second pixel electrode c02 coincides with the start time of the second scan signal output by the second scan line G20 to turn on the second thin-film transistor T2. While the second thin-film transistor T2 is in the on-state based on the second scan signal, one of the source and drain of the second thin-film transistor T2 provides the second data signal to the other of the source and drain of the second thin-film transistor T2, thereby outputting the second data signal to the second pixel electrode c02 and charging the second pixel electrode c02. This prevents leakage in the second thin-film transistor T2 due to long-term operation, which could cause errors in the voltage value of the second pixel electrode c02. The end time of the first data signal output by the second data line D20 to charge the second pixel electrode c02 and the end time of the second scan signal output by the second scan line G20 to turn on the second thin-film transistor T2 can be the same as or different from each other.

[0069] In the same pixel unit 01, the starting moment of the first scanning signal output by the first scanning line G10 to turn on the first thin film transistor T1 may also be the same as the starting moment of the second scanning signal output by the second scanning line G20 to turn on the second thin film transistor T2, the starting moment of the first data signal output by the first data line D10 to charge the first pixel electrode c01, and the starting moment of the second data signal output by the second data line D20 to charge the second pixel electrode c02, so that the first thin film transistor T1 and the second thin film transistor T2 in the same pixel unit 01 are turned on at the same time and the first data signal and the second data signal are output to the first pixel electrode c01 and the second pixel electrode c02 respectively. Moreover, the end moment of the first scanning signal output by the first scanning line G10 to turn on the first thin film transistor T1 is the same as the end moment of the second scanning signal output by the second scanning line G20 to turn on the second thin film transistor T2, and the end moment of the first data signal output by the first data line D10 to charge the first pixel electrode c01 may be the same as or different from the end moment of the first scanning signal output by the first scanning line G10 to turn on the first thin film transistor T1, and the end moment of the first data signal output by the second data line D20 to charge the second pixel electrode c02 may be the same as or different from the end moment of the second scanning signal output by the second scanning line G20 to turn on the second thin film transistor T2.

[0070] like Figure 8 As shown, the liquid crystal display panel 1000 further includes a data driver 400, which is electrically connected to both the first data line D10 and the second data line D20. The data driver 400 is configured to transmit one of the first data signal and the second data signal to the first data line D10 and to transmit the other of the first data signal and the second data signal to the second data line.

[0071] The data driver 400 transmits a first data signal to the first data line D10 in the array substrate 100, and then transmits a second data signal to the second data line D20 in the counter substrate 200. Within the same pixel unit 01, the first pixel subunit 10 has a first voltage value based on the first data signal transmitted by the first data line D10, and the second pixel subunit 20 has a second voltage value based on the second data signal transmitted by the second data line D20. Because the first and second voltage values ​​differ, a voltage difference is formed between the first and second pixel subunits 10 and 20, and the liquid crystal molecules in the corresponding areas are charged based on the voltage difference, thereby deflecting.

[0072] The data driver 400 transmits a second data signal to the first data line D10 in the array substrate 100, and the data driver 400 transmits a first data signal to the second data line D20 in the opposing substrate 200. In the same pixel unit 01, the first pixel subunit 10 has a first voltage value based on the second data signal transmitted by the first data line D10, and the second pixel subunit 20 has a second voltage value based on the first data signal transmitted by the second data line D20. Because the first voltage value and the second voltage value are different, a voltage difference is formed between the first pixel subunit 10 and the second pixel subunit 20, and the liquid crystal molecules in the corresponding areas are charged based on the voltage difference to achieve deflection. Because the first voltage value and the second voltage value are the same, the first pixel subunit 10 and the second pixel subunit 20 have the same potential, and the liquid crystal molecules in the corresponding areas do not deflect.

[0073] The data driver 400 generates a first data signal and a second data signal, and provides one of the first data signal and the second data signal to the first data line D10 and the other of the first data signal and the second data signal to the second data line D20. The data driver 400 may include a chip-on-film data driver circuit or a data driver chip (Data Driver IC, DIC). The data driver chip is electrically connected to the first data line D10 and the second data line D20 via a flexible film and / or a pad.

[0074] In this embodiment, the first data signal and the second data signal are provided by the same data driver 400 , that is, the charging voltage of the first pixel subunit 10 and the charging voltage of the second pixel subunit 20 in each pixel unit 01 are adjusted and controlled by the same data driver 400 .

[0075] Compared to the technical solution in the related art in which a common electrode is provided on the entire surface of the opposing substrate 200 and the voltage of the common electrode portion corresponding to the first pixel sub-unit 10 cannot be individually adjusted and controlled, the liquid crystal display panel 1000 provided in this embodiment can individually adjust and control the charging voltage of the first pixel sub-unit 10 on the array substrate 100 and the second pixel sub-unit 20 on the opposing substrate 200 through the data driver 400, thereby achieving individual adjustment and control of the voltage difference formed by any pixel unit 01 in the liquid crystal display panel 1000, reducing the possibility of flickering and / or mura phenomena in the display screen of the liquid crystal display panel 1000, and improving the display quality of the liquid crystal display panel 1000.

[0076] like Figure 9As shown, the data driver 400 includes a first data sub-driver 401 and a second data sub-driver 402. The first data sub-driver 401 is electrically connected to the first data line D10 and transmits one of a first data signal and a second data signal. The second data sub-driver 402 is electrically connected to the second data line D20 and transmits the other of the first data signal and the second data signal.

[0077] The first data sub-driver 401 transmits a first data signal to the first data line D10 in the array substrate 100, while the second data sub-driver 402 transmits a second data signal to the second data line D20 in the opposing substrate 200. Within the same pixel unit 01, the first pixel sub-unit 10 has a first voltage value based on the first data signal transmitted by the first data line D10, and the second pixel sub-unit 20 has a second voltage value based on the second data signal transmitted by the second data line D20. Because the first and second voltage values ​​differ, a voltage difference is formed between the first pixel sub-unit 10 and the second pixel sub-unit 20, and the liquid crystal molecules in the corresponding areas are charged based on the voltage difference, thereby deflecting.

[0078] The first data sub-driver 401 transmits a second data signal to the first data line D10 in the array substrate 100, while the second data sub-driver 402 transmits the first data signal to the second data line D20 in the opposing substrate 200. Within the same pixel unit 01, the first pixel sub-unit 10 has a first voltage value based on the second data signal transmitted by the first data line D10, and the second pixel sub-unit 20 has a second voltage value based on the first data signal transmitted by the second data line D20. Because the first and second voltage values ​​differ, a voltage difference is formed between the first pixel sub-unit 10 and the second pixel sub-unit 20, and the liquid crystal molecules in the corresponding areas are charged based on the voltage difference, thereby deflecting.

[0079] The first data sub-driver 401 generates one of a first data signal and a second data signal and provides the first data signal to the first data line D10. The first data sub-driver 401 may include a chip-on-film type data driver circuit or a data driver chip (Data Driver IC, DIC), which may be electrically connected to the first data line D10 via a flexible film and / or a pad.

[0080] The second data sub-driver 402 generates the other of the first data signal and the second data signal and provides the other of the first data signal and the second data signal to the second data line D20. The second data sub-driver 402 may include a chip-on-film type data driver circuit or a data driver chip (Data Driver IC, DIC), which may be electrically connected to the second data line D20 via a flexible film and / or a pad.

[0081] In this embodiment, the first data signal and the second data signal are provided by different data drivers, that is, the charging voltage of the first pixel sub-unit 10 and the charging voltage of the second pixel sub-unit 20 in each pixel unit 01 are adjusted and controlled respectively by the first data sub-driver 401 and the second data sub-driver 402, so as to reduce the lead-out load of the data driver and improve the data signal output delay problem.

[0082] like Figure 8 as well as Figure 9 As shown, the liquid crystal display panel 1000 further includes a timing controller 500. The timing controller 500 is electrically connected to the data driver 400. The timing controller 500 is configured to provide display data for generating a first data signal and a second data signal to the data driver 400. That is, the data driver 400 decodes the display data provided by the timing controller 500, decodes the display data into a voltage difference signal, and generates the first data signal and the second data signal based on the voltage difference signal.

[0083] The timing controller 500 is mounted on a printed circuit board (PCB) or a flexible printed circuit film in the form of a chip on film. The timing controller 500 receives input image data and input control signals from an external device (such as a host device or image processor). The input display data may include multiple pixel data for multiple pixel units 01, and the input control signals may include a master clock signal, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal. The timing controller 500 then generates display data based on the received input image data.

[0084] like Figure 8 as well as Figure 9 As shown, the liquid crystal display panel 1000 further includes a scan driver 600, and the first scan line G10 and the second scan line G20 are both electrically connected to the scan driver 600. The scan driver 600 is configured to provide a first scan signal to the first scan line and a second scan signal to the second scan line, wherein the first scan signal and the second scan signal have the same timing and the same voltage value.

[0085] The scan driver 600 includes multiple cascaded scan driving circuits, and the first scan line G10 and the second scan line G20 electrically connected to the same pixel unit 01 are electrically connected to a scan driving circuit, so that scan signals with the same timing and the same voltage value can be simultaneously provided to the first scan line G10 and the second scan line G20 through one scan driving circuit.

[0086] The scan driver 600 is also electrically connected to the timing controller 500 . The timing controller 500 generates a scan driving control signal in response to an externally provided signal to drive the scan driver 600 to operate.

[0087] In this embodiment, the first scan line G10 and the second scan line G20 are electrically connected to the scan driver 600, and the scan driver 600 controls the timing and voltage value of the first scan signal output to the first scan line G10 and the timing and voltage value of the second scan signal output to the second scan line G20, so that the scan driver 600 can control the charging time of each first pixel sub-unit 10 and the charging time of each second pixel sub-unit 20.

[0088] like Figure 10a 、 Figure 10b as well as Figure 10c As shown, in the liquid crystal display panel 1000, a plurality of first scan lines G10 extend from a first direction D1 and are arranged along a second direction D2. The first scan lines G10 scan row by row along the second direction D2. A plurality of second scan lines G20 extend from the first direction D1 and are arranged along the second direction D2. The second scan lines G20 scan row by row along the second direction D2. The first direction D1 intersects the second direction D2. The first direction D1 may be the row direction of the plurality of pixel units O1 arranged in an array, and the second direction D2 may be the column direction of the plurality of pixel units O1 arranged in an array.

[0089] At the first moment, the signal transmitted by the m-th first scan line G10_m is the first scan signal Scan1, and the signal transmitted by the m-th second scan line G20_m is the second scan signal Scan2. The m-th first scan line G10_m is electrically connected to the pixel unit 01 in the m-th row, and the m-th second scan line G20_m is electrically connected to the pixel unit 01 in the m-th row. Therefore, at the first moment t1, the m-th first scan line G10_m and the m-th second scan line G20_m simultaneously charge the pixel unit 01 in the m-th row.

[0090] like Figure 10a As shown, at a first moment, the first scan signal Scan1 transmitted by the m-th first scan line G10_m is a signal that turns on the first pixel sub-unit 10 of the pixel unit 01 in the m-th row, and the second scan signal Scan2 transmitted by the m-th second scan line G10_m is a signal that turns on the second pixel sub-unit 20 of the pixel unit 01 in the m-th row. Furthermore, at the first moment, the third scan signal Scan3 transmitted by the remaining first scan lines G10 (such as the m+1-th first scan line G10_m+1) other than the m-th first scan line G10_m is a signal that turns off the first pixel sub-unit 10 of the corresponding row, and the fourth scan signal Scan4 transmitted by the remaining second scan lines G20 (such as the m+1-th second scan line G20_m+1) other than the m-th second scan line G20_m is a signal that turns off the second pixel sub-unit 20 of the corresponding row.

[0091] At any given moment, the first scan signal Scan1 and the third scan signal Scan3 are different, and the second scan signal Scan2 and the fourth scan signal Scan4 are different. If the first scan signal Scan1 is a high-level signal, the third scan signal Scan3 is a low-level signal; if the first scan signal Scan1 is a low-level signal, the third scan signal Scan3 is a high-level signal. If the second scan signal Scan2 is a high-level signal, the fourth scan signal Scan4 is a low-level signal; if the second scan signal Scan2 is a low-level signal, the fourth scan signal Scan4 is a high-level signal.

[0092] At the second moment t2, the signal transmitted by the m+1th first scan line G10_m+1 is the first scan signal Scan1, and the signal transmitted by the m+1th second scan line G20_m+1 is the second scan signal Scan2. The m+1th first scan line G10_m+1 is electrically connected to the pixel unit 01 in the m+1th row, and the m+1th second scan line G20_m+1 is electrically connected to the pixel unit 01 in the m+1th row. Therefore, at the second moment t2, the m+1th first scan line G10_m+1 and the m+1th second scan line G20_m+1 simultaneously charge the pixel unit 01 in the m+1th row.

[0093] like Figure 10b As shown, at the second moment, the first scan signal Scan1 transmitted by the m+1th first scan line G10_m+1 is a signal that turns on the first pixel sub-unit 10 of the pixel unit 01 in the m+1th row, and the second scan signal Scan2 transmitted by the m+1th second scan line G10_m+1 is a signal that turns on the second pixel sub-unit 20 of the pixel unit 01 in the m+1th row. Furthermore, at the second moment, the third scan signal Scan3 transmitted by the remaining first scan lines G10 (such as the m+2th first scan line G10_m+2) except the m+1th first scan line G10_m+1 is a signal that turns off the first pixel sub-unit 10 of the corresponding row, and the fourth scan signal Scan4 transmitted by the remaining second scan lines G20 (such as the m+2th second scan line G20_m+2) except the m+1th second scan line G20_m+1 is a signal that turns off the second pixel sub-unit 20 of the corresponding row.

[0094] At the third moment t3, the signal transmitted by the m+2th first scan line G10_m+2 is the first scan signal Scan1, and the signal transmitted by the m+2th second scan line G20_m+2 is the second scan signal Scan2. The m+2th first scan line G10_m+2 is electrically connected to the pixel unit 01 in the m+2th row, and the m+2th second scan line G20_m+2 is electrically connected to the pixel unit 01 in the m+2th row. Therefore, at the third moment t3, the m+2th first scan line G10_m+2 and the m+2th second scan line G20_m+2 simultaneously charge the pixel unit 01 in the m+2th row.

[0095] like Figure 10c As shown, at the third moment, the first scan signal Scan1 transmitted by the (m+2)th first scan line G10_m+2 is a signal that turns on the first pixel sub-unit 10 of the pixel unit 01 in the (m+2)th row, and the second scan signal Scan2 transmitted by the (m+2)th second scan line G20_m+2 is a signal that turns on the second pixel sub-unit 20 of the pixel unit 01 in the (m+2)th row. Furthermore, at the third moment, the third scan signal Scan3 transmitted by the remaining first scan lines G10 (such as the (m+1)th first scan line G10_m+1) except the (m+2)th first scan line G10_m+2 is a signal that turns off the first pixel sub-unit 10 of the corresponding row, and the fourth scan signal Scan4 transmitted by the remaining second scan lines G20 (such as the (m+1)th second scan line G20_m+1) except the (m+2)th second scan line G20_m+2 is a signal that turns off the second pixel sub-unit 20 of the corresponding row.

[0096] In the liquid crystal display panel 1000 provided in this embodiment, the multiple first scan lines G10 are scanned row by row, and the multiple second scan lines G20 are scanned row by row, that is, the first moment, the second moment and the third moment are all different, and the first moment is smaller than the second moment, and the second moment is smaller than the third moment. The first scan lines G10 and the second scan lines G20 electrically connected to the same row of pixel units 01 are scanned simultaneously to control the deflection of the liquid crystal molecules in the area corresponding to the same row of pixel units 01.

[0097] Of course, the present application may have many other embodiments. Without departing from the spirit and essential points of the present application, technicians familiar with the field may make various corresponding changes and modifications based on the present application, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present application.

Claims

1. A liquid crystal display panel, characterized in that: include: an array substrate, the array substrate comprising a plurality of first scan lines, a plurality of first data lines, and a plurality of first pixel sub-units, the plurality of first scan lines and the plurality of first data lines defining a plurality of pixel electrode regions, a first pixel sub-unit being disposed in a pixel electrode region, and a first pixel sub-unit being electrically connected to a first scan line and a first data line; an opposing substrate disposed opposite to the array substrate, the opposing substrate comprising a plurality of second scan lines, a plurality of second data lines, and a plurality of second pixel sub-units, the plurality of second scan lines and the plurality of second data lines defining a plurality of opposing electrode regions, a second pixel sub-unit being disposed in the opposing electrode region, a second pixel sub-unit being electrically connected to a second scan line and a second data line, a position of the second pixel sub-unit in the opposing substrate corresponding to a position of the first pixel sub-unit in the array substrate, and the second pixel unit and the corresponding first pixel sub-unit forming a pixel unit; a liquid crystal layer, the liquid crystal layer being provided between the array substrate and the counter substrate; In one of the pixel units, one of the first data signal and the second data signal input to the first pixel sub-unit by the first data line has a first voltage value, and the other of the first data signal and the second data signal input to the second pixel sub-unit by the second data line has a second voltage value.

2. The liquid crystal display panel according to claim 1, wherein The liquid crystal display panel also includes a data driver, and the first data line and the second data line are both electrically connected to the data driver. The data driver is used to transmit one of the first data signal and the second data signal to the first data line, and to transmit the other of the first data signal and the second data signal to the second data line.

3. The liquid crystal display panel according to claim 2, wherein: The liquid crystal display panel further includes a timing controller; The timing controller is electrically connected to the data driver, and is configured to provide the data driver with display data for generating the first data signal and the second data signal.

4. The liquid crystal display panel according to claim 2, wherein: The data driver includes a first data sub-driver and a second data sub-driver; The first data sub-driver is electrically connected to the first data line, and the first data sub-driver transmits one of the first data signal and the second data signal; The second data sub-driver is electrically connected to the second data line, and the second data sub-driver transmits the other of the first data signal and the second data signal.

5. The liquid crystal display panel according to claim 1, wherein When displaying a picture with a grayscale value of zero, in the same pixel unit, the first voltage value and the second voltage value are the same; When displaying an image with a grayscale value greater than zero, in the same pixel unit, the first voltage value and the second voltage value are different.

6. The liquid crystal display panel according to claim 5, wherein: In an nth frame displaying a grayscale value greater than zero, the first voltage value of the first data signal transmitted by the first data line is greater than the second voltage value of the second data signal transmitted by the second data line; In the (n+1)th frame displaying a grayscale value greater than zero, the first voltage value of the first data signal transmitted by the first data line is less than the second voltage value of the second data signal transmitted by the second data line; Wherein, n is an integer greater than or equal to 1.

7. The liquid crystal display panel according to claim 1, wherein The first pixel subunit includes a first thin film transistor and a first pixel electrode, wherein a gate of the first thin film transistor is electrically connected to the first scan line, one of a source and a drain of the first thin film transistor is electrically connected to the first data line, and the other of the source and the drain of the first thin film transistor is electrically connected to the first pixel electrode; The second pixel subunit includes a second thin film transistor and a second pixel electrode, the gate of the second thin film transistor is electrically connected to the second scan line, one of the source and the drain of the second thin film transistor is electrically connected to the first data line, and the other of the source and the drain of the second thin film transistor is electrically connected to the second pixel electrode.

8. The liquid crystal display panel according to claim 7, wherein: In one of the pixel units, the starting moment of the first scanning signal output by the first scanning line to turn on the first thin film transistor is the same as the starting moment of the second scanning signal output by the second scanning line to turn on the second thin film transistor, and the ending moment of the first scanning signal is the same as the ending moment of the second scanning signal.

9. The liquid crystal display panel according to claim 7 or 8, characterized in that: In one of the pixel units, the starting moment of the first scanning signal output by the first scanning line to turn on the first thin film transistor is the same as the starting moment of the first data signal output by the first data line to charge the first pixel electrode, and the starting moment of the second scanning signal output by the second scanning line to turn on the second thin film transistor is the same as the starting moment of the second data signal output by the second data line to charge the second pixel electrode.

10. The liquid crystal display panel according to claim 8, wherein The liquid crystal display panel further includes a scan driver, the first scan line and the second scan line are both electrically connected to the scan driver, and the scan driver is configured to provide the first scan signal to the first scan line and provide the second scan signal to the second scan line.

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