Bandgap reference circuit

Abstract

The application relates to a bandgap reference circuit. The bandgap reference circuit of the application comprises a voltage mode reference voltage generation circuit configured to provide an intermediate reference voltage; a current mode bandgap reference circuit configured to be adjusted according to the intermediate reference voltage to generate and output an arbitrary adjustable reference voltage; and a start-up circuit configured to be controlled by the intermediate reference voltage to provide a start-up signal for the voltage mode reference voltage generation circuit to make the voltage mode reference voltage generation circuit out of a zero current balance state; or the voltage mode reference voltage generation circuit outputs the intermediate reference voltage and the start-up circuit stops working. The intermediate reference voltage output by the voltage mode reference voltage generation circuit is adjusted by the current mode bandgap reference circuit to obtain an arbitrary adjustable reference voltage, thus overcoming the defects caused by the voltage mode or the current mode structure used alone.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a bandgap reference circuit. Background Technology

[0002] Reference voltage generators are critical components in analog circuits, power management, and radio frequency circuits. To meet application requirements, the reference voltage and / or reference current provided by the reference voltage generator must be sufficiently stable and largely unaffected by process technology, voltage, and temperature.

[0003] However, commonly used reference voltage generators often have several shortcomings. For example, ... Figure 1 As shown, the voltage-mode reference voltage generation circuit 01 includes a first PMOS transistor (P-type metal-oxide-semiconductor field-effect transistor) Ma1, a second PMOS transistor Ma2, a third PMOS transistor Ma3, a first operational amplifier Ua1, a first resistor Ra1, a second resistor Ra2, a first PNP transistor (PNP type bipolar junction transistor) Qa1, a second PNP transistor Qa2, and a third PNP transistor Qa3.

[0004] The sources of the first PMOS transistor Ma1, the second PMOS transistor Ma2, and the third PMOS transistor Ma3 are connected to the first power supply terminal VDD1. The gates of the first PMOS transistor Ma1, the second PMOS transistor Ma2, and the third PMOS transistor Ma3 are connected to the output terminal of the first operational amplifier Ua1. The drain of the first PMOS transistor Ma1 is connected to the positive input terminal of the first operational amplifier Ua1 and the first terminal of the first resistor Ra1. The second terminal of the first resistor Ra1 is connected to the emitter of the first PNP transistor Qa1. The drain of the second PMOS transistor Ma2 is connected to the output terminal of the first operational amplifier Ua1. The negative input terminal of the amplifier Ua1 is connected to the emitter of the second PMOS transistor Ma2; the drain of the third PMOS transistor Ma3 is connected to the first terminal of the second resistor Ra2, and the second terminal of the second resistor Ra2 is connected to the emitter of the third PNP transistor Qa3; the base and collector of the first PNP transistor Qa1, the base and collector of the second PMOS transistor Ma2, the base and collector of the third PMOS transistor Ma3 are respectively connected to the first ground terminal GND1; the drain of the third PMOS transistor Ma3 is configured as the output reference voltage Vbgr.

[0005] The aforementioned voltage-mode reference voltage generation circuit 01, through its voltage-mode bandgap reference structure, can provide a reference voltage Vbgr that is unaffected by process, voltage, and temperature. However, due to the limitations of this structure, it can only output a reference voltage Vbgr of approximately 1.2V. This voltage-mode structure cannot be used if a reference voltage of 1.8V, 2V, or higher is desired.

[0006] For example, such as Figure 2 As shown, the current-mode reference voltage generation circuit 02 includes a fourth PMOS transistor Mb1, a fifth PMOS transistor Mb2, a sixth PMOS transistor Mb3, a second operational amplifier Ub1, a third resistor Rb1, a fourth resistor Rb2, a fifth resistor Rb3, a sixth resistor Rb4, a fourth PNP transistor Qb1, and a fifth PNP transistor Qb2.

[0007] The sources of the fourth PMOS transistor Mb1, the fifth PMOS transistor Mb2, and the sixth PMOS transistor Mb3 are connected to the second power supply terminal VDD2. The gates of the fourth PMOS transistor Mb1, the fifth PMOS transistor Mb2, and the sixth PMOS transistor Mb3 are connected to the output terminal of the second operational amplifier Ub1. The drain of the fourth PMOS transistor Mb1 is connected to the positive input terminal of the second operational amplifier Ub1, the first terminal of the third resistor Rb1, and the first terminal of the fifth resistor Rb3. The second terminal of the third resistor Rb1 is connected to the emitter of the fourth PNP transistor Qb1. The fifth PMOS transistor... The drain of transistor Mb2 is connected to the negative input terminal of the second operational amplifier Ub1, the emitter of the fifth PNP transistor Qb2, and the first terminal of the fourth resistor Rb2, respectively. The drain of the sixth PMOS transistor Mb3 is connected to the first terminal of the sixth resistor Rb4. The second terminal of the fifth resistor Rb3, the base and collector of the fourth PNP transistor Qb1, the base and collector of the fifth PNP transistor Qb2, the second terminal of the fourth resistor Rb2, and the second terminal of the sixth resistor Rb4 are all connected to the second ground terminal GND2. The drain of the sixth PMOS transistor Mb3 is configured as the output reference voltage Vbgr.

[0008] The aforementioned current-mode reference voltage generation circuit 02 can achieve multiple operating points and output a reference voltage Vbgr below 1V. However, the presence of two parallel resistors (i.e., resistors b2 and b3) in this structure reduces the impedance at the virtual ground of the operational amplifier, leading to an increase in the impact of the offset voltage on the reference voltage Vbgr. Furthermore, the addition of these two resistors increases the layout area. Moreover, in order for the current-mode reference voltage generation circuit 02 to operate at multiple operating points, the startup circuit is crucial and difficult to design. Summary of the Invention

[0009] In view of this, embodiments of this application provide a bandgap reference circuit to solve at least one problem existing in the prior art.

[0010] This application provides a bandgap reference circuit, the bandgap reference circuit comprising:

[0011] The voltage-mode reference voltage generation circuit is configured to provide an intermediate reference voltage;

[0012] A current-mode bandgap reference circuit is configured to adjust according to the intermediate reference voltage to generate and output an arbitrarily adjustable reference voltage; and

[0013] The startup circuit is configured such that, when the voltage value of the intermediate reference voltage meets the startup control conditions, the startup circuit is controlled by the intermediate reference voltage to provide a startup signal to the voltage-mode reference voltage generating circuit, so that the voltage-mode reference voltage generating circuit leaves the zero-current balance state; when the voltage value of the intermediate reference voltage meets the startup control conditions, the voltage-mode reference voltage generating circuit outputs the intermediate reference voltage, and the startup circuit stops working.

[0014] In one optional embodiment, the voltage-mode reference voltage generation circuit includes a first operational amplifier module and a reference voltage generation module;

[0015] The first operational amplifier module includes a 27th PMOS transistor, a 28th PMOS transistor, a 29th PMOS transistor, a 30th PMOS transistor, a 31st PMOS transistor, a 32nd PMOS transistor, a 7th NMOS transistor, an 8th NMOS transistor, a 9th NMOS transistor, a 10th NMOS transistor, an 11th NMOS transistor, and a 12th NMOS transistor;

[0016] The gates of the 27th and 28th PMOS transistors are configured as input enable signals. The drain of the 27th PMOS transistor is connected to the drain, gate, ninth, and tenth NMOS transistors, respectively. The source of the 7th NMOS transistor is connected to the drain, gate, eleventh, and twelfth NMOS transistors, respectively. The drain of the 28th PMOS transistor is connected to the source of the 31st and 32nd PMOS transistors, respectively. The gate of the 31st PMOS transistor is configured as an input enable signal. The gate of the 32nd PMOS transistor serves as the fourth positive input terminal of the first operational amplifier module, and the gate of the 32nd PMOS transistor serves as the fourth negative input terminal of the first operational amplifier module. The drain of the 31st PMOS transistor is connected to the source of the 9th NMOS transistor and the drain of the 11th NMOS transistor, respectively. The drain of the 32nd PMOS transistor is connected to the source of the 10th NMOS transistor and the drain of the 12th NMOS transistor, respectively. The source of the 9th NMOS transistor is connected to the drain of the 29th PMOS transistor, the gate of the 29th PMOS transistor, and the gate of the 30th PMOS transistor, respectively. The drain of the 10th NMOS transistor is connected to the drain of the 30th PMOS transistor and is configured to output the second stacked control signal.

[0017] The sources of the 27th PMOS transistor, the 28th PMOS transistor, the 29th PMOS transistor, and the 30th PMOS transistor are connected to the power supply voltage terminal, respectively. The sources of the 8th NMOS transistor, the 11th NMOS transistor, and the 12th NMOS transistor are connected to the ground terminal, respectively.

[0018] The reference voltage generation module includes a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a sixth PNP transistor, a seventh PNP transistor, an eighth PNP transistor, a tenth resistor, and an eleventh resistor;

[0019] The emitter of the sixth PNP transistor and the fourth negative input terminal of the first operational amplifier module are connected to the drain of the nineteenth PMOS transistor, respectively. The emitter of the seventh PNP transistor is connected to the first terminal of the eleventh resistor. The second terminal of the eleventh resistor and the fourth positive input terminal of the first operational amplifier module are connected to the drain of the twentieth PMOS transistor, respectively. The emitter of the eighth PNP transistor is connected to the first terminal of the tenth resistor. The second terminal of the tenth resistor is connected to the drain of the twenty-first PMOS transistor and is configured as the output intermediate reference voltage. The base, collector, base, collector, and base of the sixth PNP transistor, the seventh PNP transistor, the eighth PNP transistor, and the eighth PNP transistor are all connected to ground.

[0020] The gates of the 22nd PMOS transistor, the 23rd PMOS transistor, and the 24th PMOS transistor are respectively configured to input a second stacking control signal or a start signal. The sources of the 22nd PMOS transistor, the 23rd PMOS transistor, and the 24th PMOS transistor are respectively connected to the power supply voltage terminal. The drain of the 22nd PMOS transistor is connected to the source of the 19th PMOS transistor, the drain of the 23rd PMOS transistor is connected to the source of the 20th PMOS transistor, and the drain of the 24th PMOS transistor is connected to the source of the 21st PMOS transistor. The gates of the 19th PMOS transistor, the 20th PMOS transistor, and the 21st PMOS transistor are respectively configured to input a first stacking control signal.

[0021] In one optional embodiment, the current-mode bandgap reference circuit includes a second operational amplifier module and a reference voltage output module;

[0022] The second operational amplifier module is configured to input the intermediate reference voltage and negatively feedback the feedback voltage determined according to the intermediate reference current to adjust the generation of the intermediate reference current;

[0023] The reference voltage output module is configured to generate and output the reference voltage based on the current mirrored by the intermediate reference current.

[0024] In one optional embodiment, the second operational amplifier module includes a bias current output module, a third operational amplifier, and a source follower;

[0025] The bias current output module includes a twenty-fifth PMOS transistor and a twenty-sixth PMOS transistor.

[0026] The gate of the 26th PMOS transistor is configured to input a second stack control signal or a start signal. The source of the 26th PMOS transistor is connected to the power supply voltage terminal. The drain of the 26th PMOS transistor is connected to the source of the 25th PMOS transistor. The gate of the 25th PMOS transistor is configured to input a first stack control signal. The drain of the 25th PMOS transistor is configured to output a bias current.

[0027] The third positive input terminal of the third operational amplifier is configured to input the intermediate reference voltage, and the bias current input terminal of the third operational amplifier is configured to input the bias current.

[0028] The source follower includes a first NMOS transistor and a seventh resistor;

[0029] The gate of the first NMOS transistor is connected to the third output terminal of the third operational amplifier. The source of the first NMOS transistor is connected to the first terminal of the seventh resistor and the third negative input terminal of the third operational amplifier, respectively. The second terminal of the seventh resistor is connected to ground. The drain of the first NMOS transistor is configured as the output terminal of the second operational amplifier module.

[0030] In one optional embodiment, the third operational amplifier includes a second NMOS transistor, a third NMOS transistor, a ninth resistor, a ninth PMOS transistor, an eleventh PMOS transistor, a thirteenth PMOS transistor, a tenth PMOS transistor, a twelfth PMOS transistor, a fourteenth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first capacitor, and a sixth NMOS transistor.

[0031] The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor and the gate of the third NMOS transistor and is configured as the input bias current. The source of the second NMOS transistor and the source of the third NMOS transistor are connected to ground. The drain of the third NMOS transistor is connected to the first terminal of the ninth resistor, the gate of the ninth PMOS transistor, the gate of the eleventh PMOS transistor, and the gate of the thirteenth PMOS transistor. The second terminal of the ninth resistor is connected to the drain of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the fourteenth PMOS transistor. The source of the tenth PMOS transistor, the source of the twelfth PMOS transistor, and the source of the fourteenth PMOS transistor are connected to the power supply voltage terminal. The drain of the tenth PMOS transistor is connected to the source of the ninth PMOS transistor, the drain of the twelfth PMOS transistor is connected to the source of the eleventh PMOS transistor, and the drain of the fourteenth PMOS transistor is connected to the source of the thirteenth PMOS transistor.

[0032] The gate of the seventh PMOS transistor is configured as the input intermediate reference voltage, the gate of the eighth PMOS transistor is configured as the input feedback voltage, the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are respectively connected to the drain of the eleventh PMOS transistor, the drain of the seventh PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is respectively connected to the drain of the eighth PMOS transistor, the first terminal of the first capacitor and the gate of the sixth NMOS transistor, and the drain of the sixth NMOS transistor is respectively connected to the second terminal of the first capacitor and the drain of the thirteenth PMOS transistor and is configured as the third output terminal of the third operational amplifier;

[0033] The sources of the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected to ground.

[0034] In an alternative embodiment, the third operational amplifier further includes a fifteenth PMOS transistor;

[0035] The source and drain of the fifteenth PMOS transistor are connected to the power supply voltage terminal, and the gate of the fifteenth PMOS transistor is connected to the gate of the tenth PMOS transistor.

[0036] In one alternative embodiment, the reference voltage output module includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, and an eighth resistor;

[0037] The drain of the sixteenth PMOS transistor is connected to the output terminal of the second operational amplifier module, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor, respectively. The sources of the sixteenth PMOS transistor and the seventeenth PMOS transistor are connected to the power supply voltage terminal, respectively. The drain of the seventeenth PMOS transistor is connected to the first terminal of the eighth resistor and is configured to output the reference voltage. The second terminal of the eighth resistor is connected to the ground terminal.

[0038] In an alternative embodiment, the reference voltage output module further includes an eighteenth PMOS transistor;

[0039] The gate of the eighteenth PMOS transistor is connected to the gate of the sixteenth PMOS transistor, the source of the eighteenth PMOS transistor is connected to the power supply voltage terminal, and the drain of the eighteenth PMOS transistor is configured to output the reference current.

[0040] In one optional embodiment, the startup circuit includes a 37th PMOS transistor, a 14th NMOS transistor, a 15th NMOS transistor, a 33rd PMOS transistor, a 34th PMOS transistor, a 35th PMOS transistor, a 36th PMOS transistor, a 38th PMOS transistor, and a 16th NMOS transistor;

[0041] The gate of the 37th PMOS transistor and the gate of the 14th NMOS transistor are respectively configured as the input intermediate reference voltage, and the drain of the 37th PMOS transistor is connected to the drain of the 14th NMOS transistor and the gate of the 15th NMOS transistor.

[0042] The source of the 33rd PMOS transistor is connected to the power supply voltage terminal. The gate and drain of the 33rd PMOS transistor are connected to the source of the 34th PMOS transistor, the gate and drain of the 34th PMOS transistor are connected to the source of the 35th PMOS transistor, the gate and drain of the 35th PMOS transistor are connected to the source of the 36th PMOS transistor, and the gate and drain of the 36th PMOS transistor are connected to the source of the 37th PMOS transistor.

[0043] The gate of the 38th PMOS transistor and the gate of the 16th NMOS transistor are respectively configured to input the second switch control signal. The source of the 38th PMOS transistor is connected to the power supply voltage terminal. The drain of the 38th PMOS transistor is connected to the drain of the 16th NMOS transistor and is configured to output the start signal. The source of the 16th NMOS transistor is connected to the drain of the 15th NMOS transistor. The sources of the 14th NMOS transistor and the 15th NMOS transistor are respectively connected to the ground terminal.

[0044] In one optional embodiment, the bandgap reference circuit further includes a start / stop control circuit;

[0045] The start-stop control circuit includes a first inverter, a second inverter, and a thirteenth NMOS transistor;

[0046] The first inverter is configured to invert the power control signal to obtain and output the second switch control signal; the second inverter is configured to invert the second switch control signal to obtain and output the first switch control signal.

[0047] The gate of the thirteenth NMOS transistor is configured to input the first switch control signal, the drain of the thirteenth NMOS transistor M13d is connected to the output terminal of the voltage-mode reference voltage generation circuit, and the source of the thirteenth NMOS transistor is connected to ground.

[0048] The beneficial effects of the technical solution provided in this application include: adjusting the intermediate reference voltage output by the voltage-mode reference voltage generation circuit through the current-mode bandgap reference circuit, thereby obtaining an arbitrarily adjustable reference voltage, overcoming the defects caused by using only voltage-mode or current-mode structures, and enabling the acquisition of reference voltages lower than 1V, 1.2V, 1.8V, 2V, or higher or lower. Furthermore, through the startup circuit, the intermediate reference voltage is used to achieve startup control of the bandgap reference circuit, allowing the bandgap reference circuit to overcome the zero-parallelism point.

[0049] Additional aspects and advantages of the embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of this application. Attached Figure Description

[0050] The accompanying drawings, incorporated in and forming part of this specification, illustrate embodiments conforming to this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but rather to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. In the drawings:

[0051] Figure 1 A circuit diagram showing a specific example of a voltage-mode reference voltage generation circuit;

[0052] Figure 2 A circuit diagram showing a specific example of a current-mode reference voltage generation circuit;

[0053] Figure 3 This is a schematic block diagram of a specific example of a bandgap reference circuit in an embodiment of this application;

[0054] Figure 4 The circuit diagram is a specific example of a bandgap reference circuit in the embodiments of this application;

[0055] Figure 5 This is a circuit diagram of a specific example of the third operational amplifier in the embodiments of this application. Detailed Implementation

[0056] To make the technical solutions and beneficial effects of the embodiments of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which the embodiments of this application pertain.

[0057] It should be noted that the terms "first," "second," etc., may be used herein to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. The singular forms "a," "an," and "the" may also be intended to include the plural forms unless the context clearly indicates otherwise. The term "comprising" is used to identify the presence of included features, but does not exclude the presence or addition of one or more other features. The term "and / or" includes any and all combinations of the related listed items.

[0058] This application provides a bandgap reference circuit, such as... Figure 3 As shown, the bandgap reference circuit 001 includes:

[0059] The voltage-mode reference voltage generation circuit 10 is configured to provide an intermediate reference voltage vb;

[0060] A current-mode bandgap reference circuit 20 is configured to be adjusted according to an intermediate reference voltage vb to generate and output an arbitrarily adjustable reference voltage Vbgr; and

[0061] The startup circuit 30 is configured to provide a startup signal to the voltage-mode reference voltage generating circuit when the voltage value of the intermediate reference voltage meets the startup control conditions, so that the voltage-mode reference voltage generating circuit leaves the zero-current balance state; when the voltage value of the intermediate reference voltage meets the startup control conditions, the voltage-mode reference voltage generating circuit outputs the intermediate reference voltage and the startup circuit stops working.

[0062] In this embodiment, the voltage-mode reference voltage generation circuit 10 can be configured according to actual needs to obtain the desired intermediate reference voltage vb. This intermediate reference voltage vb can be a zero-temperature voltage. For example, the voltage-mode reference voltage generation circuit 10 can be the aforementioned voltage-mode reference voltage generation circuit 01 or other circuits capable of providing a reference voltage.

[0063] The current-mode bandgap reference circuit 20 can be configured according to actual needs to adjust based on the intermediate reference voltage vb. It can generate an intermediate reference current based on the intermediate reference voltage, thereby obtaining an arbitrary desired reference voltage Vbgr from the intermediate reference current. The intermediate reference current can be a zero-temperature current. By converting the intermediate reference voltage into an intermediate reference current, and then converting the intermediate reference current into a reference voltage, an arbitrarily adjustable reference voltage can be obtained during the conversion process. For example, Ohm's law can be used to generate and output an arbitrarily adjustable reference voltage based on the intermediate reference current. The method of generating the intermediate reference current can be configured according to actual needs; for example, a current-mode bandgap reference structure can be used to provide this intermediate reference current.

[0064] The conditions for requiring and disabling startup control can be set according to actual needs. These conditions can be determined based on whether the intermediate reference voltage vb reaches the required voltage threshold. For example, the intermediate reference voltage vb may meet the startup control condition if its value is less than the voltage threshold, while it may meet the disabling control condition if its value is greater than or equal to the voltage threshold.

[0065] This embodiment adjusts the intermediate reference voltage output by the voltage-mode reference voltage generation circuit using a current-mode bandgap reference circuit, thereby obtaining an arbitrarily adjustable reference voltage. This overcomes the shortcomings of using only voltage-mode or current-mode structures, enabling the generation of reference voltages below 1V, 1.2V, 1.8V, 2V, or higher or lower. Furthermore, a startup circuit utilizes the intermediate reference voltage to control the startup of the voltage-mode reference voltage generation circuit, thus eliminating the zero-parallelism point.

[0066] In an alternative implementation, such as Figure 4 As shown, the voltage-mode reference voltage generation circuit 10 includes a first operational amplifier module 11 and a reference voltage generation module 12;

[0067] The first operational amplifier module 11 includes the twenty-seventh PMOS transistor (P-type metal-oxide-semiconductor field-effect transistor) M1d, the twenty-eighth PMOS transistor M2d, the twenty-ninth PMOS transistor M7d, the thirtieth PMOS transistor M8d, the thirty-first PMOS transistor M5d, the thirty-second PMOS transistor M6d, the seventh NMOS transistor (N-type metal-oxide-semiconductor field-effect transistor) M3d, the eighth NMOS transistor M4d, the ninth NMOS transistor M9d, the tenth NMOS transistor M10d, the eleventh NMOS transistor M11d, and the twelfth NMOS transistor M12d;

[0068] The gates of the 27th PMOS transistor M1d and the 28th PMOS transistor M2d are configured as input start signals. The drain of the 27th PMOS transistor M1d is connected to the drain, gate, and 9th NMOS transistor M9d, respectively, and the gate of the 10th NMOS transistor M10d. The source of the 7th NMOS transistor M3d is connected to the drain, gate, and 11th NMOS transistor M12d, respectively, and the gate of the 8th NMOS transistor M4d, respectively, and the gate of the 11th NMOS transistor M11d, respectively, and the gate of the 12th NMOS transistor M12d. The drain of the 28th PMOS transistor M2d is connected to the source of the 31st PMOS transistor M5d and the source of the 32nd PMOS transistor M6d, respectively. The gate of the 31st PMOS transistor M5d is configured as... The fourth positive input terminal Vp of the first operational amplifier module 11 is used. The gate of the thirty-second PMOS transistor M6d serves as the fourth negative input terminal Vn of the first operational amplifier module 11. The drain of the thirty-first PMOS transistor M5d is connected to the source of the ninth NMOS transistor M9d and the drain of the eleventh NMOS transistor M11d. The drain of the thirty-second PMOS transistor M6d is connected to the source of the tenth NMOS transistor M10d and the drain of the twelfth NMOS transistor M12d. The source of the ninth NMOS transistor M9d is connected to the drain of the twenty-ninth PMOS transistor M7d, the gate of the twenty-ninth PMOS transistor M7d, and the gate of the thirtieth PMOS transistor M8d. The drain of the tenth NMOS transistor M10d is connected to the drain of the thirtieth PMOS transistor M8d and is configured to output the second stacked control signal.

[0069] The sources of the twenty-seventh PMOS transistor M1d, the twenty-eighth PMOS transistor M2d, the twenty-ninth PMOS transistor M7d, and the thirtieth PMOS transistor M8d are connected to the power supply voltage terminal vdda, respectively. The sources of the eighth NMOS transistor M4d, the eleventh NMOS transistor M11d, and the twelfth NMOS transistor M12d are connected to the ground terminal vssa, respectively.

[0070] The reference voltage generation module 12 includes the nineteenth PMOS transistor M1b, the twentieth PMOS transistor M2b, the twenty-first PMOS transistor M3b, the twenty-second PMOS transistor M5b, the twenty-third PMOS transistor M6b, the twenty-fourth PMOS transistor M7b, the sixth PNP transistor Q6, the seventh PNP transistor Q7, the eighth PNP transistor Q8, the tenth resistor R10, and the eleventh resistor R11.

[0071] The emitter of the sixth PNP transistor Q6 and the fourth negative input terminal Vn of the first operational amplifier module 11 are connected to the drain of the nineteenth PMOS transistor M1b, respectively. The emitter of the seventh PNP transistor Q7 is connected to the first terminal of the eleventh resistor R11. The second terminal of the eleventh resistor R11 and the fourth positive input terminal Vp of the first operational amplifier module 11 are connected to the drain of the twentieth PMOS transistor M2b, respectively. The emitter of the eighth PNP transistor Q8 is connected to the first terminal of the tenth resistor R10. The second terminal of the tenth resistor R10 is connected to the drain of the twenty-first PMOS transistor M3b and is configured to output the intermediate reference voltage vb. The base and collector of the sixth PNP transistor Q6, the base and collector of the seventh PNP transistor Q7, the base and collector of the eighth PNP transistor Q8 are connected to the ground terminal vssa, respectively.

[0072] The gates of the 22nd PMOS transistor M5b, the 23rd PMOS transistor M6b, and the 24th PMOS transistor M7b are respectively configured to input a second stacking control signal or a start signal. The sources of the 22nd PMOS transistor M5b, the 23rd PMOS transistor M6b, and the 24th PMOS transistor M7b are respectively connected to the power supply voltage terminal vdda. The drain of the 22nd PMOS transistor M5b is connected to the source of the 19th PMOS transistor M1b. The drain of the 23rd PMOS transistor M6b is connected to the source of the 20th PMOS transistor M2b. The drain of the 24th PMOS transistor M7b is connected to the source of the 21st PMOS transistor M3b. The gates of the 19th PMOS transistor M1b, the 20th PMOS transistor M2b, and the 21st PMOS transistor M3b are respectively configured to input a first stacking control signal va.

[0073] In this embodiment, the 27th PMOS transistor M1d, the 28th PMOS transistor M2d, the 7th NMOS transistor M3d, the 31st PMOS transistor M5d, the 32nd PMOS transistor M6d, and the 29th PMOS transistor M7d form a first cascode current mirror. Different stacking control signals provide bias voltages to the first cascode current mirror, allowing for a more reasonable setting of the voltage difference between the different stacking control signals, thus reducing voltage margin occupation. The stacking control signals may include a first stacking control signal va and a second stacking control signal. The stacking control signal or start signal can be provided internally by the bandgap reference circuit 001 or by a control device external to the bandgap reference circuit 001. This control device can be programmable. For example, the first stacking control signal va can be provided by the self-biasing of the bandgap reference circuit. This embodiment improves the output impedance of the current source through the cascode current source structure.

[0074] Those skilled in the art will understand that the first operational amplifier module 11 can be configured according to actual needs to obtain the desired op-amp function. For example, as Figure 4 As shown, the first operational amplifier module 11 can be a folded cascode operational amplifier to improve loop gain. The amplification stage of this folded cascode operational amplifier can output a second stacked control signal, which is provided internally by the bandgap reference circuit 001.

[0075] In one alternative embodiment, the current-mode bandgap reference circuit 20 includes a second operational amplifier module 21 and a reference voltage output module 22;

[0076] The second operational amplifier module 21 is configured to input an intermediate reference voltage vb and to negatively feed back a feedback voltage determined based on the intermediate reference current in order to adjust the generation of the intermediate reference current.

[0077] The reference voltage output module 22 is configured to generate and output a reference voltage Vbgr based on the current mirrored by the intermediate reference current.

[0078] In this embodiment, the method of determining the feedback voltage based on the intermediate reference current can be set according to actual needs. For example, it can be obtained by using a conversion resistor, injecting the intermediate reference current into one end of the conversion resistor and grounding the other end to form a voltage drop. Furthermore, the conversion resistor can be set to a resistor with a temperature coefficient to obtain an intermediate reference current with zero temperature current. This embodiment forms a current-mode bandgap reference structure through a second operational amplifier module and combines it with a voltage-mode reference voltage generation circuit to form a hybrid-mode bandgap reference structure. This eliminates the defects of a single current-mode structure, reduces the impact of offset voltage on the reference voltage Vbgr, saves layout area, avoids the design of a complex startup circuit, and allows for an arbitrarily adjustable reference voltage Vbgr.

[0079] In one optional embodiment, the second operational amplifier module 21 includes a bias current output module, a third operational amplifier, and a source follower;

[0080] The bias current output module includes the twenty-fifth PMOS transistor M4b and the twenty-sixth PMOS transistor M8b;

[0081] The gate of the 26th PMOS transistor M8b is configured to input the second stack control signal or the start signal. The source of the 26th PMOS transistor M8b is connected to the power supply voltage terminal vdda. The drain of the 26th PMOS transistor M8b is connected to the source of the 25th PMOS transistor M4b. The gate of the 25th PMOS transistor M4b is configured to input the first stack control signal va. The drain of the 25th PMOS transistor M4b is configured to output the bias current ibias.

[0082] The third positive input terminal of the third operational amplifier OP3 is configured to input the intermediate reference voltage vb, and the bias current input terminal of the third operational amplifier OP3 is configured to input the bias current ibias.

[0083] The source follower includes the first NMOS transistor M12b and the seventh resistor R7;

[0084] The gate of the first NMOS transistor M12b is connected to the third output terminal of the third operational amplifier OP3. The source of the first NMOS transistor M12b is connected to the first terminal of the seventh resistor R7 and the third negative input terminal of the third operational amplifier OP3. The second terminal of the seventh resistor R7 is connected to the ground terminal vssa. The drain of the first NMOS transistor M12b is configured as the output terminal of the second operational amplifier module 21.

[0085] In this embodiment, the bias current output module is configured to provide bias current to the third operational amplifier. Specifically, the magnitude of the operational amplifier's bias current can be generated by a voltage-mode reference voltage generation circuit to control the operational amplifier's startup. Providing bias current through the voltage-mode reference voltage generation circuit allows for a better increase in the output impedance of the operational amplifier's current source, thus improving operational amplifier performance. The input terminal of the source follower (such as the gate of the first NMOS transistor M12b) is connected to the third output terminal of the third operational amplifier, and the feedback terminal of the source follower (the source of the first NMOS transistor M12b) is configured as the output feedback voltage. Forming negative feedback through the source follower reduces the impact of the offset voltage on the reference voltage Vbgr and saves layout area, obtaining an arbitrarily adjustable reference voltage Vbgr to meet usage requirements. The source follower can be configured according to actual needs and is not limited to this. The seventh resistor R7 can be a resistor with a temperature coefficient; for example, it can be a zero-temperature resistor composed of two resistors (R7a and R7b) connected in series to provide zero-temperature current.

[0086] In this embodiment, the emitter current ratio of the sixth PNP transistor Q6, the seventh PNP transistor Q7, and the eighth PNP transistor Q8 can be 1:N:1, thereby obtaining the intermediate reference voltage vb generated at point X.

[0087]

[0088] Among them, V X This represents the intermediate reference voltage vb, V generated at point X. BE R represents the voltage drop between the emitter and collector of the eighth PNP transistor Q8. 11 This indicates the resistance value of the eleventh resistor, R11. 10 This indicates the resistance value of the tenth resistor, R10, in V. T This represents the thermal voltage, V, at a temperature of 300K. T It is typically 26mV.

[0089] Due to V X =V Y , Among them, V Y I represents the voltage generated at point Y. ref R1 represents the intermediate reference current output from the source of the first NMOS transistor M12b, and R7 represents the resistance value of the seventh resistor R7. Therefore, the reference voltage Vbgr can be derived as follows:

[0090]

[0091] Among them, V bgr The reference voltage Vbgr is represented by R8, and the resistance value of the eighth resistor R8 is represented by R8.

[0092] Therefore, it can be seen that by inputting the zero-temperature voltage at point X (i.e., the intermediate reference voltage vb output by the voltage-mode reference voltage generation circuit 10) through the third positive input terminal of the third operational amplifier OP3, and then utilizing the virtual short characteristic of the operational amplifier, a zero-temperature current (i.e., the intermediate reference current) can be generated at the source of the first NMOS transistor M12b (i.e., point Y) through the seventh resistor R7. Then, through the eighth resistor R8, any reference voltage Vbgr output value can be obtained.

[0093] In an alternative implementation, such as Figure 5 As shown, the third operational amplifier includes a second NMOS transistor M1p, a third NMOS transistor M2p, a ninth resistor R9, a ninth PMOS transistor M3p, an eleventh PMOS transistor M9p, a thirteenth PMOS transistor M12p, a tenth PMOS transistor M4p, a twelfth PMOS transistor M10p, a fourteenth PMOS transistor M13p, a seventh PMOS transistor M6p, an eighth PMOS transistor M8p, a fourth NMOS transistor M5p, a fifth NMOS transistor M7p, a first capacitor C1, and a sixth NMOS transistor M11p.

[0094] The drain of the second NMOS transistor M1p is connected to the gate of the second NMOS transistor M1p and the gate of the third NMOS transistor M2p, respectively, and is configured as the input bias current ibias. The source of the second NMOS transistor M1p and the source of the third NMOS transistor M2p are connected to ground vssa, respectively. The drain of the third NMOS transistor M2p is connected to the first terminal of the ninth resistor, the gate of the ninth PMOS transistor M3p, the gate of the eleventh PMOS transistor M9p, and the gate of the thirteenth PMOS transistor M12p, respectively. The second terminal of the ninth resistor R9 is connected to the drain of the ninth PMOS transistor M3p and the gate of the eleventh PMOS transistor M9p, respectively. The gates of the OS transistor M4p, the twelfth PMOS transistor M10p, and the fourteenth PMOS transistor M13p are connected; the sources of the tenth PMOS transistor M4p, the twelfth PMOS transistor M10p, and the fourteenth PMOS transistor M13p are connected to the power supply voltage terminal vdda respectively; the drain of the tenth PMOS transistor M4p is connected to the source of the ninth PMOS transistor M3p; the drain of the twelfth PMOS transistor M10p is connected to the source of the eleventh PMOS transistor M9p; and the drain of the fourteenth PMOS transistor M13p is connected to the source of the thirteenth PMOS transistor M12p.

[0095] The gate of the seventh PMOS transistor M6p is configured as the input intermediate reference voltage vb, and the gate of the eighth PMOS transistor M8p is configured as the input feedback voltage. The sources of the seventh PMOS transistor M6p and the eighth PMOS transistor M8p are respectively connected to the drain of the eleventh PMOS transistor M9p. The drain of the seventh PMOS transistor M6p is respectively connected to the drain of the fourth NMOS transistor M5p, the gate of the fourth NMOS transistor M5p, and the gate of the fifth NMOS transistor M7p. The drain of the fifth NMOS transistor M7p is respectively connected to the drain of the eighth PMOS transistor M8p, the first terminal of the first capacitor C1, and the gate of the sixth NMOS transistor M11p. The drain of the sixth NMOS transistor M11p is respectively connected to the second terminal of the first capacitor C1 and the drain of the thirteenth PMOS transistor M12p and is configured as the third output terminal of the third operational amplifier OP3.

[0096] The source of the fourth NMOS transistor M5p, the source of the fifth NMOS transistor M7p, and the source of the sixth NMOS transistor M11p are connected to ground vssa, respectively.

[0097] In this embodiment, the third operational amplifier OP3 is configured to perform differential amplification based on the intermediate reference voltage vb and the feedback voltage. The third output terminal of the third operational amplifier OP3 is connected to the input terminal of the source follower. Miller compensation can be achieved through the first capacitor C1, improving output accuracy and stability.

[0098] The input pair of the differential amplifier is formed by the seventh PMOS transistor M6p and the eighth PMOS transistor M8p, but it is not limited to this. The input pair can also be formed using a first transistor module and a second transistor module, respectively. The first transistor module can be configured to turn on or off under the control of the intermediate reference voltage vb; the second transistor module can be configured to turn on or off under the control of the feedback voltage. Both the first transistor module and the second transistor module can include a high-side power transistor circuit. The high-side power transistor circuit is a high-side switching circuit in which power transistors are combined between the positive terminal of the power supply and the high-voltage terminal of the load. The high-side power transistor circuit includes a control terminal, a first signal terminal, and a second signal terminal. Its working principle is that under the control of the control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off, so as to connect or block the signal transmission between the first signal terminal and the second signal terminal. The power transistor combination can include at least one of NMOS transistors, PMOS transistors, and other transistors. For example, in the high-side power transistor circuit, the power transistor combination can include PMOS transistors. The first transistor module and the second transistor module form an input pair. The first signal terminals of the first transistor module and the second transistor module can be connected to each other and input bias current, while the second signal terminals of the first transistor module and the second transistor module provide output respectively.

[0099] The amplified output of the third operational amplifier OP3 is provided by the sixth NMOS transistor M11p, but is not limited to this. For example, the sixth NMOS transistor M11p can be replaced by a third transistor module. The third transistor module may include a low-side power transistor circuit. The low-side power transistor circuit is a low-side switching circuit in which power transistors are combined between the low-voltage terminal of the load and the reference point (which may be the negative terminal of the power supply). The low-side power transistor circuit includes a control terminal, a first signal terminal, and a second signal terminal. Its operating principle is that, under the control of the control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off, so as to connect or block the signal transmission between the first signal terminal and the second signal terminal. The power transistor combination may include at least one of NMOS transistors, PMOS transistors, and other transistors. For example, in the low-side power transistor circuit, the power transistor combination may include NMOS transistors.

[0100] A common-source, common-gate current source is formed by the ninth PMOS transistor M3p, the eleventh PMOS transistor M9p, the thirteenth PMOS transistor M12p, the tenth PMOS transistor M4p, the twelfth PMOS transistor M10p, and the fourteenth PMOS transistor M13p. A bias voltage is provided through the ninth resistor R9 to control the output current supplied by the current source. The common-source, common-gate current source can also be configured with more layers. A voltage divider obtained by connecting more resistors in series can be used to provide a bias voltage to each layer, controlling the conduction or disconnection of each layer, thereby achieving switching control of the third operational amplifier OP3. This embodiment of the application improves the stability of the current supply and increases the output impedance of the current source through the common-source, common-gate structure.

[0101] In an alternative embodiment, the third operational amplifier OP3 further includes a fifteenth PMOS transistor M14p;

[0102] The source and drain of the fifteenth PMOS transistor M14p are connected to the power supply voltage terminal vdda, and the gate of the fifteenth PMOS transistor M14p is connected to the gate of the tenth PMOS transistor M4p.

[0103] In this embodiment, the capacitor is formed by the fifteenth PMOS transistor M14p, which can reduce the fluctuation of its gate potential and improve the stability of the current source.

[0104] In an alternative implementation, such as Figure 4 As shown, the reference voltage output module 22 includes a sixteenth PMOS transistor M9b, a seventeenth PMOS transistor M10b, and an eighth resistor R8;

[0105] The drain of the sixteenth PMOS transistor M9b is connected to the output terminal of the second operational amplifier module 21, the gate of the sixteenth PMOS transistor M9b, and the gate of the seventeenth PMOS transistor M10b, respectively. The sources of the sixteenth PMOS transistor M9b and the seventeenth PMOS transistor M10b are connected to the power supply voltage terminal vdda, respectively. The drain of the seventeenth PMOS transistor M10b is connected to the first terminal of the eighth resistor R8 and is configured as the output reference voltage Vbgr. The second terminal of the eighth resistor R8 is connected to the ground terminal vssa.

[0106] In this embodiment, the reference voltage Vbgr can be adjusted by changing the resistance value of the eighth resistor R8, thus achieving adjustable output reference voltage. A current mirror is formed by the sixteenth PMOS transistor M9b and the seventeenth PMOS transistor M10b, realizing the function of a current source and improving the stability of the current supply. However, this is not a limitation; other current supply modules with current source functions can also be used.

[0107] In an alternative embodiment, the reference voltage output module 22 further includes an eighteenth PMOS transistor M11b;

[0108] The gate of the eighteenth PMOS transistor M11b is connected to the gate of the sixteenth PMOS transistor M9b, the source of the eighteenth PMOS transistor M11b is connected to the power supply voltage terminal vdda, and the drain of the eighteenth PMOS transistor M11b is configured to output the reference current Iref.

[0109] In this embodiment, a reference current Iref with zero temperature current is provided through a current mirror structure, and its stability is improved.

[0110] In an alternative implementation, such as Figure 4 As shown, the startup circuit 30 includes the thirty-seventh PMOS transistor M1c, the fourteenth NMOS transistor M5c, the fifteenth NMOS transistor M2c, the thirty-third PMOS transistor M6c, the thirty-fourth PMOS transistor M7c, the thirty-fifth PMOS transistor M8c, the thirty-sixth PMOS transistor M9c, the thirty-eighth PMOS transistor M3c, and the sixteenth NMOS transistor M4c.

[0111] The gate of the 37th PMOS transistor M1c and the gate of the 14th NMOS transistor M5c are respectively configured to input intermediate reference voltage vb, and the drain of the 37th PMOS transistor M1c is connected to the drain of the 14th NMOS transistor M5c and the gate of the 15th NMOS transistor M2c.

[0112] The source of the thirty-third PMOS transistor M6c is connected to the power supply voltage terminal vdda. The gate and drain of the thirty-third PMOS transistor M6c are connected to the source of the thirty-fourth PMOS transistor M7c. The gate and drain of the thirty-fourth PMOS transistor M7c are connected to the source of the thirty-fifth PMOS transistor M8c. The gate and drain of the thirty-fifth PMOS transistor M8c are connected to the source of the thirty-sixth PMOS transistor M9c. The gate and drain of the thirty-sixth PMOS transistor M9c are connected to the source of the thirty-seventh PMOS transistor M1c.

[0113] The gates of the 38th PMOS transistor M3c and the 16th NMOS transistor M4c are configured to input the second switch control signal. The source of the 38th PMOS transistor M3c is connected to the power supply voltage terminal vdda. The drain of the 38th PMOS transistor M3c is connected to the drain of the 16th NMOS transistor M4c and is configured to output the start signal. The source of the 16th NMOS transistor M4c is connected to the drain of the 15th NMOS transistor M2c. The sources of the 14th NMOS transistor M5c and the 15th NMOS transistor M2c are connected to the ground terminal vssa.

[0114] In this embodiment, a biasing module is constructed using the 33rd PMOS transistor M6c, the 34th PMOS transistor M7c, the 35th PMOS transistor M8c, and the 36th PMOS transistor M9c to provide a desired bias voltage to the 37th PMOS transistor M1c. This ensures that the 37th PMOS transistor M1c is completely turned off when the intermediate reference voltage vb is high, thus improving stability. The biasing module is not limited to this and can be configured according to actual needs; for example, the number of PMOS transistors with gate and drain connections can be increased or decreased. A first level-shifting module is constructed using the 37th PMOS transistor M1c and the 14th NMOS transistor M5c, but is not limited to this. The first level-shifting module may include a high-side power transistor circuit and a low-side power transistor circuit connected in series between the biasing module and the ground terminal vssa. For example, when the intermediate reference voltage is low, the high-side power transistor circuit is turned on and the low-side power transistor circuit is turned off to control the output high level. When the intermediate reference voltage is high, the low-side power transistor circuit is turned on and the high-side power transistor circuit is turned off to control the output to a low level, thereby achieving localized output and a high conversion rate. In this embodiment, through the bias supply module and the first level conversion module, the internal circuitry of the bandgap reference circuit monitors the voltage value of the intermediate reference voltage, enabling the bandgap reference circuit to overcome the zero-parallelism point.

[0115] The second level shifting circuit is composed of the 38th PMOS transistor M3c and the 16th NMOS transistor M4c, but is not limited to this. The second level shifting module may include a high-side power transistor circuit and a low-side power transistor circuit connected in series between the power supply voltage terminal vdda and the drain of the 15th NMOS transistor M2c, achieving localized output and a high conversion rate. For example, when the second switch control signal pdb is high, the high-side power transistor circuit is turned off and the low-side power transistor circuit is turned on to control the output low level, thereby controlling the injected current of the bandgap reference circuit and eliminating the zero-coupling point. Conversely, when the second switch control signal pdb is low, the high-side power transistor circuit is turned on and the low-side power transistor circuit is turned off to control the output high level, detaching from the control of the intermediate reference voltage vb.

[0116] In this embodiment, at the instant the entire bandgap reference circuit is powered on, the intermediate reference voltage vb outputs 0V (i.e., point X is 0V). At this time, the 37th PMOS transistor M1c and the 15th NMOS transistor M2c turn on, and the first-stage inverting signal pdb outputs a high level, causing the 38th PMOS transistor M3c to turn off and the 16th NMOS transistor M4c to turn on. This pulls down the voltage at points C and D, injecting current into the bandgap reference circuit, freeing the entire circuit from the zero-parallel point, and outputting the intermediate reference voltage vb. After outputting the intermediate reference voltage vb, the 37th PMOS transistor M1c and the 15th NMOS transistor M2c turn off, that is, the startup circuit is shut down, allowing the bandgap reference circuit to break free from the control of the startup circuit.

[0117] In an optional embodiment, the bandgap reference circuit 001 further includes a start / stop control circuit;

[0118] The start-stop control circuit includes a first inverter U1, a second inverter U2, and a thirteenth NMOS transistor M13d;

[0119] The first inverter U1 is configured to invert the power control signal pd_bgr to obtain and output the second switch control signal pdb; the second inverter U2 is configured to invert the second switch control signal pdb to obtain and output the first switch control signal pd;

[0120] The gate of the thirteenth NMOS transistor M13d is configured to input the first switch control signal, the drain of the thirteenth NMOS transistor M13d is connected to the output terminal of the voltage-mode reference voltage generation circuit, and the source of the thirteenth NMOS transistor M13d is connected to the ground terminal vssa.

[0121] In this embodiment, the power control signal pd_bgr can be a control device external to the bandgap reference circuit 001. This control device can be programmable. The input port of the power control signal pd_bgr can be the power-down port of the entire bandgap reference circuit 001. When it is set to a high potential (e.g., power supply voltage), the second switch control signal pdb is at a low potential (e.g., zero potential), the first switch control signal pd is at a high potential, and the entire bandgap reference circuit 001 is turned off; conversely, when the power control signal pd_bgr is at a low potential, the bandgap reference circuit 001 is turned on. This embodiment improves the stability and speed of start-stop control and reduces energy consumption by turning the output of the intermediate reference voltage on or off under the control of the power control signal.

[0122] A controllable semiconductor switching device is constructed using the thirteenth NMOS transistor M13d, but is not limited to this. The controllable semiconductor switching device can include at least one of the following: BJT (Biotransistor), SCR (Silicon Controlled Rectifier), GTO (Gate Turn-Off Thyristor), MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), MCT (MOS-Controlled Thyristor), and SIT (Static Induction Transistor). The controllable semiconductor switching device can be connected between the output terminal and ground of the voltage-mode reference voltage generation circuit, or between the output terminal and the power supply voltage terminal of the voltage-mode reference voltage generation circuit, to turn on or off under the control of a first switching control signal, thereby controlling the output of the intermediate reference voltage vb. In this embodiment, the thirteenth NMOS transistor M13d is used to achieve start-stop control of the bandgap reference circuit, enabling rapid start-stop.

[0123] The first switch control signal is not limited to being generated by the start / stop control circuit; it can also be provided by a control device external to the bandgap reference circuit 001. This control device can be programmable.

[0124] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A bandgap reference circuit, characterized in that, The bandgap reference circuit includes: The voltage-mode reference voltage generation circuit is configured to provide an intermediate reference voltage; A current-mode bandgap reference circuit is configured to adjust according to the intermediate reference voltage to generate and output an arbitrarily adjustable reference voltage; and The startup circuit is configured such that, when the voltage value of the intermediate reference voltage meets the startup control conditions, the startup circuit is controlled by the intermediate reference voltage to provide a startup signal to the voltage-mode reference voltage generating circuit, so that the voltage-mode reference voltage generating circuit leaves the zero-current balance state; when the voltage value of the intermediate reference voltage meets the startup control conditions, the voltage-mode reference voltage generating circuit outputs the intermediate reference voltage, and the startup circuit stops working. The current-mode bandgap reference circuit includes a second operational amplifier module and a reference voltage output module; the second operational amplifier module is configured to input the intermediate reference voltage and negatively feedback the feedback voltage determined according to the intermediate reference current to adjust the generation of the intermediate reference current; the reference voltage output module is configured to generate and output the reference voltage according to the current mirrored by the intermediate reference current.

2. The bandgap reference circuit according to claim 1, characterized in that, The voltage-mode reference voltage generation circuit includes a first operational amplifier module and a reference voltage generation module; The first operational amplifier module includes a 27th PMOS transistor, a 28th PMOS transistor, a 29th PMOS transistor, a 30th PMOS transistor, a 31st PMOS transistor, a 32nd PMOS transistor, a 7th NMOS transistor, an 8th NMOS transistor, a 9th NMOS transistor, a 10th NMOS transistor, an 11th NMOS transistor, and a 12th NMOS transistor; The gates of the 27th and 28th PMOS transistors are configured as input enable signals. The drain of the 27th PMOS transistor is connected to the drain, gate, ninth, and tenth NMOS transistors, respectively. The source of the 7th NMOS transistor is connected to the drain, gate, eleventh, and twelfth NMOS transistors, respectively. The drain of the 28th PMOS transistor is connected to the source of the 31st and 32nd PMOS transistors, respectively. The gate of the 31st PMOS transistor is configured as an input enable signal. The gate of the 32nd PMOS transistor serves as the fourth positive input terminal of the first operational amplifier module, and the gate of the 32nd PMOS transistor serves as the fourth negative input terminal of the first operational amplifier module. The drain of the 31st PMOS transistor is connected to the source of the 9th NMOS transistor and the drain of the 11th NMOS transistor, respectively. The drain of the 32nd PMOS transistor is connected to the source of the 10th NMOS transistor and the drain of the 12th NMOS transistor, respectively. The source of the 9th NMOS transistor is connected to the drain of the 29th PMOS transistor, the gate of the 29th PMOS transistor, and the gate of the 30th PMOS transistor, respectively. The drain of the 10th NMOS transistor is connected to the drain of the 30th PMOS transistor and is configured to output the second stacked control signal. The sources of the 27th PMOS transistor, the 28th PMOS transistor, the 29th PMOS transistor, and the 30th PMOS transistor are connected to the power supply voltage terminal, respectively. The sources of the 8th NMOS transistor, the 11th NMOS transistor, and the 12th NMOS transistor are connected to the ground terminal, respectively. The reference voltage generation module includes a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a sixth PNP transistor, a seventh PNP transistor, an eighth PNP transistor, a tenth resistor, and an eleventh resistor; The emitter of the sixth PNP transistor and the fourth negative input terminal of the first operational amplifier module are connected to the drain of the nineteenth PMOS transistor, respectively. The emitter of the seventh PNP transistor is connected to the first terminal of the eleventh resistor. The second terminal of the eleventh resistor and the fourth positive input terminal of the first operational amplifier module are connected to the drain of the twentieth PMOS transistor, respectively. The emitter of the eighth PNP transistor is connected to the first terminal of the tenth resistor. The second terminal of the tenth resistor is connected to the drain of the twenty-first PMOS transistor and is configured as the output intermediate reference voltage. The base, collector, base, collector, and base of the sixth PNP transistor, the seventh PNP transistor, the eighth PNP transistor, and the eighth PNP transistor are all connected to ground. The gates of the 22nd PMOS transistor, the 23rd PMOS transistor, and the 24th PMOS transistor are respectively configured to input a second stacking control signal or a start signal. The sources of the 22nd PMOS transistor, the 23rd PMOS transistor, and the 24th PMOS transistor are respectively connected to the power supply voltage terminal. The drain of the 22nd PMOS transistor is connected to the source of the 19th PMOS transistor, the drain of the 23rd PMOS transistor is connected to the source of the 20th PMOS transistor, and the drain of the 24th PMOS transistor is connected to the source of the 21st PMOS transistor. The gates of the 19th PMOS transistor, the 20th PMOS transistor, and the 21st PMOS transistor are respectively configured to input a first stacking control signal.

3. The bandgap reference circuit according to claim 1, characterized in that, The second operational amplifier module includes a bias current output module, a third operational amplifier, and a source follower; The bias current output module includes a twenty-fifth PMOS transistor and a twenty-sixth PMOS transistor. The gate of the 26th PMOS transistor is configured to input a second stack control signal or a start signal. The source of the 26th PMOS transistor is connected to the power supply voltage terminal. The drain of the 26th PMOS transistor is connected to the source of the 25th PMOS transistor. The gate of the 25th PMOS transistor is configured to input a first stack control signal. The drain of the 25th PMOS transistor is configured to output a bias current. The third positive input terminal of the third operational amplifier is configured to input the intermediate reference voltage, and the bias current input terminal of the third operational amplifier is configured to input the bias current. The source follower includes a first NMOS transistor and a seventh resistor; The gate of the first NMOS transistor is connected to the third output terminal of the third operational amplifier. The source of the first NMOS transistor is connected to the first terminal of the seventh resistor and the third negative input terminal of the third operational amplifier, respectively. The second terminal of the seventh resistor is connected to ground. The drain of the first NMOS transistor is configured as the output terminal of the second operational amplifier module.

4. The bandgap reference circuit according to claim 3, characterized in that, The third operational amplifier includes a second NMOS transistor, a third NMOS transistor, a ninth resistor, a ninth PMOS transistor, an eleventh PMOS transistor, a thirteenth PMOS transistor, a tenth PMOS transistor, a twelfth PMOS transistor, a fourteenth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first capacitor, and a sixth NMOS transistor. The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor and the gate of the third NMOS transistor and is configured as the input bias current. The source of the second NMOS transistor and the source of the third NMOS transistor are connected to ground. The drain of the third NMOS transistor is connected to the first terminal of the ninth resistor, the gate of the ninth PMOS transistor, the gate of the eleventh PMOS transistor, and the gate of the thirteenth PMOS transistor. The second terminal of the ninth resistor is connected to the drain of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the fourteenth PMOS transistor. The source of the tenth PMOS transistor, the source of the twelfth PMOS transistor, and the source of the fourteenth PMOS transistor are connected to the power supply voltage terminal. The drain of the tenth PMOS transistor is connected to the source of the ninth PMOS transistor, the drain of the twelfth PMOS transistor is connected to the source of the eleventh PMOS transistor, and the drain of the fourteenth PMOS transistor is connected to the source of the thirteenth PMOS transistor. The gate of the seventh PMOS transistor is configured as the input intermediate reference voltage, the gate of the eighth PMOS transistor is configured as the input feedback voltage, the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are respectively connected to the drain of the eleventh PMOS transistor, the drain of the seventh PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is respectively connected to the drain of the eighth PMOS transistor, the first terminal of the first capacitor and the gate of the sixth NMOS transistor, and the drain of the sixth NMOS transistor is respectively connected to the second terminal of the first capacitor and the drain of the thirteenth PMOS transistor and is configured as the third output terminal of the third operational amplifier; The sources of the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected to ground.

5. The bandgap reference circuit according to claim 4, characterized in that, The third operational amplifier also includes a fifteenth PMOS transistor; The source and drain of the fifteenth PMOS transistor are connected to the power supply voltage terminal, and the gate of the fifteenth PMOS transistor is connected to the gate of the tenth PMOS transistor.

6. The bandgap reference circuit according to claim 1, characterized in that, The reference voltage output module includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, and an eighth resistor; The drain of the sixteenth PMOS transistor is connected to the output terminal of the second operational amplifier module, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor, respectively. The sources of the sixteenth PMOS transistor and the seventeenth PMOS transistor are connected to the power supply voltage terminal, respectively. The drain of the seventeenth PMOS transistor is connected to the first terminal of the eighth resistor and is configured to output the reference voltage. The second terminal of the eighth resistor is connected to the ground terminal.

7. The bandgap reference circuit according to claim 6, characterized in that, The reference voltage output module also includes an eighteenth PMOS transistor; The gate of the eighteenth PMOS transistor is connected to the gate of the sixteenth PMOS transistor, the source of the eighteenth PMOS transistor is connected to the power supply voltage terminal, and the drain of the eighteenth PMOS transistor is configured to output the reference current.

8. The bandgap reference circuit according to claim 1, characterized in that, The startup circuit includes the 37th PMOS transistor, the 14th NMOS transistor, the 15th NMOS transistor, the 33rd PMOS transistor, the 34th PMOS transistor, the 35th PMOS transistor, the 36th PMOS transistor, the 38th PMOS transistor, and the 16th NMOS transistor; The gate of the 37th PMOS transistor and the gate of the 14th NMOS transistor are respectively configured as the input intermediate reference voltage, and the drain of the 37th PMOS transistor is connected to the drain of the 14th NMOS transistor and the gate of the 15th NMOS transistor. The source of the 33rd PMOS transistor is connected to the power supply voltage terminal. The gate and drain of the 33rd PMOS transistor are connected to the source of the 34th PMOS transistor, the gate and drain of the 34th PMOS transistor are connected to the source of the 35th PMOS transistor, the gate and drain of the 35th PMOS transistor are connected to the source of the 36th PMOS transistor, and the gate and drain of the 36th PMOS transistor are connected to the source of the 37th PMOS transistor. The gate of the 38th PMOS transistor and the gate of the 16th NMOS transistor are respectively configured to input the second switch control signal. The source of the 38th PMOS transistor is connected to the power supply voltage terminal. The drain of the 38th PMOS transistor is connected to the drain of the 16th NMOS transistor and is configured to output the start signal. The source of the 16th NMOS transistor is connected to the drain of the 15th NMOS transistor. The sources of the 14th NMOS transistor and the 15th NMOS transistor are respectively connected to the ground terminal.

9. The bandgap reference circuit according to any one of claims 1-8, characterized in that, The bandgap reference circuit also includes a start / stop control circuit; The start-stop control circuit includes a first inverter, a second inverter, and a thirteenth NMOS transistor; The first inverter is configured to invert the power control signal to obtain and output the second switch control signal; The second inverter is configured to invert the second switch control signal to obtain and output the first switch control signal; The gate of the thirteenth NMOS transistor is configured to receive the first switch control signal, the drain of the thirteenth NMOS transistor is connected to the output terminal of the voltage-mode reference voltage generation circuit, and the source of the thirteenth NMOS transistor is connected to ground.

Images