Data processing method, computing device and computer readable storage medium

Abstract

The present disclosure relates to a method, a computing device and a computer-readable storage medium for data processing. The method includes: in response to one of the input data in a first format and the output data in a second format being a continuous tensor, and the other of the input data in the first format and the output data in the second format being a non-continuous tensor, wherein both the first format and the second format are dedicated data formats for artificial intelligence chips, traversing the shape of the continuous tensor; based on the currently traversed logical coordinates of the continuous tensor, the step size of the continuous tensor and the step size of the non-continuous tensor, calculating the physical address of the non-continuous tensor corresponding to the currently traversed logical coordinates of the continuous tensor; and based on the currently traversed logical coordinates of the continuous tensor and the calculated corresponding physical address of the non-continuous tensor, performing non-continuous copying. As a result, the present disclosure can at least improve the overall performance of artificial intelligence chips in data processing.

Description

Technical Field

[0001] The present disclosure generally relates to the field of information processing, and in particular, to a data processing method, a computing device, and a computer-readable storage medium. Background Art

[0002] AI chips usually have a dedicated data format (also called a dedicated data layout), which is different from the data format on the host side. For example, the data format on the host side is a plain format in which memory addresses are continuous by dimension.

[0003] In artificial intelligence chips, deformation (View) type operators can move data of tensors in memory, and deformation type operators can also only logically convert continuous tensors into non-continuous tensors without data movement. For example, View type operators can include Reshape operators, Permute operators, and Slice operators. In some modes used for artificial intelligence model training (such as eager mode), there may be a large number of View type operators. In order to avoid the performance overhead caused by frequent data movement, these View type operators usually logically convert continuous tensors into non-continuous tensors. When the artificial intelligence model needs to use non-continuous tensors, it is necessary to re-open a piece of memory space for uncontiguous copy (Uncontiguous Copy, also known as Strided Copy) operations to ensure that the data is continuous in memory.

[0004] In traditional data processing technology solutions, when a View type operator needs to convert data in a dedicated data format into data in another dedicated data format, it usually calls a Reorder operator to convert the dedicated data format and the Plain format, and performs the non-continuous copy involved in the Plain format data. However, AI chips have poor performance when processing data in the Plain format; and AI chips invoking the Reorder operator will generate additional overhead, further reducing the overall performance of the AI ​​chip.

[0005] In summary, the shortcomings of the traditional data processing technical solution are: non-continuous copying is performed on data in plain format, and the Reorder operator needs to be called before and after the non-continuous copying, resulting in poor data processing performance. Summary of the invention

[0006] In response to the above problems, the present disclosure provides a data processing method, a computing device, and a computer-readable storage medium, which can at least improve the overall performance of artificial intelligence chips in data processing.

[0007] According to a first aspect of the present disclosure, a method for data processing is provided, the method comprising: in response to one of input data in a first format and output data in a second format being a continuous tensor, and the other of the input data in the first format and the output data in the second format being a non-continuous tensor, wherein both the first format and the second format are dedicated data formats for artificial intelligence chips, traversing the shape (Shape) of the continuous tensor; calculating a physical address of the non-continuous tensor corresponding to the currently traversed logical coordinates of the continuous tensor based on the currently traversed logical coordinates of the continuous tensor and the stride (Stride) of the non-continuous tensor; and performing non-continuous copying based on the currently traversed logical coordinates of the continuous tensor and the calculated physical address of the corresponding non-continuous tensor.

[0008] In some embodiments, the dedicated data format of the artificial intelligence chip is a format in which memory addresses are continuous in blocks.

[0009] In some embodiments, the method also includes: determining whether the input data and the output data are continuous; if the input data is continuous and the output data is discontinuous, determining the input data as a continuous tensor and determining the output data as a non-continuous tensor; and if the input data is discontinuous and the output data is continuous, determining the input data as a non-continuous tensor and determining the output data as a continuous tensor.

[0010] In some embodiments, calculating the physical address of a non-continuous tensor corresponding to the currently traversed logical coordinates of a continuous tensor includes: in response to the output data being a continuous tensor and the input data being a non-continuous tensor, performing the following operations: calculating the logical address of the corresponding input data based on the currently traversed logical coordinates of the output data; calculating the logical coordinates of the corresponding input data based on the logical address of the corresponding input data; and calculating the physical address of the corresponding input data based on the logical coordinates of the corresponding input data.

[0011] In some embodiments, based on the currently traversed logical coordinates of the output data, calculating the logical address of the corresponding input data includes: multiplying the currently traversed logical coordinates of the output data by the step size of the input data to obtain the corresponding logical address of the input data.

[0012] In some embodiments, calculating the logical coordinates of the corresponding input data based on the logical address of the corresponding input data includes: calculating the logical coordinates of the corresponding input data based on the logical address of the corresponding input data and the step size of the input data.

[0013] In some embodiments, calculating the physical address of the corresponding input data based on the logical coordinates of the corresponding input data includes: calculating the physical address offset value of the corresponding input data based on the logical coordinates of the corresponding input data and the shape of the input data; and calculating the physical address of the corresponding input data based on the physical address offset value of the corresponding input data and the memory starting address.

[0014] In some embodiments, based on the currently traversed logical coordinates of the continuous tensor and the calculated physical address of the corresponding non-continuous tensor, performing non-continuous copying includes: reading the target data based on the physical address of the corresponding input data; and writing the read target data to the output data according to the currently traversed logical coordinates of the output data.

[0015] In some embodiments, calculating the physical address of a non-continuous tensor corresponding to the currently traversed logical coordinates of a continuous tensor includes: in response to the input data being a continuous tensor and the output data being a non-continuous tensor, performing the following operations: calculating the logical address of the corresponding output data based on the currently traversed logical coordinates of the input data; calculating the logical coordinates of the corresponding output data based on the logical address of the corresponding output data; and calculating the physical address of the corresponding output data based on the logical coordinates of the corresponding output data.

[0016] In some embodiments, based on the currently traversed logical coordinates of the continuous tensor and the calculated physical address of the corresponding non-continuous tensor, performing non-continuous copying includes: reading target data based on the currently traversed logical coordinates of the input data; and writing the read target data to the output data according to the physical address of the output data.

[0017] According to a second aspect of the present disclosure, a computing device is provided, comprising: at least one processor; and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, and when the instructions are executed by the at least one processor, the computing device executes the method of the first aspect of the present disclosure.

[0018] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program code is stored. When the computer program code is executed, the method of the first aspect of the present disclosure is executed.

[0019] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements.

[0021] Figure 1 A schematic diagram illustrating the process of traditional data processing.

[0022] Figure 2 The flowchart of the data processing method according to the embodiment of the present disclosure is illustrated.

[0023] Figure 3 A flowchart of a method for calculating a physical address of a non-continuous tensor corresponding to a currently traversed logical coordinate of a continuous tensor according to an embodiment of the present disclosure is illustrated.

[0024] Figure 4A Exemplary input data according to an embodiment of the present disclosure is illustrated.

[0025] Figure 4B The diagram illustrates an exemplary physical arrangement of input data in a memory according to an embodiment of the present disclosure.

[0026] Figure 4C Exemplary output data according to an embodiment of the present disclosure is illustrated.

[0027] Figure 4D The figure illustrates an exemplary physical arrangement of output data on a memory according to an embodiment of the present disclosure.

[0028] Figure 5 A flowchart of a method for calculating a physical address of a non-continuous tensor corresponding to a currently traversed logical coordinate of a continuous tensor according to an embodiment of the present disclosure is illustrated.

[0029] Figure 6 A block diagram of an electronic device suitable for implementing an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0030] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0031] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0032] Figure 1 The figure shows a schematic diagram of the traditional data processing process. Figure 1 As shown, the View type operator in the artificial intelligence chip converts the input data in the four-dimensional activation format into the output data in the matrix format by performing the following process, where both the Activation format and the Matrix format are dedicated data formats for artificial intelligence chips: converting the input data in the Activation format into the first intermediate data in the Plain format by reordering (for example, calling the Reorder operator); modifying the step size ( Figure 1 ); performing non-continuous copying to convert the first intermediate data in the Plain format into the second intermediate data in the Plain format; converting the second intermediate data in the Plain format into output data in the Matrix format by reordering (for example, calling a Reorder operator).

[0033] exist Figure 1 In the traditional data processing technical solution shown, non-continuous copying is performed on data in a plain format, and a Reorder operator needs to be called before and after the non-continuous copying, resulting in poor performance.

[0034] In order to at least partially solve one or more of the above problems and other potential problems, the exemplary embodiments of the present disclosure propose a technical solution for data processing. In the embodiments of the present disclosure, by traversing the shape of the continuous tensor, based on the logical coordinates currently traversed by the continuous tensor and the step size of the non-continuous tensor, the physical address of the non-continuous tensor corresponding to the logical coordinates currently traversed by the continuous tensor is calculated, and based on the logical coordinates currently traversed by the continuous tensor and the calculated physical address of the corresponding non-continuous tensor, a non-continuous copy is performed, so that the non-continuous copy is directly performed under the data of the dedicated data format of the artificial intelligence chip, and there is no need to call the Reorder operator before and after the non-continuous copy, thereby at least improving the overall performance of the artificial intelligence chip in data processing.

[0035] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same reference numeral in each figure.

[0036] Figure 2 The flowchart of the method 200 for data processing according to the embodiment of the present disclosure is shown. The method 200 can be executed by an artificial intelligence chip or by Figure 6 The electronic device 600 shown is executed. It should be understood that the method 200 may further include additional blocks not shown and / or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0037] It should be noted that the artificial intelligence chip used to implement the embodiments of the present disclosure may depend on the actual situation, and the present disclosure does not limit this. For example, the artificial intelligence chip used to implement the embodiments of the present disclosure is a GPU, GPGPU, etc. for deep learning. For another example, the artificial intelligence chip used to implement the embodiments of the present disclosure may have one or more processing units, and the one or more processing units may include dedicated processing units such as GPGPU, GPU, FPGA, and ASIC.

[0038] exist Figure 2 In the illustrated embodiment, in response to one of the input data in the first format and the output data in the second format being a continuous tensor, and the other of the input data in the first format and the output data in the second format being a non-continuous tensor, wherein both the first format and the second format are dedicated data formats for the artificial intelligence chip, the artificial intelligence chip can perform steps 202 to 206.

[0039] For continuous tensors, the order in which the elements of the underlying one-dimensional array are stored in memory is consistent with the order of the elements in the row-major one-dimensional expansion. For example, you can refer to the subsequent combination Figure 4C and Figure 4D The described embodiments will not be described in detail here.

[0040] For non-contiguous tensors, the order in which the elements of the underlying one-dimensional array are stored in memory is inconsistent with the order of the elements expanded in row-major one-dimensional order. For example, you can refer to the subsequent combination Figure 4A and Figure 4B The described embodiments will not be described in detail here.

[0041] Regarding the dedicated data format of the artificial intelligence chip, it refers to a data format designed specifically for the artificial intelligence chip, and it is different from the Plain format. For example, the dedicated data format of the artificial intelligence chip is a format in which the memory address is continuous in blocks. For example, the dedicated data format of the artificial intelligence chip includes the Matrix format, the Activation format, the convolution weight (ConvWeight) format, the two-dimensional vector (Vector) format, and the deep convolution weight (DWCWeight) format, etc. It should be noted that the dedicated data format of the artificial intelligence chip may depend on the actual situation, and the embodiments of the present disclosure are not limited to this.

[0042] At step 202, the shape of the continuous tensor is traversed.

[0043] Regarding the shape of a tensor, it refers to the amount of data in each dimension of the tensor. For example, you can refer to the subsequent combination Figure 4A and Figure 4C The described embodiments will not be described in detail here.

[0044] Regarding traversing the shape of a continuous tensor, it refers to traversing each element in the continuous tensor according to the shape of the continuous tensor. It should be noted that the manner, order, granularity, etc. of traversing each element when traversing the shape of the continuous tensor may depend on the actual situation, and the embodiments of the present disclosure do not limit this. For example, traversing the shape of the continuous tensor includes traversing the shape of the continuous tensor at a memory-friendly granularity.

[0045] In step 204, based on the currently traversed logical coordinates of the continuous tensor and the step size of the non-continuous tensor, the physical address of the non-continuous tensor corresponding to the currently traversed logical coordinates of the continuous tensor is calculated.

[0046] Regarding logical coordinates, they refer to the semantic coordinates of tensors. For example, you can refer to the subsequent combination Figure 3 , Figure 4A and Figure 4C The described embodiments will not be described in detail here.

[0047] Regarding the stride, it refers to the number of elements in the tensor in memory that need to be skipped in order to get the next element along each dimension. For example, you can refer to the subsequent combination Figure 3 , 4A to 4D The described embodiments will not be described in detail here.

[0048] Regarding the physical address, it refers to the address of the tensor in memory. For example, you can refer to the subsequent combination Figure 4B and Figure 4D The described embodiments will not be described in detail here.

[0049] Regarding calculating the physical address of the non-continuous tensor corresponding to the logical coordinates currently traversed by the continuous tensor, for example, reference can be made to the subsequent combination Figure 3 and 4A to 4D The described embodiments may also refer to the following combined Figure 5 The described embodiments will not be described in detail here.

[0050] In step 206, non-continuous copying is performed based on the currently traversed logical coordinates of the continuous tensor and the calculated physical addresses of the corresponding non-continuous tensors.

[0051] Regarding non-continuous copying, it means that the artificial intelligence chip opens up a new memory space and converts continuous tensors and non-continuous tensors through copying.

[0052] Regarding the non-continuous copying based on the currently traversed logical coordinates of the continuous tensor and the calculated physical addresses of the corresponding non-continuous tensors, for example, please refer to the subsequent combination Figure 3 and 4A to 4D The described embodiments may also refer to the following combined Figure 5 The described embodiments will not be described in detail here.

[0053] In the embodiments of the present disclosure, by traversing the shape of the continuous tensor, the physical address of the non-continuous tensor corresponding to the currently traversed logical coordinates of the continuous tensor and the step size of the non-continuous tensor is calculated, and based on the currently traversed logical coordinates of the continuous tensor and the calculated physical address of the corresponding non-continuous tensor, non-continuous copying is performed, so that the non-continuous copying is directly performed under the data of the dedicated data format of the artificial intelligence chip, and there is no need to call the Reorder operator before and after the non-continuous copying, thereby at least improving the overall performance of the artificial intelligence chip in data processing.

[0054] It should be noted that the embodiments of the present disclosure do not limit which of the input data in the first format and the output data in the second format is a continuous tensor and which is a discontinuous tensor. For example, in some embodiments of the present disclosure, the data processing method further includes: determining whether the input data and the output data are continuous; if the input data is continuous and the output data is discontinuous, determining the input data as a continuous tensor and determining the output data as a discontinuous tensor; and if the input data is discontinuous and the output data is continuous, determining the input data as a discontinuous tensor and determining the output data as a continuous tensor.

[0055] Combine the following Figure 3 and 4A to 4D An exemplary method for calculating the physical address of a non-continuous tensor corresponding to the currently traversed logical coordinates of a continuous tensor is described.

[0056] Figure 3 The flowchart of the method 300 for calculating the physical address of a non-continuous tensor corresponding to the logical coordinates currently traversed by the continuous tensor according to the embodiment of the present disclosure is shown. The method 300 can be executed by an artificial intelligence chip or by Figure 6 The electronic device 600 shown is executed. It should be understood that the method 300 may also include additional blocks not shown and / or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0057] Figure 4A Exemplary input data according to an embodiment of the present disclosure is illustrated. Figure 4B The diagram illustrates an exemplary physical arrangement of input data in a memory according to an embodiment of the present disclosure. Figure 4C Exemplary output data according to an embodiment of the present disclosure is illustrated. Figure 4D The figure illustrates an exemplary physical arrangement of output data on a memory according to an embodiment of the present disclosure.

[0058] exist 4A to 4D In the example shown, the input data is a non-continuous tensor, the output data is a continuous tensor, the shape of the input data is [4,3], and the input data is, for example, a matrix of 4 rows and 3 columns; the shape of the output data is [3,4], and the output data is, for example, a matrix of 3 rows and 4 columns; the step size of the input data is [1,3], and the step size of the input data, for example, represents accessing the data by moving 3 data at a time in the dimensional direction corresponding to the column, and the step size of the output data is [4,1], and the step size of the output data, for example, represents accessing the data by moving 4 data at a time in the dimensional direction corresponding to the row. It is worth noting that, taking the step size of the input data as [n,m] as an example, it represents accessing the data by moving n data in the original data each time in the first dimension and moving m data in the original data each time in the second dimension.

[0059] In addition, it should be noted that in the present disclosure, taking the shape of a tensor (or "input data" or "output data") as [n,m,p] as an example, it represents that the tensor (or "input data" or "output data") has n data elements in its first dimension, m data elements in its second dimension, and p data elements in its third dimension. Therefore, the number of data elements possessed by the tensor (or "input data" or "output data") is n*m*p. If the coordinates of one of the data elements are [q,r,s], then the position of the data element in the tensor (or "input data" or "output data") corresponds to the coordinate value "q" in the first dimension, the coordinate value "r" in the second dimension, and the coordinate value "s" in the third dimension.

[0060] exist Figure 3 In the described embodiment, in response to the output data being a continuous tensor and the input data being a non-continuous tensor, the artificial intelligence chip can perform steps 302 to 306.

[0061] In step 302, based on the currently traversed logical coordinates of the output data, the corresponding logical address of the input data is calculated.

[0062] For example, the currently traversed logical coordinates of the output data are multiplied by the step length of the input data to obtain the corresponding logical address of the input data.

[0063] For example, combined with 4A to 4D In the described embodiment, it is assumed that the logical coordinates of the output data currently traversed are [2,1]. In this case, the output data currently traversed is Figure 4C The shaded data "9" in the figure, the input data corresponding to the currently traversed output data is Figure 4A The shaded data "9" in the figure can be calculated based on the following formula (1):

[0064] The logical address of the input data = the logical coordinate of the output data currently traversed [0] * the step length of the input data [0] + the logical coordinate of the output data currently traversed [1] * the step length of the input data [1] Formula (1)

[0065] For example, based on formula (1), the corresponding logical address of the input data can be calculated as

[0066] 2 * 1 + 1 * 3 = 5.

[0067] In step 304, the logical coordinates of the corresponding input data are calculated based on the logical addresses of the corresponding input data.

[0068] For example, based on the logical address of the corresponding input data and the step length of the input data, the logical coordinates of the corresponding input data are calculated.

[0069] For example, combined with 4A to 4D In the described embodiment, it is assumed that the logical address of the corresponding input data is 5. The logical coordinates of the corresponding input data can be calculated based on the following formula (2) and formula (3):

[0070] Logical coordinate of input data [0] = logical address of input data / step length of input data [1] Formula (2)

[0071] Logical coordinate of input data [1] = Logical address of input data – Logical coordinate of input data [0] * Step length of input data [1] Formula (3)

[0072] For example, based on formula (2) and formula (3), the corresponding logical coordinates of the input data can be calculated as [5 / 3 = 1, (5 – 1 * 3) = 2], that is, [1, 2].

[0073] In step 306, the physical address of the corresponding input data is calculated based on the logical coordinates of the corresponding input data.

[0074] For example, based on the logical coordinates of the corresponding input data and the shape of the input data, the physical address offset value of the corresponding input data is calculated; and based on the physical address offset value of the corresponding input data and the memory starting address, the physical address of the corresponding input data is calculated.

[0075] For example, combined with 4A to 4D In the described embodiment, it is assumed that the logical coordinates of the corresponding input data are [1, 2]. The physical address offset value of the corresponding input data can be calculated based on the following formula (4):

[0076] The physical address offset value of the input data = the logical coordinate of the input data [0] * the shape of the input data [1] + the logical coordinate of the input data [1] Formula (4)

[0077] For example, based on formula (4), the physical address offset value of the corresponding input data can be calculated as 1 * 3 + 2 = 5. For example, by offsetting the physical address offset value of the input data by 5 based on the memory start address of the input data, the physical address of the corresponding input data "9" can be calculated, such as Figure 4B shown.

[0078] In combination Figure 3 and 4A to 4D In the described embodiment, based on the currently traversed logical coordinates of the continuous tensor and the calculated physical address of the corresponding non-continuous tensor, non-continuous copying is performed, for example, including: reading the target data based on the physical address of the corresponding input data; and writing the read target data to the output data according to the currently traversed logical coordinates of the output data.

[0079] For example, writing the read target data to the output data according to the currently traversed logical coordinates of the output data includes: calculating the physical address of the currently traversed output data based on the read target data according to the currently traversed logical coordinates of the output data; and writing the read target data to the physical address of the currently traversed output data, such as Figure 4DIt should be noted that the implementation method of calculating the physical address of the currently traversed output data can be similarly referred to the implementation method of calculating the physical address of the input data, which will not be repeated here.

[0080] Figure 5 The flowchart of the method 500 for calculating the physical address of a non-continuous tensor corresponding to the logical coordinates currently traversed by the continuous tensor according to the embodiment of the present disclosure is shown. The method 500 can be executed by an artificial intelligence chip or by Figure 6 The electronic device 600 shown is executed. It should be understood that the method 500 may further include additional blocks not shown and / or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0081] exist Figure 5 In the described embodiment, in response to the input data being a continuous tensor and the output data being a non-continuous tensor, the artificial intelligence chip can perform steps 502 to 506.

[0082] In step 502, based on the currently traversed logical coordinates of the input data, the corresponding logical address of the output data is calculated.

[0083] In step 504, the logical coordinates of the corresponding output data are calculated based on the logical addresses of the corresponding output data.

[0084] In step 506, the physical address of the corresponding output data is calculated based on the logical coordinates of the corresponding output data.

[0085] It should be noted that Figure 5 The specific implementation of steps 502 to 506 in the above method may depend on the actual situation, and the present disclosure will not elaborate on this. Figure 5 The specific implementation of steps 502 to 506 in the embodiment can be similarly referred to in Figure 3 The specific implementation of steps 302 to 306 in will not be repeated here.

[0086] In combination Figure 5 In the described embodiment, based on the currently traversed logical coordinates of the continuous tensor and the calculated physical addresses of the corresponding non-continuous tensors, the non-continuous copying includes: reading the target data based on the currently traversed logical coordinates of the input data; and writing the read target data to the output data according to the physical address of the output data. The specific implementation method can be similarly referred to in conjunction with Figure 3 and 4A to 4D The specific implementation of the described embodiment will not be described in detail here.

[0087] In addition, in some embodiments of the present disclosure, a computing device is proposed, comprising: at least one processor; and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, and when the instructions are executed by the at least one processor, the computing device executes method 200, method 300, and method 500 as described above.

[0088] In addition, in some embodiments of the present disclosure, a computer-readable storage medium is provided, on which a computer program code is stored. When the computer program code is executed, the method 200, the method 300, and the method 500 described above are executed.

[0089] Figure 6 Schematically shows a block diagram of an electronic device 600 suitable for implementing an embodiment of the present disclosure. The electronic device 600 can be used to execute the method 200, the method 300 and the method 500. Figure 6 As shown, the electronic device 600 includes a central processing unit (i.e., CPU 602), which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (i.e., ROM 604) or loaded from a storage unit 616 to a random access memory (i.e., RAM 606). In RAM 606, various programs and data required for the operation of the electronic device 600 can also be stored. CPU 602, ROM 604 and RAM 606 are connected to each other via a bus 608. An input / output interface (i.e., I / O interface 610) is also connected to the bus 608.

[0090] Multiple components in the electronic device 600 are connected to the I / O interface 610, including: an input unit 612, an output unit 614, and a storage unit 616. The CPU 602 performs the various methods and processes described above, such as executing the method 200, the method 300, and the method 500. For example, in some embodiments, the method 200, the method 300, and the method 500 may be implemented as a computer software program, which is stored in a machine-readable medium, such as the storage unit 616. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 600 via the ROM 604 and / or the communication unit 618. When the computer program is loaded into the RAM 606 and executed by the CPU 602, one or more operations in the method 200, the method 300, and the method 500 described above may be performed. Alternatively, in other embodiments, the CPU 602 may be configured to perform one or more actions in the method 200, the method 300, and the method 500 by any other appropriate means (e.g., by means of firmware).

[0091] It should be further noted that the present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0092] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0093] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0094] The computer program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect through the Internet). In some embodiments, by using the state information of the computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit may execute the computer-readable program instructions, thereby implementing various aspects of the present invention.

[0095] Various aspects of the present invention are described herein with reference to the flow chart and / or block diagram of the method, device (system), and computer program product according to an embodiment of the present invention. It should be understood that each box of the flow chart and / or block diagram and the combination of each box in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0096] These computer-readable program instructions can be provided to a processor in a voice interaction device, a general-purpose computer, a special-purpose computer, or a processing unit of other programmable data processing devices, thereby producing a machine, so that when these instructions are executed by a processing unit of a computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions enable the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0097] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0098] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the equipment, method and computer program product according to multiple embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of this module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0099] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for data processing, characterized in that: The method comprises: In response to one of the input data in the first format and the output data in the second format being a continuous tensor, and the other of the input data in the first format and the output data in the second format being a non-continuous tensor, wherein both the first format and the second format are dedicated data formats for an artificial intelligence chip, Iterate over the shapes of consecutive tensors; Based on the currently traversed logical coordinates of the continuous tensor and the step size of the non-continuous tensor, calculate the physical address of the non-continuous tensor corresponding to the currently traversed logical coordinates of the continuous tensor; and Based on the currently traversed logical coordinates of the continuous tensor and the calculated physical addresses of the corresponding non-continuous tensors, non-continuous copies are performed; Calculating the physical address of the non-continuous tensor corresponding to the currently traversed logical coordinates of the continuous tensor includes: In response to the output data being a continuous tensor and the input data being a non-continuous tensor, the following operations are performed: Based on the currently traversed logical coordinates of the output data, the corresponding logical address of the input data is calculated; Based on the logical address of the corresponding input data, the logical coordinates of the corresponding input data are calculated; and Based on the logical coordinates of the corresponding input data, the physical address of the corresponding input data is calculated; Wherein, based on the currently traversed logical coordinates of the output data, the corresponding logical address of the input data is calculated to include: Multiply the currently traversed logical coordinate of the output data by the step length of the input data to obtain the corresponding logical address of the input data; Based on the logical address of the corresponding input data, the logical coordinates of the corresponding input data are calculated including: Based on the logical address of the corresponding input data and the step length of the input data, the logical coordinates of the corresponding input data are calculated.

2. The method according to claim 1, characterized in that The specialized data format for AI chips is a format in which memory addresses are continuous in blocks.

3. The method according to claim 1, characterized in that The method further comprises: Determine whether the input data and output data are continuous; If the input data is continuous and the output data is non-continuous, determining the input data as a continuous tensor and determining the output data as a non-continuous tensor; and If the input data is discontinuous and the output data is continuous, the input data is determined as a discontinuous tensor and the output data is determined as a continuous tensor.

4. The method according to claim 1, characterized in that Based on the logical coordinates of the corresponding input data, the physical address of the corresponding input data is calculated including: Based on the logical coordinates of the corresponding input data and the shape of the input data, a physical address offset value of the corresponding input data is calculated; and Based on the physical address offset value of the corresponding input data and the memory start address, the physical address of the corresponding input data is calculated.

5. The method according to claim 4, characterized in that Based on the currently traversed logical coordinates of the continuous tensor and the calculated physical addresses of the corresponding non-continuous tensors, the non-continuous copying includes: Reading target data based on the physical address of the corresponding input data; and The read target data is written into the output data according to the logical coordinates currently traversed by the output data.

6. The method according to claim 1, characterized in that Calculating the physical address of the non-continuous tensor corresponding to the currently traversed logical coordinates of the continuous tensor also includes: In response to the input data being a continuous tensor and the output data being a non-continuous tensor, the following operations are performed: Based on the currently traversed logical coordinates of the input data, the corresponding logical address of the output data is calculated; Based on the logical address of the corresponding output data, the logical coordinates of the corresponding output data are calculated; and Based on the logical coordinates of the corresponding output data, the physical address of the corresponding output data is calculated.

7. The method according to claim 6, characterized in that Based on the currently traversed logical coordinates of the continuous tensor and the calculated physical addresses of the corresponding non-continuous tensors, the non-continuous copying includes: Reading target data based on the currently traversed logical coordinates of the input data; and The read target data is written to the output data at the physical address of the output data.

8. A computing device comprising: at least one processor; as well as At least one memory, the at least one memory being coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, causing the computing device to perform the method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program code stored thereon, wherein the computer program code, when executed, performs the method according to any one of claims 1 to 7.

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