Pixel driving circuit and display panel

Abstract

The application discloses a pixel driving circuit and a display panel, and belongs to the technical field of display. The pixel driving circuit comprises a pixel unit and a driving circuit. The pixel unit comprises red / green / blue pixels arranged in a preset arrangement mode. The driving circuit comprises a plurality of control circuits. The control end of the control circuit is connected with a gate driving line group. The first end of the control circuit is connected with a target data line. The second end of the control circuit is connected with adjacent red pixel groups, green pixel groups or blue pixel groups. The gate driving line group comprises adjacent and simultaneously driven first / second gate driving lines. The target data line is used for writing the same data into the red pixel groups, the green pixel groups or the blue pixel groups. In the same frame, the first / second gate driving lines are used for simultaneously controlling the red pixel groups, the green pixel groups or the blue pixel groups to drive display, thereby solving the problem that the DLG technology cannot be used under the TRD pixel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to pixel driving circuits and display panels. Background Technology

[0002] With the rapid development of display technology, users have increasingly higher requirements for display product drivers. As a result, DLG (Dual Line Gate) technology has emerged. However, when using DLG technology in the commonly used TRD pixel driver circuit, two different color pixels may display the same grayscale, which will prevent the display of RGB monochrome images and cause the display panel to be unable to display colors normally. Therefore, there is an urgent need for a new pixel driver circuit to solve the problem that DLG technology cannot be used under TRD pixels. Summary of the Invention

[0003] The main purpose of this application is to provide a pixel driving circuit and a display panel, which aims to solve the technical problem that DLG technology cannot be used under TRD pixels.

[0004] To achieve the above objectives, this application provides a pixel driving circuit, which includes a pixel unit and a driving circuit. The pixel unit includes red pixels, green pixels and blue pixels arranged in a preset manner. The driving circuit includes multiple sets of control circuits.

[0005] The control terminal of the control circuit is connected to the gate drive line group, the first terminal of the control circuit is connected to the target data line, and the second terminal of the control circuit is connected to the adjacent red pixel group, or the adjacent green pixel group, or the adjacent blue pixel group.

[0006] The gate driving line group includes a first gate driving line and a second gate driving line that are adjacent and driven simultaneously. The target data line is used to write the same data to the red pixel group, or the green pixel group, or the blue pixel group, and in the same frame, the first gate driving line and the second gate driving line simultaneously control the red pixel group, or the green pixel group, or the blue pixel group to drive the display.

[0007] Optionally, when the preset arrangement is that the red pixels, green pixels, and blue pixels are arranged sequentially in the rows of the pixel units, and the red pixels, green pixels, and blue pixels are arranged sequentially in the columns of the pixel units, the adjacent red pixel group is a first red pixel and a second red pixel that are diagonally adjacent, the adjacent green pixel group is a first green pixel and a second green pixel that are diagonally adjacent, and the adjacent blue pixel group is a first blue pixel and a second blue pixel that are diagonally adjacent.

[0008] Optionally, the control circuit includes a first thin-film transistor and a second thin-film transistor;

[0009] The control terminal of the first thin-film transistor is connected to the first gate driving line, the control terminal of the second thin-film transistor is connected to the second gate driving line, and the target data line is connected to the first terminal of the first thin-film transistor and the first terminal of the second thin-film transistor, respectively.

[0010] When the second terminal of the first thin-film transistor is connected to the first red pixel, the second terminal of the second thin-film transistor is connected to the second red pixel; or, when the second terminal of the first thin-film transistor is connected to the first green pixel, the second terminal of the second thin-film transistor is connected to the second green pixel; or, when the second terminal of the first thin-film transistor is connected to the first blue pixel, the second terminal of the second thin-film transistor is connected to the second blue pixel.

[0011] Optionally, when the preset arrangement is that the red pixels, green pixels, or blue pixels are arranged in rows of the pixel units, and the columns of the pixel units are arranged in order of red pixels, green pixels, and blue pixels, the adjacent red pixel group is a horizontally adjacent third red pixel and fourth red pixel, the adjacent green pixel group is a horizontally adjacent third green pixel and fourth green pixel, and the adjacent blue pixel group is a horizontally adjacent third blue pixel and fourth blue pixel.

[0012] Optionally, the control circuit includes a third thin-film transistor and a fourth thin-film transistor;

[0013] The control terminal of the third thin-film transistor is connected to the first gate driving line, the control terminal of the fourth thin-film transistor is connected to the second gate driving line, and the target data line is connected to the first terminal of the third thin-film transistor and the first terminal of the fourth thin-film transistor, respectively.

[0014] When the second terminal of the third thin-film transistor is connected to the third red pixel, the second terminal of the fourth thin-film transistor is connected to the fourth red pixel; or, when the second terminal of the third thin-film transistor is connected to the third green pixel, the second terminal of the fourth thin-film transistor is connected to the fourth green pixel; or, when the second terminal of the third thin-film transistor is connected to the third blue pixel, the second terminal of the fourth thin-film transistor is connected to the fourth blue pixel.

[0015] Optionally, when the target data line is the first data line, the red pixel group, the green pixel group, and the blue pixel group are odd-numbered rows of pixels.

[0016] Optionally, when the target data line is the second data line, the red pixel group, the green pixel group, and the blue pixel group are even-numbered rows of pixels.

[0017] Optionally, the target data line is connected sequentially to the red pixel group, the blue pixel group, and the green pixel group through multiple control circuits.

[0018] Optionally, when the number of pixel units is odd, a pseudo gate drive line is added to the first or last row of the pixel units.

[0019] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including an array substrate, the array substrate including the pixel arrangement structure as described above.

[0020] This application proposes a pixel driving circuit and a display panel. The pixel driving circuit is optimized to provide a pixel driving circuit comprising: red, green, and blue pixels arranged sequentially in a preset pattern within a pixel unit, and multiple sets of control circuits within the driving circuit. Because when DLG technology is applied to the pixel driving circuit of a commonly used TRD (True Pixel Rendering) system, two different color pixels may display the same grayscale, thus preventing the display of RGB monochrome images and causing the display panel to fail to display colors correctly. This application, combining the aforementioned modules, connects the control terminal of the control circuit to the gate driving line group. The first terminal of the control circuit is connected to the target data line, and the second terminal of the control circuit is connected to an adjacent red pixel group, or an adjacent green pixel group, or an adjacent blue pixel group. Simultaneously, the target data line is used to write the same data to the red pixel group, or the green pixel group, or the blue pixel group. Then, by simultaneously controlling the red pixel group, or the green pixel group, or the blue pixel group through the first gate driving line and the second gate driving line, the same pixel is simultaneously driven to write system data, thus realizing the use of DLG technology under TRD pixels. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 This is a functional module diagram of an embodiment of the pixel driving circuit of this application;

[0023] Figure 2 This is a schematic diagram of the pixel driving circuit of a commonly used TRD.

[0024] Figure 3 This is a waveform control diagram of a commonly used pixel driving circuit;

[0025] Figure 4 This is a schematic diagram of a circuit connection for pixel arrangement in the pixel driving circuit of this application;

[0026] Figure 5 This is a schematic diagram of the structure of the display panel involved in the embodiments of this application;

[0027] Figure 6 This is a waveform control diagram of pixel arrangement in the pixel driving circuit of this application;

[0028] Figure 7 This is another circuit connection diagram of pixel arrangement in the pixel driving circuit of this application;

[0029] Figure 8 This is another waveform control diagram of pixel arrangement in the pixel driving circuit of this application;

[0030] Figure 9 This is a circuit connection diagram of a switch in the pixel driving circuit of this application;

[0031] Figure 10 This is another circuit connection diagram of the switch in the pixel driving circuit of this application.

[0032] Explanation of icon numbers:

[0033] label name label name 1001 processor 1002 Communication bus 1003 User Interface 1004 Network interface 1005 memory Q Gate drive line group G1 First gate drive line G2 Second gate drive line D Target data line R Red pixel G green pixel B blue pixel 10 control circuit 200 pixel unit 21 Red pixel group 22 Green pixel group 23 Blue pixel group G1-Gn First to nth gate drive lines D1-Dn First to nth data lines T1 First thin-film transistor T2 Second thin-film transistor G0 Pseudo-gate drive line T3 Third thin-film transistor T4 Fourth thin-film transistor

[0034] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0035] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0036] This application provides a pixel driving circuit, referring to... Figure 1 , Figure 1 This is a functional module diagram of an embodiment of a pixel driving circuit according to this application.

[0037] In this embodiment, the pixel driving circuit includes a pixel unit 200 and a driving circuit 100 (not shown in the figure). The pixel unit 200 includes a red pixel R, a green pixel G and a blue pixel B arranged in a preset arrangement. The driving circuit 100 includes multiple sets of control circuits 10.

[0038] The control terminal of the control circuit 10 is connected to the gate drive line group Q, the first terminal of the control circuit 10 is connected to the target data line D, and the second terminal of the control circuit 10 is connected to the adjacent red pixel group 21, or the adjacent green pixel group 22, or the adjacent blue pixel group 23.

[0039] The gate driving line group Q includes an adjacent and simultaneously driven first gate driving line G1 and second gate driving line G2. The target data line D is used to write the same data to the red pixel group R, or the green pixel group G, or the blue pixel group B, and in the same frame, the first gate driving line G1 and the second gate driving line G2 simultaneously control the red pixel group R, or the green pixel group G, or the blue pixel group B to drive the display.

[0040] It's worth noting that Dual-Line Gate (DLG) technology in LCDs has garnered attention. Also known as refresh rate doubling technology, DLG works by simultaneously opening two scan lines in the panel's GDL circuit, with both lines receiving the same scan signal. In this mode, the number of vertically displayed pixels is effectively halved, doubling the refresh rate without altering the existing hardware or chip processing power. Meanwhile, in the LCD display industry, TRD (True Reflection Drill) design is gaining increasing popularity due to its ability to reduce the number of COF (Chip on Film) layers, thus lowering costs. (See also...) Figure 2 , Figure 2 This is a connection diagram of a commonly used TRD (Triple Row Driving) pixel driving circuit. In a TRD display panel, adjacent rows are connected by the same data line to pixels of different colors. Figure 3 , Figure 3 This is a waveform control diagram of a commonly used pixel driving circuit, specifically for... Figure 1 The traditional pixel arrangement only allows writing data to pixels row by row (each row's gate is opened sequentially, and the data corresponding to the RGBRGB pixels is written sequentially in RGBRGB). However, in DLG mode, the gates of two pixels of different colors are opened simultaneously (every two rows of gates are opened sequentially, and the data written to the corresponding RGBRGB sub-pixels will be RRGGBB, which will cause abnormal screen display). The same data will be filled in, making it impossible to display RGB monochrome images, and the display panel will not be able to display colors normally. Therefore, how to use DLG technology under TRD pixels has become an urgent problem to be solved.

[0041] In this embodiment, a pixel unit 200 is obtained by arranging red pixels R, green pixels G, and blue pixels B in a preset arrangement. At the same time, the control terminals of each control circuit 10 of the driving circuit 100 are connected to the gate driving line group Q. The first terminal of the control circuit 10 is connected to the target data line D, and the second terminal of the control circuit 10 is connected to the adjacent red pixel group 21, or the adjacent green pixel group 22, or the adjacent blue pixel group 23. Thus, the control terminals of the control circuit 10 are connected to the adjacent and simultaneously driven first gate driving line G1 and second gate driving line G2, thereby realizing DLG technology. Furthermore, based on the connection between the control terminal of the control circuit 10 and the second terminal and the first terminal of the control circuit 10, and the fact that the target data line D is used to write the same data to the red pixel group R, or the green pixel group G, or the blue pixel group B, it is possible to simultaneously control the red pixel group R, or the green pixel group G, or the blue pixel group B for display via the first gate driving line G1 and the second gate driving line G2. Here, the target data line D refers to a data line designed between the red pixel group 21, or the green pixel group 22, or the blue pixel group 23, such as... Figure 1 The example uses one red pixel group 21, one green pixel group 22, and one blue pixel group 23 to demonstrate how normal pixel display using DLG technology is achieved under the TRD design.

[0042] This embodiment proposes a pixel driving circuit and a display panel. This application optimizes the pixel driving circuit, resulting in a pixel driving circuit comprising: red pixels, green pixels, and blue pixels arranged sequentially in a preset pattern within a pixel unit, and multiple sets of control circuits in the driving circuit. Since the application of DLG technology in commonly used TRD pixel driving circuits results in two different color pixels displaying the same grayscale, thus preventing the display of RGB monochrome images and causing the display panel to fail to display colors correctly, this application combines the above modules. The control terminal of the control circuit is connected to the gate driving line group; the first terminal of the control circuit is connected to the target data line; and the second terminal of the control circuit is connected to the adjacent red pixel group, or adjacent green pixel group, or adjacent blue pixel group. Simultaneously, the target data line is used to write the same data to the red pixel group, or green pixel group, or blue pixel group. Then, by simultaneously controlling the red pixel group, or green pixel group, or blue pixel group for display through the first gate driving line and the second gate driving line, the first gate driving line and the second gate driving line simultaneously drive the same pixels to write system data, thus realizing the use of DLG technology under TRD pixels.

[0043] Furthermore, referring to Figure 4 , Figure 4 This is a schematic diagram of the circuit connection for pixel arrangement in the pixel driving circuit of this application.

[0044] In some feasible embodiments, when the preset arrangement is that the red pixel R, the green pixel G, and the blue pixel B are arranged sequentially in the rows of the pixel unit 200, and the red pixel R, the green pixel G, and the blue pixel B are arranged sequentially in the columns of the pixel unit 200, the adjacent red pixel group 21 consists of a first red pixel and a second red pixel that are diagonally adjacent, the adjacent green pixel group 22 consists of a first green pixel and a second green pixel that are diagonally adjacent, and the adjacent blue pixel group 23 consists of a first blue pixel and a second blue pixel that are diagonally adjacent.

[0045] Furthermore, in some feasible embodiments, the control circuit 10 includes a first thin-film transistor T1 and a second thin-film transistor T2;

[0046] The control terminal of the first thin-film transistor T1 is connected to the first gate driving line G1, the control terminal of the second thin-film transistor T2 is connected to the second gate driving line G2, and the target data line D is connected to the first terminal of the first thin-film transistor T1 and the first terminal of the second thin-film transistor T2 respectively.

[0047] When the second terminal of the first thin-film transistor T1 is connected to the first red pixel, the second terminal of the second thin-film transistor T2 is connected to the second red pixel; or, when the second terminal of the first thin-film transistor T1 is connected to the first green pixel, the second terminal of the second thin-film transistor T2 is connected to the second green pixel; or, when the second terminal of the first thin-film transistor T1 is connected to the first blue pixel, the second terminal of the second thin-film transistor T2 is connected to the second blue pixel.

[0048] In this embodiment, the design can implement DLG technology based on improvements in pixel arrangement. By arranging red pixels R, green pixels G, and blue pixels B sequentially in rows and columns of pixel unit 200, the same pixels in the entire pixel unit 200 are arranged diagonally to the left, thus ensuring the existence of pixel groups of the same color diagonally. The connection between the first thin-film transistor T1 and the second thin-film transistor T2 in the control circuit 10 controls these same pixel groups. Referring to the control circuit 10, there are multiple control circuits 10 composed of two thin-film transistors in the entire pixel unit 200, ensuring that G1 and G2 simultaneously drive D2 to sequentially write green pixels G, red pixels R, and blue pixels B. (Refer to...) Figure 6 , Figure 6This is a waveform control diagram of pixel arrangement in the pixel driving circuit of this application. By controlling G1 and G2, G3 and G4 to be turned on simultaneously, Data (D1-Dn) is written to the green pixel G, the red pixel R and the blue pixel B in sequence, thereby realizing the use of DLG technology under TRD pixels.

[0049] For example, refer to Figure 7 , Figure 7 This is another circuit connection diagram of pixel arrangement in the pixel driving circuit of this application, based on Figure 4 The entire arrangement is designed so that the rows of pixel unit 200 are arranged sequentially with red pixels R, blue pixels B, and green pixels G, and the columns of pixel unit 200 are arranged sequentially with red pixels R, green pixels G, and blue pixels B. This means that identical pixels within the entire pixel unit 200 are arranged diagonally to the right, thus ensuring that there are groups of pixels of the same color diagonally. In other words, the arrangement can achieve diagonal identical pixels in two ways: either the rows are arranged sequentially with red pixels R, blue pixels B, and green pixels G, or the rows are arranged sequentially with red pixels R, green pixels G, and blue pixels B. (Refer to...) Figure 8 , Figure 8 This is another waveform control diagram of pixel arrangement in the pixel driving circuit of this application. By controlling G1 and G0, G3 and G2 to be turned on at the same time, Data (D1-Dn) is written to the green pixel G, the red pixel R and the blue pixel B in sequence, thereby realizing the use of DLG technology under TRD pixels.

[0050] It should be noted that the transistors used in all embodiments of this application can be TFTs (Thin Film Transistors), field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source, and the other is called the drain. The characteristics of each port of the first thin film transistor T1 can be determined according to G, D, and S, where G is the gate of T1, S is the source of T1, and D is the drain of T1. The characteristics of the other transistors can be determined according to... Figure 4 The configuration of the transistors is defined as follows: the middle terminal of each transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the transistors used in this application embodiment may include both P-type and N-type transistors. P-type transistors conduct when the gate is low and are cut off when the gate is high, while N-type transistors conduct when the gate is high and are cut off when the gate is low. The conduction modes of the first gate drive voltage Vgate and the second gate drive voltage Share_Vgate differ for N-type and P-type transistors, and the corresponding control methods also differ. The specific control depends on the actual transistor and is not limited here.

[0051] Furthermore, in some feasible embodiments, the first thin-film transistor T1 to the third thin-film transistor T3 can be low-temperature polycrystalline silicon thin-film transistors, oxide semiconductor thin-film transistors, or amorphous silicon thin-film transistors. The transistors in the driving circuit provided in this application are all made of the same material, thereby avoiding the impact of differences between transistors of different materials on the driving circuit.

[0052] Furthermore, in some feasible embodiments, reference is made to Figure 9 , Figure 9 This is a circuit connection diagram of a switch in the pixel driving circuit of this application. When the preset arrangement is that the red pixel R, or the green pixel G, or the blue pixel B are arranged in rows of the pixel unit 200, and the red pixel R, the green pixel G, and the blue pixel B are arranged in columns of the pixel unit 200 in sequence, the adjacent red pixel group 21 is a horizontally adjacent third red pixel and fourth red pixel, the adjacent green pixel group 22 is a horizontally adjacent third green pixel and fourth green pixel, and the adjacent blue pixel group 23 is a horizontally adjacent third blue pixel and fourth blue pixel.

[0053] In some feasible embodiments, the control circuit 10 includes a third thin-film transistor T3 and a fourth thin-film transistor T4;

[0054] The control terminal of the third thin-film transistor T3 is connected to the first gate driving line G1, the control terminal of the fourth thin-film transistor T4 is connected to the second gate driving line G2, and the target data line D is connected to the first terminal of the third thin-film transistor T3 and the first terminal of the fourth thin-film transistor T4 respectively.

[0055] When the second terminal of the third thin-film transistor T3 is connected to the third red pixel, the second terminal of the fourth thin-film transistor T4 is connected to the fourth red pixel; or, when the second terminal of the third thin-film transistor T3 is connected to the third green pixel, the second terminal of the fourth thin-film transistor T4 is connected to the fourth green pixel; or, when the second terminal of the third thin-film transistor T3 is connected to the third blue pixel, the second terminal of the fourth thin-film transistor T4 is connected to the fourth blue pixel.

[0056] In this embodiment, the design can implement DLG technology based on improvements to the connection of the control circuit 10. By designing a preset arrangement where red pixels R, green pixels G, or blue pixels B are arranged in rows of pixel units 200, and red pixels R, green pixels G, and blue pixels B are arranged sequentially in columns of pixel units 200, the same pixels in the entire pixel unit 200 are arranged in rows. This ensures the existence of pixel groups of the same color horizontally, and thus, the same pixel driving is achieved through the connection of the control circuit 10. In other words, the pixel arrangement uses a TFT cross-row pixel access method, thus forming a column on the data line (refer to...). Figure 9 Taking D2 as an example, the sub-pixel color solved from top to bottom is RRBBBGGRRBBBGG, meaning that two adjacent sub-pixels have the same color, fulfilling the requirements of DLG driving. Thus, when using DLG driving, the gate is opened every two rows, and the corresponding RRBBBGGRRBBBGG sub-pixels will have their corresponding RRBBBGGRRBBBGG data written, allowing for normal monochrome display. Furthermore, based on the control circuit 10, DLG technology is implemented under TRD pixels.

[0057] Furthermore, when the target data line D is the first data line, the red pixel group 21, the green pixel group 22, and the blue pixel group 22 are odd-numbered rows of pixels.

[0058] In some feasible embodiments, when the target data line D is the second data line, the red pixel group 21, the green pixel group 22 and the blue pixel group 23 are even-numbered rows of pixels.

[0059] In this embodiment, since pixel unit 200 consists of a group of pixels with the same color in the horizontal direction, it needs to be controlled differently for the first data line and the second data line. The first data line is controlled by an odd-numbered data line, and the second by an even-numbered data line. One is the uplink drive in the DLG, and the other is the downlink drive in the DLG. (See reference...) Figure 9 D2 and D3 are connected to thin-film transistors in two different ways, and can be driven specifically based on pixel unit 200, thereby realizing DLG.

[0060] Furthermore, in some feasible embodiments, reference is made to Figure 10 , Figure 10 This is another circuit connection diagram of the switch in the pixel driving circuit of this application. The target data line is connected to the red pixel group 21, the blue pixel group 22 and the green pixel group 23 in sequence through multiple control circuits.

[0061] In some feasible embodiments, when the number of rows of pixel units 200 is odd, a pseudo gate drive line G0 is added to the first or last row of the pixel units 200.

[0062] In this embodiment, the entire target data line is sequentially connected to the red pixel group 21, the blue pixel group 22, and the green pixel group 23 via multiple control circuits. This allows the timing of data writing to the target data line to be controlled in the order of red pixel group 21, blue pixel group 22, and green pixel group 23. This enables unified control of the data line's writing timing or separate control of the data line's writing timing, thereby improving [the system's performance]. Figure 9 The thin-film transistors in the circuit can be connected to achieve DLG.

[0063] For example, such as Figure 10 and Figure 7 As shown, when the number of pixel rows is odd, taking a sub-pixel in D2 data as an example, the first row of pixels does not have paired Gates for driving. Therefore, not all pixels in the first row can be illuminated. Figure 7 and Figure 10 A pair of G0 and G1 gates is added before the first G1 gate to ensure that every two gates in a row are paired, thus enabling normal driving of the first row. Furthermore, by controlling the driving timing of the first two rows, both G0 and G1 gates are enabled, allowing the first row's R pixels to receive R data. Since the first row's G0 gate is outside the display area, it does not affect the display. Similarly, a Gn+1 gate can be added after the last row, enabling Gn and Gn+1 to drive B data in pairs. This ensures the accuracy of DLG control.

[0064] Furthermore, embodiments of this application also propose a display panel, which includes at least an array substrate, the array substrate including the pixel arrangement structure described above. The display panel may further include the pixel arrangement structure described above, see reference... Figure 5 , Figure 5 This is a schematic diagram of the structure of the display panel involved in the embodiments of this application.

[0065] like Figure 5As shown, the display panel may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. The memory 1005 may also optionally be a storage device independent of the aforementioned processor 1001.

[0066] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on the display panel and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0067] like Figure 5 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and computer programs.

[0068] exist Figure 5 In the display panel shown, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in this embodiment can be set in the display panel, and the display panel calls the computer program stored in the memory 1005 through the processor 1001 and controls the above-mentioned pixel driving circuit.

[0069] The various embodiments of the display panel in this application can be referred to the various embodiments of the pixel driving circuit in this application, and will not be repeated here.

[0070] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0071] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0073] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes a pixel unit and a driving circuit. The pixel unit includes red pixels, green pixels and blue pixels arranged in a preset arrangement. The driving circuit includes multiple sets of control circuits. The control terminal of the control circuit is connected to the gate drive line group, the first terminal of the control circuit is connected to the target data line, and the second terminal of the control circuit is connected to the adjacent red pixel group, or the adjacent green pixel group, or the adjacent blue pixel group. The gate driving line group includes adjacent and simultaneously driven first and second gate driving lines. The target data line is used to write the same data to the red pixel group, or the green pixel group, or the blue pixel group, and in the same frame, simultaneously control the red pixel group, or the green pixel group, or the blue pixel group for display via the first and second gate driving lines. Specifically, when the preset arrangement is that the red pixels, or the green pixels, or the blue pixels are arranged in rows of the pixel units, and the columns of the pixel units are arranged sequentially as red pixels, green pixels, and blue pixels, adjacent red pixel groups are horizontally adjacent third and fourth red pixels, adjacent green pixel groups are horizontally adjacent third and fourth green pixels, and adjacent blue pixel groups are... The control circuit for the horizontally adjacent third and fourth blue pixels includes a third thin-film transistor (TFT) and a fourth TFT. The control terminal of the third TFT is connected to the first gate driving line, and the control terminal of the fourth TFT is connected to the second gate driving line. The target data line is connected to the first terminal of the third TFT and the first terminal of the fourth TFT, respectively. When the second terminal of the third TFT is connected to the third red pixel, the second terminal of the fourth TFT is also connected to the fourth red pixel; or, when the second terminal of the third TFT is connected to the third green pixel, the second terminal of the fourth TFT is also connected to the fourth green pixel; or, when the second terminal of the third TFT is connected to the third blue pixel, the second terminal of the fourth TFT is also connected to the fourth blue pixel.

2. The pixel driving circuit as described in claim 1, characterized in that, When the preset arrangement is that the red pixels, green pixels, and blue pixels are arranged sequentially in rows of the pixel units, and the red pixels, green pixels, and blue pixels are arranged sequentially in columns of the pixel units, the adjacent red pixel group is a first red pixel and a second red pixel that are diagonally adjacent, the adjacent green pixel group is a first green pixel and a second green pixel that are diagonally adjacent, and the adjacent blue pixel group is a first blue pixel and a second blue pixel that are diagonally adjacent.

3. The pixel driving circuit as described in claim 2, characterized in that, The control circuit includes a first thin-film transistor and a second thin-film transistor. The control terminal of the first thin-film transistor is connected to the first gate driving line, the control terminal of the second thin-film transistor is connected to the second gate driving line, and the target data line is connected to the first terminal of the first thin-film transistor and the first terminal of the second thin-film transistor, respectively. When the second terminal of the first thin-film transistor is connected to the first red pixel, the second terminal of the second thin-film transistor is connected to the second red pixel; or, when the second terminal of the first thin-film transistor is connected to the first green pixel, the second terminal of the second thin-film transistor is connected to the second green pixel; or, when the second terminal of the first thin-film transistor is connected to the first blue pixel, the second terminal of the second thin-film transistor is connected to the second blue pixel.

4. The pixel driving circuit as described in claim 1, characterized in that, When the target data line is the first data line, the red pixel group, the green pixel group, and the blue pixel group are odd-numbered rows of pixels.

5. The pixel driving circuit as described in claim 1, characterized in that, When the target data line is the second data line, the red pixel group, the green pixel group, and the blue pixel group are even-numbered rows of pixels.

6. The pixel driving circuit as described in any one of claims 2 or 3, characterized in that, The target data line is connected sequentially to the red pixel group, the blue pixel group, and the green pixel group through multiple control circuits.

7. The pixel driving circuit as described in any one of claims 2 or 3, characterized in that, When the number of pixel units is odd, a pseudo gate drive line is added to the first or last row of the pixel unit.

8. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a pixel driving circuit as described in any one of claims 1-7.

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