Method of forming a semiconductor structure

Abstract

This disclosure provides a method for forming a semiconductor structure, including forming a dielectric stack on a substrate; forming a mask layer on the dielectric stack; forming a first opening in the mask layer to expose the dielectric stack; forming a second opening in the dielectric stack to expose the substrate, wherein the second opening communicates with the first opening; forming a fill layer in the first and second openings; removing the mask layer and the fill layer to expose the sidewalls of the dielectric stack; and forming a capacitor in the second opening of the dielectric stack. Here, the profile of the capacitor is not adversely affected, and thus the structural robustness of the capacitor can be improved.

Description

Technical Field

[0001] This disclosure relates to a method for forming semiconductor structures. Background Technology

[0002] Capacitors can be used in a wide variety of semiconductor circuits. For example, capacitors can be used in memory circuits for dynamic random access memory (DRAM) or any other type of memory circuit. DRAM memory circuits are manufactured by replicating millions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. A DRAM cell is an addressable location that can store bits of data (binary bits). In a common form, a DRAM cell may include two circuit elements: a storage capacitor and an access field-effect transistor (FET). Summary of the Invention

[0003] The technical state disclosed herein is a method for forming a semiconductor structure.

[0004] According to some embodiments of this disclosure, a method of forming a semiconductor structure includes forming a dielectric stack on a substrate; forming a mask layer on the dielectric stack; forming a first opening in the mask layer to expose the dielectric stack; forming a second opening in the dielectric stack to expose a substrate, wherein the second opening communicates with the first opening; forming a fill layer in the first and second openings; removing the mask layer and the fill layer to expose the sidewalls of the dielectric stack; and forming a capacitor in the second opening of the dielectric stack.

[0005] In some embodiments disclosed herein, a filler layer is formed such that the filler layer contacts the mask layer and the substrate.

[0006] In some embodiments disclosed herein, the masking layer and the filler layer comprise the same material.

[0007] In some embodiments disclosed herein, the removal of the mask layer and the fill layer are performed simultaneously using an etching process.

[0008] In some embodiments disclosed herein, the method of forming a semiconductor structure further includes performing a cleaning process before removing the mask layer and the fill layer.

[0009] In some embodiments disclosed herein, forming a dielectric stack further includes forming a first sacrificial layer on a substrate and forming a second sacrificial layer on the first sacrificial layer.

[0010] In some embodiments disclosed herein, a filler layer is formed such that the filler layer covers the sidewalls of the first sacrificial layer and the sidewalls of the second sacrificial layer.

[0011] In some embodiments disclosed herein, forming a dielectric stack further includes forming a first support layer on a substrate, forming a second support layer on a first sacrificial layer, and forming a third support layer on a second sacrificial layer.

[0012] In some embodiments disclosed herein, forming a capacitor in a second opening in a dielectric stack includes forming a lower electrode layer along the sidewalls of the dielectric stack. A portion of a third support layer is removed to form a first aperture exposing a second sacrificial layer. The second sacrificial layer is removed from the first aperture. A high-dielectric-constant dielectric layer is formed along the sidewalls of the lower electrode layer. An upper electrode layer is formed along the sidewalls of the high-dielectric-constant dielectric layer.

[0013] In some embodiments disclosed herein, the method of forming a semiconductor structure further includes forming a semiconductor layer located between the first support layer and the second support layer and between the second support layer and the third support layer.

[0014] In some embodiments disclosed herein, forming a capacitor in a second opening in the dielectric stack further includes removing a portion of the second support layer to form a second aperture exposing the first sacrificial layer. The first sacrificial layer is removed from the second aperture before forming a high-dielectric-constant dielectric layer.

[0015] In some embodiments disclosed herein, forming a capacitor in a second opening in the dielectric stack further includes removing a horizontal portion of the lower electrode layer to expose the substrate before removing the first sacrificial layer.

[0016] The technical state disclosed herein is a method for forming a semiconductor structure.

[0017] According to some embodiments of this disclosure, a method for forming a semiconductor structure includes forming a dielectric stack on a substrate, wherein forming the dielectric stack includes sequentially forming a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer. A mask layer is formed on the dielectric stack. A first opening is formed in the mask layer to expose the third support layer of the dielectric stack. A second opening is formed in the dielectric stack to expose the substrate, wherein the second opening communicates with the first opening. A fill layer is formed in the first and second openings, and a native oxide layer is formed on the top surface of the fill layer and the top surface of the mask layer. A cleaning process is performed to remove the native oxide layer. An etching process is performed to remove the mask layer and the fill layer. A capacitor is formed in the second opening of the dielectric stack.

[0018] In some embodiments disclosed herein, the etching process is a wet etching process.

[0019] In some embodiments disclosed herein, the cleaning process and the etching process are performed by using different etching solutions.

[0020] In some embodiments disclosed herein, the cleaning process is performed by using an acidic etching solution, and the etching process is performed by using an alkaline etching solution.

[0021] In some embodiments disclosed herein, the first sacrificial layer and the second sacrificial layer remain unchanged when the cleaning process is performed.

[0022] In some embodiments disclosed herein, the filler layer is formed such that it is surrounded by a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer.

[0023] In some embodiments disclosed herein, a filler layer is formed such that the filler layer extends from the substrate to the mask layer.

[0024] In some embodiments disclosed herein, the masking layer and the filler layer are polysilicon layers.

[0025] According to the embodiments disclosed above, since a filler layer is formed in the first opening of the mask layer and the second opening of the dielectric stack, the filler layer can protect the dielectric structure during the etching process (i.e., the etching process to remove the mask layer), so that the outline of the second opening is not damaged. In this way, the outline of the capacitor is not adversely affected, and thus the structural robustness of the capacitor can be improved.

[0026] It should be understood that the foregoing general description and the following detailed description are merely examples and are intended to provide further explanation of this disclosure. Attached Figure Description

[0027] To make the above and other objects, features, advantages and embodiments disclosed herein more apparent and understandable, the accompanying drawings are described below:

[0028] Figures 1 to 15 Cross-sectional views are shown of various intermediate stages of a method for forming a semiconductor structure according to some embodiments of this disclosure.

[0029] Figure 16 Draw Figure 15 A magnified view of a portion of the image.

[0030] Figure 17 yes Figure 16 The top view. Detailed Implementation

[0031] The following describes several embodiments of this disclosure with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential and therefore should not be used to limit this disclosure. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner. Furthermore, for the reader's convenience, the dimensions of the components in the drawings are not drawn to scale.

[0032] As used in this disclosure, “about,” “approximately,” or “substantially” generally refers to within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the meaning of the terms “about,” “approximately,” or “substantially” can be inferred.

[0033] Furthermore, for ease of description, spatially relative terms such as "below," "under," "below," "above," "above," and the like may be used in some embodiments of this disclosure to describe the relationship between one element or feature as depicted in the figures and other elements or features(s). These spatially relative terms are intended to cover different orientations of elements in use or operation, in addition to those described in the figures. Elements may be additionally positioned (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used in some embodiments of this disclosure are interpreted accordingly.

[0034] Figures 1 to 15 Cross-sectional views are shown of intermediate stages in a method for forming a semiconductor structure according to some embodiments of this disclosure. (See also...) Figure 1 A dielectric stack DS is formed on the substrate 110. Specifically, forming the dielectric stack DS on the substrate 110 includes forming a first support layer 120 on the substrate 110, forming a first sacrificial layer 130 on the first support layer 120, forming a second support layer 140 on the first sacrificial layer 130, forming a second sacrificial layer 150 on the second support layer 140, and forming a third support layer 160 on the second sacrificial layer 150. In other words, the dielectric stack DS includes the first support layer 120, the first sacrificial layer 130, the second support layer 140, the second sacrificial layer 150, and the third support layer 160 formed sequentially.

[0035] In some embodiments, substrate 110 includes metal lines 112 that contact a first support layer 120 of the dielectric stack DS. The metal lines 112 may comprise tungsten (W) or other suitable metals. In some embodiments, substrate 110 also includes interconnect structures having contacts, transistors, or other similar components. Therefore, capacitors subsequently formed in the dielectric stack DS (e.g., Figure 14 and Figure 15 The capacitor Ca in the substrate 110 is connected to other components (e.g., transistors).

[0036] In some embodiments, the first support layer 120, the second support layer 140, and the third support layer 160 comprise nitrides, such as silicon nitride. In some embodiments, the first sacrificial layer 130 and the second sacrificial layer 150 comprise oxides. The first sacrificial layer 130 and the second sacrificial layer 150 may be made of different materials. When the first sacrificial layer 130 is formed, a dopant is doped into the first sacrificial layer 130, the aforementioned dopant comprising boron, phosphorus, or a combination thereof. For example, the first sacrificial layer 130 is made of boro-phospho-silicate-glass (BPSG), BPSG being silicon oxide doped with boron and phosphorus. In some embodiments, the second sacrificial layer 150 is made of silane (SiH4) oxide or other suitable oxide materials.

[0037] After forming a dielectric stack DS on substrate 110, a masking layer 170 is formed on the dielectric stack DS. The masking layer 170 contacts a third support layer 160 of the dielectric stack DS. The masking layer 170 is formed such that the third support layer 160 is located between the masking layer 170 and the second sacrificial layer 150. In some embodiments, the masking layer 170 comprises a semiconductor material, such as polysilicon.

[0038] After forming a mask layer 170 on the dielectric stack DS, a patterned mask 180 is formed on the mask layer 170. Forming the patterned mask 180 may involve forming a mask structure on the mask layer 170 and then patterning the aforementioned mask structure to expose a portion of the mask layer 170. In some embodiments, the patterned mask 180 and the mask layer 170 comprise different materials. The patterned mask 180 may comprise an oxide, such as tetraethoxysilane (TEOS), while the mask layer 170 comprises polysilicon.

[0039] See Figure 2 A first opening 190 is formed in the mask layer 170 to expose the third support layer 160 of the dielectric stack DS. The mask layer 170 is etched using a patterned mask 180 as an etch mask. In some embodiments, etching the mask layer 170 to form the first opening 190 is performed by a dry etching process.

[0040] See Figure 2 and Figure 3 After forming the first opening 190, a second opening 200 is formed in the dielectric stack DS to expose the substrate 110, wherein each of the second openings 200 is in communication (e.g., fluid communication) with the corresponding first opening 190. In other words, the dielectric stack DS is etched along the first opening 190 to form the second opening 200 in the dielectric stack DS. The second opening 200 may expose the sidewall DS1 of the dielectric stack DS. In some embodiments, etching the dielectric stack DS to form the second opening 200 is performed by a dry etching process. For example, a dry etchant, such as hydrogen (H2) and nitrogen (N2), can be selected for the dry etching process. In some embodiments, the top portion 152 of the second sacrificial layer 150 closest to the third support layer 160 of the dielectric stack DS has the minimum width due to the etching process performed to form the second opening 200. In other words, a portion of each of the second openings 200, the aforementioned portion, has the maximum width adjacent to the top portion 152 of the second sacrificial layer 150. In some implementations, the patterned mask 180 is removed before the second opening 200 is formed.

[0041] See Figure 3 and Figure 4 After forming the second opening 200 in the dielectric stack DS, a filling layer 210 is formed in the first opening 190 and the second opening 200, and a native oxide layer 220 is formed over the top surface 212 of the filling layer 210 and the top surface 172 of the masking layer 170. When the filling layer 210 is exposed to air under ambient conditions, the native oxide layer 220 is formed on the top surface 212 of the filling layer 210 (i.e., the exposed surface of the filling layer 210). Similarly, when the masking layer 170 is exposed to air under ambient conditions, the native oxide layer 220 is further formed on the top surface 172 of the masking layer 170 (i.e., the exposed surface of the masking layer 170). Therefore, the native oxide layer 220 is formed over both the top surface 172 of the masking layer 170 and the top surface 212 of the filling layer 210. In some embodiments, the native oxide layer 220 is a thin film and is made of silicon dioxide (SiO2).

[0042] In some embodiments, the fill layer 210 contacts the mask layer 170, the dielectric stack DS, and the substrate 110. Specifically, the fill layer 210 contacts the sidewalls of the mask layer 170 and the metal lines 112 of the substrate 110. The fill layer 210 can extend from the metal lines 112 of the substrate 110 to the mask layer 170. In some embodiments, the fill layer 210 contacts and is surrounded by the first support layer 120, the first sacrificial layer 130, the second support layer 140, the second sacrificial layer 150, and the third support layer 160 of the dielectric stack DS. Because the fill layer 210 covers the sidewalls 133 of the first sacrificial layer 130 and the second sacrificial layer 150, the fill layer 210 can prevent the first sacrificial layer 130 and the second sacrificial layer 150 from being etched in subsequent etching processes (e.g., ...). Figure 5 Cleaning process 230 and Figure 6 The etching process 240 in the dielectric layer is damaged during this process. In some embodiments, the fill layer 210 has the same material as the mask layer 170 to achieve a high fill rate in the second opening 200 of the dielectric stack DS. The fill layer 210 and the mask layer 170 may comprise polysilicon, semiconductor materials, or other suitable materials. For example, since both the fill layer 210 and the mask layer 170 are polysilicon layers, there is no interface between the fill layer 210 and the mask layer 170.

[0043] See Figure 4 and Figure 5 A cleaning process 230 is performed to remove the native oxide layer 220, exposing the fill layer 210 and the mask layer 170. Since the first sacrificial layer 130 and the second sacrificial layer 150 are covered by the fill layer 210, they remain unchanged during the cleaning process 230. If the fill layer 210 does not cover the sidewalls 133 of the first sacrificial layer 130 and the sidewalls 153 of the second sacrificial layer 150, the first sacrificial layer 130 and the second sacrificial layer 150 will be damaged during the cleaning process 230, adversely affecting the capacitors formed in the dielectric stack DS (e.g., in...). Figure 15 The performance of the capacitor (Ca) in the middle.

[0044] In some embodiments, cleaning process 230 is performed by using an acidic etching solution. For example, the acidic etching solution of cleaning process 230 contains a fluoride-based solution, such as hydrofluoric acid (HF). The chemical reaction is performed by reacting the native oxide layer 220 (e.g., SiO2) with a fluoride-based (F-) solution to remove the native oxide layer 220. The chemical reaction is illustrated by the following chemical equation (I).

[0045] SiO2+F - →SiF6 2- (I).

[0046] See Figure 5 and Figure 6 An etching process 240 is performed to remove the mask layer 170 and the fill layer 210, exposing the sidewalls DS1 (i.e., the sidewalls of the first support layer 120, the first sacrificial layer 130, the second support layer 140, the second sacrificial layer 150, and the third support layer 160). Furthermore, the etching process 240 is performed to remove the mask layer 170 and the fill layer 210, causing the second opening 200 of the dielectric stack DS to be reformed. The metal lines 112 of the substrate 110 are exposed through the second opening 200.

[0047] In some embodiments, the removal of mask layer 170 and fill layer 210 is performed simultaneously using a single (one-pass) etch process. Since mask layer 170 and fill layer 210 comprise the same material (e.g., polysilicon), they can be removed simultaneously during etch process 240. In some embodiments, etch process 240 may include, for example, an anisotropic etch process using an etch solution that is selectively etchable on mask layer 170 and fill layer 210 but substantially does not etch the dielectric stack DS. In other words, the etch solution of etch process 240 has a high selective etch rate on mask layer 170 and fill layer 210, resulting in near-zero etch amounts on the support layers (i.e., first support layer 120, second support layer 140, and third support layer 160) and sacrificial layers (i.e., first sacrificial layer 130 and second sacrificial layer 150). By employing the methods described above (e.g., forming a fill layer 210, followed by cleaning process 230 and etching process 240), the first sacrificial layer 130 and the second sacrificial layer 150 are not excessively damaged, and therefore the profile of the second opening 200 of the dielectric stack DS is not excessively expanded. In this way, the profile of the capacitor formed in subsequent processes is not adversely affected, and the capacitor structure can be robust (e.g., preventing short circuits in the capacitor). Furthermore, the critical width dimension of the second opening 200 of the dielectric stack DS (i.e., the maximum width of the dielectric stack DS near the top portion 152 of the second sacrificial layer 150 minus the width approximately 100 nanometers downward from the aforementioned maximum width) can be reduced, wherein the critical width dimension of the second opening 200 is in the range of approximately 1.5 nanometers to approximately 2 nanometers. If a fill layer 210 is not formed in the dielectric stack DS before performing cleaning process 230 and etching process 240, the critical dimension of the width of the second opening 200 will be in the range of about 4 nanometers to about 5 nanometers, thereby adversely affecting the profile of the capacitor formed in subsequent processes (e.g., the capacitor structure is unstable, resulting in a short circuit).

[0048] In some embodiments, cleaning process 230 and etching process 240 are performed using a wet etching process. Cleaning process 230 and etching process 240 can be performed by using different etching solutions. For example, cleaning process 230 is performed using an acidic etching solution, and etching process 240 is performed using an alkaline etching solution. In some embodiments, the etching solution of etching process 240 comprises a hydroxide-based solution, such as ammonium hydroxide (NH4OH). The chemical reaction is performed by reacting the mask layer 170 and the filler layer 210 (e.g., silicon (Si)) with hydroxide-based (OH) solutions. - The solution reaction removes the masking layer 170 and the filler layer 210. The chemical reaction is illustrated by the following chemical equation (II).

[0049] Si + OH- → SiO3 2- +H2(II).

[0050] See Figures 7 to 15 A capacitor Ca is formed in the second opening 200 of the dielectric stack DS. Further, see [link to documentation]. Figure 7 A lower electrode layer 250 is formed in the second opening 200 of the dielectric stack DS. The lower electrode layer 250 may include a horizontal portion 252 and a vertical portion 254 connected to the horizontal portion 252, wherein the horizontal portion 252 contacts the top surface of the dielectric stack DS and the metal line 112 of the substrate 110, and the vertical portion 254 runs along the sidewall DS1 of the dielectric stack DS. In some embodiments, the lower electrode layer 250 comprises titanium nitride (TiN) or other suitable conductive material.

[0051] See Figure 8 A portion of the third support layer 160 is removed to form a first hole H1 exposing the second sacrificial layer 150. In some embodiments, a portion of the lower electrode layer 250 and a portion of the second sacrificial layer 150 are removed. This results in the second sacrificial layer 150 having a stepped profile (i.e., an exposed top surface and exposed sidewalls perpendicular to the exposed top surface). In some embodiments, the removal of a portion of the third support layer 160 to form the first hole H1 is performed by a dry etching process.

[0052] See Figure 8 and Figure 9 The second sacrificial layer 150 of the dielectric stack DS is removed from the first hole H1. In some embodiments, an etching process is performed to remove the second sacrificial layer 150. For example, the second sacrificial layer 150 is removed by using a wet etching process, and the etching solution of the wet etching process contains a fluoride-based solution, such as hydrofluoric acid (HF). After the second sacrificial layer 150 is removed, a space S1 is formed between the second support layer 140 and the third support layer 160.

[0053] See Figure 10 A second hole H2 is formed in the second support layer 140 to expose a portion of the first sacrificial layer 130. In some embodiments, the second support layer 140 is etched to form the second hole H2 by a dry etching process. See also Figure 10 and Figure 11 After forming the second hole H2 in the second support layer 140, the horizontal portion 252 of the lower electrode layer 250 is removed, leaving the vertical portion 254 of the lower electrode layer 250. This exposes the top surface of the third support layer 160 and the metal lines 112 of the substrate 110. In some embodiments, the horizontal portion 252 of the lower electrode layer 250 is etched using a dry etching process.

[0054] See Figure 11 and Figure 12 The first sacrificial layer 130 of the dielectric stack DS is removed through the second hole H2. In some embodiments, an etching process is performed to remove the first sacrificial layer 130. For example, the first sacrificial layer 130 is removed by using a wet etching process, and the etching solution of the wet etching process contains a fluoride-based solution, such as hydrofluoric acid (HF). After the first sacrificial layer 130 is removed, a space S2 is formed between the second support layer 140 and the first support layer 120, and the space S1 and space S2 are connected through the second hole H2 in the second support layer 140. The first support layer 120, the second support layer 140, and the third support layer 160 are connected through the lower electrode layer 250.

[0055] See Figure 13 A high-k dielectric layer 260 is formed along the sidewall of the lower electrode layer 250. The high-k dielectric layer 260 can be formed along the sidewall of the lower electrode layer 250 in spaces S1 and S2. The high-k dielectric layer 260 can also be formed along the sidewall of the lower electrode layer 250 in the second opening 200 of the second dielectric stack DS. Furthermore, the high-k dielectric layer 260 can be formed along the sidewall, top and bottom surfaces of the second support layer 140, the sidewall, top and bottom surfaces of the third support layer 160, and the top surface of the first support layer 120. In some embodiments, the high-k dielectric layer 260 is formed on the metal lines 112 of the substrate 110, and the high-k dielectric layer 260 contacts the metal lines 112 of the substrate 110.

[0056] In some embodiments, the high dielectric constant dielectric layer 260 comprises hafnium oxide (HfO). In various examples, the high dielectric constant dielectric layer 260 comprises a metal oxide (e.g., HfSiO2, ZnO, ZrO2, Ta2O5, Al2O3, or the like), a metal nitride, or a combination thereof.

[0057] See Figure 14An upper electrode layer 270 is formed along the high-dielectric-constant dielectric layer 260. The upper electrode layer 270 may be formed along the sidewalls of the high-dielectric-constant dielectric layer 260 in spaces S1 and S2. The upper electrode layer 270 may also be formed along the sidewalls of the high-dielectric-constant dielectric layer 260 in the second opening 200 of the dielectric stack DS. In some embodiments, the upper electrode layer 270 is located above the horizontal surface of the high-dielectric-constant dielectric layer 260. The upper electrode layer 270 may comprise titanium nitride (TiN) or other suitable conductive materials. In some embodiments, the upper electrode layer 270 and the lower electrode layer 250 comprise the same material.

[0058] See Figure 14 and Figure 15 A semiconductor layer 280 is formed in the space S1 between the first support layer 120 and the second support layer 140, the space S2 between the second support layer 140 and the third support layer 160, and the second hole H2 in the second support layer 140. The semiconductor layer 280 can completely fill the second opening 200, spaces S1 and S2 of the dielectric stack DS. The semiconductor layer 280 can also contact and cover the upper electrode layer 270 above the third support layer 160. In this way, a capacitor Ca is formed in the second opening 200 and spaces S1 and S2. Since the second opening 200 is not over-expanded during the previous etching process, the profile of the capacitor Ca is not adversely affected, and the structure of the capacitor Ca can be stabilized (e.g., preventing short circuits in the capacitor Ca).

[0059] In some embodiments, the semiconductor structure includes multiple support layers (i.e., a first support layer 120, a second support layer 140, and a third support layer 160) and a capacitor Ca. The first support layer 120, the second support layer 140, and the third support layer 160 are arranged from bottom to top and are spaced apart from each other. In other words, the third support layer 160 is located on the second support layer 140, and the second support layer 140 is located on the first support layer 120. In some embodiments, the width of the second support layer 140 is smaller than the width of the third support layer 160 or the width of the first support layer 120. Each of the capacitors Ca includes a lower electrode layer 250, a high-dielectric-constant dielectric layer 260, and an upper electrode layer 270. It should be noted that... Figure 15 The capacitor Ca in the example is illustrative; the capacitor Ca is not limited to... Figure 15 The structure shown. For example, capacitor Ca contains other layers.

[0060] Figure 16 Draw Figure 15 A magnified view of region R in the image, and Figure 17 yes Figure 16 The top view. Region R is drawn. Figure 15The capacitor Ca in the semiconductor structure. In some embodiments, Figure 16 The profile of region R in the middle is along Figure 17 Cut off line AA in the middle. For example... Figure 17 As shown, semiconductor layer 280 is surrounded by upper electrode layer 270, upper electrode layer 270 is surrounded by high dielectric constant dielectric layer 260, and high dielectric constant dielectric layer 260 is surrounded by lower electrode layer 250. That is, semiconductor layer 280 is located at the center, upper electrode layer 270 is concentrically arranged along semiconductor layer 280, high dielectric constant dielectric layer 260 is concentrically arranged along upper electrode layer 270, and lower electrode layer 250 is concentrically arranged along high dielectric constant dielectric layer 260. Semiconductor layer 280 has a circular outline. Each of lower electrode layer 250, high dielectric constant dielectric layer 260, and upper electrode layer 270 has a circular annular outline.

[0061] While the embodiments have been disclosed in detail above, other embodiments are possible and are not intended to limit the scope of this disclosure. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments disclosed herein.

[0062] Those skilled in the art can make various changes or substitutions without departing from the spirit and scope of this disclosure, and all such changes or substitutions should be covered within the scope of protection of the appended claims.

[0063] [Symbol Explanation]

[0064] 110:Substrate

[0065] 112: Metal wire

[0066] 120: First support layer

[0067] 130: First Sacrifice Layer

[0068] 133: Sidewall

[0069] 140: Second support layer

[0070] 150: Second Sacrificial Layer

[0071] 152: Top section

[0072] 153: Sidewall

[0073] 160: Third support layer

[0074] 170: Mask layer

[0075] 172: Top surface

[0076] 180: Patterned Mask

[0077] 190: First Opening

[0078] 200: Second opening

[0079] 210: Fill layer

[0080] 212: Top surface

[0081] 220: Primary oxide layer

[0082] 230: Cleaning process

[0083] 240: Etching process

[0084] 250: Lower electrode layer

[0085] 252: Horizontal section

[0086] 254: Vertical section

[0087] 260: High dielectric constant dielectric layer

[0088] 270: Upper electrode layer

[0089] 280: Semiconductor layer

[0090] Ca: Capacitor

[0091] DS: Dielectric Stack

[0092] DS1: Sidewall

[0093] H1: First hole

[0094] H2: Second hole

[0095] R: Region

[0096] S1: Space

[0097] S2: Space

[0098] AA: Line.

Claims

1. A method for forming a semiconductor structure, characterized in that, Include: Dielectric stacks are formed on the substrate; A masking layer is formed on the dielectric stack; A first opening is formed in the masking layer to expose the dielectric stack; A second opening is formed in the dielectric stack to expose the substrate, wherein the second opening communicates with the first opening; A filling layer is formed in the first opening and the second opening; Remove the masking layer and the filler layer to expose the sidewalls of the dielectric stack; as well as A capacitor is formed in the second opening of the dielectric stack.

2. The method of claim 1, wherein the fill layer is formed such that the fill layer contacts the mask layer and the substrate.

3. The method of claim 1, wherein the masking layer and the filling layer comprise the same material.

4. The method of claim 1, wherein the removal of the mask layer and the fill layer is performed simultaneously using an etching process.

5. The method according to claim 1, wherein, Also includes: A cleaning process is performed before removing the mask layer and the filler layer.

6. The method of claim 1, wherein forming the dielectric stack further comprises: A first sacrificial layer is formed on the substrate; and A second sacrificial layer is formed on the first sacrificial layer.

7. The method of claim 6, wherein the filler layer is formed such that the filler layer covers the sidewalls of the first sacrificial layer and the sidewalls of the second sacrificial layer.

8. The method of claim 6, wherein forming the dielectric stack further comprises: A first support layer is formed on the substrate; A second support layer is formed on the first sacrificial layer; and A third support layer is formed on the second sacrificial layer.

9. The method of claim 8, wherein forming the capacitor in the second opening of the dielectric stack comprises: A lower electrode layer is formed along the sidewall of the dielectric stack; A portion of the third support layer is removed to create a first hole that exposes the second sacrificial layer; Remove the second sacrificial layer from the first hole; A high dielectric constant dielectric layer is formed along the sidewall of the lower electrode layer; as well as An upper electrode layer is formed along the sidewall of the high dielectric constant dielectric layer.

10. The method according to claim 9, wherein, Also includes: A semiconductor layer is formed between the first support layer and the second support layer, and between the second support layer and the third support layer.

11. The method of claim 9, wherein forming the capacitor in the second opening of the dielectric stack further comprises: Remove a portion of the second support layer to form a second hole exposing the first sacrificial layer; and Before forming the high dielectric constant dielectric layer, the first sacrificial layer is removed from the second hole.

12. The method of claim 11, wherein forming the capacitor in the second opening of the dielectric stack further comprises: Before removing the first sacrificial layer, the horizontal portion of the lower electrode layer is removed to expose the substrate.

13. A method for forming a semiconductor structure, characterized in that, Include: A dielectric stack is formed on a substrate, wherein forming the dielectric stack includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer formed sequentially; A masking layer is formed on the dielectric stack; A first opening is formed in the masking layer to expose the third support layer of the dielectric stack; A second opening is formed in the dielectric stack to expose the substrate, wherein the second opening communicates with the first opening; A filler layer is formed in the first opening and the second opening, and a native oxide layer is formed on the top surface of the filler layer and the top surface of the masking layer; Perform a cleaning process to remove the original oxide layer; An etching process is performed to remove the mask layer and the filler layer; as well as A capacitor is formed in the second opening of the dielectric stack.

14. The method of claim 13, wherein the etching process is a wet etching process.

15. The method of claim 13, wherein the cleaning process and the etching process are performed using different etching solutions.

16. The method of claim 15, wherein the cleaning process is performed by using an acidic etching solution, and the etching process is performed by using an alkaline etching solution.

17. The method of claim 13, wherein the first sacrificial layer and the second sacrificial layer remain unchanged when the cleaning process is performed.

18. The method of claim 13, wherein the filling layer is formed such that the filling layer is surrounded by the first support layer, the first sacrificial layer, the second support layer, the second sacrificial layer and the third support layer.

19. The method of claim 13, wherein the fill layer is formed such that the fill layer extends from the substrate to the mask layer.

20. The method of claim 13, wherein the masking layer and the filling layer are polysilicon layers.

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