A data dependency-based war variable analysis method and system
By using a data-dependent WAR variable analysis method, which leverages control flow graphs and path analysis during the compilation phase and replaces memory references with memory addresses, the inaccuracy and high runtime overhead of WAR variable analysis are resolved, achieving efficient WAR variable identification and system state consistency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2023-12-11
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies suffer from poor performance or excessive runtime overhead when analyzing Write-After-Read (WAR) variables in programs due to inaccurate memory reference level analysis, especially in scenarios where power outages occur in IoT devices, making it difficult to guarantee system state consistency.
A data-dependent WAR variable analysis method is adopted. By analyzing the control flow graph and path during the compilation stage, and replacing memory references with memory addresses, WAR variables are accurately identified and backed up at runtime to ensure system state consistency.
It enables accurate identification of WAR variables at compile time, reduces runtime overhead, improves system state consistency and performance, avoids redundant backups, and reduces data volume and computational overhead.
Smart Images
Figure CN117555552B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of data processing technology, and in particular relates to a method and system for analyzing WAR variables based on data dependencies. Background Technology
[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.
[0003] With the continuous development of IoT devices and related technologies, the functionality of IoT devices will face significant challenges. Using traditional battery power limits IoT terminals, requiring periodic battery replacement or recharging. Energy harvesting systems allow the system to obtain energy from the surrounding environment to function, eliminating dependence on batteries, but they face frequent power outages. When a sudden power outage occurs, the system stops operating, data is lost, and when the system resumes operation, it restarts from a point far from the point of interruption, resulting in a non-progress problem.
[0004] In a task-based intermittent computing system, the running program is divided into different small tasks. When a power interruption occurs and is restored, the system resumes execution from the beginning of the last task, thus ensuring program correctness and forward continuity. To ensure system continuity before and after a failure, all variables that may generate Write-After-Read (WAR) dependencies need to be specially backed up and saved. Otherwise, the same variable may have different values at the same location before and after the program interruption, leading to program errors. Therefore, how to analyze WAR variables in the program becomes a problem that needs to be solved.
[0005] One current solution is to identify WAR variable dependencies at the compile-time level using memory references. However, for the same code block, the specific objects accessed in different instances are not entirely consistent. Therefore, memory reference-level analysis cannot effectively capture dynamic memory behavior, leading to poor performance. For example, in data access, an array may contain many variables, but each access may only access one of them. The memory access method assumes that all variables in the array may be accessed, thus saving and backing up all variables, resulting in significant redundancy.
[0006] Another alternative approach is to use a sophisticated memory management mechanism at runtime to record every read or write operation, thereby checking whether each variable is a WAR variable. This method creates a copy of each specific variable the first time it is accessed, redirects all subsequent modifications to that copy, and commits all changes after program execution. This approach not only incurs significant runtime overhead but also backs up variables that are not actually WAR variables but are considered WAR variables, leading to redundant operations. Summary of the Invention
[0007] To address at least one of the technical problems mentioned above, this invention provides a data-dependent WAR variable analysis method and system. It proposes a more granular data-dependent method, considering that most memory references are data-dependent. Therefore, regardless of whether a variable is a WAR variable or not, it is a data-dependent variable. The memory address is used instead of the memory reference to accurately and efficiently obtain the memory address of the WAR variable.
[0008] To achieve the above objectives, the present invention adopts the following technical solution:
[0009] The first aspect of the present invention provides a data-dependent WAR variable analysis method, including a compilation phase and a runtime phase;
[0010] During the compilation stage:
[0011] Obtain the control flow graph of the task, and use path analysis in the control flow graph to obtain the global WAR variable dependencies;
[0012] Perform overlap analysis on the memory addresses of read and write operations in the obtained global WAR variable dependencies;
[0013] Based on the overlap analysis results, the memory references that may fall into the dependencies of the global WAR variable in the task are calculated;
[0014] During runtime: memory addresses are used instead of memory references, memory addresses that are dependent on global WAR variables are calculated, and the corresponding data is backed up so as to maintain system state consistency in the event of a power outage.
[0015] Furthermore, the process of obtaining the control flow graph of the task, and obtaining the global WAR variable dependencies through path analysis within the control flow graph, includes:
[0016] Define local WAR variable dependencies and global WAR variable dependencies by combining the control flow graph and the dynamic access behavior of each memory reference obtained;
[0017] Based on the task-based control flow graph, the path sets for write operations and read operations are obtained. Combined with the definition of local WAR variable dependencies and the preset path sets for write operations and read operations, the global WAR variable dependencies are obtained.
[0018] Furthermore, the control flow graph of the task is denoted as G = (B, E), where B = {B i} represents the set of instructions called basic blocks at the assembly level, and E is the set of edges in the control flow graph, where edges represent the control flow between instructions.
[0019] The dynamic access behavior analysis of each memory reference includes: using symbolic execution to calculate the address expression of the memory reference. Symbolic backward execution will traverse the control flow graph in reverse to find the mapping between local variables and shared variables, and finally obtain the address expression of the shared variables.
[0020] Furthermore, the preset rule is: if any path in the path set of write operations contains a read operation on a variable that is the same as the object of the write operation, obtain part of the WAR variable dependency;
[0021] If a read operation is accessed again after a write operation in a partial WAR variable dependency, then this partial WAR variable dependency is not a global WAR variable dependency.
[0022] Furthermore, the local WAR variable dependency is defined as a tuple containing a write operation and a read operation for the same variable, where the write operation may be accessed before the read operation. The global WAR variable dependency of a task is defined as a variable that is read first and then written at the start of the task. If a variable is a partial WAR variable dependency in the code segment of a task, then it may not be a global WAR variable dependency of the task.
[0023] Furthermore, the overlap analysis of the memory addresses of read and write operations in the obtained global WAR variable dependencies includes:
[0024] The question of whether the memory address expressions of read and write operations can access the same address is transformed into the question of whether a system of linear equations has a solution;
[0025] Using linear algebra, we can determine whether there are overlapping addresses by calculating whether a system of linear equations has a solution. If the system of equations has no solution, then memory references A and B will not overwrite each other.
[0026] If the system of equations has a solution, then there are two cases: certain coverage and possible coverage. If two memory references using different symbols always access the same memory address, then it is a case of certain coverage; otherwise, it is a case of possible coverage.
[0027] Furthermore, the calculation of memory references in the task that may fall into the dependency of the global WAR variable based on the overlap analysis results includes:
[0028] If all preceding write operations in the RAW dependency of a read operation must overlap with the read operation, then the first operation on the variable must be a write operation, and the variable accessed by the read operation is not a WAR variable.
[0029] Furthermore, if a read operation will never overlap with a subsequent write operation, then the read and write operations in a partial WAR dependency will target different memory addresses, and therefore the variables accessed by the read operation will not be WAR variables; otherwise, the variables accessed by the read operation will be treated as WAR variables, and the data dependency address expression of the read operation will be recorded and backed up.
[0030] A second aspect of the present invention provides a data-dependent WAR variable analysis system, including a compilation module and a runtime module;
[0031] The compilation module is configured as follows:
[0032] Obtain the control flow graph of the task, and use path analysis in the control flow graph to obtain the global WAR variable dependencies;
[0033] Perform overlap analysis on the memory addresses of read and write operations in the obtained global WAR variable dependencies;
[0034] Based on the overlap analysis results, the memory references that may fall into the dependencies of the global WAR variable in the task are calculated;
[0035] The runtime module is configured to replace memory references with memory addresses, calculate the memory addresses that global WAR variables depend on, and back up the corresponding data so as to maintain system state consistency during power outages.
[0036] A third aspect of the present invention provides a computer-readable storage medium.
[0037] A computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the steps of a data-dependent WAR variable analysis method as described above.
[0038] A fourth aspect of the present invention provides a computer device.
[0039] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps in a data-dependent WAR variable analysis method as described above.
[0040] Compared with the prior art, the beneficial effects of the present invention are:
[0041] Existing methods either produce pessimistic analysis results or incur significant runtime overhead, negatively impacting system progress. To accurately and effectively analyze WAR dependencies, this invention proposes a data-dependent WAR analysis method. This method calculates WAR dependencies at compile time based on address expressions that depend on data, yielding data-dependent WAR analysis results. At runtime, the system can accurately locate WAR variables that may be trapped in WAR dependencies based on shared data, with minimal runtime overhead.
[0042] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0043] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.
[0044] Figure 1 This is a flowchart of the WAR variable analysis method based on data dependency provided in an embodiment of the present invention;
[0045] Figure 2 This is a WAR dependency and RAW dependency graph provided in an embodiment of the present invention;
[0046] Figure 3 This is a comparison of the running time of the method of the present invention provided in the embodiments of the present invention with that of existing analysis methods. Detailed Implementation
[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0048] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0049] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0050] WAR dependency analysis is crucial for the design of task-based intermittent computing systems. Existing methods either produce pessimistic analysis results or incur significant runtime overhead, negatively impacting system progress. To accurately and effectively analyze WAR dependencies, this invention proposes a data-dependent WAR analysis method. This method calculates WAR dependencies at compile time based on address expressions that depend on data, yielding WAR analysis results that depend on data. At runtime, the system can accurately locate WAR variables that may fall into WAR dependencies based on shared data, with minimal runtime overhead.
[0051] Example 1
[0052] according to Figure 1 This embodiment provides a data-dependent WAR variable analysis method, including the following steps:
[0053] The compilation phase includes:
[0054] Step 1: Obtain the control flow graph of the task, and obtain the global WAR variable dependencies through path analysis in the control flow graph;
[0055] Step 101: Obtain the program's control flow graph (CFG), and obtain the set of variable paths through path analysis in the control flow graph;
[0056] WAR variable analysis is performed on the program's control flow graph (CFG), denoted as G = (B, E), where B = {B...}. i} represents the set of instructions called basic blocks at the assembly level, and E is the set of edges in the control flow graph, where edges represent the control flow between instructions.
[0057] During WAR variable analysis, the process of obtaining the variable path set is as follows:
[0058] Define the basic block at the program entry point as B1; define a variable path, which represents a set, for any basic block B i One of its path sets p iLet B1 represent the set of different basic blocks that can exist from the starting basic block B1, denoted as:
[0059] p i ={B1,B k ,…,B i}
[0060] The set of all paths leading to the same basic block is denoted as P. i .
[0061] Note that since this embodiment only calculates different basic blocks on different paths, rather than ordered basic blocks on precise paths, the path set can be obtained effectively through the abstract interpretation method.
[0062] Step 102: Use symbolic execution to traverse the control flow graph in reverse and calculate the address expression of the memory reference;
[0063] To accurately obtain the dynamic access behavior of each memory reference, the address expression of memory reference 'a' is calculated using symbolic execution, as shown below:
[0064]
[0065] Among them, S i Base represents a shared variable that affects the memory address accessed by A. A This represents the starting address of the array, or the memory address where the variable is located. a i This indicates the size of each dimension of the array (if accessing the array).
[0066] This address expression can be obtained by reversing the symbolic representation. Some memory references can be explicitly accessed through local variables.
[0067] Symbolic backward execution traverses the control flow graph in reverse to find the mapping between local and shared variables, and ultimately obtains the address expression for the shared variables.
[0068] The resulting address expressions are categorized into the following three types:
[0069] Constant expression: a memory reference corresponding to a scalar.
[0070] Linear expression: corresponds to a memory reference that has a linear relationship with the shared variable.
[0071] Unpredictable expressions: such as memory accesses that are not linearly related to shared variables or memory accesses that depend on input.
[0072] Step 103: Perform WAR dependency analysis and RAW dependency analysis on the flow control graph of each task to obtain the dependency graph of read-write relationships in the tasks, which is then used for the overlap analysis in Step 2. Specifically, this includes:
[0073] Step 1031: Perform WAR dependency analysis on the flow control graph of each task;
[0074] Given the excessive overhead of existing WAR analysis, an improved data dependency WAR variable analysis method combines address analysis and WAR variable analysis to accurately obtain the memory addresses of WAR variables. The following section first introduces WAR dependency analysis and RAW dependency analysis. Both analysis methods are performed on each CFG (Computer-Generated Group) composed of tasks.
[0075] A local WAR dependency is defined as a 2-tuple containing a write operation and a read operation for the same variable, denoted as (B(A), W(A)), where the write operation may be accessed before the read operation. Note that a task's global WAR variable is defined as a variable that is read before being written at the start of the task. If a variable is a partial WAR dependency in a task's code segment, it may not be a global WAR variable for the task. Partial WAR analysis focuses on write operations, such as write operation W. A .
[0076] The specific analysis method is as follows: First, obtain the set of paths for variable write operations. If in a set Any path contains the write operation W. A If a read operation is performed on a variable that is the same as the operation on the target variable, then a partial WAR dependency is acquired, and this path will be denoted as... WAR dependencies are denoted as:
[0077]
[0078] Step 1032: If, in a partial WAR dependency (R(A)), W(A)), the read operation is accessed again after a write operation, then this partial WAR dependency is not a global WAR dependency. For all found partial WAR dependencies, perform RAW dependency analysis on the read operations using the same method as in Step 1031, ultimately yielding the following... Figure 2 The dependency graph shown.
[0079] Step 2: Perform overlap analysis on the memory addresses of read and write operations in the obtained global WAR variable dependencies;
[0080] Step 201: Based on the WAR dependency analysis of variables, the WAR dependency of memory addresses was further analyzed based on the global WAR dependency relationship of each variable.
[0081] We begin with an analysis of the overlap between two memory address expressions. Assume there exists a set of read / write operations (R, W) with corresponding memory addresses (A, B). We can transform the question of whether a set of read / write operations can access the same memory address into the question of whether a system of linear equations has a solution.
[0082] For example, an expression for two memory addresses:
[0083]
[0084]
[0085] If two expressions for memory addresses can access the same address `addr`, then we can obtain the following set of equations:
[0086]
[0087]
[0088] In the formula, A is the memory address accessed by the two different read / write operations, and B is the memory address accessed by the two different read / write operations. S represents the size of each dimension of the array. n For several shared variables used to access array elements, C A For, C B These are the starting addresses of the two arrays.
[0089] This transforms the question of whether two address expressions can access the same address into the question of whether a system of linear equations has a solution.
[0090] Step 202: Use linear algebra to determine whether there are overlapping addresses by calculating whether the system of linear equations has a solution, corresponding to the three cases of NEVER, MAY, and MUST.
[0091] Using linear algebra methods, compare the coefficient matrix M and the augmented matrix of the system of linear equations. The average rank, denoted as r(M) and Based on linear algebra:
[0092] like Then the system of equations has no solution.
[0093] like Then the system of equations has a solution.
[0094] Correspondingly, if the system of equations has no solution, then memory references A and B will not overwrite each other (NEVER);
[0095] If the system of equations has a solution, then there are two cases: MUST and MAY. If two memory references using different symbols always access the same memory address, then it is a MUST case; otherwise, it is a MAY case.
[0096] Step 3: Based on the overlap analysis results, calculate the memory references in the task that may fall into the global WAR variable dependency, that is, the memory references with the judgment result of MUST and MAY.
[0097] Select each read operation in the global WAR dependency as the target to perform WAR analysis on the dependent data.
[0098] In a RAW dependency, each read operation may have several preceding write operations, while in a WAR dependency there is one subsequent write operation. If all preceding write operations in a read operation's RAW dependency must overlap with the read operation, then the first operation on the variable must be a write operation, and the variable accessed by the read operation is not a WAR variable.
[0099] Furthermore, if a read operation is guaranteed not to overlap with a subsequent write operation, then the read and write operations within a partial WAR dependency will target different memory addresses; therefore, the variables accessed by the read operation will not be WAR variables. Otherwise, the variables accessed by the read operation are treated as WAR variables, and the data dependency address expression of the read operation is recorded and backed up.
[0100] Operational phase
[0101] During the runtime phase, the system uses the previously obtained address expressions belonging to WAR variables to substitute the shared variables in the expressions with specific values to calculate the specific memory addresses that the global WAR depends on, and backs up the corresponding data so as to maintain the consistency of the system state when power is lost.
[0102] The following analysis uses a specific code segment as an example. By observing the code segment from lines 20 to 24, and taking the instruction hash[mi][0] = T1 + T2 at line 24 as an example, we will further explain the data dependency WAR analysis.
[0103]
[0104] There is a write operation on hash[mi][0] at line 24. Searching for read operations within the path, we find two read operations on hash[mi][0] (line 23) and hash[mi][6] (line 20) before the write operation. Therefore, we obtain two partial WAR dependencies:
[0105] (Base(hash)mi*32,Base(hash)+mi*32),
[0106] (Base(hash)mi*32+24,Base(hash)+mi*32);
[0107] Next, we perform RAW analysis again on the two read operations to find write operations along the path: For the first read operation hash[mi][0], a write operation to hash[mi][7] occurs on line 20, and a write operation to hash[mi][6] occurs on line 23, thus revealing two partial RAW dependencies:
[0108] (Base(hash)mi*32+4,Base(hash)+mi*32),
[0109] (Base(hash)mi*32+28, Base(hash)+mi*32);
[0110] Similarly, for the second read operation hash[mi][6], we can also obtain a partial RAW dependency:
[0111] (Base(hash)mi*32+28, Base(hash)+mi*32+24),
[0112] In all the partially RAW dependencies, all address expressions are guaranteed not to overwrite each other (NEVER); in all the partially WAR dependencies, only one address expression is guaranteed to overwrite (MUST):
[0113] (Base(hash)mi*32, Base(hash)+mi*32),
[0114] At this point, the WAR variable obtained from the data dependency analysis has been calculated:
[0115] Base(hash) + mi * 32,
[0116] That is, hash[mi][0].
[0117] Data shows that the method of this invention has superior overall performance compared to existing methods: Under the same operating environment, the amount of data that needs to be backed up by the method of this invention is much smaller than that of static analysis methods, which typically require about 30 times more data to be backed up; Compared to runtime-based analysis methods, the amount of data that needs to be backed up is similar, but the method of this invention does not require additional memory overhead such as WAR variable identification and memory management, and the overhead of address calculation is also relatively small, resulting in superior overall performance.
[0118] By comparing existing static analysis methods with the existing runtime-based analysis method Alpaca under different benchmarks, the runtime of different analysis methods is as follows: Figure 3 As shown in Table 1, the required backup data volume is compared in sequence.
[0119] Table 1. Comparison of required backup data size calculated by different analysis methods (unit: KB)
[0120]
[0121] Through Table 1 and Figure 3 As can be seen, in the tested cases, the solution of this invention significantly reduces the amount of data that needs to be backed up compared to static analysis methods. This indicates that the method of this invention is more accurate in identifying WAR variables and avoids a lot of redundancy. This is even more obvious in programs such as the Cuckoo search algorithm, which involves a large number of array accesses and is prone to misjudging WAR variables. At the same time, the overall speed is faster. On the other hand, compared with the existing dynamic analysis method Alpaca, the size of the data to be backed up is not much different, indicating that the identification accuracy of this invention is close to that of pure runtime analysis, but its performance in terms of execution time is also better.
[0122] Example 2
[0123] This embodiment provides a WAR variable analysis system based on data dependencies, including a compilation module and a runtime module;
[0124] The compilation module is configured as follows:
[0125] Obtain the control flow graph of the task, and use path analysis in the control flow graph to obtain the global WAR variable dependencies;
[0126] Perform overlap analysis on the memory addresses of read and write operations in the obtained global WAR variable dependencies;
[0127] Based on the overlap analysis results, the memory references that may fall into the dependencies of the global WAR variable in the task are calculated;
[0128] The runtime module is configured to replace memory references with memory addresses, calculate the memory addresses that global WAR variables depend on, and back up the corresponding data so as to maintain system state consistency during power outages.
[0129] Example 3
[0130] This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the data-dependent WAR variable analysis method described above.
[0131] Example 4
[0132] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the data-dependent WAR variable analysis method described above.
[0133] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.
[0134] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0135] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0136] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0137] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0138] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A data-dependent WAR variable analysis method, characterized in that, Includes the compilation phase and the runtime phase; During the compilation stage: Obtain the control flow graph of the task, and use path analysis in the control flow graph to obtain the global WAR variable dependencies; Perform overlap analysis on the memory addresses of read and write operations in the obtained global WAR variable dependencies; The memory references that fall into the dependencies of the global WAR variable in the task are calculated based on the overlap analysis results; During runtime: memory addresses are used instead of memory references, memory addresses that are dependent on global WAR variables are calculated, and corresponding data is prepared in order to maintain system state consistency during power outages; The step of performing overlap analysis on the memory addresses of read and write operations in the obtained global WAR variable dependencies includes: The question of whether the memory address expressions of read and write operations can access the same address is transformed into the question of whether a system of linear equations has a solution; The system of linear equations is as follows: ， ， Where A and B are the memory addresses accessed by two different read and write operations. The size of each dimension of the array. For several shared variables used to access array elements, , These are the starting addresses of the two arrays. An expression representing two memory addresses can access the same address; Using linear algebra, we can determine whether there are overlapping addresses by calculating whether a system of linear equations has a solution. If the system of equations has no solution, then memory references A and B will not overwrite each other. If the system of equations has a solution, then there are two cases: guaranteed coverage and possible coverage. If two memory references using different symbols always access the same memory address, then it is a guaranteed coverage case; otherwise, it is a possible coverage case. The calculation of memory references in the task that fall into the dependency of the global WAR variable based on the overlap analysis results includes: If all preceding write operations in the RAW dependency of a read operation must overlap with the read operation, then the first operation on the variable must be a write operation, and the variable accessed by the read operation is not a WAR variable. Furthermore, if a read operation does not overlap with a subsequent write operation, the read and write operations in a partial WAR dependency will target different memory addresses, and therefore the variables accessed by the read operation will not be WAR variables; otherwise, the variables accessed by the read operation will be treated as WAR variables, and the data dependency address expression of the read operation will be recorded for backup.
2. The WAR variable analysis method based on data dependency as described in claim 1, characterized in that, The control flow graph for acquiring the task, through path analysis, yields global WAR variable dependencies, including: Define local WAR variable dependencies and global WAR variable dependencies by combining the control flow graph and the dynamic access behavior of each memory reference obtained; Based on the task-based control flow graph, the path sets for write operations and read operations are obtained. Combined with the definition of local WAR variable dependencies and the preset path sets for write operations and read operations, the global WAR variable dependencies are obtained.
3. The WAR variable analysis method based on data dependency as described in claim 2, characterized in that, The control flow graph of the task is denoted as ,in, This refers to the set of instructions called basic blocks at the assembly level. It is the set of edges in the control flow graph, where edges represent the control flow between instructions; The dynamic access behavior analysis of each memory reference includes: using symbolic execution to calculate the address expression of the memory reference. Symbolic backward execution will traverse the control flow graph in reverse to find the mapping between local variables and shared variables, and finally obtain the address expression of the shared variables.
4. The WAR variable analysis method based on data dependency as described in claim 2, characterized in that, The preset rule is: if any path in the path set of write operations contains a read operation on a variable that is the same as the object of the write operation, obtain part of the WAR variable dependency; If a read operation is accessed again after a write operation in a partial WAR variable dependency, then this partial WAR variable dependency is not a global WAR variable dependency.
5. The WAR variable analysis method based on data dependency as described in claim 4, characterized in that, The definition of a local WAR variable dependency is a tuple containing a write operation and a read operation for the same variable, where the write operation is accessed before the read operation. The definition of a task's global WAR variable dependency is a variable that is read first and then written at the start of the task. If a variable is a partial WAR variable dependency in a task's code segment, then it is not a global WAR variable dependency of the task.
6. A WAR variable analysis system based on data dependency, characterized in that, A method for implementing a data-dependent WAR variable analysis method according to any one of claims 1-5, comprising a compilation module and a runtime module; The compilation module is configured as follows: Obtain the control flow graph of the task, and use path analysis in the control flow graph to obtain the global WAR variable dependencies; Perform overlap analysis on the memory addresses of read and write operations in the obtained global WAR variable dependencies; The memory references that fall into the dependencies of the global WAR variable in the task are calculated based on the overlap analysis results; The runtime module is configured to replace memory references with memory addresses, calculate the memory addresses that global WAR variables depend on, and back up the corresponding data so as to maintain system state consistency during power outages.
7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the data-dependent WAR variable analysis method as described in any one of claims 1-5.
8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the data-dependent WAR variable analysis method as described in any one of claims 1-5.