A time-to-digital converter with differential symmetric parallel comparison

Abstract

The application discloses a differential symmetric parallel comparison time-to-digital converter, comprising: single-ended to differential module one, a delay-locked loop, single-ended to differential module two, differential voltage-controlled delay chain module one, differential voltage-controlled delay chain module two, a time comparator array and an encoder; wherein the delay-locked loop adopts a differential voltage-controlled delay unit to improve the suppression ability to power noise, to accelerate the locking time, to dynamically control the delay chain bias voltage Vc, so that the time-to-digital converter has good robustness. The application improves the suppression ability to power noise by adopting the differential voltage-controlled delay unit in the delay-locked loop, accelerates the locking time, dynamically controls the delay chain bias voltage Vc, so that the time-to-digital converter has good robustness; a new parallel comparison arrangement mode is designed, which provides convenience for subsequent layout design and arrangement, realizes the layout arrangement of the topology structure symmetry and the same wire length, and improves the linearity of the time-to-digital converter.

Description

Technical Field

[0001] This invention belongs to the technical field of lidar optical signal receiver systems, specifically relating to a differential symmetric parallel comparison time-to-digital converter. Background Technology

[0002] Light Detection and Ranging (LiDAR) is an optical technology widely used to measure the distance to targets and acquire 3D maps of scenes. It has applications in various fields of science and daily life, such as autonomous driving, gesture recognition, 3D scanners, and security monitoring. Miniaturization and chip-based architecture of LiDAR systems are effective solutions to address the large size and high cost of existing LiDAR products. By utilizing integrated circuit technology to integrate the analog receiver circuitry of the LiDAR front-end onto a single chip, and simultaneously forming multi-channel or even array-scale systems, the difficulty of system debugging is greatly reduced, and the cost of LiDAR products is significantly lowered, promoting the large-scale application of LiDAR in fields such as intelligent robots and autonomous driving. The ranging principles of LiDAR typically include triangulation, interferometry, indirect time-of-flight, direct time-of-flight, and frequency-modulated continuous wave (FM-CFW). Compared with other implementation schemes, LiDAR based on the direct time-of-flight ranging principle offers a good trade-off in terms of measurement distance, resolution, and system complexity, making it perfectly suitable for applications such as autonomous driving. Therefore, based on the direct time-of-flight ranging principle, it is of great significance to customize the analog receiving circuit of the lidar front end, improve the performance of each module unit circuit, and at the same time, study the high-precision time-to-digital converter circuit for accurate measurement of direct time of flight.

[0003] Direct time-of-flight (DTMF) lidar directly measures the time interval between the START signal of laser emission and the STOP signal of the reflected echo from the object. A time-to-digital converter (TDD) circuit converts this time information into binary code, thus obtaining the distance information to the target object. Therefore, the accuracy of the DTD directly determines the accuracy of the distance measurement. Currently, the most commonly used DTD circuit is the parallel comparison DTD based on a delay-locked loop (PLL) that dynamically adjusts the total delay of the voltage-controlled delay chain. Its timing is relatively simple, it exhibits good robustness under different temperature and process angles, and its time resolution is the delay time of a single-stage voltage-controlled delay unit. It is often used in the fine quantization unit circuits of high-resolution DTD systems.

[0004] In traditional parallel comparison time-to-digital converters (PDCs), the START signal at the laser emission moment generates multi-phase delayed signals at the outputs of each stage via a voltage-controlled delay chain. The STOP signal at the object echo reflection moment bypasses the voltage-controlled delay chain and is directly compared with the multi-phase delayed signals generated by the START signal in the voltage-controlled delay chain in a time comparator array to ultimately determine the time interval between the START and STOP signals. However, traditional single-ended voltage-controlled delay chains are significantly affected by power supply noise. Furthermore, because the STOP signal is directly connected to one input of each stage of the time comparator, the load on the STOP signal differs significantly from the load on the outputs of the START signal at each stage of the voltage-controlled delay chain. This mismatch in the driving capabilities of the two inputs of the time comparators greatly affects the accuracy of the discrimination result, and consequently, the precision of the parallel comparison time-to-digital converter. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a differential symmetric parallel comparison time-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A differential symmetric parallel comparison time-to-digital converter, comprising:

[0007] The system comprises: a single-ended to differential module 1, a delay phase-locked loop (PLL), a single-ended to differential module 2, a differential voltage-controlled delay chain module 1, a differential voltage-controlled delay chain module 2, a time comparator array, and an encoder; among which,

[0008] The single-ended to differential module one is used to convert the single-ended signal START into a differential signal and output it to the differential voltage-controlled delay chain module one;

[0009] The single-ended to differential module 2 is used to convert the single-ended signal STOP into a differential signal and output it to the differential voltage-controlled delay chain module 2;

[0010] The delay phase-locked loop employs a differential voltage-controlled delay unit to generate a delay chain bias voltage Vc based on the reference clock signal CLK_REF and output it to the differential voltage-controlled delay chain module one and the differential voltage-controlled delay chain module two, such that the total delay of each of the sixteen voltage-controlled delay units in the differential voltage-controlled delay chain module one and the differential voltage-controlled delay chain module two is equal to one clock cycle of the reference clock signal CLK_REF;

[0011] The differential voltage-controlled delay chain module 1 is used to output a first multi-phase delay signal to the time comparator array based on the differential signal obtained by converting the single-ended signal START and the voltage-controlled delay units at each stage in itself;

[0012] The differential voltage-controlled delay chain module 2 is used to output a second multi-phase delay signal to the time comparator array based on the differential signal obtained by converting the single-ended signal STOP and the voltage-controlled delay units at each stage in itself;

[0013] The time comparator array is used to compare each bit of the first multi-phase delayed signal and the second multi-phase delayed signal in sequence, and output the corresponding thermometer code;

[0014] The encoder is used to convert the thermometer code into binary code, and output the binary code as the output result.

[0015] In one embodiment of the present invention, the circuit structure of the differential voltage-controlled delay chain module one includes:

[0016] The system consists of a 32-stage voltage-controlled delay unit and two dummy voltage-controlled delay units at the beginning and end; among which,

[0017] The positive input terminal of the first-stage dummy unit is connected to the positive output terminal of the single-ended to differential module one, the negative input terminal of the first-stage dummy unit is connected to the negative output terminal of the single-ended to differential module one, the control terminal of the first-stage dummy unit is connected to the control terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit, the positive output terminal of the first-stage dummy unit is connected to the positive input terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit, and the negative output terminal of the first-stage dummy unit is connected to the negative input terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit.

[0018] Each stage of the 32-stage voltage-controlled delay unit is connected in series with the next stage. The control terminals of each stage are interconnected. The control terminal of the 32nd stage voltage-controlled delay unit is connected to the control terminal of the tail-stage dummy unit. The positive output terminal of the 32nd stage voltage-controlled delay unit is connected to the positive input terminal of the tail-stage dummy unit, and the negative output terminal of the 32nd stage voltage-controlled delay unit is connected to the negative input terminal of the tail-stage dummy unit. The positive output terminal of each stage of the 32-stage voltage-controlled delay unit serves as the output signal terminal ST. p <1> ~ST p <32> The negative output terminal of each stage of the thirty-two voltage-controlled delay unit is sequentially used as the output signal terminal ST. n <1> ~ST n <32> ;

[0019] The control terminal of the tail-stage dummy unit is connected to the output terminal of the delay phase-locked loop.

[0020] In one embodiment of the present invention, the circuit structure of the differential voltage-controlled delay chain module two includes:

[0021] The system includes a 16-stage voltage-controlled delay unit and two voltage-controlled delay units at the beginning and end, which function as dummy 1 units; among them,

[0022] The positive input terminal of the first-stage dummy1 unit is connected to the positive output terminal of the single-ended to differential module 2, the negative input terminal of the first-stage dummy1 unit is connected to the negative output terminal of the single-ended to differential module 2, the control terminal of the first-stage dummy1 unit is connected to the control terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit, the positive output terminal of the first-stage dummy1 unit is connected to the positive input terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit, and the negative output terminal of the first-stage dummy1 unit is connected to the negative input terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit.

[0023] Each stage of the sixteen-stage voltage-controlled delay unit (VDCD) is connected in series with the next stage VDCD. The control terminals of each stage are interconnected. The control terminal of the sixteenth stage VDCD is connected to the control terminal of the tail-stage dummy1 unit. The positive output terminal of the sixteenth stage VDCD is connected to the positive input terminal of the tail-stage dummy1 unit, and the negative output terminal of the sixteenth stage VDCD is connected to the negative input terminal of the tail-stage dummy1 unit. The positive output terminal of each stage of the sixteen-stage VDCD serves as the output signal terminal SP. p <1> ~SP p <16> The negative output terminal of each stage of the sixteen-stage voltage-controlled delay unit is sequentially used as the output signal terminal SP. n <1> ~SP n <32> ;

[0024] The control terminal of the primary dummy1 unit is connected to the output terminal of the delay phase-locked loop.

[0025] In one embodiment of the present invention, the time comparator array includes:

[0026] A time comparator array at the positive output of the delay chain and a time comparator array at the negative output of the delay chain; wherein...

[0027] The time comparator array at the positive output of the delay chain includes sixteen stages of time comparators; the first terminal of the nth stage time comparator in the sixteen stages is connected to the output signal terminal ST. p <n+16> The connection is made between the second terminal of the nth stage time comparator in the sixteen-stage time comparator and the output signal terminal SP.p The <17-n> connection is used, where the output of the nth time comparator in the sixteen-level time comparator is the output of the time comparator array OUT<2n-1>, which is the positive output of the delay chain; 16≥n≥1.

[0028] In one embodiment of the present invention, the time comparator array at the negative output of the delay chain includes: fifteen stages of time comparators; wherein...

[0029] The first terminal and the output signal terminal ST of the xth stage time comparator in the fifteen-stage time comparator n <x+16> After inversion, the second terminal of the xth stage time comparator in the fifteen-stage time comparator is connected to the output signal terminal SP. n The <16-x> connection is used, where the output of the xth time comparator in the fifteen-level time comparator is the output of the time comparator array OUT<2x>, where 15≥x≥1.

[0030] In one embodiment of the present invention, the output terminal OUT<2n-1> of the time comparator array at the positive output terminal of the delay chain and the output terminal OUT<2x> of the time comparator array at the negative output terminal of the delay chain are combined to form the output terminal OUT of the time comparator array. <s>31≥s≥1, the output terminal OUT of the time comparator array <s>The output is a 31-bit thermometer code.

[0031] In one embodiment of the present invention, the input terminal of the encoder is connected to the output terminal of the time comparator array; the encoder converts the 31-bit thermometer code output by the time comparator array into a 5-bit binary code.

[0032] The beneficial effects of this invention are:

[0033] 1. The delay phase-locked loop proposed in this invention uses a differential voltage-controlled delay unit to improve the suppression of power supply noise, speed up the locking time, and dynamically control the delay chain bias voltage Vc, so that the time-to-digital converter has good robustness.

[0034] 2. By adopting a single-ended to differential module and a differential voltage-controlled delay chain module, both the START and STOP signals generate multi-phase delay signals through the delay chain. The symmetrical layout ensures that the loads of the delay signals sent to the corresponding time comparators of the two channels are completely consistent, eliminating the discrimination error introduced by load mismatch and improving the accuracy of the time-to-digital converter.

[0035] 3. This invention designs a novel parallel comparison arrangement, which allows signals to be sequentially fed into the time comparator array starting from the final output of the voltage-controlled delay chain module one and the first output of the differential voltage-controlled delay chain module two. This provides convenience for subsequent layout design and layout, and realizes a layout with symmetrical topology and the same trace length, thereby improving the linearity of the time-to-digital converter. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a traditional parallel compare-time to digital converter.

[0037] Figure 2 A schematic diagram of a differential symmetric parallel comparison time-to-digital converter provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the structure of a differential symmetric parallel comparison time-to-digital converter provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the time comparator array of a differential symmetric parallel comparison time-to-digital converter provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram illustrating the process of measuring and outputting the time interval between the signals START and STOP of a differential symmetric parallel comparison time-to-digital converter provided in an embodiment of the present invention.

[0041] Figure Labels

[0042] 100 - Single-ended to differential module one; 200 - Delay phase-locked loop; 300 - Single-ended to differential module two; 400 - Differential voltage-controlled delay chain module one; 500 - Differential voltage-controlled delay chain module two; 600 - Time comparator array; 700 - Encoder; 601 - Time comparator array at the positive output of the delay chain; 602 - Time comparator array at the negative output of the delay chain. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] For a schematic diagram of a traditional parallel compare-time to digital converter, please refer to [link / reference]. Figure 1 .Depend on Figure 1 As can be seen, a traditional parallel comparison time-to-digital converter may include: a delay phase-locked loop, a single-ended voltage-controlled delay chain for the START signal channel, a time comparator, and an encoder.

[0045] In traditional parallel comparison-time-to-digital converters (PCDs), the START signal at the laser emission moment is used to generate multi-phase delayed signals at the outputs of each stage of a single-ended voltage-controlled delay (VCD) chain. The STOP signal at the object's echo reflection moment is directly compared with the START signal at the outputs of each stage of the VCD chain in a time comparator, bypassing the VCD chain, to determine the time interval between the START and STOP signals. However, traditional VCD chains are significantly affected by power supply noise. Furthermore, because the STOP signal is directly connected to one input of each time comparator stage, the load on the STOP signal differs considerably from the load on the outputs of the START signal at each stage of the VCD chain. This mismatch in the driving capabilities of the two inputs of the time comparator greatly affects the accuracy of the judgment result, thus impacting the precision of the PCD.

[0046] To address the aforementioned problems, embodiments of the present invention provide a differential symmetric parallel comparison time-to-digital converter, such as... Figure 2 As shown, it may include:

[0047] The system includes: a single-ended to differential converter module 100, a delay phase-locked loop 200, a single-ended to differential converter module 2 300, a differential voltage-controlled delay chain module 1 400, a differential voltage-controlled delay chain module 2 500, a time comparator array 600, and an encoder 700; among which,

[0048] The single-ended to differential module 100 is used to convert the single-ended signal START into a differential signal and output it to the differential voltage-controlled delay chain module 400;

[0049] The single-ended to differential module 2 300 is used to convert the single-ended signal STOP into a differential signal and output it to the differential voltage-controlled delay chain module 2 500;

[0050] The delay phase-locked loop 200 uses differential voltage-controlled delay units to generate a delay chain bias voltage Vc based on the reference clock signal CLK_REF and output it to differential voltage-controlled delay chain module 1 400 and differential voltage-controlled delay chain module 2 500, so that the total delay of every sixteen voltage-controlled delay units in differential voltage-controlled delay chain module 1 400 and differential voltage-controlled delay chain module 2 500 is equal to one clock cycle of the reference clock signal CLK_REF;

[0051] The differential voltage-controlled delay chain module 400 is used to output the first multi-phase delay signal to the time comparator array 600 based on the differential signal obtained by converting the single-ended signal START and the voltage-controlled delay units in its own stages;

[0052] Differential voltage-controlled delay chain module 2 500 is used to output a second multi-phase delay signal to the time comparator array 600 based on the differential signal obtained by converting the single-ended signal STOP and the voltage-controlled delay units in itself.

[0053] The time comparator array 600 is used to compare each bit of the first multi-phase delayed signal and the second multi-phase delayed signal in sequence, and output the corresponding thermometer code;

[0054] The encoder 700 is used to convert thermometer codes into binary codes and output the binary codes as the output result.

[0055] The delay phase-locked loop proposed in this invention uses a differential voltage-controlled delay unit to improve the suppression of power supply noise and speed up the locking time. It dynamically controls the bias voltage Vc of the delay chain, giving the time-to-digital converter better robustness. By using a single-ended to differential module and a differential voltage-controlled delay chain module, both the START and STOP signals generate multi-phase delay signals through the delay chain. Furthermore, by utilizing a symmetrical layout, the load of the delay signals sent to the corresponding time comparators of the two channels is completely consistent, eliminating the discrimination error introduced by load mismatch and improving the accuracy of the time-to-digital converter.

[0056] Please refer to the schematic diagram of the differential symmetric parallel comparison time-to-digital converter provided in this embodiment of the invention. Figure 3 To facilitate understanding, the following will be combined with... Figure 3 Each module in the embodiments of the present invention will be described separately.

[0057] Single-ended to differential module 1

[0058] See Figure 3 The input terminal of the single-ended to differential module 100 is connected to the single-ended signal START, and the positive and negative output terminals of the single-ended to differential module 100 are respectively connected to the positive and negative input terminals of the differential voltage-controlled delay chain module 400.

[0059] The single-ended to differential module 100 is used to convert the single-ended signal START into a differential signal and output it to the differential voltage-controlled delay chain module 400.

[0060] Single-ended to differential module 2

[0061] See Figure 3 The input terminal of the single-ended to differential module 2 300 is connected to the single-ended signal STOP, and the positive and negative output terminals of the single-ended to differential module 2 300 are respectively connected to the positive and negative input terminals of the differential voltage-controlled delay chain module 2 500.

[0062] The single-ended to differential module 2 300 is used to convert the single-ended signal STOP into a differential signal and output it to the differential voltage-controlled delay chain module 2 500.

[0063] Delayed phase-locked loop

[0064] See Figure 3 The input terminal of the delay phase-locked loop 200 is connected to the reference clock signal CLK_REF, and the output terminal of the delay phase-locked loop 200 is connected to the control terminal of the differential voltage-controlled delay chain module 400 and the control terminal of the differential voltage-controlled delay chain module 500, respectively.

[0065] The delay phase-locked loop 200 is used to generate a delay chain bias voltage Vc based on the reference clock signal CLK_REF and output it to the control terminals of differential voltage-controlled delay chain module 400 and differential voltage-controlled delay chain module 500, so that the total delay of every sixteen voltage-controlled delay units in differential voltage-controlled delay chain module 400 and differential voltage-controlled delay chain module 500 is equal to one clock cycle of the reference clock signal CLK_REF.

[0066] The delay phase-locked loop 200 proposed in this embodiment of the invention adopts a differential voltage-controlled delay unit, which has the advantages of simple circuit structure, high loop stability, low phase noise, short lock time and low power consumption. Compared with the phase-locked loop in the traditional technology, it is more suitable for the application scenarios of time-to-digital converters. The delay phase-locked loop 200 proposed in this embodiment of the invention improves the ability to suppress power supply noise by adopting a differential voltage-controlled delay unit. The loop dynamically controls the bias voltage of the differential voltage-controlled delay chain, so that the voltage-controlled delay chain has a stable delay time under different operating temperatures, manufacturing processes and power supply voltages, providing a time interval with good robustness for parallel comparison time-to-digital converters.

[0067] Differential voltage-controlled delay chain module 1

[0068] See details Figure 3 The upper part of the circuit structure of the differential voltage-controlled delay chain module 400 may include:

[0069] The system consists of a 32-stage voltage-controlled delay unit and two dummy voltage-controlled delay units at the beginning and end; among which,

[0070] The positive input terminal of the first-stage dummy unit is connected to the positive output terminal of the single-ended to differential module 100, the negative input terminal of the first-stage dummy unit is connected to the negative output terminal of the single-ended to differential module 100, the control terminal of the first-stage dummy unit is connected to the control terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit, the positive output terminal of the first-stage voltage-controlled delay unit is connected to the positive input terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit, and the negative output terminal of the first-stage dummy unit is connected to the negative input terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit.

[0071] In the 32-stage voltage-controlled delay unit (VCD) unit, each stage is connected in series with the next stage. The control terminals of each stage are interconnected. The control terminal of the 32nd stage VCD unit is connected to the control terminal of the tail-end dummy unit. The positive output of the 32nd stage VCD unit is connected to the positive input of the tail-end dummy unit, and the negative output of the 32nd stage VCD unit is connected to the negative input of the tail-end dummy unit. The positive output of each stage of the 32-stage VCD unit serves as the output signal ST. p <1> ~ST p <32> The negative output terminal of each stage of the 32-stage voltage-controlled delay unit is sequentially used as the output signal terminal ST. n <1> ~ST n <32> ;

[0072] The control terminal of the tail stage dummy unit is connected to the output terminal of the delay phase-locked loop 200.

[0073] The differential voltage-controlled delay chain module 400 is used to output the first multi-phase delay signal to the time comparator array 600 based on the differential signal obtained by converting the single-ended signal START and the voltage-controlled delay units in its own stages.

[0074] Differential voltage-controlled delay chain module two

[0075] See details Figure 3 The lower half of the circuit structure of the differential voltage-controlled delay chain module 2500 may include:

[0076] The system includes a 16-stage voltage-controlled delay unit and two voltage-controlled delay units at the beginning and end, which function as dummy 1 units; among them,

[0077] The positive input terminal of the first-stage dummy1 unit is connected to the positive output terminal of the single-ended to differential module 300, the negative input terminal of the first-stage dummy1 unit is connected to the negative output terminal of the single-ended to differential module 300, the control terminal of the first-stage dummy1 unit is connected to the control terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit, the positive output terminal of the first-stage dummy1 unit is connected to the positive input terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit, and the negative output terminal of the first-stage dummy1 unit is connected to the negative input terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit.

[0078] In the sixteen-stage voltage-controlled delay unit (VCD) unit, each stage is connected in series with the next stage. The control terminals of each stage are interconnected. The control terminal of the sixteenth stage VCD unit is connected to the control terminal of the tail-stage dummy1 unit. The positive output terminal of the sixteenth stage VCD unit is connected to the positive input terminal of the tail-stage dummy1 unit, and the negative output terminal of the sixteenth stage VCD unit is connected to the negative input terminal of the tail-stage dummy1 unit. The positive output terminal of each stage VCD unit serves as the output signal terminal SP. p <1> ~SP p <16> The negative output terminal of each stage of the sixteen-stage voltage-controlled delay unit is sequentially used as the output signal terminal SP. n <1> ~SP n <32> ;

[0079] The control terminal of the primary dummy1 unit is connected to the output terminal of the delay phase-locked loop 200.

[0080] The differential voltage-controlled delay chain module 2500 is used to output a second multi-phase delay signal to the time comparator array 600 based on the differential signal obtained by converting the single-ended signal STOP and the voltage-controlled delay units in its own stages.

[0081] The differential symmetric parallel comparison time-to-digital converter proposed in this embodiment employs a single-ended to differential module and a differential voltage-controlled delay chain. This allows both the START and STOP signals to generate multi-phase delay signals through the differential voltage-controlled delay chain. By using a symmetrical circuit layout and adding voltage-controlled delay units as dummy units and dummy1 units at the beginning and end stages, the delay signal loads sent to the corresponding time comparator inputs of the two channels are completely consistent. This eliminates the discrimination error introduced by load mismatch and improves the accuracy of the differential symmetric parallel comparison time-to-digital converter.

[0082] Time comparator array

[0083] Please refer to the schematic diagram of the time comparator array of a differential symmetric parallel comparison time-to-digital converter provided in this embodiment of the invention. Figure 4 .

[0084] Specifically, the time comparator array 600 may include:

[0085] The delay chain includes a time comparator array 601 at the positive output and a time comparator array 602 at the negative output; wherein...

[0086] The delay chain positive output time comparator array 601 may include sixteen-stage time comparators; the first terminal of the nth stage time comparator in the sixteen-stage time comparators is connected to the output signal terminal ST. p <n+16> Connect the second terminal of the nth stage time comparator in the sixteen-stage time comparator to the output signal terminal SP. p <17-n> connection, the output of the nth time comparator in the sixteen-stage time comparator is used as the positive output of the delay chain. The output of the time comparator array 601 is OUT<2n-1>; 16≥n≥1.

[0087] If the output signal terminal ST of the differential voltage controlled delay chain module 400 p <n+16> The rising edge of the output signal lags behind the output signal terminal SP of the differential voltage-controlled delay chain module 2500. p When the rising edge of the output signal <17-n> occurs, the output terminal OUT<2n-1> of the time comparator array 601 at the positive output terminal of the delay chain will output a low level.

[0088] If the output signal terminal ST of the differential voltage controlled delay chain module 400 p <n+16>The rising edge of the output signal leads the output signal of the differential voltage-controlled delay chain module 2500 at the SP terminal. p When the rising edge of the output signal <17-n> occurs, the output terminal OUT<2n-1> of the time comparator array 601 at the positive output terminal of the delay chain will output a high level.

[0089] The time comparator array 602 at the negative output of the delay chain may include: fifteen stages of time comparators; wherein...

[0090] The first terminal and output signal ST of the xth stage time comparator in a 15-stage time comparator n <x+16> After inversion, the second terminal of the xth stage time comparator in the fifteen-stage time comparator is connected to the output signal terminal SP. n <16-x> connection, the output of the xth time comparator in the fifteen-stage time comparator is used as the negative output of the delay chain. The output of the time comparator array 602 is OUT<2x>, 15≥x≥1.

[0091] If the output signal terminal ST of the differential voltage controlled delay chain module 400 n <x+16> The output signal, after being inverted, has a falling edge that lags behind the output signal terminal SP of the differential voltage-controlled delay chain module 2500. n When the output signal of <16-x> falls, the output terminal OUT<2x> of the time comparator array 602 at the negative output terminal of the delay chain outputs a low level.

[0092] If the output signal terminal ST of the differential voltage controlled delay chain module 400 n <x+16> The output signal, after being inverted, has a falling edge that leads the output signal SP of the differential voltage-controlled delay chain module 2500. n When the falling edge of the output signal <16-x> occurs, the output terminal OUT<2x> of the time comparator array 602 at the negative output terminal of the delay chain will output a low level.

[0093] Specifically, the output terminal OUT<2n-1> of the time comparator array 601 at the positive output terminal of the delay chain and the output terminal OUT<2x> of the time comparator array 602 at the negative output terminal of the delay chain are combined to form the output terminal OUT of the time comparator array 600. <s>31≥s≥1, the output terminal OUT of the time comparator array 600 <s>The output is a 31-bit thermometer code.

[0094] This invention effectively utilizes the positive and negative output terminals of the differential voltage-controlled delay chain and designs a novel parallel comparison arrangement. This allows the START signal to be sequentially fed into the time comparator array from the last stage output terminal of the voltage-controlled delay chain where it resides and the first stage output terminal of the voltage-controlled delay chain where the STOP signal resides. This provides convenience for subsequent layout design and achieves a layout with a symmetrical topology and the same trace length, thereby improving the linearity of the time-to-digital converter.

[0095] encoder

[0096] The input terminal of encoder 700 is connected to the output terminal of time comparator array 600; encoder 700 converts the 31-bit thermometer code output by time comparator array 600 into a 5-bit binary code. The encoder 700 used in this embodiment of the invention is a conventional encoder; please refer to the prior art for details.

[0097] A schematic diagram illustrating the process of measuring and outputting the time interval between the START and STOP signals of a differential symmetric parallel comparison time-to-digital converter provided in this embodiment of the invention is available in the following diagram: Figure 5 . Specifically caused by Figure 5 It can be seen that, in this embodiment of the invention, the time interval between the START and STOP signals at the input of the differential symmetric parallel comparison time-to-digital converter is 20.3td. Here, td is the delay time of a single-stage voltage-controlled delay unit. After passing through the single-ended to differential module and the differential voltage-controlled delay chain, the START signal first exits from the output signal terminal ST. p <17> The STOP signal, input to the first terminal of the first-stage time comparator, passes through a single-ended to differential converter and a differential voltage-controlled delay chain, and first exits from the output signal terminal SP. p <16> The input is given to the second terminal of the first-stage time comparator, and the rising edge of the START signal reaches ST. p <17> The propagation delay between the rising edges of the output signal is greater than that between the STOP signal and the SP signal. p <16> The propagation delay between the rising edges of the output signal is increased by an additional voltage-controlled delay unit (VCD) with a delay time td. Furthermore, the rising edge of the original input START signal leads the rising edge of the STOP signal by 20.3td. Therefore, ST... p <17> The rising edge of the output signal is equal to that of SP. p <16> The rising edge of the output signal leads by 19.3td, and the output terminal OUT of the first-stage time comparator... <1> The output of ST is high, which is "1"; similarly, the START signal passes through a single-ended to differential converter and a differential voltage-controlled delay chain before exiting ST. n <26> The STOP signal, after being input to the first terminal of the twentieth-stage time comparator via an inverter, passes through a single-ended to differential converter and a differential voltage-controlled delay chain before exiting from SP. n <6> The output is inverted and input to the second terminal of the twentieth-stage time comparator. The rising edge of the START signal reaches ST. n <26> The propagation delay between the falling edges of the output signal is greater than that between the STOP signal and the SP signal. n <6> The propagation delay between the falling edges of the output signal is increased by 20 stages of voltage-controlled delay unit delay time (20td), while the rising edge of the original input START signal leads the rising edge of the STOP signal by 20.3td. Therefore, ST... n <26> The falling edge ratio of the output signal to SP n <6> The falling edge of the output signal leads by 0.3td, and the output terminal OUT of the twentieth-stage time comparator... <20> The output is high, which is "1"; the START signal passes through a single-ended to differential converter and a differential voltage-controlled delay chain before exiting from ST. p <27> The STOP signal, input to the first terminal of the 21st stage time comparator, passes through a single-ended to differential converter and a differential voltage-controlled delay chain before exiting from SP. p <6> The input is given to the second terminal of the twenty-first stage time comparator. The rising edge of the START signal reaches ST. p <27> The propagation delay between the rising edges of the output signal is greater than that between the STOP signal and the SP signal. p <6> The propagation delay between the rising edges of the output signal is increased by 21td by a 21-stage voltage-controlled delay unit, while the rising edge of the original input START signal leads the rising edge of the STOP signal by 20.3td. Therefore, ST... p <27> The rising edge of the output signal is equal to that of SP. p <6> The rising edge of the output signal lags by 0.7td, and the output terminal OUT of the twenty-first stage time comparator... <21> The output is low, which is "0"; therefore, it can be concluded that the output terminals OUT of each subsequent stage are low. <21> ~OUT <31> The output results are all low level, that is, all are "0", forming a 31-bit thermometer code, which is then decoded into binary code "10101" in the encoder module, indicating that the calculation result is 21td. The entire differential symmetric parallel comparison time-to-digital converter completes the measurement of the input time interval of 20.3td between the rising edge of the START signal and the rising edge of the STOP signal.

[0098] The differential symmetric parallel comparison time-to-digital converter provided by this invention features a delay phase-locked loop (PLL) with advantages such as simple circuit structure, high loop stability, low phase noise, short lock time, and low power consumption. Compared to PLLs, it is more suitable for the application scenarios of time-to-digital converters. The delay PLL of this invention uses a differential voltage-controlled delay unit to improve the suppression of power supply noise. The loop dynamically controls the bias voltage of the differential voltage-controlled delay chain module, enabling the differential voltage-controlled delay chain module to have a stable delay time under different operating temperatures, manufacturing processes, and power supply voltages, providing a robust time interval for the parallel comparison time-to-digital converter.

[0099] This differential symmetrical parallel comparison time-to-digital converter employs a single-ended to differential module and a differential voltage-controlled delay chain module. This allows both the START and STOP signals to generate multi-phase delayed signals through the delay chain. The symmetrical circuit layout, along with voltage-controlled delay units added at the beginning and end as dummy and dummy1 units, ensures that the loads of the delayed signals fed into the corresponding time comparator inputs of the two channels are completely identical. This eliminates the discrimination error introduced by load mismatch and improves the accuracy of the parallel comparison time-to-digital converter.

[0100] The differential voltage-controlled delay chain module with differential voltage-controlled delay unit proposed in this invention improves the voltage-controlled delay chain's ability to suppress power supply noise. It adopts a symmetrical circuit layout, enabling the STOP signal to also generate a multi-phase delayed signal through the differential voltage-controlled delay chain. Furthermore, it introduces a novel parallel comparison arrangement, eliminating load mismatch at the output terminals of each event comparator and improving the accuracy and linearity of the parallel comparison time-to-digital converter.

[0101] In summary, the differential symmetric parallel comparison time-to-digital converter designed in this invention has good power supply noise suppression capability, effectively improving the linearity and accuracy of the time-to-digital converter, and has broad application prospects in the field of lidar optical signal receiver system technology and high-precision time-to-digital conversion system.

[0102] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.< / s> < / s> < / s> < / s>

Claims

1. A differential symmetric parallel comparison time-to-digital converter, characterized in that, include: The system includes a single-ended to differential module 1 (100), a delay phase-locked loop (200), a single-ended to differential module 2 (300), a differential voltage-controlled delay chain module 1 (400), a differential voltage-controlled delay chain module 2 (500), a time comparator array (600), and an encoder (700); among which, The single-ended to differential module (100) is used to convert the single-ended signal START into a differential signal and output it to the differential voltage-controlled delay chain module (400); The single-ended to differential module 2 (300) is used to convert the single-ended signal STOP into a differential signal and output it to the differential voltage-controlled delay chain module 2 (500); The delay phase-locked loop (200) employs a differential voltage-controlled delay unit to generate a delay chain bias voltage Vc based on the reference clock signal CLK_REF and output it to the differential voltage-controlled delay chain module one (400) and the differential voltage-controlled delay chain module two (500), such that the total delay of each of the sixteen voltage-controlled delay units in the differential voltage-controlled delay chain module one (400) and the differential voltage-controlled delay chain module two (500) is equal to one clock cycle of the reference clock signal CLK_REF; The differential voltage-controlled delay chain module (400) is used to output a first multi-phase delay signal to the time comparator array (600) based on the differential signal obtained by converting the single-ended signal START and the voltage-controlled delay units at each stage in itself. The differential voltage-controlled delay chain module 2 (500) is used to output a second multi-phase delay signal to the time comparator array (600) based on the differential signal obtained by converting the single-ended signal STOP and the voltage-controlled delay units in itself. The time comparator array (600) is used to compare each bit of the first multi-phase delay signal and the second multi-phase delay signal in sequence, and output the corresponding thermometer code; The encoder (700) is used to convert the thermometer code into binary code and output the binary code as the output result.

2. The differential symmetric parallel comparison time-to-digital converter according to claim 1, characterized in that, The circuit structure of the differential voltage-controlled delay chain module one (400) includes: The system consists of a 32-stage voltage-controlled delay unit and two dummy voltage-controlled delay units at the beginning and end; among which, The positive input terminal of the first-stage dummy unit is connected to the positive output terminal of the single-ended to differential module (100), the negative input terminal of the first-stage dummy unit is connected to the negative output terminal of the single-ended to differential module (100), the control terminal of the first-stage dummy unit is connected to the control terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit, the positive output terminal of the first-stage dummy unit is connected to the positive input terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit, and the negative output terminal of the first-stage dummy unit is connected to the negative input terminal of the first-stage voltage-controlled delay unit in the thirty-two-stage voltage-controlled delay unit. Each stage of the 32-stage voltage-controlled delay unit is connected in series with the next stage. The control terminals of each stage are interconnected. The control terminal of the 32nd stage voltage-controlled delay unit is connected to the control terminal of the tail-stage dummy unit. The positive output terminal of the 32nd stage voltage-controlled delay unit is connected to the positive input terminal of the tail-stage dummy unit, and the negative output terminal of the 32nd stage voltage-controlled delay unit is connected to the negative input terminal of the tail-stage dummy unit. The positive output terminal of each stage of the 32-stage voltage-controlled delay unit serves as the output signal terminal ST. p <1> ~ST p <32> The negative output terminal of each stage of the thirty-two voltage-controlled delay unit is sequentially used as the output signal terminal ST. n <1> ~ST n <32> ; The control terminal of the tail-stage dummy unit is connected to the output terminal of the delay phase-locked loop (200).

3. A differential symmetric parallel comparison time-to-digital converter according to claim 2, characterized in that, The circuit structure of the differential voltage-controlled delay chain module two (500) includes: The system includes a 16-stage voltage-controlled delay unit and two voltage-controlled delay units at the beginning and end, which function as dummy 1 units; among them, The positive input terminal of the first-stage dummy1 unit is connected to the positive output terminal of the single-ended to differential module two (300), the negative input terminal of the first-stage dummy1 unit is connected to the negative output terminal of the single-ended to differential module two (300), the control terminal of the first-stage dummy1 unit is connected to the control terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit, the positive output terminal of the first-stage dummy1 unit is connected to the positive input terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit, and the negative output terminal of the first-stage dummy1 unit is connected to the negative input terminal of the first-stage voltage-controlled delay unit in the sixteen-stage voltage-controlled delay unit. Each stage of the sixteen-stage voltage-controlled delay unit (VDCD) is connected in series with the next stage VDCD. The control terminals of each stage are interconnected. The control terminal of the sixteenth stage VDCD is connected to the control terminal of the tail-stage dummy1 unit. The positive output terminal of the sixteenth stage VDCD is connected to the positive input terminal of the tail-stage dummy1 unit, and the negative output terminal of the sixteenth stage VDCD is connected to the negative input terminal of the tail-stage dummy1 unit. The positive output terminal of each stage of the sixteen-stage VDCD serves as the output signal terminal SP. p <1> ~SP p <16> The negative output terminal of each stage of the sixteen-stage voltage-controlled delay unit is sequentially used as the output signal terminal SP. n <1> ~SP n <32> ; The control terminal of the primary dummy1 unit is connected to the output terminal of the delay phase-locked loop (200).

4. A differential symmetric parallel comparison time-to-digital converter according to claim 3, characterized in that, The time comparator array (600) includes: The delay chain includes a time comparator array (601) at the positive output terminal and a time comparator array (602) at the negative output terminal; wherein, The time comparator array (601) at the positive output of the delay chain includes sixteen stages of time comparators; the first terminal of the nth stage time comparator in the sixteen stages is connected to the output signal terminal ST. p <n+16> The connection is made between the second terminal of the nth stage time comparator in the sixteen-stage time comparator and the output signal terminal SP. p <17-n> connection, the output of the nth time comparator in the sixteen-level time comparator is used as the output of the time comparator array (601) of the delay chain positive output terminal OUT<2n-1>; 16≥n≥1.

5. A differential symmetric parallel comparison time-to-digital converter according to claim 4, characterized in that, The time comparator array (602) at the negative output of the delay chain includes: fifteen stages of time comparators; wherein, The first terminal and the output signal terminal ST of the xth stage time comparator in the fifteen-stage time comparator n <x+16> After inversion, the second terminal of the xth stage time comparator in the fifteen-stage time comparator is connected to the output signal terminal SP. n <16-x> connection, the output of the xth time comparator in the fifteen-level time comparator is used as the output of the time comparator array (602) of the delay chain negative output terminal OUT<2x>, 15≥x≥1.

6. A differential symmetric parallel comparison time-to-digital converter according to claim 5, characterized in that, The output terminal OUT<2n-1> of the time comparator array (601) at the positive output end of the delay chain and the output terminal OUT<2x> of the time comparator array (602) at the negative output end of the delay chain are combined to form the output terminal OUT of the time comparator array (600). <s>31≥s≥1, the output terminal OUT of the time comparator array (600) <s> The output is a 31-bit thermometer code.< / s> < / s> <s> <s> 7. A differential symmetric parallel comparison time-to-digital converter according to claim 6, characterized in that, The input terminal of the encoder (700) is connected to the output terminal of the time comparator array (600); the encoder (700) converts the 31-bit thermometer code output by the time comparator array (600) into a 5-bit binary code. < / s> < / s>

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