Driving substrate, preparation method thereof and display panel

Abstract

Embodiments of the present application disclose a driving substrate, a preparation method thereof and a display panel. The driving substrate of the embodiments of the present application is provided with a first thin film transistor in a pixel area and a second thin film transistor in a frame area. The first active layer of the first thin film transistor comprises an amorphous silicon layer and a microcrystalline silicon layer arranged in stack. The channel of the second active layer of the second thin film transistor comprises polycrystalline silicon, so that the mobility of the second thin film transistor is greater than that of the first thin film transistor. Since the polycrystalline silicon can be formed by crystallization of the amorphous silicon layer and the microcrystalline silicon layer arranged in stack as a whole, the process is simplified, so that the mobility of the second thin film transistor in the frame area can be improved while the cost is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving substrate, its fabrication method, and a display panel. Background Technology

[0002] In the a-Si process array substrate of related technologies, compared with the thin film transistors outside the plane (border area), the thin film transistors inside the plane (pixel area) need to have lower mobility. However, the use of uniform amorphous silicon as the channel of the thin film transistors results in insufficient mobility of the thin film transistors outside the plane.

[0003] For example, in demultiplexing circuits, time-division multiplexing is required during data signal input to reduce the number of source driver chip pins and the number of driver chips. Therefore, the thin-film transistors in the demultiplexing circuit need to have a high mobility. To meet these requirements, the current approach is to replace the out-of-plane a-Si thin-film transistors with IGZO thin-film transistors. However, this method is costly and makes the fabrication process of the entire array substrate more complicated. Summary of the Invention

[0004] This application provides a driving substrate, a method for fabricating the same, and a display panel, which can improve the mobility of the second thin-film transistor located in the bezel area while reducing costs.

[0005] This application provides a driving substrate, including a pixel region and a border region, wherein the border region is located on at least one side of the pixel region, and the driving substrate includes:

[0006] Substrate;

[0007] A first thin-film transistor is disposed on the substrate and located in the pixel region. The first thin-film transistor includes a first active layer, which includes a first amorphous silicon layer and a first microcrystalline silicon layer. The first microcrystalline silicon layer is disposed on the side of the first amorphous silicon layer away from the substrate.

[0008] A second thin-film transistor is disposed on the substrate and located in the border region. The second thin-film transistor includes a second active layer, the channel of which includes polysilicon. The electron mobility of the second thin-film transistor is greater than that of the first thin-film transistor.

[0009] Optionally, in some embodiments of this application, the first active layer includes a first source contact, a first drain contact, and a first channel. The first source contact is connected to one side of the first channel, and the first drain contact is connected to the other side of the first channel. The first source contact, the first drain contact, and the first channel all include the first amorphous silicon layer and the first microcrystalline silicon layer stacked together.

[0010] The second active layer includes a second source contact, a second drain contact, and a second channel. The second source contact is connected to one side of the second channel, and the second drain contact is connected to the other side of the second channel. The materials of the second source contact, the second drain contact, and the second channel are all polycrystalline silicon.

[0011] Optionally, in some embodiments of this application, the first active layer further includes a first source contact, a first drain contact, and a first channel. The first source contact is connected to one side of the first channel, and the first drain contact is connected to the other side of the first channel. The first source contact, the first drain contact, and the first channel all include the first amorphous silicon layer and the first microcrystalline silicon layer stacked together.

[0012] The second active layer further includes a second source contact, a second drain contact, and a second channel. The second source contact is connected to one side of the second channel, and the second drain contact is connected to the other side of the second channel. The second channel is the polycrystalline silicon. The second source contact includes a second amorphous silicon layer and a second microcrystalline silicon layer. The second microcrystalline silicon layer is directly disposed on the side of the second amorphous silicon layer away from the substrate. The second drain contact includes a third amorphous silicon layer and a third microcrystalline silicon layer. The third microcrystalline silicon layer is disposed on the side of the third amorphous silicon layer away from the substrate.

[0013] Optionally, in some embodiments of this application, the polycrystalline silicon is formed by stacking an amorphous silicon layer and a microcrystalline silicon layer as a whole, wherein the amorphous silicon layer is disposed in the same layer as the first amorphous silicon layer, and the microcrystalline silicon layer is disposed in the same layer as the first microcrystalline silicon layer.

[0014] Optionally, in some embodiments of this application, the grain width of the polycrystalline silicon is greater than 2 micrometers.

[0015] Optionally, in some embodiments of this application, the grain width of the polycrystalline silicon is greater than or equal to 6 micrometers.

[0016] Optionally, in some embodiments of this application, the thickness of the first microcrystalline silicon layer is between 10% and 30% of the thickness of the first active layer.

[0017] Optionally, in some embodiments of this application, the driving substrate further includes a gate insulating layer, the first thin-film transistor includes a first gate, the second thin-film transistor includes a second gate, the first gate and the second gate are both disposed on the substrate, the gate insulating layer covers the first gate and the second gate, the first active layer is disposed on the side of the gate insulating layer away from the substrate, and the second active layer is disposed on the side of the gate insulating layer away from the substrate.

[0018] In the orthographic projection pattern of the driving substrate, the first active layer overlaps with the first gate, and the second active layer overlaps with the second gate;

[0019] The gate insulating layer includes a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer is disposed on the side of the silicon oxide layer away from the substrate.

[0020] Optionally, in some embodiments of this application, the thickness of the silicon nitride layer is greater than the thickness of the silicon oxide layer.

[0021] Optionally, in some embodiments of this application, the thickness of the silicon oxide layer is less than or equal to 250 nanometers, and the thickness of the silicon nitride layer is between 200 nanometers and 400 nanometers.

[0022] Optionally, in some embodiments of this application, the first thin-film transistor further includes a first ohmic contact layer, a first source, and a first drain, and the second thin-film transistor further includes a second ohmic contact layer, a second source, and a second drain;

[0023] One first ohmic contact layer is disposed on the first source contact portion, and another first ohmic contact layer is disposed on the first drain contact portion. The first source electrode is connected to the first source contact portion through the first ohmic contact layer, and the first drain electrode is connected to the first drain contact portion through the first ohmic contact layer.

[0024] One second ohmic contact layer is disposed on the second source contact portion, and another second ohmic contact layer is disposed on the second drain contact portion. The second source electrode is connected to the second source contact portion through the second ohmic contact layer, and the second drain electrode is connected to the second drain contact portion through the second ohmic contact layer.

[0025] Optionally, in some embodiments of this application, the driving substrate includes a demultiplexing circuit, the demultiplexing circuit includes a plurality of second thin-film transistors, the gate of one of the second thin-film transistors is connected to a signal control terminal, the first terminals of the plurality of second thin-film transistors are all connected to a data signal input terminal, and the second terminal of one of the second thin-film transistors is connected to a data line.

[0026] Accordingly, this application also provides a display panel, which includes a driving substrate as described in any of the above embodiments.

[0027] This application also provides a method for preparing a driving substrate, which includes the following steps:

[0028] A first gate and a second gate are formed on a substrate, wherein the first gate is located in the pixel region and the second gate is located in the border region;

[0029] A gate insulating layer is formed on the substrate, the gate insulating layer covering the first gate and the second gate;

[0030] An amorphous silicon material layer and a microcrystalline silicon material layer are sequentially formed on the gate insulating layer. The amorphous silicon material layer and the microcrystalline silicon material layer are patterned to form a first active layer located in the pixel region and a second active layer located in the border region. The first active layer includes a first source contact, a first drain contact, and a first channel. The first source contact is connected to one side of the first channel, and the first drain contact is connected to the other side of the first channel. The first source contact, the first drain contact, and the first channel all include a first amorphous silicon layer and a first microcrystalline silicon layer stacked together.

[0031] At least a portion of the second active layer is subjected to dehydrogenation and crystallization treatment to form polycrystalline silicon. The second active layer includes a second source contact, a second drain contact, and a second channel. The second source contact is connected to one side of the second channel, and the second drain contact is connected to the other side of the second channel. The second channel is the polycrystalline silicon.

[0032] An ohmic contact material layer and a source / drain metal layer are sequentially formed on the side of the first active layer and the second active layer away from the substrate, and the ohmic contact material layer and the source / drain metal layer are patterned to form a first source, a first drain, a first ohmic contact layer, a second ohmic contact layer, a second source, and a second drain. The first gate, the first active layer, the first ohmic contact layer, the first source, and the first drain constitute a first thin-film transistor. The second gate, the second active layer, the second ohmic contact layer, the second source, and the second drain constitute a second thin-film transistor. The first source is connected to the first source contact portion through a first ohmic contact layer, the first drain is connected to the first drain contact portion through another first ohmic contact layer, the second source is connected to the second source contact portion through a second ohmic contact layer, and the second drain is connected to the second drain contact portion through another second ohmic contact layer.

[0033] In this embodiment, the driving substrate has a first thin-film transistor in the pixel region and a second thin-film transistor in the border region. The first active layer of the first thin-film transistor includes a stacked amorphous silicon layer and a microcrystalline silicon layer, and the channel of the second active layer of the second thin-film transistor includes polycrystalline silicon, so that the mobility of the second thin-film transistor is greater than that of the first thin-film transistor. Furthermore, since polycrystalline silicon can be crystallized from the stacked amorphous silicon layer and the microcrystalline silicon layer as a whole, the process is simplified, and this application can improve the mobility of the second thin-film transistor located in the border region while reducing costs. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the driving substrate provided in the embodiments of this application;

[0035] Figure 2 This is another structural schematic diagram of the driving substrate provided in the embodiments of this application;

[0036] Figure 3 This is another structural schematic diagram of the driving substrate provided in the embodiments of this application;

[0037] Figure 4 This is a driving circuit diagram of the driving substrate provided in the embodiments of this application;

[0038] Figure 5 This is a schematic diagram of step B1 of the method for preparing the driving substrate provided in the embodiments of this application;

[0039] Figure 6 This is a schematic diagram of step B2 of the method for preparing the driving substrate provided in the embodiments of this application;

[0040] Figure 7 This is a schematic diagram of step B3 of the method for preparing the driving substrate provided in the embodiments of this application;

[0041] Figure 8 This is a schematic diagram of step B4 of the method for preparing the driving substrate provided in the embodiments of this application;

[0042] Figure 9 This is a schematic diagram of step B9 of the method for preparing the driving substrate provided in the embodiments of this application;

[0043] Figure 10 This is a schematic diagram of step B10 of the method for preparing the driving substrate provided in the embodiments of this application. Detailed Implementation

[0044] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc., are used only as indications and do not impose numerical requirements or establish a sequence.

[0045] This application provides a driving substrate, a method for fabricating the same, and a display panel, which are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0046] Please refer to Figure 1 This application provides a driving substrate 100, including a pixel region AA and a border region NA, wherein the border region NA is located on at least one side of the pixel region AA. The driving substrate 100 includes a substrate 11, a first thin-film transistor T1, and a second thin-film transistor T2.

[0047] A first thin-film transistor T1 is disposed on a substrate 11 and located in pixel region AA. The first thin-film transistor T1 includes a first active layer y1, which includes a first amorphous silicon layer y11 and a first microcrystalline silicon layer y12. The first microcrystalline silicon layer y12 is disposed on the side of the first amorphous silicon layer y11 away from the substrate 11.

[0048] A second thin-film transistor T2 is disposed on the substrate 11 and located in the border region NA. The second thin-film transistor T2 includes a second active layer y2, the channel of which comprises polysilicon. The electron mobility of the second thin-film transistor T2 is greater than that of the first thin-film transistor T1.

[0049] In this embodiment, the driving substrate 100 has a first thin-film transistor T1 disposed in the pixel region AA and a second thin-film transistor T2 disposed in the border region NA. The first active layer y1 of the first thin-film transistor T1 includes a stacked amorphous silicon layer y11 and a microcrystalline silicon layer y12. The channel of the second active layer y2 of the second thin-film transistor T2 includes polycrystalline silicon, which makes the mobility of the second thin-film transistor T2 greater than that of the first thin-film transistor T1. Since polycrystalline silicon can be crystallized from the stacked amorphous silicon layer and the microcrystalline silicon layer as a whole, i.e., the whole is crystallized once by laser, the process is simplified, so that this application can reduce the cost while increasing the mobility of the second thin-film transistor T2 located in the border region NA.

[0050] Optionally, the first microcrystalline silicon layer y12 is directly disposed on the first amorphous silicon layer y11.

[0051] Optionally, the first thin-film transistor T1 and the second thin-film transistor T2 can each be a top-gate, bottom-gate, or dual-gate thin-film transistor. This application uses the example of both the first thin-film transistor T1 and the second thin-film transistor T2 being bottom-gate thin-film transistors for illustration, but it is not limited thereto.

[0052] Optionally, the first active layer y1 further includes a first source contact ys1, a first drain contact yd1, and a first channel yg1. The first source contact ys1 is connected to one side of the first channel yg1, and the first drain contact yd1 is connected to the other side of the first channel yg1. The first source contact ys1, the first drain contact yd1, and the first channel yg1 each include a first amorphous silicon layer y11 and a first microcrystalline silicon layer y12 stacked together.

[0053] The second active layer y2 also includes a second source contact ys2, a second drain contact yd2, and a second channel yg2. The second source contact ys2 is connected to one side of the second channel yg2, and the second drain contact yd2 is connected to the other side of the second channel yg2. The second channel yg2 is polycrystalline silicon.

[0054] In this case, compared to the first channel yg1 of the first thin film transistor T1, which is composed of stacked amorphous silicon layers and microcrystalline silicon layers, the second channel yg2 of the second thin film transistor T2 is composed of polycrystalline silicon, which has a higher electron mobility.

[0055] In this embodiment, the second source contact ys2 includes a second amorphous silicon layer y22 and a second microcrystalline silicon layer y23, with the second microcrystalline silicon layer y23 disposed on the side of the second amorphous silicon layer y22 away from the substrate 11. The second drain contact yd2 includes a third amorphous silicon layer y24 and a third microcrystalline silicon layer y25, with the third microcrystalline silicon layer y25 disposed on the side of the third amorphous silicon layer y24 away from the substrate 11.

[0056] The second channel yg2 is polysilicon, meaning it is a single-layer polysilicon layer y21. The polysilicon layer y21 extends from the channel region of the second active layer y2 and is disposed in the source and drain contact regions of the second active layer y2. This means that the second source contact ys2 also includes a portion of the polysilicon layer y21, and the second drain contact yd2 also includes a portion of the polysilicon layer y21.

[0057] In other words, this embodiment employs a localized crystallization method, allowing the stacked amorphous silicon layer and microcrystalline silicon layer to be locally crystallized as a whole. Compared to full-surface crystallization, this reduces process costs and improves process efficiency. Furthermore, the portion of the polycrystalline silicon layer y21 located in the source and drain contact regions can enhance the conductivity of the second source contact ys2 and the second drain contact yd2.

[0058] It is understood that the polycrystalline silicon layer (polysilicon) y21 is formed by crystallizing stacked amorphous silicon layers and microcrystalline silicon layers as a whole. The amorphous silicon layer is disposed on the same layer as the first amorphous silicon layer y11, and the microcrystalline silicon layer is disposed on the same layer as the first microcrystalline silicon layer y12. Since the polycrystalline silicon in the second active layer y2 is formed by crystallizing the same material as the first active layer y1 of the pixel region AA, no additional high-mobility semiconductor material is required, which can reduce the process cost.

[0059] In addition, compared to crystallizing polycrystalline silicon using amorphous silicon, crystallizing polycrystalline silicon using stacked amorphous silicon layers and microcrystalline silicon layers results in a significant reduction in crystallization energy required for the same thickness, for example, by more than 30%. This is because the microcrystalline silicon layer is already crystalline silicon, and during the conversion to polycrystalline silicon, the microcrystalline silicon layer can act as a seed crystal to induce rapid crystallization of amorphous silicon.

[0060] Optionally, the electron mobility of the second thin-film transistor T2 is greater than or equal to 150 cm⁻¹. 2 / Vs, for example, could be 155cm 2 / Vs、160cm 2 / Vs、165cm 2 / Vs、170cm 2 / Vs、175cm 2 / Vs、180cm 2 / Vs、185cm 2 / Vs、190cm 2 / Vs、195cm 2 / Vs or 200cm 2 / Vs etc.

[0061] Please refer to Figure 2 In some embodiments, the polysilicon layer y21 is located only in the channel region of the second thin-film transistor T2.

[0062] Please refer to Figure 3 In some embodiments, the second source contact ys2, the second drain contact yd2, and the second channel yg2 are all made of polycrystalline silicon, meaning the entire second active layer y2 is a polycrystalline silicon layer y21. Crystallization of the entire second active layer y2 can be achieved through regional laser scanning crystallization, improving processing efficiency and further enhancing the conductivity of the second source contact ys2 and the second drain contact yd2.

[0063] Optionally, the grain width of the polycrystalline silicon layer y21 is greater than 2 micrometers. For example, the grain width of the polycrystalline silicon layer y21 can be 2.1 micrometers, 2.2 micrometers, 2.3 micrometers, 2.5 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, or 7 micrometers, etc.

[0064] Understandably, with the same channel width, the larger the grain width and the fewer the grain boundaries of the polycrystalline silicon layer y21, the higher the channel mobility.

[0065] Optionally, the grain width of the polycrystalline silicon layer y21 is greater than or equal to 6 micrometers. When using a blue laser diode annealing process, the grain width of the crystalline silicon layer y21 can be greater than or equal to 6 micrometers, further improving the channel mobility. For example, the grain width of the polycrystalline silicon layer y21 can be 6 micrometers, 6.1 micrometers, 6.2 micrometers, 6.3 micrometers, 6.4 micrometers, 6.5 micrometers, 6.6 micrometers, 6.7 micrometers, 6.8 micrometers, 6.9 micrometers, 7 micrometers, 7.5 micrometers, or 8 micrometers, etc.

[0066] Optionally, the thickness of the first microcrystalline silicon layer y12 is between 10% and 30% of the thickness of the first active layer y1.

[0067] The greater the proportion of the thickness of the first microcrystalline silicon layer y12, the higher the mobility of the first active layer y1 and the longer its film formation time. However, when the thickness of the first microcrystalline silicon layer y12 reaches a certain level, the efficiency of increasing its mobility will become lower and lower. Therefore, the thickness of the first microcrystalline silicon layer y12 is set to account for 10% to 30% of the thickness of the first active layer y1, so as to maximize the benefits of the mobility and film formation time of the first active layer y1.

[0068] Optionally, the thickness of the first microcrystalline silicon layer y12 is between 10 nanometers and 30 nanometers, for example, it can be 10 nanometers, 11 nanometers, 12 nanometers, 13 nanometers, 14 nanometers, 15 nanometers, 16 nanometers, 17 nanometers, 18 nanometers, 19 nanometers, 20 nanometers, 21 nanometers, 22 nanometers, 23 nanometers, 24 nanometers, 25 nanometers, 26 nanometers, 27 nanometers, 28 nanometers, 29 nanometers or 30 nanometers.

[0069] Optionally, the thickness of the first active layer y1 is between 90 nanometers and 120 nanometers, for example, it can be 90 nanometers, 95 nanometers, 100 nanometers, 105 nanometers, 110 nanometers, 115 nanometers or 120 nanometers.

[0070] Optionally, the driving substrate 100 further includes a gate insulating layer 12. A first thin-film transistor T1 includes a first gate 131. A second thin-film transistor T2 includes a second gate 132. Both the first gate 131 and the second gate 132 are disposed on the substrate 11. The gate insulating layer 12 covers the first gate 131 and the second gate 132. A first active layer y1 is disposed on the side of the gate insulating layer 12 away from the substrate 11. A second active layer y2 is disposed on the side of the gate insulating layer 12 away from the substrate 11.

[0071] In the orthographic projection pattern of the driving substrate 100, the first active layer y1 overlaps with the first gate 131. The second active layer y2 overlaps with the second gate 132.

[0072] The gate insulating layer 12 includes a silicon oxide layer 121 and a silicon nitride layer 122. The silicon nitride layer 122 is disposed on the side of the silicon oxide layer 121 away from the substrate 11.

[0073] It is important to understand that the thickness of the gate insulating layer 12 affects the threshold voltage of the thin-film transistor. Specifically, in the fabrication process of the active layer, an amorphous silicon material layer is stacked with a microcrystalline silicon material layer for full-surface deposition, followed by patterning, and polycrystalline silicon is formed by local crystallization of the stacked layers in the border region NA.

[0074] That is, the bottom layer of the channel of the first active layer y1 in the pixel area AA is the first amorphous silicon layer y11, and the channel of the second active layer y2 in the border area NA is polycrystalline silicon.

[0075] Since the interface defects of amorphous silicon in the amorphous silicon process cannot be matched with silicon oxide, silicon nitride layer 122 is used to provide a stable interface for the first amorphous silicon layer y11 to improve the stability of the first active layer y1.

[0076] In addition, when a thin-film transistor with an amorphous silicon channel is turned on, electrons in the amorphous silicon migrate downwards and combine with defects in silicon oxide, resulting in an increase in holes in the amorphous silicon, which in turn causes the threshold voltage to drift to the right.

[0077] Therefore, the thickness of the silicon nitride layer 122 is set to be greater than the thickness of the silicon oxide layer 121 to reduce the risk of rightward drift of the threshold voltage of the first thin film transistor T1.

[0078] Optionally, the thickness of the silicon oxide layer 121 is less than or equal to 250 nanometers. For example, the thickness of the silicon oxide layer 121 can be 250 nanometers, 240 nanometers, 230 nanometers, 220 nanometers, 210 nanometers, 200 nanometers, 190 nanometers, 180 nanometers, 170 nanometers, 160 nanometers, 150 nanometers, or 140 nanometers, etc.

[0079] The silicon oxide layer 121 has a thickness of less than or equal to 250 nanometers to reduce the risk of electrons in amorphous silicon combining with the silicon oxide layer 121, thereby reducing the risk of rightward drift of the threshold voltage of the first thin film transistor T1.

[0080] The thickness of the silicon nitride layer 122 is between 200 nanometers and 400 nanometers. For example, the thickness of the silicon nitride layer 122 can be 200 nanometers, 210 nanometers, 220 nanometers, 230 nanometers, 240 nanometers, 250 nanometers, 260 nanometers, 270 nanometers, 280 nanometers, 290 nanometers, 300 nanometers, 310 nanometers, 320 nanometers, 330 nanometers, 340 nanometers, 350 nanometers, 360 nanometers, 370 nanometers, 380 nanometers, 390 nanometers, or 400 nanometers.

[0081] Furthermore, for the same thickness and area, the hydrogen content of the silicon nitride layer 122 is much greater than that of the silicon oxide layer 121. When the second active layer y2 of the border region NA undergoes dehydrogenation, the silicon nitride layer 122 will also release hydrogen. The thicker the silicon nitride layer 122 is, the higher its hydrogen content will be, and the higher the risk of hydrogen explosion during dehydrogenation.

[0082] Therefore, the thickness of the silicon nitride layer 122 is between 200 nanometers and 400 nanometers, which can reduce the risk of rightward drift of the threshold voltage of the first thin film transistor T1, and also reduce the risk of hydrogen explosion during the dehydrogenation treatment of the second active layer y2.

[0083] Optionally, the first thin-film transistor T1 further includes a first ohmic contact layer 141, a first source 151, and a first drain 152. The second thin-film transistor T2 further includes a second ohmic contact layer 142, a second source 153, and a second drain 154.

[0084] A first ohmic contact layer 141 is disposed on the first source contact ys1, and another first ohmic contact layer 141 is disposed on the first drain contact yd1. The first source electrode 151 is connected to the first source contact ys1 through the first ohmic contact layer 141, and the first drain electrode 152 is connected to the first drain contact yd1 through the first ohmic contact layer 141.

[0085] A second ohmic contact layer 142 is disposed on the second source contact ys2, and another second ohmic contact layer 142 is disposed on the second drain contact yd2. The second source electrode 153 is connected to the second source contact ys2 through the second ohmic contact layer 142, and the second drain electrode 154 is connected to the second drain contact yd2 through the second ohmic contact layer 142.

[0086] Optionally, the driving substrate 100 may also include a protective layer 16 and an electrode 17. The protective layer 16 covers the first thin film transistor T1 and the second thin film transistor T2, and the electrode 17 is connected to the first drain contact yd1 of the first thin film transistor T1 through a via.

[0087] Optionally, the driving substrate 100 can be an array substrate for liquid crystal display or a driving backplane for electroluminescent display.

[0088] Optional, such as Figure 4 As shown, the driving substrate 100 is an array substrate, and the second thin film transistor T2 serves as the switching device for the demultiplexing circuit Dex of the driving substrate 100.

[0089] The driving substrate 100 includes a demultiplexing circuit Dex. The demultiplexing circuit Dex includes a plurality of second thin-film transistors T2. The gate of one second thin-film transistor T2 is connected to a signal control terminal Data. The first terminals of the plurality of second thin-film transistors T2 are all connected to a data signal input terminal, and the second terminal of one second thin-film transistor T2 is connected to a data line. A data line is connected to a plurality of first thin-film transistors T1.

[0090] The demultiplexing circuit Dex includes three second thin-film transistors T2, the first terminals of which are all connected to the data signal input terminal Data. The gate of the first second thin-film transistor T2 is connected to the first control signal terminal De1, and the second terminal of the first second thin-film transistor T2 is connected to the first terminal of a first thin-film transistor T1, which is connected to an electrode 17 (corresponding to the red pixel R).

[0091] The gate of the second thin-film transistor T2 is connected to the second control signal terminal De2, and the second electrode of the second thin-film transistor T2 is connected to the first electrode of another first thin-film transistor T1. The second electrode of the other first thin-film transistor T1 is connected to another electrode 17 (corresponding to the green pixel G).

[0092] The gate of the third second thin film transistor T2 is connected to the third control signal terminal De3, and the second electrode of the third second thin film transistor T2 is connected to the first electrode of another first thin film transistor T1. The second electrode of the other first thin film transistor T1 is connected to another electrode 17 (corresponding to the blue pixel B).

[0093] The gate of the first thin-film transistor T1 in the first row is connected to the scan signal terminal Scan1. The gate of the first thin-film transistor T1 in the second row is connected to the scan signal terminal Scan2.

[0094] By setting up the demultiplexing circuit Dex, the number of data signal input terminals can be reduced, thereby reducing the number of source driver chips.

[0095] Accordingly, this application also provides a method for preparing a driving substrate 100, which includes the following steps:

[0096] Step B1, please refer to Figure 5 A first gate 131 and a second gate 132 are formed on the substrate 11. The first gate 131 is located in the pixel region AA, and the second gate 132 is located in the border region NA. The border region NA is located on at least one side of the pixel region AA.

[0097] Optionally, the substrate 11 can be a rigid substrate or a flexible substrate. The material of the substrate 11 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene dicarboxylate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefins, polyimide, or polyurethane.

[0098] The first gate 131 and the second gate 132 are formed using the same photolithography process and are made of the same material. The first gate 131 and the second gate 132 can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, an alloy containing any of the aforementioned metal elements, or an alloy combining any of the aforementioned metal elements. Furthermore, the first gate 131 and the second gate 132 can have a single-layer structure or a stacked structure of two or more layers.

[0099] The thickness of the first gate 131 and the second gate 132 is between 2000 angstroms and 6000 angstroms, for example, it can be 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms or 6000 angstroms.

[0100] Step B2, please refer to Figure 6 A gate insulating layer 12 is formed on the substrate 11, and the gate insulating layer 12 covers the first gate 131 and the second gate 132.

[0101] Alternatively, a silicon oxide layer 121 and a silicon nitride layer 122 can be sequentially formed on the substrate 11 using a chemical vapor deposition process.

[0102] Optionally, the thickness of the silicon oxide layer 121 is less than or equal to 250 nanometers. The thickness of the silicon nitride layer 122 is between 200 nanometers and 400 nanometers.

[0103] Step B3, please refer to Figure 7 An amorphous silicon material layer fjg and a microcrystalline silicon material layer wjg are sequentially formed on the gate insulating layer 12. The amorphous silicon material layer fjg and the microcrystalline silicon material layer wjg are patterned to form a first active layer y1 located in the pixel region AA and a second active layer y2 located in the border region NA. The first active layer y1 includes a first source contact ys1, a first drain contact yd1 and a first channel yg1. The first source contact ys1 is connected to one side of the first channel yg1 and the first drain contact yd1 is connected to the other side of the first channel yg1. The first source contact ys1, the first drain contact yd1 and the first channel yg1 all include a first amorphous silicon layer y11 and a first microcrystalline silicon layer y12 stacked together.

[0104] Optionally, the thickness of the microcrystalline silicon material layer wjg is between 10 nanometers and 30 nanometers, for example, it can be 10 nanometers, 11 nanometers, 12 nanometers, 13 nanometers, 14 nanometers, 15 nanometers, 16 nanometers, 17 nanometers, 18 nanometers, 19 nanometers, 20 nanometers, 21 nanometers, 22 nanometers, 23 nanometers, 24 nanometers, 25 nanometers, 26 nanometers, 27 nanometers, 28 nanometers, 29 nanometers or 30 nanometers.

[0105] The sum of the thicknesses of the microcrystalline silicon material layer wjg and the amorphous silicon material layer fjg is between 90 nanometers and 120 nanometers, for example, it can be 90 nanometers, 95 nanometers, 100 nanometers, 105 nanometers, 110 nanometers, 115 nanometers or 120 nanometers.

[0106] Optionally, the sum of the thicknesses of the microcrystalline silicon material layer wjg and the amorphous silicon material layer fjg is 100 nanometers. This maximizes the efficiency of the mobility and film formation time of the first active layer y1.

[0107] Step B4, please refer to Figure 8 At least a portion of the second active layer y2 is subjected to hydrogen removal and crystallization treatment using a Blue Laser Diode Annealing (BLDA) process to form polycrystalline silicon. The second active layer y2 includes a second source contact ys2, a second drain contact yd2, and a second channel yg2. The second source contact ys2 is connected to one side of the second channel yg2, and the second drain contact yd2 is connected to the other side of the second channel yg2. The second channel yg2 is polycrystalline silicon.

[0108] Optionally, in the second active layer y2, only the second channel yg2 may be a polysilicon layer y21, or the entire second active layer y2 may be a polysilicon layer y21, or the polysilicon layer y21 may extend from the channel region into the source / drain contact region.

[0109] In this process, a blue laser diode annealing process is first used to remove hydrogen from the second active layer y2, followed by a blue laser diode annealing process to crystallize the second active layer y2. The energy required for the crystallization stage is significantly greater than that required for the dehydrogenation stage.

[0110] Because amorphous silicon and microcrystalline silicon are used as crystallization raw materials, the addition of microcrystalline silicon reduces the energy required for dehydrogenation and annealing by more than 30% compared to crystallization of pure amorphous silicon at the same thickness.

[0111] It is important to understand that, under the blue laser diode annealing process, the energy required for the crystallization of pure amorphous silicon is in the range of 350 kW / cm². 2 Up to 450kw / cm 2 The energy required for hydrogen removal is in the range of 150 kW / cm². 2 Up to 250kw / cm 2 .

[0112] In one embodiment, polycrystalline silicon can also be formed using conventional laser processes.

[0113] Step B5, please refer to Figure 9 An ohmic contact material layer and a source / drain metal layer are sequentially formed on the side of the first active layer y1 and the second active layer y2 away from the substrate 11. The ohmic contact material layer and the source / drain metal layer are patterned to form a first source 151, a first drain 152, a first ohmic contact layer 141, a second ohmic contact layer 142, a second source 153, a second drain 154, and a second channel yg2. The first gate 131, the first active layer y1, the first ohmic contact layer 141, the first source 151, and the first drain 152 constitute a first thin-film transistor T1. The second gate... The second thin-film transistor T2 is composed of a first source 151, a second active layer y2, a second ohmic contact layer 142, a second source 153, and a second drain 154. The first source 151 is connected to the first source contact ys1 through a first ohmic contact layer 141, the first drain 152 is connected to the first drain contact yd1 through another first ohmic contact layer 141, the second source 153 is connected to the second source contact ys2 through a second ohmic contact layer 142, and the second drain 154 is connected to the second drain contact yd2 through another second ohmic contact layer 142.

[0114] Optionally, the thickness of the first ohmic contact layer 141 and the second ohmic contact layer 142 is between 15 nanometers and 40 nanometers, for example, it can be 15 nanometers, 16 nanometers, 17 nanometers, 18 nanometers, 19 nanometers, 20 nanometers, 21 nanometers, 22 nanometers, 23 nanometers, 24 nanometers, 25 nanometers, 26 nanometers, 27 nanometers, 28 nanometers, 29 nanometers, 30 nanometers, 31 nanometers, 32 nanometers, 33 nanometers, 34 nanometers, 35 nanometers or 40 nanometers.

[0115] The first source electrode 151, the first drain electrode 152, the second source electrode 153, and the second drain electrode 154 can be formed using a metallic element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, an alloy composed of any of the aforementioned metallic elements, or an alloy combining any of the aforementioned metallic elements. Furthermore, the first source electrode 151, the first drain electrode 152, the second source electrode 153, and the second drain electrode 154 can have a single-layer structure or a stacked structure of two or more layers.

[0116] Step B6, please refer to Figure 10 A protective layer 16 and an electrode 17 are sequentially formed on the first thin-film transistor T1 and the second thin-film transistor T2.

[0117] The protective layer 16 can be formed using a chemical vapor deposition process. The material of the protective layer 16 can be at least one of silicon nitride and silicon oxide. The thickness of the protective layer 16 is between 1500 angstroms and 4000 angstroms, for example, it can be 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms or 4000 angstroms.

[0118] Optionally, photolithography and dry etching processes can be used to etch the protective layer 16 to form vias.

[0119] The material of electrode 17 includes, but is not limited to, transparent metal oxides, such as ITO. The thickness of electrode 17 is between 400 angstroms and 1500 angstroms, for example, it can be 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms or 1500 angstroms.

[0120] Optionally, a physical vapor deposition process can be used to form the electrode material layer, followed by photolithography and etching processes to obtain the patterned electrode 17.

[0121] Accordingly, this application also provides a display panel, which includes the driving substrate 100 as described in any of the above embodiments.

[0122] Optionally, the display panel can be either a liquid crystal display panel or an electroluminescent panel.

[0123] It should be noted that the structure of the driving substrate in the display panel is similar to or the same as that of the driving substrate 100 in the above embodiment, so it will not be described again here.

[0124] The display panel of this application embodiment has a first thin-film transistor disposed in the pixel area of ​​the array substrate and a second thin-film transistor disposed in the bezel area. The first active layer of the first thin-film transistor includes a stacked amorphous silicon layer and a microcrystalline silicon layer, and the channel of the second active layer of the second thin-film transistor includes polycrystalline silicon, so that the mobility of the second thin-film transistor is greater than that of the first thin-film transistor. Furthermore, since polycrystalline silicon can be crystallized from the stacked amorphous silicon layer and the microcrystalline silicon layer as a whole, the process is simplified, and this application can improve the mobility of the second thin-film transistor located in the bezel area while reducing costs.

[0125] The foregoing has provided a detailed description of a driving substrate, its fabrication method, and a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A driving substrate, comprising a pixel region and a border region, wherein the border region is located on at least one side of the pixel region, characterized in that, include: Substrate; A first thin-film transistor is disposed on the substrate and located in the pixel region. The first thin-film transistor includes a first active layer, which includes a first amorphous silicon layer and a first microcrystalline silicon layer. The first microcrystalline silicon layer is disposed on the side of the first amorphous silicon layer away from the substrate. The first active layer includes a first channel, which includes the first amorphous silicon layer and the first microcrystalline silicon layer stacked together. The second thin-film transistor is disposed on the substrate and located in the border region. The second thin-film transistor includes a second active layer and a second channel. The second channel is polycrystalline silicon and has a thickness greater than that of the first microcrystalline silicon layer. The electron mobility of the second thin-film transistor is greater than that of the first thin-film transistor.

2. The driving substrate according to claim 1, characterized in that, The first active layer includes a first source contact and a first drain contact. The first source contact is connected to one side of the first channel, and the first drain contact is connected to the other side of the first channel. Both the first source contact and the first drain contact include the first amorphous silicon layer and the first microcrystalline silicon layer stacked together. The second active layer includes a second source contact and a second drain contact. The second source contact is connected to one side of the second channel, and the second drain contact is connected to the other side of the second channel. The material of both the second source contact and the second drain contact is polysilicon.

3. The driving substrate according to claim 1, characterized in that, The first active layer further includes a first source contact and a first drain contact. The first source contact is connected to one side of the first channel, and the first drain contact is connected to the other side of the first channel. Both the first source contact and the first drain contact include the first amorphous silicon layer and the first microcrystalline silicon layer stacked together. The second active layer further includes a second source contact and a second drain contact. The second source contact is connected to one side of the second channel, and the second drain contact is connected to the other side of the second channel. The second source contact includes a second amorphous silicon layer and a second microcrystalline silicon layer. The second microcrystalline silicon layer is disposed on the side of the second amorphous silicon layer away from the substrate. The second drain contact includes a third amorphous silicon layer and a third microcrystalline silicon layer. The third microcrystalline silicon layer is disposed on the side of the third amorphous silicon layer away from the substrate.

4. The driving substrate according to any one of claims 1-3, characterized in that, The polycrystalline silicon is formed by stacking amorphous silicon layers and microcrystalline silicon layers as a whole, wherein the amorphous silicon layer is disposed in the same layer as the first amorphous silicon layer, and the microcrystalline silicon layer is disposed in the same layer as the first microcrystalline silicon layer.

5. The driving substrate according to any one of claims 1-3, characterized in that, The grain width of the polycrystalline silicon is greater than 2 micrometers.

6. The driving substrate according to claim 5, characterized in that, The grain width of the polycrystalline silicon is greater than or equal to 6 micrometers.

7. The driving substrate according to any one of claims 1-3, characterized in that, The thickness of the first microcrystalline silicon layer is between 10% and 30% of the thickness of the first active layer.

8. The driving substrate according to any one of claims 2 or 3, characterized in that, The driving substrate further includes a gate insulating layer, the first thin film transistor includes a first gate, the second thin film transistor includes a second gate, the first gate and the second gate are both disposed on the substrate, the gate insulating layer covers the first gate and the second gate, the first active layer is disposed on the side of the gate insulating layer away from the substrate, and the second active layer is disposed on the side of the gate insulating layer away from the substrate. In the orthographic projection pattern of the driving substrate, the first active layer overlaps with the first gate, and the second active layer overlaps with the second gate; The gate insulating layer includes a silicon oxide layer and a silicon nitride layer, wherein the silicon nitride layer is disposed on the side of the silicon oxide layer away from the substrate.

9. The driving substrate according to claim 8, characterized in that, The thickness of the silicon nitride layer is greater than the thickness of the silicon oxide layer.

10. The driving substrate according to claim 8, characterized in that, The thickness of the silicon oxide layer is less than or equal to 250 nanometers, and the thickness of the silicon nitride layer is between 200 nanometers and 400 nanometers.

11. The driving substrate according to claim 8, characterized in that, The first thin-film transistor further includes a first ohmic contact layer, a first source, and a first drain; the second thin-film transistor further includes a second ohmic contact layer, a second source, and a second drain. One first ohmic contact layer is disposed on the first source contact portion, and another first ohmic contact layer is disposed on the first drain contact portion. The first source electrode is connected to the first source contact portion through the first ohmic contact layer, and the first drain electrode is connected to the first drain contact portion through the first ohmic contact layer. One second ohmic contact layer is disposed on the second source contact portion, and another second ohmic contact layer is disposed on the second drain contact portion. The second source electrode is connected to the second source contact portion through the second ohmic contact layer, and the second drain electrode is connected to the second drain contact portion through the second ohmic contact layer.

12. The driving substrate according to any one of claims 1-3, characterized in that, The driving substrate includes a demultiplexing circuit, which includes a plurality of second thin-film transistors. The gate of one of the second thin-film transistors is connected to a signal control terminal. The first terminals of the plurality of second thin-film transistors are all connected to a data signal input terminal. The second terminal of one of the second thin-film transistors is connected to a data line.

13. A display panel, characterized in that, Includes the driving substrate as described in any one of claims 1-12.

14. A method for fabricating a driving substrate, characterized in that, Includes the following steps: A first gate and a second gate are formed on a substrate, wherein the first gate is located in the pixel region and the second gate is located in the border region; A gate insulating layer is formed on the substrate, the gate insulating layer covering the first gate and the second gate; An amorphous silicon material layer and a microcrystalline silicon material layer are sequentially formed on the gate insulating layer. The amorphous silicon material layer and the microcrystalline silicon material layer are patterned to form a first active layer located in the pixel region and a second active layer located in the border region. The first active layer includes a first source contact, a first drain contact, and a first channel. The first source contact is connected to one side of the first channel, and the first drain contact is connected to the other side of the first channel. The first source contact, the first drain contact, and the first channel all include a first amorphous silicon layer and a first microcrystalline silicon layer stacked together. At least a portion of the second active layer is subjected to dehydrogenation and crystallization treatment to form polycrystalline silicon. The second active layer includes a second source contact, a second drain contact, and a second channel. The second source contact is connected to one side of the second channel, and the second drain contact is connected to the other side of the second channel. The second channel is the polycrystalline silicon. An ohmic contact material layer and a source / drain metal layer are sequentially formed on the side of the first active layer and the second active layer away from the substrate, and the ohmic contact material layer and the source / drain metal layer are patterned to form a first source, a first drain, a first ohmic contact layer, a second ohmic contact layer, a second source, and a second drain. The first gate, the first active layer, the first ohmic contact layer, the first source, and the first drain constitute a first thin-film transistor, and the second gate, the second active layer, the second ohmic contact layer, the second source, and the second drain constitute a second thin-film transistor. The first source is connected to the first source contact portion through a first ohmic contact layer, the first drain is connected to the first drain contact portion through another first ohmic contact layer, the second source is connected to the second source contact portion through a second ohmic contact layer, and the second drain is connected to the second drain contact portion through another second ohmic contact layer.

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