Current phase estimation method and dead-time compensation method for cascaded multilevel inverter

Abstract

The application discloses a current phase estimation method and a dead-time compensation method of a cascaded multi-level inverter, and belongs to the technical field of power electronics. d When the current phase angle is, the dead-time error voltage u d of the H-bridge submodule is determined as 0; when the current phase angle is, the dead-time error voltage u DC of the H-bridge submodule is determined as d ; when the current phase angle is, the dead-time error voltage u d of the H-bridge submodule is determined as on ; when the current phase angle is, the dead-time error voltage u off of the H-bridge submodule is determined as DC ; Fourier expansion coefficients of fundamental wave components of ideal output voltages u idl and u d of the H-bridge submodule are solved respectively, then the Fourier expansion coefficients are added, and the Fourier coefficients of the fundamental wave components of the output voltage of the cascaded multi-level inverter are accumulated to calculate a phase lag angle; and according to the estimated current phase angle, the turned-on angles of the H-bridge submodules after compensation are calculated. The application does not depend on current detection, and can effectively inhibit low-order harmonics introduced by the dead-time effect.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and more specifically, relates to a current phase estimation method and a dead-time compensation method for cascaded multilevel inverters. Background Technology

[0002] Very low frequency (3-30kHz) electromagnetic waves have advantages such as low propagation loss and strong penetration, and are therefore widely used in underwater communication, positioning, navigation, and timing. To meet the requirements of low harmonics, high voltage, and high power for VLF electromagnetic wave transmission, multilevel inverters that use cascaded transformers to superimpose the output levels of the H-bridge inverter submodules have become the primary choice. For VLF electromagnetic wave transmission, the fundamental frequency of the multilevel inverter needs to be greater than 20kHz. To suppress low-order harmonics and reduce switching losses, Selective Harmonic Elimination Pulse Width Modulation (SHEPWM) with a switching frequency equal to the fundamental frequency is typically used. Theoretically, N submodules can eliminate all harmonics of order 2N-1 and below. However, due to the turn-on and turn-off delays of power devices, a dead time needs to be set when the upper and lower transistors on the same bridge arm switch their operating states. The insertion of the dead time results in a loss of H-bridge output level, introducing additional low-order harmonics, the so-called dead-time effect. Due to the high fundamental frequency and multiple levels, the low-order harmonics introduced by the dead-time effect in cascaded multilevel inverters become the main source of harmonics in the output voltage, which severely restricts their high-frequency application and must be compensated for.

[0003] Since SHEPWM is a carrier-free pre-programmed modulation, only dead-time compensation methods based on adjusting the PWM pulse width can be applied. Currently, pulse-width-based dead-time compensation methods are mostly applied to single H-bridge topologies, with limited research on cascaded multilevel inverters. Traditional methods require detecting current polarity at the start of the dead time to select appropriate dead-time compensation actions. However, in high-frequency cascaded multilevel inverters, due to the fundamental current frequency being greater than 20kHz, the sampling circuit struggles to accurately detect current polarity due to limited sampling rates and current zero-crossing clamping. Furthermore, because cascaded multilevel inverters employ a distributed control structure, the main controller communicates with each H-bridge submodule via fiber optics, resulting in communication delays. The current polarity information obtained through sampling lags behind the actual dead-time, causing under-compensation or over-compensation of the dead-time voltage, which in turn leads to increased low-order harmonics.

[0004] Overall, existing dead-time compensation methods for high-frequency cascaded multilevel inverters rely on current measurement, resulting in poor dead-time compensation performance and making it difficult to meet the low-harmonic requirements of very low frequency transmission systems. Summary of the Invention

[0005] To address the shortcomings and improvement needs of existing technologies, this invention provides a current phase estimation method and a dead-zone compensation method for cascaded multilevel inverters. The aim is to solve the technical problem that existing dead-zone compensation methods for high-frequency cascaded multilevel inverters rely on current polarity detection, resulting in poor dead-zone compensation performance and difficulty in meeting the low harmonic requirements of very low frequency transmission systems.

[0006] To achieve the above objectives, according to one aspect of the present invention, a current phase estimation method for a cascaded multilevel inverter is provided, comprising:

[0007] (S1) Calculate the ideal current phase angle of the H-bridge submodule in the cascaded multilevel inverter.

[0008] (S2) After calculating the Fourier expansion coefficients of the fundamental component of the actual output voltage of each H-bridge submodule, the output voltage u of the cascaded multilevel inverter is obtained by superimposing them. mul The Fourier expansion coefficients of the fundamental component are used to calculate the output voltage u. mul The phase angle of the fundamental component is used as the phase lag angle. For any H-bridge submodule, the Fourier expansion coefficients of the fundamental component of its actual output voltage are calculated as follows:

[0009] The ideal output voltage u of the H-bridge submodule idl Perform a Fourier expansion to obtain the output voltage u. idl Fourier expansion coefficients a of the fundamental component 1_idl and b 1_idl ;

[0010] Determine the dead zone error voltage u d And perform a Fourier expansion on it to obtain the dead zone error voltage u. d Fourier expansion coefficients a of the fundamental component 1_d and b 1_d ;when At that time, u d =0; when At that time, the dead zone error voltage u d The level width is Amplitude is -V DC ;when At that time, the dead zone error voltage u d The level width is δ d +δ on -δ off The amplitude is -V DC ;

[0011] According to a 1_s =a 1_idl +a 1_d b 1_s =b1_idl +b 1_d Calculate the actual output voltage u of the H-bridge submodule. s Fourier expansion coefficients a of the fundamental component 1_s and b 1_s ;

[0012] (S3) According to Estimate the current phase angle of each H-bridge submodule

[0013] Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d Indicates the angle corresponding to the dead time; V DC This indicates the DC bus voltage.

[0014] Furthermore, in step (S1),

[0015] Where ω0 is the fundamental angular frequency; L c and R c L represents the parasitic inductance and parasitic resistance of the transmission line, respectively. g and R g These represent the load inductance and load resistance, respectively; k is the transformer winding coefficient in the cascaded multilevel inverter; L eq and R eq These represent the equivalent leakage inductance and equivalent winding resistance of a cascaded multilevel inverter, respectively.

[0016] Furthermore, R eq =N(R1+k) 2 R2), L eq =N(L1+k) 2 L2);

[0017] Where N represents the number of transformers cascaded in the cascaded multilevel inverter, R1 and R2 represent the primary winding resistance and secondary winding resistance of the transformer, respectively, and L1 and L2 represent the primary leakage inductance and secondary leakage inductance of the transformer, respectively.

[0018] Furthermore, when hour,

[0019] when hour,

[0020] when hour,

[0021] Furthermore,

[0022] Where, θ e This indicates the shutdown angle of the H-bridge submodule.

[0023] According to another aspect of the present invention, a dead-time compensation method for a cascaded multilevel inverter based on current phase estimation is provided, comprising:

[0024] The current phase estimation method for cascaded multilevel inverters provided by this invention is used to estimate the current phase angle of each H-bridge submodule in the cascaded multilevel inverter, and the compensated turn-on angle of each H-bridge submodule is calculated based on the current phase angle of each H-bridge submodule.

[0025] The phase-shift control signals of each switching device in the H-bridge submodule are allocated according to the compensated turn-on angle to achieve dead-zone compensation;

[0026] For any H-bridge submodule, and θ s_com Let represent the current phase angle and the compensated turn-on angle, respectively. Then:

[0027] when When, θ s_com =θ s ;

[0028] when hour,

[0029] when When, θ s_com =θ s -δ d_e ;

[0030] Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d The angle corresponding to the dead time; δ d_e =δ d +δ on -δ off V is the effective dead time; DC This indicates the DC bus voltage.

[0031] According to another aspect of the present invention, a current phase estimation device for a cascaded multilevel inverter is provided, comprising:

[0032] A computer-readable storage medium for storing computer programs;

[0033] And a processor for reading a computer program stored in a computer-readable storage medium and executing the current phase estimation method for cascaded multilevel inverters provided by the present invention.

[0034] According to another aspect of the present invention, a controller for a cascaded multilevel inverter based on current phase estimation is provided, including the current phase estimation device for the cascaded multilevel inverter provided by the present invention, as well as a compensation module and a control module;

[0035] The compensation module is used to calculate the compensated turn-on angle of each H-bridge submodule based on the current phase angle estimated by the current phase estimation device.

[0036] The control module is used to distribute the phase-shift control signals of each switching device in the H-bridge submodule according to the compensated turn-on angle to achieve dead-zone compensation;

[0037] For any H-bridge submodule, and θ s_com Let represent the current phase angle and the compensated turn-on angle, respectively. Then:

[0038] when When, θ s_com =θ s ;

[0039] when hour,

[0040] when When, θ s_com =θ s -δ d_e ;δ d_e =δ d +δ on -δ off Effective dead time;

[0041] Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d Indicates the angle corresponding to the dead time; V DC This indicates the DC bus voltage.

[0042] According to another system of the present invention, a cascaded multilevel inverter system is provided, comprising: a cascaded multilevel inverter and a controller for the cascaded multilevel inverter based on current phase estimation provided by the present invention.

[0043] This invention discovers that three types of dead-time errors will occur in cascaded multilevel inverters, namely:

[0044] 1. When During the dead time, there is no level loss and the dead time error voltage is 0.

[0045] 2. When At that time, from the current crossing zero point to the end of the dead time, the H-bridge output voltage is 0, and the dead time error voltage is equal to the level width. Amplitude is -V DC square wave;

[0046] 3. When During the entire dead time, the H-bridge output voltage is 0, and the dead time error voltage is a level width equal to δ. d_e The amplitude is -V DC A square wave, where δ d_e The effective dead time is defined as δ. d_e =δ d +δ on -δ off .

[0047] Among them, the phase angle of the current flowing through the H-bridge inverter submodule θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d The angle corresponding to the dead time; δ d_e =δ d +δ on -δ off V is the effective dead time; DC This indicates the DC bus voltage.

[0048] Therefore, this invention first estimates the current phase value in the H-bridge submodule of the cascaded multilevel inverter, and then performs corresponding compensation. Based on the topology of the cascaded multilevel inverter and the characteristics of SHEPWM modulation, the key to dead-time compensation is changed from detecting the polarity of the current flowing through each submodule in the traditional method to obtaining the phase of the cascaded current on the primary side of the transformer.

[0049] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0050] (1) The current phase estimation method for cascaded multilevel inverters provided by the present invention first calculates the ideal current phase angle of the H-bridge submodule in the cascaded multilevel inverter. Based on the calculation results, the corresponding dead zone error is estimated, the corresponding error voltage is obtained, and the phase lag angle is calculated. The calculation, combined with and This allows for the estimation of the current phase angle of the H-bridge submodule, providing a clear basis for subsequent dead-time compensation and correcting the output voltage phase lag caused by the dead-time effect. In this invention, the estimation of the current phase angle of the H-bridge submodule does not depend on current polarity detection, and because the H-bridge submodule has an ideal current phase angle... Due to the topology, calculations can be performed directly at the main controller, eliminating the delay time of fiber optic communication. Therefore, low-order harmonics introduced by the dead-zone effect can be effectively suppressed in subsequent dead-zone compensation.

[0051] (2) In the preferred embodiment of the current phase estimation method for cascaded multilevel inverters provided by the present invention, the ideal current phase angle of the H-bridge submodule is... The calculation of the current phase angle. The calculation of parameters such as the equivalent leakage inductance and equivalent winding resistance of the cascaded multilevel inverter involved in the calculation is completed by constructing a cascaded multilevel inverter system model by decoupling the cascaded transformer into a two-port Γ-type circuit and considering parasitic parameters. The calculation has high accuracy and low complexity.

[0052] (3) The dead-time compensation method for cascaded multilevel inverters based on current phase estimation provided by this invention estimates the actual current phase angle of each H-bridge submodule. Then, the corresponding dead zone error is determined, and the turn-on angle of the switching devices in each H-bridge submodule is compensated accordingly. The phase shift control signal of each switching device in the H-bridge submodule is then allocated according to the compensated turn-on angle. This can effectively compensate for the level distortion caused by the dead zone effect. At the same time, since the estimation of the current phase angle does not depend on the current detection, the current polarity detection and fiber optic communication delay time are eliminated. In high-frequency cascaded topologies, the low-order harmonics introduced by the dead zone effect can be effectively suppressed, and the waveform quality can be significantly improved. Attached Figure Description

[0053] Figure 1 For existing cascaded multilevel inverter topology;

[0054] Figure 2 This is a schematic diagram of existing methods for obtaining the switching angle of a multilevel inverter using SHEPWM technology.

[0055] Figure 3 This is a summary of the dead-zone effects that occur in the sub-modules of the cascaded multilevel inverter provided in the embodiments of the present invention during actual operation;

[0056] Figure 4 A schematic diagram of the equivalent circuit for decoupling a cascaded transformer provided in an embodiment of the present invention; wherein, (a) is a schematic diagram of the equivalent circuit of the cascaded multilevel transformer when the output level is switched, (b) is a T-type circuit of the cascaded multilevel transformer, and (c) is a Γ-type structure of the cascaded multilevel transformer;

[0057] Figure 5 A flowchart of a current phase angle estimation method for a cascaded multilevel inverter provided in an embodiment of the present invention;

[0058] Figure 6 This is a schematic diagram of the equivalent system model of the multilevel inverter after decoupling of the cascaded transformers provided in an embodiment of the present invention;

[0059] Figure 7 A phasor diagram of a cascaded multilevel inverter system provided in an embodiment of the present invention;

[0060] Figure 8 The simulated output voltage and current waveforms of a cascaded multilevel inverter are provided for embodiments of the present invention.

[0061] Figure 9 The simulation provided for the embodiments of the present invention compares the output voltage harmonic content using the traditional dead-zone compensation method and the proposed dead-zone compensation method. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0063] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0064] Before explaining the technical solution of the present invention in detail, the structure and principle of the cascaded multilevel inverter will be briefly introduced as follows.

[0065] like Figure 1 As shown, a single-phase cascaded H-bridge multilevel inverter using high-frequency transformers is a commonly used inverter circuit in very low frequency (VLF) transmission systems. Unlike traditional cascaded H-bridge converters, the H-bridge inverter submodule consists of N cascaded high-frequency transformers with independent magnetic cores. Figure 1 In the middle, T1~T NThese represent N transformers. The inputs of all submodules are connected in parallel to the same DC source, and the outputs are connected to the primary side of the transformers. The secondary sides of the transformers are connected in series. This topology using cascaded transformers avoids the requirement of multiple independent DC sources and is suitable for multilevel converters with a large number of submodules. Each inverter submodule is an H-bridge structure, with each bridge arm consisting of upper and lower switches, both of which are SiC MOSFETs. Based on the current direction, the bridge arm from which current flows is defined as the left bridge arm, and the bridge arm from which current flows is defined as the right bridge arm. The upper and lower switches of the left bridge arm, and the upper and lower switches of the right bridge arm, are respectively denoted as S1, S2, S3, and S4. Each submodule can generate -V DC 0 and +V DC Three levels, of which V DC This is the DC bus voltage.

[0066] Since the fundamental frequency is greater than 20kHz, in order to suppress voltage harmonics and reduce switching losses, this multilevel converter employs, as follows: Figure 2 The fundamental frequency shown is equal to 1 / 4 of the switching frequency in a periodic symmetrical SHEPWM. Where θ i (i = 1, 2, ..., N) is the switching angle, satisfying 0 < θ1 < ... < θ N <π / 2. A cascaded multilevel converter with N submodules can generate 2N+1 levels, theoretically eliminating all harmonics below the 2N-1th order. However, due to the turn-on and turn-off delays of power devices, simultaneously sending the turn-on and turn-off signals of the same bridge arm transistors can cause the bridge arm to shoot-through, burning out the power devices. Therefore, in practical engineering, a dead time is usually inserted into the control signals of the power transistors in the same bridge arm. During the dead time, both the upper and lower transistors are in the off state, and the output voltage of the H-bridge is determined by the bridge arm current. The introduction of dead time causes voltage distortion, making the output pulse width smaller than expected, which manifests in the frequency domain as the introduction of additional low-order harmonics, the so-called dead-time effect. Since the inverter of the VLF transmitting system is composed of multiple cascaded submodules and the fundamental frequency is greater than 20kHz, the low-order harmonics introduced by the dead-time effect become the main harmonic source of the inverter, seriously affecting communication quality and increasing the difficulty of filter design. Therefore, it is necessary to compensate for the dead-time effect.

[0067] It should be noted that, since the inverter of the VLF transmitting system is composed of multiple cascaded sub-modules and the fundamental frequency is greater than 20kHz, the cascaded multilevel inverter involved in this invention is a high-frequency cascaded multilevel inverter.

[0068] SHEPWM is a carrierless pre-programmed modulation method. The key to its dead-time compensation is accurately adjusting the pulse width of each inverter submodule to compensate for the level loss caused by the dead-time effect. Since each submodule is cascaded through a transformer, the current flowing through it is the same sine wave, and the output voltage is a square wave with sequential phase shifts. It is assumed that the output voltage of the H-bridge inverter submodule is the superposition of the ideal voltage and the dead-time error voltage. Figure 3 This is a summary of the dead-time effects that occur in the submodules during actual operation of the high-frequency cascaded multilevel inverter provided in this embodiment of the invention. Here, "S1" to "S4" represent the drive signals of the H-bridge submodule switching transistors S1 to S4 using a dead-time insertion method with delayed turn-on, respectively. s(1) "Indicates when the output current i s The actual output voltage of the H-bridge module at zero crossing after the dead time ends, "u s(2) " indicates when i s The actual output voltage of the H-bridge module when it crosses zero during the dead time, "u d(2) " indicates when i s The dead-time error voltage of the H-bridge submodule at zero crossing during the dead time, "u s(3) " indicates when i s The actual output voltage of the H-bridge module at zero crossing before the start of the dead time, "u d(3) "Indicates when the output current i s The dead-time error voltage of the H-bridge submodule when it crosses zero before the start of the dead time. The dead-time effect does not affect the symmetry of the output voltage. Taking the positive half-cycle as an example, under steady-state conditions, a multi-level inverter will exhibit the following... Figure 3 The three dead-zone error voltages shown are as follows:

[0069] 1. When During the dead time, there is no level loss and the dead time error voltage is 0.

[0070] 2. When At that time, from the current crossing zero point to the end of the dead time, the H-bridge output voltage is 0, and the dead time error voltage is equal to the level width. Amplitude is -V DC square wave;

[0071] 3. When During the entire dead time, the H-bridge output voltage is 0, and the dead time error voltage is a level width equal to δ. d_e The amplitude is -V DC A square wave, where δ d_e The effective dead time is defined as δ. d_e =δ d +δ on -δ off .

[0072] Where, δd δ on and δ off Both are in radians, representing dead time t. d Power device turn-on delay time t on and shutdown delay time t off The corresponding radians are specifically δ d =2πf0t d δ on =2πf0t on and δ off =2πf0t off f0 is the fundamental frequency. The phase of the current flowing through the H-bridge inverter submodule controls the ideal output voltage of the multilevel inverter to have a phase of 0. For resistive-inductive loads, the output current lags behind the output voltage. The range is 0 to π / 2; θ s and θ e These are the turn-on and turn-off angles of the H-bridge inverter submodule, respectively, and they are related to... Figure 2 The relationship between the switching angles of SHEPWM and θ is... s =θ i θ e =π-θ N+1-i .

[0073] Based on the above analysis, this invention proposes to complete dead-time compensation by estimating the current phase angle of the H-bridge submodule in a cascaded multilevel inverter. This allows the dead-time compensation to be transformed from detecting the polarity of the current flowing through each submodule to obtaining the phase of the cascaded current on the primary side of the transformer, based on the topology of the cascaded multilevel inverter and the characteristics of SHEPWM modulation, thus avoiding dependence on current detection.

[0074] Since different current phase angles correspond to different dead-zone error voltages, accurate estimation of the current phase angle is crucial for effective dead-zone compensation. Existing dead-zone compensation methods rely on current sensing, which is limited by high-frequency current and communication delays, making it difficult for the sampling circuit to accurately extract current phase information and promptly send it to the main controller for dead-zone compensation, resulting in poor compensation performance. This invention provides a current phase estimation method suitable for high-frequency cascaded multilevel inverters.

[0075] Modeling a cascaded multilevel inverter system is a prerequisite for current phase estimation. Unlike traditional power frequency transformers, the multilevel inverter involved in this invention has a fundamental frequency exceeding 20kHz, necessitating consideration of parasitic parameters in the cascaded transformers during modeling. However, each transformer is coupled to other cascaded transformers. Directly using the classic T-type equivalent circuit of the transformer for modeling would result in an equivalent circuit with 2N input ports and 2 output ports, leading to a complex structure and making it difficult to calculate electrical characteristics using circuit principles. Therefore, this invention proposes a cascaded transformer decoupling method that converts the cascaded transformers into equivalent two-port transformers without affecting their harmonic characteristics.

[0076] For any single transformer in a cascaded transformer system, its secondary side, in addition to connecting to the transmission cable and load, is also connected to N-1 other transformers. To avoid affecting the transformer's harmonic characteristics, the relationship between the parasitic parameters in the transformer and the load must remain unchanged before and after equivalence. When the output level of the H-bridge submodule connected to the front stage of the transformer is 0, the primary side of the transformer forms a closed loop through the submodule's power devices; when the output level of the H-bridge submodule connected to the front stage of the transformer is ±V... DC At this time, the primary side of the transformer forms a closed loop through the DC bus capacitor of the submodule. Since the magnetizing inductance of a single transformer is typically several kΩ, while the equivalent resistance of the power devices and bus capacitors is several mΩ, the voltage drop of the power devices and bus capacitors can be ignored. According to the modulation method described above, only one H-bridge submodule's output level switches at any given time. Taking the first H-bridge submodule as an example, when its output level switches, the equivalent circuit of the cascaded transformers is as follows: Figure 4 As shown in (a) of the diagram. Where, L m For transformer magnetizing inductance, R m Let L1 be the transformer excitation resistance, L2 be the leakage inductance on the primary and secondary sides of the transformer, respectively, and R1 be the winding resistance on the primary and secondary sides of the transformer, respectively. Assuming that all transformers have the same parameters, the primary side parameters are converted to the secondary side parameters. Figure 4 The circuit shown in (a) can be transformed into Figure 4 The T-type circuit shown in (b) is an example. Where R... 2_eq and L 2_eq These are the equivalent winding resistance and equivalent leakage inductance of the secondary side of the cascaded transformer, respectively, and can be calculated using the following formula:

[0077]

[0078]

[0079] Using the decoupling method described above, the multi-input cascaded transformer is equivalent to a two-port network. Because its circuit characteristics are similar to the traditional transformer T-type equivalent circuit, the cascaded transformer can be considered equivalent to a new two-port transformer. Since the parasitic parameters of the transformer and the circuit relationship of the subsequent load remain unchanged before and after the equivalence, this method does not affect the spectral characteristics of the cascaded transformer. For ease of further calculation, the circuit is further equivalent to as follows: Figure 4 The Γ-type structure shown in (c) has R eq and L eq The equivalent winding resistance and equivalent leakage inductance of the cascaded transformer are calculated using the following expressions:

[0080] R eq =N(R1+k) 2 R2)

[0081] L eq =N(L1+k) 2 L2)

[0082] After decoupling and equivalence, when analyzing the output voltage of a cascaded multilevel inverter, the output voltage of each H-bridge submodule can be considered as directly cascaded on the primary side, and then connected to the load through an equivalent two-port transformer. This decoupling method greatly simplifies the modeling of cascaded transformers, facilitates direct calculation of electrical characteristics using circuit principles, and is a prerequisite for quantitative analysis and closed-loop control of inverter systems containing cascaded transformers. In this invention, the current phase angle of the H-bridge submodule is estimated based on the above modeling method.

[0083] The following is an example.

[0084] Example 1:

[0085] A method for current phase estimation in a cascaded multilevel inverter, such as Figure 5 As shown, it includes steps (S1) to (S3).

[0086] like Figure 5 As shown, in this embodiment, step (S1) specifically includes: calculating the ideal current phase angle of the H-bridge submodule in the cascaded multilevel inverter.

[0087] Based on the above modeling method, in step (S1) of this embodiment, the ideal current phase angle of the H-bridge submodule in the cascaded multilevel inverter is calculated as follows:

[0088] (S11) Obtain the system parameters of the cascaded multilevel inverter, including the fundamental frequency f0 and dead time t. d The turn-on delay t of power devices on and shutdown delay time t off The magnetizing inductance L of the transformerm Excitation resistor R m The primary leakage inductance L1, the primary winding resistor R1, the secondary leakage inductance L2 and the secondary winding resistor R2, and the parasitic inductance L of the transmission line. c and parasitic resistance R c ;

[0089] (S12) Obtain the parasitic parameters in the cascaded multilevel inverter and transmission line, and decouple the transformer in the cascaded multilevel inverter as follows: Figure 4 The Γ-type circuit shown in (c) is used to construct a cascaded multilevel inverter system model, as follows: Figure 6 As shown, where I0 is the transformer magnetizing current, I s I is the primary current of the H-bridge inverter submodule, which is also the primary current of the transformer. g For the load current, u g U is the load voltage. mul This is the summation of the output voltages of each H-bridge submodule. Based on... Figure 6 The system model shown can be used to calculate the equivalent leakage inductance L of a cascaded multilevel inverter. eq and equivalent winding resistance R eq as follows:

[0090] R eq =N(R1+k) 2 R2)

[0091] L eq =N(L1+k) 2 L2)

[0092] Where N is the number of cascaded transformers, and k is the transformer winding coefficient;

[0093] (S13) Measure load parameters, including load inductance L g and load resistance R g ;in accordance with Figure 6 The system model shown can be used to establish Figure 7 The vector diagram of the cascaded multilevel inverter system shown indicates that, under full transformer load, I0 < 0.03I. s We can approximate I0 = 0, therefore the ideal current phase angle of the H-bridge submodule is... The following formula can be used to calculate:

[0094]

[0095] Where ω0 is the fundamental angular frequency, ω0=2πf0.

[0096] Ideal current phase angle of H-bridge module It is calculated based on the system model, does not depend on current detection, and can be directly calculated by the main controller.

[0097] In step (S1) of this embodiment, the ideal current phase angle of the H-bridge submodule is... The calculation of the current phase angle. The calculation of parameters such as the equivalent leakage inductance and equivalent winding resistance of the cascaded multilevel inverter involved in the calculation is completed by constructing a cascaded multilevel inverter system model by decoupling the cascaded transformer into a two-port Γ-type circuit and considering parasitic parameters. The calculation has high accuracy and low complexity.

[0098] Considering that both transformer parameters and transmission line parameters are affected by the fundamental frequency, as a preferred implementation method, in step (S1) of this embodiment, when obtaining the parameters of the cascaded multilevel inverter and transmission line, offline frequency sweep measurement is performed on the transformer and transmission line parameters, and function fitting is performed to obtain the relationship between the parameters and the fundamental frequency, so as to meet the dead zone compensation requirements under different fundamental frequencies.

[0099] In practical applications, load parameters can be measured offline using an LCR meter or online using a phase detector. Optionally, in this embodiment, step (S1) uses an LCR meter to measure load parameters offline.

[0100] like Figure 5 As shown, in this embodiment, step (S2) specifically includes: calculating the Fourier expansion coefficients of the fundamental component of the actual output voltage of each H-bridge submodule, and then superimposing them to obtain the output voltage u of the cascaded multilevel inverter. mul The Fourier expansion coefficients of the fundamental component are used to calculate the output voltage u. mul The phase angle of the fundamental component is used as the phase lag angle.

[0101] The ideal current phase angle of the H-bridge submodule was calculated. Afterwards, Substituting the harmonic equations of a cascaded multilevel inverter, the lag phase angle of the fundamental component in the actual output voltage compared to the ideal output voltage caused by the dead-time effect can be calculated. Specifically, the actual output voltage u of the H-bridge submodule s For the ideal output voltage u idl and dead zone error voltage u d The superposition of these harmonics results in the following harmonic equation:

[0102]

[0103] in,

[0104] a n_s =a n_idl +a n_d b n_s =b n_idl +b n_d

[0105] a n_idl and b n_idl The ideal output voltage u of the H-bridge submodule idl The Fourier expansion coefficients of the nth harmonic component are calculated using the following formula:

[0106]

[0107]

[0108] Taking n=1 and substituting it into the above formula, the ideal output voltage u can be calculated. idl Fourier expansion coefficients a of the fundamental component 1_idl and b 1_idl as follows:

[0109]

[0110]

[0111] Among them, V DC This is the DC bus voltage.

[0112] a n_d and b n_d dead zone error voltage u d The Fourier expansion coefficients of the nth harmonic component; specifically, based on the ideal current phase angle of the H-bridge submodule. It can determine the current dead zone error voltage and thus determine the corresponding dead zone error voltage u. d Therefore, in this embodiment, a n_d and b n_d The calculation method is as follows:

[0113] when hour,

[0114]

[0115] when hour,

[0116] When n is odd

[0117] when hour,

[0118] When n is odd

[0119] Taking n=1 and substituting it into the above formula, the dead zone error voltage u can be calculated. d Fourier expansion coefficients a of the fundamental component 1_d and b 1_d They are as follows:

[0120] when hour,

[0121] when hour,

[0122] when hour,

[0123] a 1_idl and b 1_idl With a 1_d and b 1_d By adding the corresponding values, the actual output voltage u can be obtained. s Fourier expansion coefficients a of the fundamental component 1_s and b 1_s .

[0124] The output voltage u of each H-bridge submodule s Fourier expansion coefficients a of the fundamental component 1_s and b 1_s Add the corresponding values ​​together to calculate u. mul Fourier expansion coefficients a of the fundamental component 1_mul and b 1_mul ,Right now:

[0125]

[0126] Among them, a 1_s (i) and b 1_s (i) represents the Fourier expansion coefficient of the fundamental component of the output voltage of the i-th H-bridge submodule.

[0127] Because under ideal conditions u mul Since the phase of the fundamental component is 0, this phase angle is the u under the influence of the dead zone effect. mul Phase lag angle of the fundamental component Therefore, the phase lag angle The calculation formula is as follows:

[0128]

[0129] like Figure 5 As shown, in this embodiment, step (S3) specifically includes:

[0130] according to Estimate the current phase angle of each H-bridge submodule

[0131] In summary, this embodiment combines the ideal current phase angle of the H-bridge submodule. and phase lag angle The estimation of the current phase angle of the H-bridge submodule provides a clear basis for subsequent dead-time compensation and corrects the output voltage phase lag caused by the dead-time effect. In this embodiment, the estimation of the current phase angle of the H-bridge submodule does not depend on current polarity detection, and due to the ideal current phase angle of the H-bridge submodule... Due to the topology, calculations can be performed directly at the main controller, eliminating the delay time of fiber optic communication. Therefore, low-order harmonics introduced by the dead-zone effect can be effectively suppressed in subsequent dead-zone compensation.

[0132] Example 2:

[0133] A dead-time compensation method for cascaded multilevel inverters based on current phase estimation includes:

[0134] The current phase estimation method for the cascaded multilevel inverter provided in Embodiment 1 above is used to estimate the current phase angle of each H-bridge submodule in the cascaded multilevel inverter, and the compensated turn-on angle of each H-bridge submodule is calculated based on the current phase angle of each H-bridge submodule.

[0135] The phase-shift control signals of each switching device in the H-bridge submodule are allocated according to the compensated turn-on angle to achieve dead-zone compensation;

[0136] For any H-bridge submodule, and θ s_com Let represent the current phase angle and the compensated turn-on angle, respectively. Then:

[0137] when When, θ s_com =θ s ;

[0138] when hour,

[0139] when When, θ s_com =θ s -δ d_e ;

[0140] Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d The angle corresponding to the dead time; δ d_e =δ d +δ on -δ off V is the effective dead time; DC This indicates the DC bus voltage.

[0141] It is easy to understand that the turn-on angle and turn-off angle of each H-bridge module can be determined based on... Figure 2 The SHEPWM modulation method shown is determined and pre-recorded in the storage unit. For any H-bridge submodule, after compensating its turn-on angle according to the above method, a phase-shift control signal is assigned to the switching transistor of the H-bridge module, and the trigger signal of the upper transistor S1 of the left bridge arm is at θ. s_com +δ d to θ s_com During the +π period, the signal is high, and the trigger signal of the lower transistor S2 of the left bridge arm is between 0 and θ. s_com and θ s_com +π+δ d The signal is high during the period up to 2π, and the trigger signal of the upper transistor S3 on the right bridge arm is at θ. e +δ d to θ e During the +π period, the signal is high, and the trigger signal of the lower transistor S4 of the right bridge arm is between 0 and θ. e and θ e +π+δ d The level is high during the period up to 2π.

[0142] In this embodiment, the actual current phase angle of each H-bridge submodule is estimated. Then, the corresponding dead zone error is determined, and the turn-on angle of the switching devices in each H-bridge submodule is compensated accordingly. The phase shift control signal of each switching device in the H-bridge submodule is then allocated according to the compensated turn-on angle. This can effectively compensate for the level distortion caused by the dead zone effect. At the same time, since the estimation of the current phase angle does not depend on the current detection, the current polarity detection and fiber optic communication delay time are eliminated. In high-frequency cascaded topologies, the low-order harmonics introduced by the dead zone effect can be effectively suppressed, and the waveform quality can be significantly improved.

[0143] Example 3:

[0144] A current phase estimation device for a cascaded multilevel inverter includes:

[0145] A computer-readable storage medium for storing computer programs;

[0146] And a processor for reading a computer program stored in a computer-readable storage medium and executing the current phase estimation method for the cascaded multilevel inverter provided in Embodiment 1 above.

[0147] Example 4:

[0148] A controller for a cascaded multilevel inverter based on current phase estimation includes the current phase estimation device for the cascaded multilevel inverter provided in Embodiment 3 above, as well as a compensation module and a control module;

[0149] The compensation module is used to calculate the compensated turn-on angle of each H-bridge submodule based on the current phase angle estimated by the current phase estimation device.

[0150] The control module is used to distribute the phase-shift control signals of each switching device in the H-bridge submodule according to the compensated turn-on angle to achieve dead-zone compensation;

[0151] For any H-bridge submodule, and θ s_com Let represent the current phase angle and the compensated turn-on angle, respectively. Then:

[0152] when When, θ s_com =θ s ;

[0153] when hour,

[0154] when When, θ s_com =θ s -δ d_e ;δ d_e =δ d +δ on -δ off Effective dead time;

[0155] Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d Indicates the angle corresponding to the dead time; V DC This indicates the DC bus voltage.

[0156] In this embodiment, the specific implementation of the compensation module and the control module can be referred to the description in Embodiment 2 above, and will not be repeated here.

[0157] Example 5:

[0158] A cascaded multilevel inverter system includes: a cascaded multilevel inverter and a controller for the cascaded multilevel inverter based on current phase estimation provided in Embodiment 4 above.

[0159] The following specific simulation examples will further explain the beneficial effects that the present invention can achieve.

[0160] Simulations were performed using MATLAB / Simulink software to verify the compensation effect of the dead-time compensation method for high-frequency cascaded multilevel inverters based on current phase estimation provided in this invention. The simulation model used a single-phase 17-level high-frequency cascaded multilevel converter and employed SHEPWM to eliminate harmonics at or below the 15th harmonic of the fundamental frequency. The DC bus voltage V was set. DC =270V, fundamental frequency f0=30kHz, dead time t d =200ns, and other system and load parameters are shown in Table 1.

[0161] Table 1

[0162] DC bus voltage <![CDATA[V DC ]]> 270V Number of H-bridge inverter submodules N 8 Submodule supporting capacitor <![CDATA[C DC ]]> 135μF Fundamental frequency <![CDATA[f0]]> 30kHz Dead Time <![CDATA[t d ]]> 200ns Power device turn-on delay time <![CDATA[t on ]]> 33.6ns Power device turn-off delay time <![CDATA[t off ]]> 60.5ns Transformer winding coefficient k 21:9 Transformer excitation resistance <![CDATA[R m ]]> 8423.9Ω Transformer magnetizing inductance <![CDATA[L m ]]> 8.4mH Transformer leakage resistance <![CDATA[R1+k 2 R2]]> 33.7mΩ Transformer leakage inductance <![CDATA[L1+k 2 L2]]> 4.7μH Transmission line parasitic resistance <![CDATA[R c ]]> 49.9mΩ Parasitic inductance of transmission lines <![CDATA[L c ]]> 3.8μH Load parameters <![CDATA[R g ,L g ]]> 9.0Ω, 5.3μH

[0163] The transformer parameters and transmission line parameters are both related to the fundamental frequency. Only the system parameters when f0 = 30kHz are listed in the table.

[0164] First, the dead time and power device delay time are converted into radians, i.e., δ. d =2πf0t d δ on =2πf0t on and δ off =2πf0t off A system model of a cascaded multilevel inverter is established using the above modeling method to calculate the equivalent leakage resistance R of the cascaded transformer. eq and equivalent leakage inductance L eq According to the dead-zone compensation method provided by the present invention, the load parameter R can be used. g and L g Estimate the phase of the current flowing through the H-bridge inverter submodule The phase information is then used to adjust the turn-on angle of each sub-module in the multilevel inverter to achieve dead-zone compensation.

[0165] Figure 8 The waveforms of the load-side voltage and current of the multilevel inverter are shown. Figure 9This paper compares the load voltage harmonic content under four conditions: no dead time, with dead time, using a traditional dead-time compensation method based on current polarity detection, and using the dead-time compensation method based on current phase estimation provided by this invention. Due to the dead-time effect, the third and fifth harmonics increase significantly, becoming the dominant harmonic components. Traditional methods rely on current polarity detection. Even if high-frequency current polarity detection is accurate in simulations, the dead-time compensation action lags behind the ideal compensation time due to the fiber optic communication delay introduced by the distributed structure of multi-level inverters. This results in over-compensation or under-compensation of the output level switching angle of submodules near the current zero-crossing point. When using the traditional method requiring current polarity detection in cascaded multi-level inverters, the third and fifth harmonics are suppressed to some extent, but are still much higher than in the case of no dead time. When using the compensation method based on current phase estimation provided by this invention, both current estimation and dead-time compensation are completed in the main controller, avoiding current polarity detection and communication delays, and effectively suppressing the third and fifth harmonics.

[0166] Since the harmonics introduced by the dead-time effect are vector-added with the ideal voltage harmonics, some higher-order harmonics actually decrease after the dead-time is inserted. To more comprehensively demonstrate the low-order harmonic suppression capability of the proposed method, the Total Harmonic Distortion (THD) index is introduced. Under four simulation conditions, the THD of the output voltage is 0.50%, 1.10%, 0.68%, and 0.50%, respectively. It can be seen that the harmonic spectrum after compensation using the method provided by this invention is the same as the harmonic spectrum without dead time, effectively suppressing the low-order harmonics introduced by the dead-time effect in high-frequency cascaded multilevel inverters.

[0167] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A current phase estimation method for a cascaded multilevel inverter, characterized in that, include: (S1) Calculate the ideal current phase angle of the H-bridge submodule in the cascaded multilevel inverter. (S2) After calculating the Fourier expansion coefficients of the fundamental component of the actual output voltage of each H-bridge submodule, the output voltage u of the cascaded multilevel inverter is obtained by superimposing them. mul The Fourier expansion coefficients of the fundamental component are used to calculate the output voltage u. mul The phase angle of the fundamental component is used as the phase lag angle. For any H-bridge submodule, the Fourier expansion coefficients of the fundamental component of its actual output voltage are calculated as follows: The ideal output voltage u of the H-bridge submodule idl Perform a Fourier expansion to obtain the output voltage u. idl Fourier expansion coefficients a of the fundamental component 1_idl and b 1_idl ; Determine the dead zone error voltage u d And perform a Fourier expansion on it to obtain the dead zone error voltage u. d Fourier expansion coefficients a of the fundamental component 1_d and b 1_d ;when At that time, u d =0; when At that time, the dead zone error voltage u d The level width is Amplitude is -V DC ;when At that time, the dead zone error voltage u d The level width is δ d +δ on -δ off The amplitude is -V DC ; According to a 1_s =a 1_idl +a 1_d b 1_s =b 1_idl +b 1_d Calculate the actual output voltage u of the H-bridge submodule. s Fourier expansion coefficients a of the fundamental component 1_s and b 1_s ; (S3) According to Estimate the current phase angle of each H-bridge submodule Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d Indicates the angle corresponding to the dead time; V DC This indicates the DC bus voltage.

2. The current phase estimation method for a cascaded multilevel inverter as described in claim 1, characterized in that, In step (S1), Where ω0 is the fundamental angular frequency; L c and R c L represents the parasitic inductance and parasitic resistance of the transmission line, respectively. g and R g These represent the load inductance and load resistance, respectively; k is the transformer winding coefficient in the cascaded multilevel inverter; L eq and R eq These represent the equivalent leakage inductance and equivalent winding resistance of the cascaded multilevel inverter, respectively.

3. The current phase estimation method for a cascaded multilevel inverter as described in claim 2, characterized in that, R eq =N(R1+k 2 R2),L eq =N(L1+k 2 L2); Wherein, N represents the number of transformers cascaded in the cascaded multilevel inverter, R1 and R2 represent the primary winding resistance and secondary winding resistance of the transformer, respectively, and L1 and L2 represent the primary leakage inductance and secondary leakage inductance of the transformer, respectively.

4. The current phase estimation method for a cascaded multilevel inverter as described in any one of claims 1 to 3, characterized in that, when hour, when hour, when hour, 5. The current phase estimation method for a cascaded multilevel inverter as described in any one of claims 1 to 3, characterized in that, Where, θ e This indicates the shutdown angle of the H-bridge submodule.

6. A dead-time compensation method for a cascaded multilevel inverter based on current phase estimation, characterized in that, include: The current phase estimation method of the cascaded multilevel inverter according to any one of claims 1 to 5 is used to estimate the current phase angle of each H-bridge submodule in the cascaded multilevel inverter, and the compensated turn-on angle of each H-bridge submodule is calculated based on the current phase angle of each H-bridge submodule. The phase-shift control signals of each switching device in the H-bridge submodule are allocated according to the compensated turn-on angle to achieve dead-zone compensation; For any H-bridge submodule, and θ s_com Let represent the current phase angle and the compensated turn-on angle, respectively. Then: When θ s_com = θ s ; when hour, when When, θ s_com =θ s -δ d_e ;δ d_e =δ d +δ on -δ off Effective dead time; Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d Indicates the angle corresponding to the dead time; V DC This indicates the DC bus voltage.

7. A current phase estimation device for a cascaded multilevel inverter, characterized in that, include: A computer-readable storage medium for storing computer programs; And a processor, configured to read a computer program stored in the computer-readable storage medium and execute the current phase estimation method for the cascaded multilevel inverter as described in any one of claims 1 to 5.

8. A controller for a cascaded multilevel inverter based on current phase estimation, characterized in that, It includes the current phase estimation device for the cascaded multilevel inverter as described in claim 6, as well as a compensation module and a control module; The compensation module is used to calculate the compensated turn-on angle of each H-bridge submodule based on the current phase angle estimated by the current phase estimation device. The control module is used to distribute the phase-shift control signal of each switching device in the H-bridge submodule according to the compensated turn-on angle to achieve dead zone compensation; For any H-bridge submodule, and θ s_com Let represent the current phase angle and the compensated turn-on angle, respectively. Then: When θ s_com = θ s ; when hour, When θ s_com = θ s - δ d_e ; Where, θ s δ represents the turn-on angle of the H-bridge submodule. on and δ off δ represents the angle corresponding to the turn-on delay time and turn-off delay time of the switching device, respectively. d The angle corresponding to the dead time; δ d_e =δ d +δ on -δ off V is the effective dead time; DC This indicates the DC bus voltage.

9. A cascaded multilevel inverter system, characterized in that, include: Cascaded multilevel inverter and the controller of the cascaded multilevel inverter based on current phase estimation as described in claim 8.

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