Code Generation Method, Device, Electronic Device and Storage Medium

Abstract

The present invention discloses a code generation method, apparatus, electronic device and storage medium. Among them, the method includes: obtaining a physical behavior model based on a modeling and simulation language, where the physical behavior model includes a first physical feature and a first behavior feature of a target circuit; in response to a step size setting operation, determining a discrete time step, and performing discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model; performing code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model. Based on the technical solution of the embodiments of the present invention, it is possible to automatically, efficiently and accurately convert a physical behavior model based on a modeling and simulation language into target code based on a hardware description language.

Description

Technical Field

[0001] The present invention relates to the field of computer application technologies, and in particular, to a code generation method, apparatus, electronic device, and storage medium. Background Art

[0002] Modelica is a language for modeling and simulating multi-domain physical systems, which can describe the system behaviors of multiple domains such as electrical, mechanical, and thermodynamics. In the field of hardware design, Verilog is a commonly used hardware description language for describing digital logic circuits. Converting a Modelica model into Verilog code can achieve the conversion from a high-level system-level description to a low-level hardware implementation.

[0003] The traditional method for converting a Modelica model into Verilog code is as follows: first, relevant technicians in the field analyze the model features of the Modelica model, and then manually write Verilog code based on the model features. However, due to the complexity of the Modelica model, the efficiency of code writing is poor and the accuracy is also difficult to guarantee. Therefore, there is currently a lack of a method for automatically, efficiently, and accurately converting a Modelica model into Verilog code. Summary of the Invention

[0004] The present invention provides a code generation method, apparatus, electronic device, and storage medium to solve the technical problem that there is currently a lack of a method for automatically, efficiently, and accurately converting a Modelica model into Verilog code.

[0005] According to one aspect of the present invention, a code generation method is provided, wherein the method includes:

[0006] Obtain a physical behavior model based on a modeling and simulation language, wherein the physical behavior model includes the first physical features and the first behavior features of a target circuit;

[0007] In response to a step size setting operation, determine a discrete time step size, and perform discrete processing on the input physical behavior model based on the discrete time step size to obtain a discrete equivalent model;

[0008] Perform code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model.

[0009] According to another aspect of the present invention, a code generation apparatus is provided, wherein the apparatus includes:

[0010] A model acquisition module, configured to obtain a physical behavior model based on a modeling and simulation language, wherein the physical behavior model includes the first physical features and the first behavior features of a target circuit;

[0011] A discrete processing module, configured to determine a discrete time step in response to a step size setting operation, and perform discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model;

[0012] A code conversion module, configured to perform code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model.

[0013] According to another aspect of the present invention, there is provided an electronic device, including:

[0014] At least one processor; and

[0015] A memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and when the computer program is executed by the at least one processor, the at least one processor is enabled to execute the code generation method according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the code generation method according to any embodiment of the present invention when executed.

[0018] The technical solution of the embodiment of the present invention includes: obtaining a physical behavior model based on a modeling and simulation language, where the physical behavior model includes a first physical feature and a first behavior feature of a target circuit; determining a discrete time step in response to a step size setting operation, and performing discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model; performing code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model. The present invention realizes automatically, efficiently and accurately converting a physical behavior model based on a modeling and simulation language into target code based on a hardware description language.

[0019] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0021] Figure 1 is a flowchart of a code generation method provided in Embodiment 1 of the present invention;

[0022] Figure 2 is a flowchart of a code generation method provided in Embodiment 2 of the present invention;

[0023] Figure 3 is an overall flowchart of a code generation method provided in the embodiments of the present invention;

[0024] Figure 4 is a flowchart of determining a discrete equivalent model provided in the embodiments of the present invention;

[0025] Figure 5 is a schematic structural diagram of a code generation device provided in Embodiment 3 of the present invention;

[0026] Figure 6 is a schematic structural diagram of an electronic device for implementing the code generation method of the embodiments of the present invention. Detailed implementation manners

[0027] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0029] Embodiment 1

[0030] Figure 1 FIG. 0 is a flowchart of a code generation method provided by Embodiment 1 of the present invention. This embodiment is applicable to the case of generating Verilog code corresponding to a Modelica model. This method can be executed by a code generation device, which can be implemented in the form of software and can be configured in computer software. As Figure 1 shown, the method includes:

[0031] S110. Obtain a physical behavior model based on a modeling and simulation language, where the physical behavior model includes a first physical feature and a first behavior feature of a target circuit.

[0032] The modeling and simulation language can be understood as an open and object-oriented language for modeling and simulating dynamic systems. Optionally, the modeling and simulation language can be Modelica.

[0033] The target circuit can be understood as a digital logic circuit.

[0034] The physical behavior model can be understood as a model representing the physical features and behavior features of the target circuit.

[0035] The first physical feature can be understood as the physical feature of the target circuit described by the physical behavior model. The first behavior feature can be understood as the behavior feature of the target circuit described by the physical behavior model. In the embodiments of the present invention, the first physical feature and the first behavior feature are related to the application scenario and are not specifically limited herein.

[0036] S120. In response to a step size setting operation, determine a discrete time step, and perform discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model.

[0037] The step size setting operation can be understood as an operation for setting the discrete time step. In the embodiments of the present invention, the step size setting operation can be preset according to the scenario requirements and is not specifically limited herein. Optionally, the step size setting operation can be a selection operation for a preset step size option.

[0038] The discrete time step can be understood as the time step for discretizing the physical behavior model. In the embodiments of the present invention, the discrete time step can be preset according to the scenario requirements and is not specifically limited herein. Exemplarily, the discrete time step can be 1 s, 2 s, 3 s, etc.

[0039] The discrete equivalent model can be understood as a discretized model equivalent to the physical behavior model.

[0040] In an embodiment of the present invention, the physical behavior model is a physically continuous behavior model in time, and the discrete equivalent model is a discretely equivalent model in time.

[0041] S130. Perform code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model.

[0042] Among them, the hardware description language can be understood as a language that can describe digital logic circuits. Exemplarily, the hardware description language can be Verilog.

[0043] The target code can be understood as code that describes the physical behavior model based on the hardware description language.

[0044] The technical solution of the embodiment of the present invention is to obtain a physical behavior model based on a modeling and simulation language, where the physical behavior model includes the first physical characteristics and the first behavior characteristics of the target circuit; in response to a step size setting operation, determine a discrete time step, and perform discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model; perform code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model. The present invention realizes automatically, efficiently and accurately converting a physical behavior model based on a modeling and simulation language into target code based on a hardware description language.

[0045] Embodiment 2

[0046] Figure 2 It is a flowchart of a code generation method provided in Embodiment 2 of the present invention. This embodiment refines the discrete processing of the input physical behavior model based on the discrete time step in the above embodiment to obtain a discrete equivalent model. As Figure 2 shown, the method includes:

[0047] S210. Obtain a physical behavior model based on a modeling and simulation language, where the physical behavior model includes the first physical characteristics and the first behavior characteristics of the target circuit.

[0048] S220. In response to a step size setting operation, determine a discrete time step.

[0049] S230. Determine the time state variables and dynamic space description of the physical behavior model, and perform discrete processing on the time state variables based on the discrete time step and the dynamic space description to obtain a plurality of discrete time points and discrete state variables corresponding to each discrete time point.

[0050] Among them, the time state variable can be understood as a state variable representing time characteristics. In the embodiments of the present invention, the time state variable can be preset according to the scenario requirements, and no specific limitation is made here.

[0051] The dynamic space description can be understood as a dynamic equation.

[0052] The discrete time points can be understood as discretized time points.

[0053] The discrete state variables can be understood as discretized state variables.

[0054] Optionally, the discrete processing of the time state variable based on the discrete time step and the dynamic space description to obtain a plurality of discrete time points and the discrete state variable corresponding to each discrete time point includes:

[0055] Determine the time state variable at the current time point of the physical behavior model, and determine the time state variable at the next time point based on the dynamic space description and the time state variable at the current time point, where the next time point is a time point determined based on the current time point and the discrete time step;

[0056] Return to execute the operation of determining the time state variable at the next time point based on the dynamic space description and the time state variable at the current time point,

[0057] Take each of the time points as the discrete time point, and take the time state variable corresponding to each discrete time point as the discrete state variable.

[0058] Among them, the determination of the time state variable at the next time point based on the dynamic space description and the time state variable at the current time point includes:

[0059] By the Euler algorithm, determine the time state variable at the next time point based on the dynamic space description and the time state variable at the current time point. Among them, the Euler algorithm can be the forward Euler method or the backward Euler method.

[0060] S240. Discretize the dynamic space description through the Euler algorithm to obtain the discretized dynamic space description.

[0061] Among them, the Euler algorithm can be understood as an algorithm for solving ordinary differential equations with given initial values. Optionally, the Euler algorithm can include the forward Euler method or the backward Euler method.

[0062] S250. Determine the continuous input signal corresponding to the physical behavior model, and determine the discrete output signal corresponding to each discrete time point according to the discrete state variable and the continuous input signal.

[0063] In the embodiment of the present invention, the physical behavior model is a time - continuous physical behavior model, and the discrete equivalent model is a time - discrete discrete equivalent model.

[0064] Among them, the continuous input signal can be understood as the time - continuous input signal corresponding to the physical behavior model.

[0065] The discrete output signal can be understood as the output signal corresponding to each discrete time point.

[0066] Optionally, the determining the discrete output signal corresponding to each discrete time point according to the discrete state variable and the continuous input signal includes:

[0067] Discretize the continuous input signal into signal values corresponding to each discrete time point based on the discrete state variable of each discrete time point;

[0068] For each discrete time point, determine the discrete output signal based on the signal value.

[0069] Among them, the signal value can be understood as the value of the continuous input signal discretized to each discrete time point.

[0070] S260. Determine the discrete equivalent model based on the discrete state variable, the discretized dynamic space description, and the discrete output signal.

[0071] Optionally, the determining the discrete equivalent model based on the discrete state variable, the discretized dynamic space description, and the discrete output signal includes:

[0072] Determine the reference equivalent model corresponding to the physical behavior model based on the discrete state variable, the discretized dynamic space description, and the discrete output signal;

[0073] Determine the second physical feature and the second behavior feature of the target circuit corresponding to the reference equivalent model;

[0074] In the case where the second physical feature is the same as the first physical feature and the first behavior feature is the same as the second behavior feature, use the reference equivalent model as the discrete equivalent model.

[0075] Among them, the reference equivalent model can be understood as a reference equivalent model.

[0076] The second physical feature can be understood as the physical feature of the target circuit described by the reference equivalent model. The second behavioral feature can be understood as the behavioral feature of the target circuit described by the reference equivalent model.

[0077] In the embodiment of the present invention, the equivalence between the discretely processed discrete equivalent model and the time - continuous physical behavior model is ensured.

[0078] S270. Perform code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model.

[0079] Optionally, the performing code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model includes:

[0080] Perform hardware description conversion on the discrete state variables corresponding to the discrete equivalent model, the discretized dynamic space description, and the discrete input signal to obtain conversion code;

[0081] Determine the components of the discrete equivalent model, determine multiple code blocks corresponding to the conversion code based on the components, and for each code block, determine a hardware description template and generate sub - code corresponding to the code block based on the hardware description template;

[0082] Determine the code running timing sequence, and integrate the sub - code based on the code running timing sequence to obtain the target code corresponding to the physical behavior model.

[0083] Wherein, the conversion code can be understood as the code of the hardware description language corresponding to the discrete state variables, the discretized dynamic space description, and the discrete input signal.

[0084] The components can be understood as the components defined in the discrete equivalent model.

[0085] The code blocks can be understood as Verilog code modules.

[0086] The sub - code can be understood as Verilog code segments.

[0087] The hardware description template can be understood as a template for generating sub - code corresponding to the code block. In the embodiment of the present invention, the hardware description templates corresponding to different code blocks can be the same or different.

[0088] The code running timing sequence can be understood as the time sequence for running the sub - code.

[0089] Optionally, the generating sub - code corresponding to the code block based on the hardware description template includes:

[0090] Determine the connection code and transfer parameter values corresponding to each of the code blocks based on the discrete equivalent model, and generate the sub-code based on the hardware description template, the connection code, and the transfer parameter values.

[0091] Wherein, the connection code is a code characterizing the connection relationship between the discrete output signals and the connection relationship between the discrete output signals and the ports of the code block, and the transfer parameter values include at least one of the parameter values of the ports of the code block, the parameter values of the discrete output signals, and the parameter values of the code block.

[0092] In the embodiments of the present invention, the efficiency, accuracy, and comprehensiveness of code conversion for the discrete equivalent model are ensured.

[0093] The technical solution of the embodiments of the present invention determines the time state variables and dynamic space descriptions of the physical behavior model, discretizes the time state variables based on the discrete time step and the dynamic space description to obtain a plurality of discrete time points and the discrete state variables corresponding to each of the discrete time points; discretizes the dynamic space description through the Euler algorithm to obtain the discretized dynamic space description; determines the continuous input signals corresponding to the physical behavior model, and determines the discrete output signals corresponding to each of the discrete time points according to the discrete state variables and the continuous input signals; determines the discrete equivalent model based on the discrete state variables, the discretized dynamic space description, and the discrete output signals. The accuracy of the discrete processing of the physical behavior model is improved, and the equivalence between the discrete equivalent model obtained by the discrete processing and the time-continuous physical behavior model is ensured.

[0094] Figure 3 is the overall flowchart of a code generation method provided according to an embodiment of the present invention. As Figure 3 shown, wherein, the Modelica model represents the physical behavior model. Optionally, the overall process of the code generation method may be:

[0095] 1. Modelica model input. The Modelica model describes the physical characteristics and behavioral characteristics of the target circuit.

[0096] 2. Discretization processing. Perform discretization processing on the Modelica model to discretize the continuous-time Modelica model into a discrete equivalent model of discrete time. Figure 4 is the flowchart of a method for determining a discrete equivalent model provided according to an embodiment of the present invention. As Figure 4 shown, the specific process of determining the discrete equivalent model (i.e., discretizing the Modelica model) may be:

[0097] Determine the time state variables of the Modelica model, discretize the time state variables through the forward Euler algorithm or the backward Euler algorithm, that is, calculate the time state variables at the next time point based on the time state variables and the dynamic space description at the current time point; use the selected Euler algorithm to transform the dynamic space description of the Modelica model into the dynamic space description of the discrete equivalent model in discrete time; discretize the continuous input signals of the continuous-time Modelica model into signal values at discrete time points, and calculate the discrete output signals at discrete time points according to the discretized state variables and continuous input signals; simulate and verify the discretized model to ensure that the physical characteristics and behavioral characteristics of the discrete equivalent model are consistent with those of the continuous-time Modelica model.

[0098] 3. Signal mapping. Perform code transformation on the discrete equivalent model to transform the component and signal information in the discrete equivalent model into Verilog code. Specifically, perform equivalent mapping on the state variables, input and output signals, and dynamic equations of the components.

[0099] 4. Module generation. Generate Verilog code modules according to the components defined in the discrete equivalent model. For a discrete equivalent model with a hierarchical structure, Verilog code sub-modules can also be generated recursively to form a hierarchical Verilog code structure.

[0100] 5. Connection generation. Generate corresponding Verilog connection code according to the connection relationships defined in the discrete equivalent model. Among them, the connection code includes the connection code between signals and the connection code between signals and module ports.

[0101] 6. Parameter passing. Pass the parameters defined in the discrete equivalent model into the generated Verilog code. Specifically, pass the parameter values to the corresponding Verilog signals, module ports, or module parameters.

[0102] 7. Code output. Each Verilog code module generates a Verilog code segment based on the hardware description template, and finally integrates the code segments according to the running timing, and outputs the generated Verilog code in the form of a file for further simulation, synthesis, and placement and routing operations in practical applications.

[0103] Based on the technical solution of the embodiment of the present invention, the problem of high complexity and low efficiency in traditional manual writing of Verilog code is solved. This application can automatically generate Verilog code, reduce manual operations, and improve the code generation efficiency.

[0104] The target code (Verilog code) generated by this application based on the hardware description language can accurately and comprehensively reflect the physical characteristics and behavioral features of the target circuit in the physical behavior model (Modelica model) based on the modeling and simulation language, ensuring the comprehensiveness and accuracy of code generation.

[0105] This application realizes determining data such as discrete time steps that meet the real-time scenario requirements based on human-computer interaction, and realizes the automatic generation of personalized Verilog code.

[0106] Embodiment III

[0107] Figure 5 It is a schematic structural diagram of a code generation device provided in Embodiment III of the present invention. As Figure 5 shown, the device includes: a model acquisition module 310, a discrete processing module 320, and a code conversion module 330. Among them,

[0108] The model acquisition module 310 is used to acquire a physical behavior model based on the modeling and simulation language, where the physical behavior model includes the first physical characteristics and the first behavioral characteristics of the target circuit; the discrete processing module 320 is used to determine a discrete time step in response to a step size setting operation, and perform discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model; the code conversion module 330 is used to perform code conversion on the discrete equivalent model to generate the target code based on the hardware description language corresponding to the physical behavior model.

[0109] The technical solution of the embodiment of the present invention is to acquire a physical behavior model based on the modeling and simulation language, where the physical behavior model includes the first physical characteristics and the first behavioral characteristics of the target circuit; determine a discrete time step in response to a step size setting operation, and perform discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model; perform code conversion on the discrete equivalent model to generate the target code based on the hardware description language corresponding to the physical behavior model. The present invention realizes automatically, efficiently and accurately converting the physical behavior model based on the modeling and simulation language into the target code based on the hardware description language.

[0110] Optionally, the discrete processing module 320 includes: a variable discrete unit, a spatial description discrete unit, a signal discrete unit, and a model discrete unit; where

[0111] The variable discrete unit is used to determine the time state variables and dynamic spatial descriptions of the physical behavior model, and perform discrete processing on the time state variables based on the discrete time step and the dynamic spatial descriptions to obtain a plurality of discrete time points and the discrete state variables corresponding to each discrete time point;

[0112] The spatial description unit describes discrete elements and is used to discretize the dynamic spatial description through the Euler algorithm to obtain the discretized dynamic spatial description;

[0113] The signal discretization unit is used to determine the continuous input signal corresponding to the physical behavior model, and determine the discrete output signal corresponding to each discrete time point according to the discrete state variables and the continuous input signal;

[0114] The model discretization unit is used to determine the discrete equivalent model based on the discrete state variables, the discretized dynamic spatial description, and the discrete output signal.

[0115] Optionally, the variable discretization unit is used for:

[0116] Determine the time state variable at the current time point of the physical behavior model, and determine the time state variable at the next time point based on the dynamic spatial description and the time state variable at the current time point, where the next time point is a time point determined based on the current time point and the discrete time step;

[0117] Return to execute the operation of determining the time state variable at the next time point based on the dynamic spatial description and the time state variable at the current time point,

[0118] Take each of the time points as the discrete time point, and take the time state variable corresponding to each discrete time point as the discrete state variable.

[0119] Optionally, the signal discretization unit is used for:

[0120] Discretize the continuous input signal into signal values corresponding to each discrete time point based on the discrete state variables at each discrete time point;

[0121] For each discrete time point, determine the discrete output signal based on the signal value.

[0122] Optionally, the model discretization unit is used for:

[0123] Determine the reference equivalent model corresponding to the physical behavior model based on the discrete state variables, the discretized dynamic spatial description, and the discrete output signal;

[0124] Determine the second physical characteristics and the second behavior characteristics of the target circuit corresponding to the reference equivalent model;

[0125] In the case where the second physical characteristics are the same as the first physical characteristics and the first behavior characteristics are the same as the second behavior characteristics, use the reference equivalent model as the discrete equivalent model.

[0126] Optionally, the code conversion module 330 includes: a code conversion unit, a template application unit, and a code integration unit; wherein,

[0127] The code conversion unit is configured to perform a hardware description conversion on the discrete state variables corresponding to the discrete equivalent model, the discretized dynamic space description, and the discrete input signal to obtain conversion code;

[0128] The template application unit is configured to determine components of the discrete equivalent model, determine a plurality of code blocks corresponding to the conversion code based on the components, and for each of the code blocks, determine a hardware description template and generate sub-code corresponding to the code block based on the hardware description template;

[0129] The code integration unit is configured to determine a code running timing sequence, and integrate the sub-code based on the code running timing sequence to obtain the target code corresponding to the physical behavior model.

[0130] Optionally, the template application unit is configured to:

[0131] Determine connection code and transfer parameter values corresponding to each of the code blocks based on the discrete equivalent model, and generate the sub-code based on the hardware description template, the connection code, and the transfer parameter values,

[0132] wherein, the connection code is code characterizing the connection relationship between the discrete output signals and the connection relationship between the discrete output signals and the ports of the code blocks, and the transfer parameter values include at least one of the parameter values of the ports of the code blocks, the parameter values of the discrete output signals, and the parameter values of the code blocks.

[0133] The code generation device provided by the embodiments of the present invention can execute the code generation method provided by any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method.

[0134] Embodiment 4

[0135] Figure 6FIG. 0 shows a schematic structural diagram of an electronic device 10 that can be used to implement embodiments of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0136] As Figure 6 shown, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc. The memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0137] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0138] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the code generation method.

[0139] In some embodiments, the code generation method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the code generation method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the code generation method by any other suitable means (e.g., by means of firmware).

[0140] The various embodiments of the systems and techniques described above in this document may be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems on a chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: implemented in one or more computer programs that may be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0141] The computer program for implementing the method of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that the computer program, when executed by the processor, causes the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0142] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0143] To provide for interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0144] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0145] A computing system may include a client and a server. The client and the server are generally far from each other and usually interact via a communication network. The relationship between the client and the server is created by computer programs that run on respective computers and have a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, and solves the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0146] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0147] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A code generation method, characterized in that, Including: Obtain a physical behavior model based on a modeling and simulation language, where the physical behavior model includes first physical characteristics and first behavior characteristics of a target circuit; In response to a step size setting operation, determine a discrete time step, and perform discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model; Perform code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model; Wherein, the performing discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model includes: Determine time state variables and a dynamic space description of the physical behavior model, and perform discrete processing on the time state variables based on the discrete time step and the dynamic space description to obtain a plurality of discrete time points and discrete state variables corresponding to each discrete time point; Perform discrete processing on the dynamic space description through an Euler algorithm to obtain a discretized dynamic space description; Determine a continuous input signal corresponding to the physical behavior model, and determine discrete output signals corresponding to each discrete time point according to the discrete state variables and the continuous input signal; Determine the discrete equivalent model based on the discrete state variables, the discretized dynamic space description, and the discrete output signals.

2. The method according to claim 1, wherein The performing discrete processing on the time state variables based on the discrete time step and the dynamic space description to obtain a plurality of discrete time points and discrete state variables corresponding to each discrete time point includes: Determine the time state variables at the current time point of the physical behavior model, and determine the time state variables at the next time point based on the dynamic space description and the time state variables at the current time point, where the next time point is a time point determined based on the current time point and the discrete time step; Return to perform the operation of determining the time state variables at the next time point based on the dynamic space description and the time state variables at the current time point; Use each of the time points as the discrete time points, and use the time state variables corresponding to each discrete time point as the discrete state variables.

3. The method according to claim 1, wherein The determining discrete output signals corresponding to each discrete time point according to the discrete state variables and the continuous input signal includes: Discretize the continuous input signal into signal values corresponding to each discrete time point based on the discrete state variables at each discrete time point; For each discrete time point, determine the discrete output signal based on the signal value.

4. The method according to claim 1, characterized in that, The determining the discrete equivalent model based on the discrete state variables, the discretized dynamic space description, and the discrete output signals includes: Determine a reference equivalent model corresponding to the physical behavior model based on the discrete state variables, the discretized dynamic space description, and the discrete output signals; Determine second physical characteristics and second behavior characteristics of the target circuit corresponding to the reference equivalent model; In the case where the second physical feature is the same as the first physical feature and the first behavioral feature is the same as the second behavioral feature, the reference equivalent model is used as the discrete equivalent model.

5. The method according to claim 1, characterized in that, The code conversion of the discrete equivalent model to generate the target code based on a hardware description language corresponding to the physical behavior model includes: Performing a hardware description conversion on the discrete state variables corresponding to the discrete equivalent model, the discretized dynamic space description, and the discrete output signal to obtain conversion code; Determining the components of the discrete equivalent model, determining a plurality of code blocks corresponding to the conversion code based on the components, and for each of the code blocks, determining a hardware description template and generating sub-code corresponding to the code block based on the hardware description template; Determining the code running timing, and integrating the sub-code based on the code running timing to obtain the target code corresponding to the physical behavior model.

6. The method according to claim 5, characterized in that, The generating of the sub-code corresponding to the code block based on the hardware description template includes: Determining connection code and transfer parameter values corresponding to each of the code blocks based on the discrete equivalent model, and generating the sub-code based on the hardware description template, the connection code, and the transfer parameter values, wherein the connection code is code representing the connection relationship between the discrete output signals and the connection relationship between the discrete output signals and the ports of the code block, and the transfer parameter values include at least one of the parameter values of the ports of the code block, the parameter values of the discrete output signals, and the parameter values of the code block.

7. A code generation device, characterized in that, It includes: A model acquisition module, configured to acquire a physical behavior model based on a modeling and simulation language, wherein the physical behavior model includes the first physical feature and the first behavioral feature of the target circuit; A discrete processing module, configured to determine a discrete time step in response to a step size setting operation, and perform discrete processing on the input physical behavior model based on the discrete time step to obtain a discrete equivalent model; A code conversion module, configured to perform code conversion on the discrete equivalent model to generate target code based on a hardware description language corresponding to the physical behavior model; wherein the discrete processing module includes: a variable discretization unit, a space description discretization unit, a signal discretization unit, and a model discretization unit; wherein the variable discretization unit is configured to determine the time state variables and the dynamic space description of the physical behavior model, and perform discrete processing on the time state variables based on the discrete time step and the dynamic space description to obtain a plurality of discrete time points and the discrete state variables corresponding to each of the discrete time points; The space description discretization unit is configured to perform discrete processing on the dynamic space description by using an Euler algorithm to obtain the discretized dynamic space description; The signal discretization unit is configured to determine the continuous input signals corresponding to the physical behavior model, and determine the discrete output signals corresponding to each of the discrete time points according to the discrete state variables and the continuous input signals; The model discrete unit is used to determine the discrete equivalent model based on the discrete state variables, the discretized dynamic space description, and the discrete output signal.

8. An electronic device, characterized in that, The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the code generation method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for implementing the code generation method according to any one of claims 1-6 when executed by a processor.

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