A Wide Bandgap Semiconductor Trench MOSFET Device Structure and Its Fabrication Method

Abstract

The present invention provides a wide-bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof, belonging to the technical field of semiconductor devices. The MOSFET device structure includes a substrate, a first epitaxial layer, a P+ buried layer, a second epitaxial layer, a P well region, and a source electrode sequentially arranged on the substrate, a drain electrode deposited on the surface of the substrate facing away from the first epitaxial layer, at least one gate electrode penetrating the P well region, and an interlayer dielectric layer for isolating the gate electrode and the source electrode. The gate electrode includes a gate dielectric layer and a gate material deposited in the gate trench. The bottom of the gate electrode is located in the second epitaxial layer; the P+ buried layer is provided with first current channels and second current channels arranged alternately; the first current channels are located directly below the gate electrode. The MOSFET device structure can not only improve the on-state characteristics of the device, but also provide better protection for the corners of the gate trench, and at the same time, it does not sacrifice the chip area.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a wide-bandgap semiconductor trench MOSFET device structure and a preparation method thereof. Background Art

[0002] Power devices prepared from wide-bandgap semiconductor materials have lower power losses and higher conversion efficiencies, and can be applied to various extremely harsh environments. Common wide-bandgap semiconductor materials mainly include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), etc. P-type doping of silicon carbide devices can be achieved by ion implantation or epitaxial growth. However, for materials with a larger bandgap than silicon carbide, such as gallium nitride, gallium oxide, diamond, and aluminum nitride, it is difficult to achieve P-type doping by ion implantation, and P-type can be achieved through special processes such as epitaxial growth or oxides.

[0003] Currently, the following main problems exist in the actual process fabrication and application of wide-bandgap semiconductor trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices: (1) The high electric field in the material drift region results in a very high electric field on the gate dielectric layer, which is aggravated at the trench corners, thus causing the gate dielectric layer to break down rapidly under high drain voltages; the tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit is poor. (2) In order to reduce the gate trench corner electric field, traditional devices need to sacrifice some chip area, so the on-state characteristics of the devices deteriorate. Summary of the Invention

[0004] To solve at least one of the above problems, the present invention provides a wide-bandgap semiconductor trench MOSFET device structure. This MOSFET device structure can not only improve the on-state characteristics of the device, but also better protect the trench corners of the gate, and at the same time, it does not sacrifice the chip area.

[0005] Specifically, the present invention adopts the following technical solutions to achieve the above purpose:

[0006] A wide-bandgap semiconductor trench MOSFET device structure includes a substrate, a first epitaxial layer disposed on the substrate, a P+ buried layer disposed on the first epitaxial layer, a second epitaxial layer disposed on the P+ buried layer, a P well region disposed on the second epitaxial layer, a source electrode deposited on the P well region, at least one gate penetrating the P well region, an interlayer dielectric layer, and a drain electrode; the drain electrode is deposited on the surface of the substrate facing away from the first epitaxial layer; the interlayer dielectric layer is used to isolate the source electrode and the gate; the gate includes a gate dielectric layer and a gate material deposited in a gate trench; the bottom of the gate is located in the second epitaxial layer; the P+ buried layer is provided with first current channels and second current channels arranged alternately; the first current channels are located directly below the gate.

[0007] In a preferred embodiment of the present invention, source trenches are disposed on both sides of the gate trench, a source dielectric layer and polysilicon are deposited in the source trenches, and a source P+ region is disposed around the outer wall of the source trenches; the second current channels are located directly below the source trenches and are in contact with the source P+ region.

[0008] In a further preferred embodiment of the present invention, the wide-bandgap semiconductor trench MOSFET device structure further includes a P+ masking layer located between the gate trench and the first current channels, and the P+ masking layer is electrically connected to the source P+ region.

[0009] In a still further preferred embodiment of the present invention, the wide-bandgap semiconductor trench MOSFET device structure further includes a P+ grounding post located in the second epitaxial layer, and the P+ grounding post is used to electrically connect the P+ buried layer and the P+ masking layer.

[0010] In a preferred embodiment of the present invention, a source N+ region is disposed between the P well region and the source electrode, and both the source N+ region and the source P+ region form ohmic contacts with the source electrode.

[0011] In a preferred embodiment of the present invention, the first epitaxial layer is an N-epitaxial layer, or / and the second epitaxial layer is an N-epitaxial layer.

[0012] In a preferred embodiment of the present invention, the material of the substrate is one of SiC, GaN, Ga2O3, diamond, and AlN.

[0013] Another object of the present invention is to provide a method for manufacturing the wide-bandgap semiconductor trench MOSFET device structure, including the following steps:

[0014] A first epitaxial layer, a P+ buried layer, and a second epitaxial layer are sequentially epitaxially grown on a substrate; a P well region is formed on a surface of the second epitaxial layer away from the P+ buried layer by an ion implantation method, a secondary epitaxy method, or a method of growing a P-type oxide; a gate trench is etched in the obtained device structure, and a gate dielectric layer and a gate material are deposited in the gate trench to fabricate a gate; an interlayer dielectric is deposited on the obtained device structure, the interlayer dielectric in contact with the gate is retained, and the interlayer dielectric in the remaining regions is removed to obtain an interlayer dielectric layer; a first current channel is formed in the P+ buried layer directly below the gate trench by an N-type ion implantation method, and second current channels are formed in the P+ buried layer on both sides of the first current channel by an N-type ion implantation method; finally, a source metal layer and a drain metal layer are deposited to obtain a source and a drain respectively.

[0015] In a preferred embodiment of the present invention, the method for preparing the wide bandgap semiconductor trench MOSFET device structure further includes the following steps: source trenches are etched on both sides of the gate trench; a source dielectric layer and polysilicon are deposited in the source trenches, and a source P+ region is formed around an outer wall of the source trenches by an ion implantation method.

[0016] In a preferred embodiment of the present invention, the method for preparing the wide bandgap semiconductor trench MOSFET device structure further includes the following steps: a source N+ region is formed on a surface of the P well region away from the second epitaxial layer by an ion implantation method.

[0017] In a preferred embodiment of the present invention, the method for preparing the wide bandgap semiconductor trench MOSFET device structure further includes the following steps: a P+ masking layer in contact with an outer surface of a bottom of the gate trench is formed in the second epitaxial layer by a P-type ion implantation method.

[0018] In a preferred embodiment of the present invention, the method for preparing the wide bandgap semiconductor trench MOSFET device structure further includes the following steps: a P+ ground post is formed in the second epitaxial layer by a P-type ion implantation method.

[0019] Compared with the prior art, the present invention has the following beneficial effects: (1) In the present invention, a P+ buried layer, a first current channel, and a second current channel are constructed under the gate trench to form a deep masking structure, which protects the trench corners of the gate trench and does not sacrifice the chip area at the same time; the current flows through the two current channels spatially respectively, improving the on-state characteristics of the device. (2) In the present invention, a P+ masking layer and a P+ grounding column are further constructed in the device to keep the P+ masking layer grounded, so as to further reduce the gate oxide electric field and improve the reliability of the device. (3) In the present invention, polysilicon is further deposited in the source trench, and a source N+ region is constructed in the device. By forming an ohmic contact at the source, the source N+ region, the source polysilicon, the source P+ region, the P+ buried layer, the P+ grounding column, and the P+ masking layer are short-circuited together, further improving the on-state characteristics of the device, while having good protection for the gate trench corners and not sacrificing the chip area. Description of the Drawings

[0020] Figure 1 It is the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention;

[0021] Figure 2 、 Figure 3 、 Figure 7 、 Figure 8 It is a schematic diagram of the device structure obtained during the process of preparing the wide-bandgap semiconductor trench MOSFET device structure in Embodiment 2 of the present invention;

[0022] Figure 4 、 Figure 5 It is a schematic diagram of the device structure obtained during the process of preparing the wide-bandgap semiconductor trench MOSFET device structure in Embodiment 3 of the present invention;

[0023] Figure 6 It is a schematic diagram of the device structure obtained during the process of preparing the wide-bandgap semiconductor trench MOSFET device structure in Embodiment 4 of the present invention;

[0024] Figures 9 to 11 It is a schematic diagram of various forms of the device structure obtained when forming the first current channel in the P+ buried layer by N-type ion implantation during the process of preparing the wide-bandgap semiconductor trench MOSFET device structure in Embodiment 4 of the present invention;

[0025] Figures 12 to 16 It is the different arrangement modes of the first current channel, the second current channel, and the P+ grounding column in the P+ buried layer when preparing the wide-bandgap semiconductor trench MOSFET device structure in Embodiment 4 of the present invention;

[0026] Figure 17 is Figure 1Schematic diagram of the path of electrons in the middle cross-section A passing through the first current channel;

[0027] Figure 18 For Figure 1 Schematic diagram of the path of electrons in the middle cross-section B passing through the second current channel.

[0028] In the figure: 1. Substrate; 21. First epitaxial layer; 22. Second epitaxial layer; 3. P+ buried layer; 4. P well region; 5. Source N+ region; 6. Gate; 61. Gate trench; 62. Gate dielectric layer; 63. Polysilicon; 71. Source trench; 72. Source dielectric layer; 81. First current channel; 82. Second current channel; 9. Interlayer dielectric layer; 10. Source; 11. Drain; 12. P+ mask layer; 13. Source P+ region; 14. Ohmic contact region; 15. P+ grounding post. Detailed implementation manners

[0029] The following content describes the technical solutions of the present invention clearly and completely in combination with embodiments, so that those skilled in the art can fully understand the present invention. Obviously, the described embodiments are only some preferred embodiments of the present invention, rather than all embodiments. Any equivalent transformation or substitution made by those of ordinary skill in the art to the following embodiments without creative work shall fall within the protection scope of the present invention.

[0030] Directional terms mentioned in this article, such as words like "up" and "down", refer to the directions in the drawings. Therefore, the directional terms are only for illustration and not for limiting the present disclosure. Ordinal numbers used in this article, such as "first", "second", etc., are only for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0031] Embodiment 1

[0032] As Figure 1 shown, this embodiment provides a wide-bandgap semiconductor trench MOSFET device structure. The MOSFET device structure includes a substrate 1, a first epitaxial layer 21 grown on the substrate 1, a P+ buried layer 3 grown on the first epitaxial layer 21, a second epitaxial layer 22 grown on the P+ buried layer 3, a P well region 4 provided on the second epitaxial layer 22, a source 10 deposited on the P well region 4, at least one gate 6 penetrating the P well region 4, an interlayer dielectric layer 9, and a drain 11. The drain 11 is deposited on the surface of the substrate 1 facing away from the first epitaxial layer 21. The interlayer dielectric layer 9 is used to isolate the source 10 and the gate 6. The gate 6 includes a deposition in the gate trench 61 ( Figure 1The gate dielectric layer 62 and the polysilicon 63 as the gate material (not shown in the figure) are within the gate trench 61. The bottom of the gate 6 is located in the second epitaxial layer 22. The P+ buried layer 3 is provided with the first current channels 81 and the second current channels 82 arranged alternately; the first current channels 81 are located directly below the gate. Among them, the first epitaxial layer is an N-epitaxial layer, and the second epitaxial layer is an N-epitaxial layer.

[0033] Further, source trenches 71 are provided on both sides of the gate trench 61. Anode dielectric layers 72 and polysilicon 63 are deposited in the source trenches 71. An anode P+ region 13 is provided around the outer wall of the source trench 71. The second current channels 82 are located directly below the source trenches 71 and are in contact with the anode P+ region 13.

[0034] Further, an anode N+ region 5 is provided between the P well region 4 and the anode 10, and both the anode N+ region 5 and the anode P+ region 13 form ohmic contacts with the anode 10 through ohmic contact regions 14.

[0035] Still further, a P+ masking layer 12 is provided between the gate trench 61 and the first current channels 81, and the P+ masking layer 12 is electrically connected to the anode P+ region 13.

[0036] Even further, a P+ grounding post 15 is provided in the second epitaxial layer 22, and the P+ grounding post 15 is used to electrically connect the P+ buried layer 3 and the P+ masking layer 12.

[0037] As Figure 17 and Figure 18 shown, Figure 17 is Figure 1 the path through which electrons in the cross-section A in the figure pass through the first current channels 81, Figure 18 is Figure 1 the path through which electrons in the cross-section B in the figure pass through the second current channels 82. Electrons can pass through in two paths from the first current channels 81 and the second current channels 82 spatially. Further, the P+ masking layer 12 can also be grounded spatially through the P+ grounding post 15 and the P+ buried layer 3, improving the on-state characteristics of the device and protecting the gate trench corners well at the same time.

[0038] Embodiment 2

[0039] The preparation method of the wide-bandgap semiconductor trench MOSFET device structure provided in this embodiment includes the following steps:

[0040] S1. Referring to Figure 1 the cross-section A in the figure, grow the first epitaxial layer 21 on the substrate 1. The material of the substrate 1 is the wide-bandgap semiconductor material SiC.

[0041] S2. Referring to Figure 1In cross-section A, a P+ buried layer 3 is grown on the surface of the first epitaxial layer 21.

[0042] S3. Refer to Figure 1 In cross-section A, a second epitaxial layer 22 is grown on the surface of the P+ buried layer 3.

[0043] S4. Refer to Figure 1 In cross-section A, a P-well region 4 is formed on the surface of the second epitaxial layer 22 by ion implantation; then a source N+ region 5 is formed on the surface of the p-well region 4 by ion implantation, obtaining the structure as Figure 2 shown.

[0044] S5. Refer to Figure 1 In cross-section A and Figure 3 , gate trenches 61 and source trenches 71 are formed on the structure of Figure 2 by dry etching; the gate trenches 61 and the source trenches 71 are arranged alternately.

[0045] S6. Refer to Figure 1 In cross-section A, a first current channel 81 is formed in the P+ buried layer 3 by N-type ion implantation at a position directly below the gate trench 61. A second current channel 82 is formed in the P+ buried layer 3 by N-type ion implantation at a position directly below the source trench 71.

[0046] S7. Refer to Figure 1 In cross-section A, cross-section B and Figure 7 , Figure 8 , a gate dielectric layer 62 and a source dielectric layer 72 are respectively deposited along the inner walls in the gate trenches 61 and the source trenches 71. Polysilicon 63 is deposited as the gate material in the gate trench 61 (see Figure 3 ), and polysilicon 63 is deposited in the source trench 71 (see Figure 3 ). The polysilicon 63 is in contact with the surfaces of the gate dielectric layer 62 and the source dielectric layer 72 respectively. An interlayer dielectric is deposited on the surface of the obtained device structure, and the interlayer dielectric in contact with the upper end surfaces of the polysilicon 63 and the gate dielectric layer 62 at the opening of the gate trench 61 is retained, and the interlayer dielectric in the remaining regions is removed to obtain an interlayer dielectric layer 9. Then, a source metal layer is continuously deposited on the surface of the obtained device structure to obtain a source 10. A drain metal layer is deposited on the surface of the substrate 1 facing away from the first epitaxial layer 21 to obtain a drain 11. Thus, a MOSFET device structure is obtained.

[0047] Embodiment 3

[0048] The difference between the preparation method of the wide-bandgap semiconductor trench MOSFET device structure provided in this embodiment and that of Embodiment 2 lies in:

[0049] Step S5. Refer to Figure 1 In cross-section A,Figure 3 , Figure 4 and Figure 5 , a gate trench 61 and a source trench 71 are formed on the structure of Figure 2 by dry etching; a P+ mask layer 12 is formed in the second epitaxial layer 22 by P-type ion implantation, and the P+ mask layer 12 is in contact with the outer surface of the bottom of the gate trench 61. The first current channel 81 is located directly below the P+ mask layer 12. A source P+ region 13 is formed around the outer sidewall of the source trench 71 by P-type ion implantation. The second current channel 82 is located directly below the source P+ region 13 and is in contact with it. The P+ mask layer 12 is electrically connected to the source P+ region 13. Both the source P+ region 13 and the source N+ region 5 form an ohmic contact region 14 with the source 10.

[0050] Embodiment 4

[0051] The difference between the preparation method of the wide-bandgap semiconductor trench MOSFET device structure provided in this embodiment and that in Embodiment 3 is as follows:

[0052] S6. Referring to Figure 1 in cross-section A and Figures 3 to 5 , at the position directly below the gate trench 61, a first current channel 81 is formed in the P+ buried layer 3 by N-type ion implantation. At the position directly below the source trench 71, a second current channel 82 is formed in the P+ buried layer 3 by N-type ion implantation. Referring to Figure 1 in cross-section B and Figure 6 , a P+ ground post 15 is formed in the second epitaxial layer 22 by P-type ion implantation, and the P+ ground post 15 is used to electrically connect the P+ buried layer 3 and the P+ mask layer 12. The finally obtained device structure is as shown in Figure 1 .

[0053] Referring to Figure 1 and Figures 9 to 11 , as an implementation manner of the present invention, Figure 9 when forming the first current channel 81 in the P+ buried layer 3 by N-type ion implantation in step S6, by controlling the thickness of the ion implantation mask at the sidewall of the gate trench 61, using the effect of lateral diffusion of the sidewall, a current spreading layer is naturally formed on part of the current path, so that the P+ mask layer 12 naturally forms a crescent shape, which can reduce the on-resistance of the device and improve the on-characteristics of the device. As another implementation manner of the present invention, Figure 10When forming the first current channel 81 in the P+ buried layer 3 by means of N-type ion implantation in step S6, the ion implantation has a lateral dispersion effect on the sidewalls of the gate trench 61, and a current spreading layer is naturally formed on the current path. At the same time, due to the trailing of the implantation, a partial current spreading layer is naturally formed at the low-concentration part at the bottom of the P+ mask layer 12, which can reduce the on-resistance of the device and improve the on-characteristics of the device. As another embodiment of the present invention, Figure 11 When forming the first current channel 81 in the P+ buried layer 3 by means of N-type ion implantation in step S6, the ion implantation has a lateral dispersion effect on the sidewalls of the gate trench 61, and a deeper current spreading layer is naturally formed on all current paths, which can reduce the on-resistance of the device and improve the on-characteristics of the device.

[0054] Referring to Figure 1 and Figures 12 to 16 , Figures 12 to 16 are different arrangement manners of the first current channel 81, the second current channel 82, and the P+ ground post 15 in the P+ buried layer 3.

[0055] It should be noted that the material of the substrate 1 can be any one of GaN, Ga2O3, diamond, and AlN in addition to silicon carbide. The formation method of the P well region 4 can also adopt secondary epitaxy or the method of growing a P-type oxide in addition to the ion implantation method.

[0056] The above are only the preferred embodiments of the present invention and are not used to limit the protection scope of the present invention. For any person skilled in the art, various changes and modifications can be made to the present invention. Any simple equivalent changes and modifications made according to the protection scope of the present invention application and the content of the specification should be included in the protection scope of the present invention.

Claims

1. A wide-bandgap semiconductor trench MOSFET device structure, characterized in that, It includes a substrate, a first epitaxial layer disposed on the substrate, a P+ buried layer disposed on the first epitaxial layer, a second epitaxial layer disposed on the P+ buried layer, a P well region disposed on the second epitaxial layer, a source electrode deposited on the P well region, at least one gate penetrating the P well region, an interlayer dielectric layer, and a drain electrode; the drain electrode is deposited on the surface of the substrate facing away from the first epitaxial layer; The interlayer dielectric layer is used to isolate the source electrode and the gate; the gate includes a gate dielectric layer and a gate material deposited in a gate trench; the bottom of the gate is located in the second epitaxial layer; The P+ buried layer is provided with first current channels and second current channels arranged alternately; The first current channels are located directly below the gate; source trenches are provided on both sides of the gate trench, and a source dielectric layer and polysilicon are deposited in the source trenches, and a source P+ region is provided around the outer wall of the source trenches; The second current channels are located directly below the source trenches and are in contact with the source P+ regions; The MOSFET device structure further includes a P+ masking layer located between the gate trench and the first current channels, and the P+ masking layer is electrically connected to the source P+ regions.

2. The wide-bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that It further includes a P+ grounding post located in the second epitaxial layer, and the P+ grounding post is used to electrically connect the P+ buried layer and the P+ masking layer.

3. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, wherein A source N+ region is provided between the P well region and the source electrode, and both the source N+ region and the source P+ region form ohmic contacts with the source electrode.

4. The wide-bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that, The first epitaxial layer is an N- epitaxial layer, or / and the second epitaxial layer is an N- epitaxial layer.

5. The wide-bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that, The material of the substrate is one of SiC, GaN, Ga2O3, diamond, and AlN.

6. The manufacturing method of the wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 5, characterized in that It includes the following steps: Epitaxially grow a first epitaxial layer, a P+ buried layer, and a second epitaxial layer on the substrate in sequence; form a P well region on the surface of the second epitaxial layer away from the P+ buried layer by means of ion implantation or secondary epitaxy or by growing a P-type oxide; etch a gate trench in the obtained device structure, and etch source trenches on both sides of the gate trench; Form a P+ masking layer in contact with the outer surface of the bottom of the gate trench in the second epitaxial layer by means of P-type ion implantation; Form a source P+ region around the outer sidewall of the source trenches by means of P-type ion implantation; Deposit a gate dielectric layer and a gate material in the gate trench to fabricate the gate; deposit a source dielectric layer and polysilicon in the source trenches; Deposit an interlayer dielectric on the obtained device structure, retain the interlayer dielectric in contact with the gate, and remove the interlayer dielectric in the remaining regions to obtain the interlayer dielectric layer; Form first current channels in the P+ buried layer directly below the gate trench by means of N-type ion implantation, and form second current channels in the P+ buried layer on both sides of the first current channels by means of N-type ion implantation; Finally, deposit a source metal layer and a drain metal layer to obtain the source electrode and the drain electrode respectively.

7. The preparation method according to claim 6, characterized in that, It includes the following steps: Form a source N+ region on the surface of the P well region away from the second epitaxial layer by means of ion implantation.

8. The preparation method according to claim 6, characterized in that, It includes the following steps: forming a P+ grounding column in the second epitaxial layer by means of P-type ion implantation.

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