A control method of a dead-time-free three-level topology

Abstract

The application relates to a dead-zone-free three-level topology, which comprises a capacitor C1 connected with the positive pole of a direct current source and the collector of an IGBT transistor S1 respectively, the other end of the capacitor C1 is connected with one end of a capacitor C2, the anode of a diode D1 and the cathode of a diode D2 respectively, the anode of the diode D2 is connected with the emitter of an IGBT transistor S3 and the collector of an IGBT transistor S4 respectively, the collector of the IGBT transistor S1 is connected with the cathode of a diode D3, the emitter of the IGBT transistor S1 is connected with the cathode of the diode D1 and the collector of an IGBT transistor S2 respectively, and the emitter of the IGBT transistor S2 is connected with the cathode of a diode D4 and one end of an inductor L1 respectively. The application further discloses a control method of the dead-zone-free three-level topology. The bridge arm in the application has no risk of through, and a dead zone needs not to be added in a driving signal, so that the dead zone can be avoided from introducing additional low-order harmonics to reduce the output power quality of the circuit; high-voltage and small-current diodes are easy to be selected, and the number of diodes is further reduced.

Description

Technical Field

[0001] This invention relates to the field of three-level topology technology, and in particular to a control method for a dead-zone-free three-level topology. Background Technology

[0002] Three-level topologies are typically used in high-voltage, high-power applications. To avoid shoot-through issues in the bridge arms, a dead time needs to be added to the drive signal. When the drive signal of one power switch goes low, the other power switch is delayed for a period of time before a high-level drive signal is applied. The dead time introduces additional low-order harmonics, reducing the quality of the circuit's output power.

[0003] Currently, dead-time-free topologies have emerged in two-level topologies, requiring only the generation of two-level output inductor circuits and corresponding freewheeling paths. However, for three-level topologies, achieving dead-time-free operation requires simultaneously generating two-level inductor circuits and corresponding freewheeling paths without increasing the number of power switching devices, posing a greater challenge to topology design methods and control strategies.

[0004] The existing three-level topology has inherent structural flaws. The DC-side power supply and power switches directly form a loop. If the power switches in the loop turn on simultaneously, the DC-side power supply will short-circuit, triggering a large instantaneous current. Although the short circuit can be avoided by controlling the power switches in the loop to prevent them from turning on simultaneously, since power switches are not ideal devices, at the instant when one power switch turns on and the other turns off, due to the unreliable turn-off of the power switches, both power switches may turn on at that instant. To avoid this phenomenon, the turn-on time of the power switches needs to be delayed. This period is called the dead zone. The introduction of the dead zone will introduce additional dead zone harmonics into the output voltage. Dead zone harmonics are additional low-order harmonics, which will reduce the power quality of the circuit output. Summary of the Invention

[0005] To address the inherent structural defects of existing three-level topologies, the present invention aims to provide a control method for a dead-zone-free three-level topology that enables three-level output without directly forming a loop between the DC power supply and the power switch, eliminates the need for a dead zone in the drive signal, avoids the introduction of additional low-order harmonics by the dead zone which would reduce the quality of the circuit output power, and further reduces the number of diodes.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a control method for a dead-zone-free three-level topology, specifically referring to: IGBT transistors S1 and S3 being complementaryly turned on, IGBT transistors S2 and S4 being complementaryly turned on, and diodes D3 and D4 being defined as vertical diodes, and diodes D1 and D2 being defined as horizontal diodes.

[0007] State 1: The output current polarity is positive, IGBT transistors S1 and S2 are turned on, and the potential at point A, which is the emitter potential of IGBT transistor S2, is equal to the positive potential on the DC side. The bridge arm output state is 1.

[0008] State 2: The output current polarity is positive, IGBT transistors S2 and S3 are turned on, the potential at point A is equal to the potential at point O, the bridge arm output state is 0, the lateral diode D1 acts as a single-phase current path, and the lateral diode D1 is not a freewheeling diode.

[0009] State 3: The output current polarity is positive, IGBT transistors S3 and S4 are turned on, and the potential at point A is equal to the negative potential on the DC side. The bridge arm output state is -1. This state is caused by the current in inductor L1 not changing abruptly when IGBT transistors S1 and S2 are turned off. It needs to be freewheeled through the longitudinal diode D4. Therefore, the longitudinal diode D4 is a freewheeling diode.

[0010] State 4: The output current polarity is negative, IGBT transistors S1 and S2 are turned on. At this time, the potential at point B, which is the collector potential of IGBT transistor S3, is equal to the positive potential of the DC side. The bridge arm output state is 1. This state is caused by the fact that when IGBT transistors S3 and S4 are turned off, the current of inductor L2 cannot change abruptly and needs to be freewheeled through the longitudinal diode D3. Therefore, the longitudinal diode D3 is a freewheeling diode.

[0011] State 5: The output current polarity is negative, IGBT transistors S2 and S3 are turned on, the potential at point B is equal to the potential at point O, the bridge arm output state is 0, the lateral diode D2 acts as a single-phase current path, and the lateral diode D2 is not a freewheeling diode.

[0012] State 6: The output current polarity is negative, IGBT transistors S3 and S4 are turned on, and the potential at point B is equal to the negative potential on the DC side. The bridge arm output state is -1.

[0013] The dead-zone-free three-level topology includes capacitor C1, capacitor C2, diodes D1, D2, D3, and D4, IGBT transistors S1, S2, S3, and S4, and inductors L1 and L2. One end of capacitor C1 is connected to the positive terminal of the DC source and the collector of IGBT transistor S1. The other end of capacitor C1 is connected to one end of capacitor C2, the anode of diode D1, and the cathode of diode D2. The other end of capacitor C2 is connected to the negative terminal of the DC source. The anode of diode D2 is connected to the emitter of IGBT transistor S3 and the collector of IGBT transistor S4. The IGBT transistor... The collector of transistor S1 is connected to the cathode of diode D3. The anode of diode D3 is connected to one end of inductor L2 and the collector of IGBT transistor S3. The emitter of IGBT transistor S1 is connected to the cathode of diode D1 and the collector of IGBT transistor S2. The emitter of IGBT transistor S2 is connected to the cathode of diode D4 and one end of inductor L1. The anode of diode D4 is connected to the negative terminal of a DC source and the emitter of IGBT transistor S4. One end of inductor L1 and one end of inductor L2 are connected in parallel to an AC source. The gates of IGBT transistors S1, S2, S3, and S4 are all connected to control signals.

[0014] States 1 and 4 achieve a positive level output for the topology, and the switching vector is represented as follows:

[0015] (1)

[0016] States 2 and 5 achieve a positive level output for the topology, and the switching vector is represented as follows:

[0017] (2)

[0018] States 3 and 6 achieve a positive level output for the topology, and the switching vector is represented as follows:

[0019] (3)

[0020] In equations (1), (2), and (3), These represent the control signals received at the gates of IGBT transistors S1, S2, S3, and S4, respectively. A value of 0 indicates that the circuit is off, and a value of 1 indicates that the circuit is on.

[0021] When the bridge arm output voltage is positive and the output current is negative, state 4 switching mode will occur. When the output voltage is negative and the output current is positive, state 3 switching mode will occur. Therefore, in these two cases, the output voltage should be forced to 0, that is, the switching vector of equation (2) should be used. This will lead to the introduction of the second harmonic, which needs to be compensated. According to the equivalent area method, the amplitude of the second harmonic is for:

[0022] (4)

[0023] in, The phase difference between the output voltage and current. The amplitude of the reference voltage. Represented as:

[0024] (5)

[0025] in, The output current amplitude, The load voltage amplitude, For inductance values, L = L1 = L2;

[0026] The instantaneous value of the second harmonic for:

[0027] (6)

[0028] in, The fundamental angular frequency is the instantaneous value of the second harmonic. Injected into the voltage reference as a compensation, thus eliminating the corresponding second harmonic.

[0029] As can be seen from the above technical solution, the beneficial effects of the present invention are as follows: First, there is no risk of shoot-through in the bridge arm, and there is no need to add a dead time to the drive signal, thus avoiding the introduction of additional low-order harmonics by the dead time, which would reduce the power quality of the circuit output; Second, compared with the traditional type I three-level topology, there is no increase in the number of external diodes, and since the freewheeling current is very small, it is easy to select high-voltage, low-current diodes, further reducing the number of diodes; Third, by eliminating the current ripple at the current zero-crossing point, the inductor freewheeling working mode is eliminated, further eliminating the need for vertical diodes. Attached Figure Description

[0030] Figure 1 This is a topological structure diagram of the present invention;

[0031] Figure 2 It is a traditional topology diagram;

[0032] Figure 3 , 4 These are diagrams of the single-phase and three-phase inverter topologies constructed according to the present invention.

[0033] Figure 5 , 6 Figures 7, 8, 9, and 10 are all schematic diagrams illustrating the working principle of the bridge arm of the topology of this invention. Detailed Implementation

[0034] like Figure 1 As shown, a dead-zone-free three-level topology includes capacitors C1 and C2, diodes D1, D2, D3, and D4, IGBT transistors S1, S2, S3, and S4, and inductors L1 and L2. One end of capacitor C1 is connected to the positive terminal of a DC source and the collector of IGBT transistor S1. The other end of capacitor C1 is connected to one end of capacitor C2, the anode of diode D1, and the cathode of diode D2. The other end of capacitor C2 is connected to the negative terminal of the DC source. The anode of diode D2 is connected to the emitter of IGBT transistor S3 and the collector of IGBT transistor S4. The collector of transistor S1 is connected to the cathode of diode D3. The anode of diode D3 is connected to one end of inductor L2 and the collector of IGBT transistor S3. The emitter of IGBT transistor S1 is connected to the cathode of diode D1 and the collector of IGBT transistor S2. The emitter of IGBT transistor S2 is connected to the cathode of diode D4 and one end of inductor L1. The anode of diode D4 is connected to the negative terminal of a DC source and the emitter of IGBT transistor S4. One end of inductor L1 and one end of inductor L2 are connected in parallel to an AC source. The gates of IGBT transistors S1, S2, S3, and S4 are all connected to control signals.

[0035] This control method specifically refers to: IGBT transistors S1 and S3 being complementaryly turned on, IGBT transistors S2 and S4 being complementaryly turned on, and diodes D3 and D4 being defined as vertical diodes, and diodes D1 and D2 being defined as horizontal diodes.

[0036] State 1: The output current, i.e., the current flowing to the AC side, is positive. IGBT transistors S1 and S2 are turned on. At this time, the potential at point A, i.e., the emitter potential of IGBT transistor S2, is equal to the positive potential on the DC side. The bridge arm output state is 1. Figure 5 As shown;

[0037] State 2: The output current polarity is positive, IGBT transistors S2 and S3 are turned on, the potential at point A is equal to the potential at point O, the bridge arm output state is 0, and the lateral diode D1 acts as a single-phase current path. The lateral diode D1 is not a freewheeling diode. Figure 6 As shown;

[0038] State 3: The output current polarity is positive, IGBT transistors S3 and S4 are turned on. At this time, the potential at point A is equal to the negative potential on the DC side, and the bridge arm output state is -1. This state occurs when IGBT transistors S1 and S2 are turned off. The current in inductor L1 cannot change abruptly and needs to freewheel through the longitudinal diode D4. Therefore, the longitudinal diode D4 is a freewheeling diode. Figure 7 As shown;

[0039] State 4: The output current polarity is negative, IGBT transistors S1 and S2 are turned on. At this time, the potential at point B, i.e., the collector potential of IGBT transistor S3, is equal to the positive potential of the DC side. The bridge arm output state is 1. This state occurs when IGBT transistors S3 and S4 are turned off. The current in inductor L2 cannot change abruptly and needs to freewheel through the longitudinal diode D3. Therefore, the longitudinal diode D3 is a freewheeling diode. Figure 8 As shown;

[0040] State 5: Output current polarity is negative, IGBT transistors S2 and S3 are turned on. At this time, the potential at point B is equal to the potential at point O, the bridge arm output state is 0, and the lateral diode D2 acts as a single-phase current path. The lateral diode D2 is not a freewheeling diode. Figure 9 As shown;

[0041] State 6: The output current polarity is negative, IGBT transistors S3 and S4 are turned on, the potential at point B is equal to the negative DC side potential, and the bridge arm output state is -1. Figure 10 As shown;

[0042] As can be seen, the topology of this invention can also achieve 3-level output, and the presence of inductors L1 and L2 avoids the shoot-through of the bridge arm, eliminating the need to add a dead time to the drive signal. Due to the presence of the freewheeling diode, the current of inductors L1 and L2 will not change abruptly. The topology has the characteristics of safe and reliable operation.

[0043] States 1 and 4 achieve a positive level output for the topology, and the switching vector is represented as follows:

[0044] (1)

[0045] States 2 and 5 achieve a positive level output for the topology, and the switching vector is represented as follows:

[0046] (2)

[0047] States 3 and 6 achieve a positive level output for the topology, and the switching vector is represented as follows:

[0048] (3)

[0049] In equations (1), (2), and (3), These represent the control signals received at the gates of IGBT transistors S1, S2, S3, and S4, respectively. A value of 0 indicates that the circuit is off, and a value of 1 indicates that the circuit is on.

[0050] For states 3 and 4, since the longitudinal diodes D3 and D4 only serve as freewheeling diodes and the current flowing through them is very small, power devices with lower current tolerance can be selected to further reduce costs.

[0051] In fact, the topology of this invention is only through Figure 5 , Figure 6 , Figure 9 , Figure 10 That is, it can achieve three-level output, if it can be eliminated through control strategy. Figure 7 , Figure 8 By using the operating mode, the longitudinal diodes D3 and D4 can be further eliminated.

[0052] Modal analysis shows that when the bridge arm output voltage is positive and the output current is negative, state 4 switching mode will occur; when the output voltage is negative and the output current is positive, state 3 switching mode will occur. Therefore, in these two cases, the output voltage should be forced to 0, i.e., the switching vector of equation (2) should be used. This will lead to the introduction of the second harmonic, which needs to be compensated. According to the equivalent area method, the amplitude of the second harmonic is... for:

[0053] (4)

[0054] in, The phase difference between the output voltage and current. The amplitude of the reference voltage. Represented as:

[0055] (5)

[0056] in, The output current amplitude, The load voltage amplitude, For inductance values, L = L1 = L2;

[0057] The instantaneous value of the second harmonic for:

[0058] (6)

[0059] in, The fundamental angular frequency is the instantaneous value of the second harmonic. Injected into the voltage reference as a compensation, thus eliminating the corresponding second harmonic.

[0060] By using the control method described above, diodes D3 and D4 can be omitted. In this case, inductors L1 and L2 can be designed as a center-tapped inductor, further reducing the size.

[0061] like Figure 2 As shown, for a traditional three-level I-type topology, the only way to achieve both no dead time and avoid large current is to connect an inductor in series with the branches of IGBT transistors S1 / S2 and S3 / S4, utilizing the characteristic that the inductor current cannot change abruptly to handle instantaneous large currents. However, while directly connecting the inductor solves the shoot-through problem, it introduces a new issue: at the moment of switching between IGBT transistors S1 / S2 and S3 / S4, the sudden change in inductor current generates instantaneous voltage spikes that can damage the power devices in the circuit. The solution is to add a freewheeling path for the inductor current. However, adding a freewheeling path, as in existing two-level dead-time-free topologies, solves the dead-time problem but still presents two problems: firstly, it adds an extra diode; secondly, at 0-level output, the circuit output lacks a filter inductor, leading to a deterioration in output power quality.

[0062] Based on the above analysis, the topology generation approach of this invention is as follows: by using the filter inductor L at the bridge arm output (e.g., Figure 2 As shown, the inductance is distributed into the bridge arms, becoming inductors L1 and L2 (as shown). Figure 1 As shown in the diagram, the characteristic that inductor current cannot change abruptly is utilized to avoid instantaneous short circuits on the DC side when the bridge arm is directly connected. The diode freewheeling current avoids abrupt changes in inductor current. Since inductors L1 and L2 can share a magnetic core, the volume of the split inductor will not increase. Furthermore, since all diodes in the circuit are external diodes, the number of diodes in the circuit will not increase. Because the freewheeling current is very small, it is easy to select high-voltage, low-current diodes, further reducing the number of diodes.

[0063] like Figure 3 , 4 The figures show the single-phase and three-phase inverter topologies constructed according to the present invention. The AC side can be connected to the power grid, an AC motor, or a local load.

[0064] In summary, the bridge arm in this invention has no shoot-through risk, eliminates the need for dead time in the drive signal, and avoids the introduction of additional low-order harmonics that would reduce the quality of the circuit output power. Compared with the traditional type-I three-level topology, it does not increase the number of external diodes, and because the freewheeling current is very small, it is easy to select high-voltage, low-current diodes, further reducing the number of diodes. By eliminating the current ripple at the current zero-crossing point, the inductor freewheeling mode is eliminated, further eliminating the need for vertical diodes.

Claims

1. A control method for a dead-zone-free three-level topology, characterized in that: Specifically, this method refers to: IGBT transistors S1 and S3 being complementary in conduction, IGBT transistors S2 and S4 being complementary in conduction, and diodes D3 and D4 being defined as vertical diodes, and diodes D1 and D2 being defined as horizontal diodes. State 1: The output current polarity is positive, IGBT transistors S1 and S2 are turned on, and the potential at point A, which is the emitter potential of IGBT transistor S2, is equal to the positive potential on the DC side. The bridge arm output state is 1. State 2: The output current polarity is positive, IGBT transistors S2 and S3 are turned on, the potential at point A is equal to the potential at point O, the bridge arm output state is 0, the lateral diode D1 acts as a single-phase current path, and the lateral diode D1 is not a freewheeling diode. State 3: The output current polarity is positive, IGBT transistors S3 and S4 are turned on, and the potential at point A is equal to the negative potential on the DC side. The bridge arm output state is -1. This state is caused by the current in inductor L1 not changing abruptly when IGBT transistors S1 and S2 are turned off. It needs to be freewheeled through the longitudinal diode D4. Therefore, the longitudinal diode D4 is a freewheeling diode. State 4: The output current polarity is negative, IGBT transistors S1 and S2 are turned on. At this time, the potential at point B, which is the collector potential of IGBT transistor S3, is equal to the positive potential of the DC side. The bridge arm output state is 1. This state is caused by the fact that when IGBT transistors S3 and S4 are turned off, the current of inductor L2 cannot change abruptly and needs to be freewheeled through the longitudinal diode D3. Therefore, the longitudinal diode D3 is a freewheeling diode. State 5: The output current polarity is negative, IGBT transistors S2 and S3 are turned on, the potential at point B is equal to the potential at point O, the bridge arm output state is 0, the lateral diode D2 acts as a single-phase current path, and the lateral diode D2 is not a freewheeling diode. State 6: The output current polarity is negative, IGBT transistors S3 and S4 are turned on, and the potential at point B is equal to the negative potential on the DC side. The bridge arm output state is -1. The dead-zone-free three-level topology includes capacitor C1, capacitor C2, diodes D1, D2, D3, and D4, IGBT transistors S1, S2, S3, and S4, and inductors L1 and L2. One end of capacitor C1 is connected to the positive terminal of the DC source and the collector of IGBT transistor S1. The other end of capacitor C1 is connected to one end of capacitor C2, the anode of diode D1, and the cathode of diode D2. The other end of capacitor C2 is connected to the negative terminal of the DC source. The anode of diode D2 is connected to the emitter of IGBT transistor S3 and the collector of IGBT transistor S4. The IGBT transistor... The collector of transistor S1 is connected to the cathode of diode D3. The anode of diode D3 is connected to one end of inductor L2 and the collector of IGBT transistor S3. The emitter of IGBT transistor S1 is connected to the cathode of diode D1 and the collector of IGBT transistor S2. The emitter of IGBT transistor S2 is connected to the cathode of diode D4 and one end of inductor L1. The anode of diode D4 is connected to the negative terminal of a DC source and the emitter of IGBT transistor S4. One end of inductor L1 and one end of inductor L2 are connected in parallel to an AC source. The gates of IGBT transistors S1, S2, S3, and S4 are all connected to control signals.

2. The control method according to claim 1, characterized in that: States 1 and 4 achieve a positive level output for the topology, and the switching vector is represented as follows: （1） States 2 and 5 achieve a positive level output for the topology, and the switching vector is represented as follows: （2） States 3 and 6 achieve a positive level output for the topology, and the switching vector is represented as follows: （3） In equations (1), (2), and (3), These represent the control signals received at the gates of IGBT transistors S1, S2, S3, and S4, respectively. A value of 0 represents off, and a value of 1 represents on.

3. The control method according to claim 1, characterized in that: When the bridge arm output voltage is positive and the output current is negative, state 4 switching mode will occur. When the output voltage is negative and the output current is positive, state 3 switching mode will occur. Therefore, in these two cases, the output voltage should be forced to 0, that is, the switching vector of equation (2) should be used. This will lead to the introduction of the second harmonic, which needs to be compensated. According to the equivalent area method, the amplitude of the second harmonic is for: （4） in, The phase difference between the output voltage and current. The amplitude of the reference voltage. Represented as: （5） in, The output current amplitude, The load voltage amplitude, For inductance values, L = L1 = L2; The instantaneous value of the second harmonic for: （6） in, The fundamental angular frequency is the instantaneous value of the second harmonic. Injected into the voltage reference as a compensation, thus eliminating the corresponding second harmonic.

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