Temperature detection control circuit and storage device

Abstract

The embodiment of the present disclosure provides a temperature detection control circuit and a storage device. The temperature detection control circuit comprises: a first signal module configured to generate an enable signal in response to a power-on signal, the enable signal being a pulse signal; a mode control module configured to receive a test signal to segmentally transmit the enable signal, output the enable signal as a first enable signal during an invalid period of the test signal, and output the enable signal as a second enable signal during a valid period of the test signal; wherein the test signal is valid in a test mode and invalid in a working mode; and a second signal module configured to receive the first enable signal, the second enable signal and a temperature measurement end signal, generate a temperature measurement enable signal based on the first enable signal and the temperature measurement end signal, and generate the temperature measurement enable signal based on the second enable signal and the temperature measurement end signal, the temperature measurement enable signal being used to control a temperature detection module to perform temperature detection.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a temperature detection and control circuit and a storage device. Background Technology

[0002] Storage devices used for storing data can be divided into volatile memory devices and non-volatile memory devices. Volatile memory devices, such as Dynamic Random Access Memory (DRAM), store data by charging or discharging capacitors in memory cells, and lose the stored data when power is off. Non-volatile memory devices, such as Flash Memory, retain the stored data even when power is off. Volatile memory devices are widely used as main memory in various devices, while non-volatile memory devices are widely used to store program code and / or data in various electronic devices such as computers, mobile devices, etc.

[0003] The temperature of a storage device affects its storage performance; therefore, temperature monitoring of the storage device is essential. Furthermore, storage devices have operating modes and test modes, both of which require temperature monitoring. Summary of the Invention

[0004] This disclosure provides a temperature detection and control circuit and a storage device, which at least facilitates the generation of a temperature measurement enable signal in both working mode and test mode.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a temperature detection control circuit, including: a first signal module configured to generate an enable signal in response to a power-on signal, the enable signal being a pulse signal; a mode control module configured to receive a test signal and transmit the enable signal in segments, output the enable signal and use the enable signal as a first enable signal during a period when the test signal is invalid, and output the enable signal and use the enable signal as a second enable signal during a period when the test signal is valid; wherein, the test signal is valid in a test mode and invalid in a working mode; and a second signal module configured to receive the first enable signal, the second enable signal, and a temperature measurement end signal, generate a temperature measurement enable signal based on the first enable signal and the temperature measurement end signal, and generate the temperature measurement enable signal based on the second enable signal and the temperature measurement end signal, the temperature measurement enable signal being used to control the temperature detection module to perform temperature detection.

[0006] In some embodiments, the first signal module includes: an oscillation circuit configured to generate an oscillation signal in response to the power-on signal; and an enable signal generation circuit configured to receive the oscillation signal and generate the enable signal based on the number of oscillations of the oscillation signal.

[0007] In some embodiments, the enable signal generation circuit includes: a counter configured to receive the oscillation signal and count the number of oscillations of the oscillation signal to obtain a count value, and to re-count the number of oscillations of the oscillation signal after the count value is zero; and a pulse generation unit configured to receive the count value, generate the enable signal when the count value reaches a preset value, and control the count value of the counter to be zero.

[0008] In some embodiments, the pulse generation unit includes: a decoding unit configured to receive the count value and generate a decoding signal when the count value reaches the preset value, the decoding signal being a pulse signal; and an output unit configured to generate an enable signal and a first reset signal in response to the decoding signal, the pulse width of the enable signal being greater than the pulse width of the decoding signal, and the first reset signal being used to control the count value of the counter to return to zero.

[0009] In some embodiments, the preset value includes a first preset value and a second preset value, and the first preset value is less than the second preset value; the decoding unit includes: a first decoding unit configured to receive the count value and generate a first decoding signal when the count value reaches the first preset value, the first decoding signal being used to control the generation of a first pulse of the enable signal; a second decoding unit configured to receive the count value and generate a second decoding signal when the count value reaches the second preset value, the second decoding signal being used to control the generation of the remaining pulses of the enable signal; the output unit is further configured to generate a shutdown signal in response to the first pulse of the enable signal, the shutdown signal controlling the first decoding unit to stop working.

[0010] In some embodiments, the mode control module includes: a first control unit having a first node, configured to receive the test signal and the enable signal, and output the enable signal through the first node during a period when the test signal is invalid; during a period when the test signal is valid, to shut off the transmission path of the enable signal provided by the first signal module to the first node, or to enable the first node to have a first preset level during a period when the test signal is valid; and a second control unit having a second node, configured to receive the test signal and the enable signal, and output the enable signal through the second node during a period when the test signal is valid; during a period when the test signal is invalid, to shut off the transmission path of the enable signal provided by the first signal module to the second node, or to enable the second node to have a second preset level during a period when the test signal is invalid.

[0011] In some embodiments, the first control unit includes: a first inverter, the input of which receives the test signal; a first NAND gate, having a first input and a second input, the first input receiving the enable signal, and the second input connected to the output of the first inverter; and a second inverter, the input of which is connected to the output of the first NAND gate, the output of which serves as the first node; the second control unit includes: a second NAND gate, having a third input and a fourth input, the third input receiving the enable signal, and the fourth input receiving the test signal; and a third inverter, the input of which is connected to the output of the second NAND gate, the output of which serves as the second node.

[0012] In some embodiments, the second signal module includes: a logic circuit configured to receive the first enable signal and the second enable signal, and generate a trigger signal, wherein the trigger signal is a pulse signal; a reset circuit configured to receive the temperature measurement end signal to generate a second reset signal; wherein the temperature measurement end signal indicates that temperature detection has not ended, in which case the second reset signal is invalid; and the temperature measurement end signal indicates that temperature detection has ended, in which case the second reset signal is valid; and a trigger circuit configured to receive the trigger signal and the second reset signal, and generate the temperature measurement enable signal; wherein during the period when the second reset signal is invalid, the temperature measurement enable signal is used to control the temperature detection module to perform temperature detection, and during the period when the second reset signal is valid, the temperature measurement enable signal is used to control the temperature detection module to end temperature detection.

[0013] In some embodiments, the logic circuit includes: a first logic circuit having a third node, configured to receive the first enable signal and output a first trigger signal via the third node; wherein, during the valid period of the test signal, the first trigger signal has a third preset level, and during the invalid period of the test signal, the first trigger signal is a pulse signal; a second logic circuit having a fourth node, configured to receive the second enable signal and output a second trigger signal via the fourth node; wherein, during the valid period of the test signal, the second trigger signal is a pulse signal, and during the invalid period of the test signal, the second trigger signal has a fourth preset level; and an AND gate circuit, with two input terminals respectively connected to the third node and the fourth node, performing an AND operation on the first trigger signal and the second trigger signal to output the trigger signal.

[0014] In some embodiments, the first logic circuit includes: a third NAND gate having a fifth input and a sixth input, the fifth input receiving the first enable signal, the sixth input being connected to the fifth input via an odd number of fourth inverters, and the output of the third NAND gate being the third node; the second logic circuit includes: a fourth NAND gate having a seventh input and an eighth input, the seventh input receiving the second enable signal, the eighth input being connected to the seventh input via an odd number of fifth inverters, and the output of the fourth NAND gate being the fourth node.

[0015] In some embodiments, the reset circuit includes: a fifth NAND gate having a ninth input and a tenth input, the ninth input receiving the temperature measurement end signal, the tenth input being connected to the ninth input via an odd number of sixth inverters, and the output of the fifth NAND gate outputting the second reset signal.

[0016] In some embodiments, the trigger circuit includes an RS flip-flop, the trigger terminal of the RS flip-flop receives the trigger signal, the reset terminal of the RS flip-flop receives the second reset signal, and the output terminal of the RS flip-flop outputs the temperature measurement enable signal.

[0017] In some embodiments, the second signal module further includes: a sixth NAND gate having an eleventh input and a twelfth input, the eleventh input being connected to the output of the RS flip-flop, and the twelfth input receiving the power-on signal; and a seventh inverter, the input of which is connected to the output of the sixth NAND gate, and the output of which outputs the temperature measurement enable signal.

[0018] According to some embodiments of this disclosure, another aspect of this disclosure provides a storage device, including: a storage array; a temperature detection and control circuit as described above; and a temperature detection module configured to detect the temperature of the storage array in response to the temperature measurement enable signal and output a temperature detection value.

[0019] In some embodiments, a register is used to store the temperature detection value; and a test circuit is used to output the temperature detection value to a test pad.

[0020] The technical solution provided in this disclosure has at least the following advantages:

[0021] In the temperature detection control circuit provided in this embodiment, the first signal module generates an enable signal after receiving a power-on signal. The mode control module receives the enable signal and a test signal. During the period when the test signal is invalid, indicating that it is in the working mode, the mode control module receives the enable signal and uses the enable signal corresponding to the invalid period of the test signal as the first enable signal. During the period when the test signal is valid, indicating that it is in the test mode, the mode control module receives the enable signal and uses the enable signal corresponding to the valid period of the test signal as the second enable signal. In this way, the mode control module can generate a first enable signal corresponding to the working mode and a second enable signal corresponding to the test mode. In the working mode, the second signal generation module receives the first enable signal and generates a temperature measurement enable signal. In the test mode, the second signal generation module receives the second enable signal and generates a temperature measurement enable signal, thereby achieving the purpose of generating a temperature measurement enable signal for controlling the temperature detection module to perform temperature detection in both the test mode and the working mode. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A block diagram of a temperature detection and control circuit provided in an embodiment of this disclosure;

[0024] Figure 2 This is a block diagram of a first signal module in a temperature detection and control circuit provided in an embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram of a circuit structure for the first signal module in a temperature detection and control circuit provided in an embodiment of this disclosure;

[0026] Figure 4 This is a signal timing diagram of each signal in the first signal module provided in an embodiment of the present disclosure;

[0027] Figure 5 This is a schematic diagram of a circuit structure of a mode control module and a second signal module 1 in a temperature detection and control circuit provided in an embodiment of the present disclosure.

[0028] Figure 6This is a signal timing diagram of each signal in the temperature detection and control circuit provided in the embodiments of this disclosure;

[0029] Figure 7 A schematic diagram of the specific circuit structure of the first logic circuit in the temperature detection and control circuit provided in the embodiments of this disclosure, and a timing diagram of each signal;

[0030] Figure 8 A schematic diagram of the specific circuit structure of the second logic circuit in the temperature detection and control circuit provided in the embodiments of this disclosure, and a timing diagram of each signal;

[0031] Figure 9 A schematic diagram of a specific circuit structure of the reset circuit in the temperature detection and control circuit provided in this embodiment of the present disclosure, as well as a timing diagram of each signal;

[0032] Figure 10 A block diagram of a storage device provided in an embodiment of this disclosure;

[0033] Figure 11 Another block diagram of a storage device provided in an embodiment of this disclosure. Detailed Implementation

[0034] Figure 1 This is a block diagram of a temperature detection and control circuit provided in an embodiment of the present disclosure.

[0035] refer to Figure 1 The temperature detection and control circuit provided in this embodiment includes: a first signal module 101, configured to generate an enable signal TSEn0 in response to a power-on signal Poweron, wherein the enable signal is a pulse signal; and a mode control module 102, configured to receive a test signal TmTSProbe and transmit the enable signal TSEn0 in segments, outputting the enable signal TSEn0 and using it as the first enable signal TSEn during the invalid period of the test signal TmTSProbe, and outputting the enable signal TSEn0 and using it as the second enable signal TmT during the valid period of the test signal TmTSProbe. SEn; wherein, the test signal TmTSProbe is valid in test mode and invalid in working mode; the second signal module 103 is configured to receive the first enable signal TSEn, the second enable signal TmTSEn, and the temperature measurement end signal TSDone, generate a temperature measurement enable signal TSCoreEn based on the first enable signal TSEn and the temperature measurement end signal TSDone, and generate a temperature measurement enable signal TSCoreEn based on the second enable signal TmTSEn and the temperature measurement end signal TSDone. The temperature measurement enable signal TSCoreEn is used to control the temperature detection module to perform temperature detection.

[0036] In the above technical solution, after receiving the power-on signal Poweron, the first signal module 101 generates an enable signal TSEn0; the mode control module 102 receives the enable signal TSEn0 and the test signal TmTSProbe. During the invalid period of the test signal TmTSProbe, indicating the operating mode, the mode control module 102 receives the enable signal TSEn0 and uses the enable signal TSEn0 corresponding to the invalid period of the test signal TmTSProbe as the first enable signal TSEn. During the valid period of the test signal TmTSProbe, indicating the test mode, the mode control module 102 receives the enable signal TSEn0 and uses the enable signal TSEn0 corresponding to the valid period of the test signal TmTSProbe as the second enable signal Tm. Thus, the mode control module 102 can generate a first enable signal TSEn corresponding to the working mode and a second enable signal corresponding to the test mode. In the working mode, the second signal generation module 103 receives the first enable signal TSEn and generates a temperature measurement enable signal TSCoreEn. In the test mode, the second signal generation module 103 receives the second enable signal TmTSEn and generates a temperature measurement enable signal TSCoreEn. This enables the generation of test enable signals using different enable signals in different modes, avoiding the influence of signal noise on the corresponding enable signal under one mode's operating conditions on the operation of another mode. In other words, it avoids the noise that occurs during the operation of either the first or second enable signal affecting the effective operation of the other.

[0037] In addition, the first enable signal TSEn corresponding to the working mode and the second enable signal TmTSEn corresponding to the test mode both come from the enable signal TSEn0 generated by the first signal module 101. That is to say, the first enable signal and the second enable signal that are effective at different times can be generated by using the enable signal TSEn0 generated by the same first signal module 101, which helps to reduce circuit complexity and save power consumption of the temperature detection and control circuit.

[0038] The temperature detection and control circuit provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0039] In some embodiments, the temperature detection control circuit can be applied to the temperature detection of the storage device. When the first signal module 101 receives the power-on signal Poweron, it indicates that the temperature detection control circuit needs to enable the temperature detection control function and needs to generate a temperature measurement enable signal TSCoreEn for controlling temperature detection.

[0040] Figure 2 This is a block diagram of a first signal module in a temperature detection and control circuit provided in an embodiment of this disclosure. Figure 3This is a schematic diagram of a circuit structure for the first signal module in the temperature detection and control circuit provided in an embodiment of this disclosure. Figure 4 The signal timing diagram of each signal in the first signal module 101 provided in the embodiments of this disclosure.

[0041] refer to Figure 2 In some embodiments, the first signal module 101 may include: an oscillation circuit 111 configured to generate an oscillation signal OSC in response to a power-on signal Poweron; and an enable signal generation circuit 121 configured to receive the oscillation signal OSC and generate an enable signal TSEn0 based on the number of oscillations of the oscillation signal OSC.

[0042] When the power-on signal Poweron is high, i.e., at logic "1", the oscillation circuit 111 starts oscillating. Understandably, in some embodiments, this power-on signal Poweron can be transmitted to both the first signal module 101 and the storage array of the storage device, indicating that the storage array is powered on to enter a working state.

[0043] The oscillation circuit 111 generates a periodically changing voltage signal, i.e., the oscillation signal OSC. The oscillation circuit 111 can be a sinusoidal oscillator or a non-sinusoidal oscillator. A sinusoidal oscillator produces a waveform very close to a sine or cosine wave, and its oscillation frequency is relatively stable. A non-sinusoidal oscillator produces a non-sinusoidal pulse waveform, such as a square wave, rectangular wave, or sawtooth wave. The frequency stability of a non-sinusoidal oscillator is not high. Accordingly, the oscillation signal OSC can be a sine or cosine wave, or it can be a square wave, rectangular wave, or sawtooth wave. Depending on the specific circuit structure of the oscillation circuit 111, the oscillation signal OSC can have different waveforms.

[0044] refer to Figure 3 In some embodiments, the oscillation circuit 111 can be an RC delay-based ring oscillator, including: a NAND gate AN, one input of which receives a power-on signal; at least two cascaded resistors R and at least two inverters inv, the first resistor R connected to the output of the NAND gate AN, the last resistor connected to the other end of the NAND gate AN via an inverter inv, and two resistors R in adjacent stages connected via an inverter inv; at least two capacitors C, one end of which is connected to the connection node of the resistors R and the input of the inverters inv, and the other end is grounded. It should be noted that... Figure 3The diagram only shows 2 resistors R, 2 inverters inv, and 2 capacitors C. In reality, the oscillation circuit 111 can include N resistors R, N inverters inv, and N capacitors C, where N can be any even number greater than or equal to 2, such as 4, 6, 8, etc.

[0045] In other examples, the oscillator circuit 111 can also be an LC oscillator or a quartz crystal oscillator, etc.

[0046] The oscillation signal OSC is transmitted to the enable signal generation circuit 121, and the enable signal generation circuit 121 acquires the oscillation period of the oscillation signal OSC. When the oscillation period reaches a preset period, a pulse is generated. After that, the oscillation period acquired by the enable signal generation circuit 121 is reset to zero and the oscillation period is acquired again. When the reacquired oscillation period reaches the preset period, the next pulse is generated. This process is repeated to generate multiple pulses to form the enable signal TSEn0.

[0047] Continue to refer to Figure 3 In some embodiments, the enable signal generation circuit 121 may include a counter 11 configured to receive an oscillation signal OSC and count the number of oscillations of the oscillation signal OSC to obtain a count value B. <n:0>And the count value B <n:0>After resetting to zero, the oscillation count of the oscillation signal OSC is restarted; pulse generation unit 12 is configured to receive the count value B. <n:0>and in count value B <n:0>When the preset value is reached, an enable signal TSEn0 is generated, and the count value B of counter 11 is controlled. <n:0>Reset to zero.

[0048] Counter 11 obtains the number of oscillation cycles of oscillation circuit 111 by counting the number of oscillations. This can be understood as the count value B. <n:0>This represents the number of periods that characterize the oscillation period. Count value B <n:0>As an external trigger signal generated by the trigger pulse generation unit 12, the enable signal TSEn0 is generated at the count value B. <n:0>When the preset value is reached, the pulse generation unit 12 generates a pulse of the enable signal TSEn0, and the count value B of the counter 11 is... <n:0>After resetting to zero, the oscillation signal OSC is counted again, and a new count value B is generated. <n:0>; in the new count value B <n:0>When a preset value is reached, the pulse generation unit 12 generates the next pulse of the enable signal TSEn0. This process is repeated continuously, with the pulse generation unit 12 generating the required enable signal TSEn0. Specifically, the pulse generation unit 12 can also be configured such that if it generates a pulse of the enable signal TSEn0, it also generates a first reset signal CntRst, and the counter 11 adjusts the count value B in response to the first reset signal CntRst. <n:0>Reset to zero.

[0049] It is understandable that the count value B <n:0>The number of periods characterizes the oscillation period, and the duration of a single oscillation period of the oscillation circuit 111 can be known, with the corresponding count value B. <n:0>It can also represent the oscillation duration, and the preset value also represents the preset duration, the count value B. <n:0>Reaching the preset value indicates that the oscillation duration meets the preset duration, and the pulse generation unit 12 generates a pulse of the enable signal TSEn0.

[0050] Counter 11 can be a flip-flop-based counting circuit. In a specific example, counter 11 can be a 16-bit counter with a corresponding count value B. <n:0>In this case, n is 15. It is understandable that the number of bits in counter 11 can be determined according to actual needs. Counter 11 has a maximum count value, and the maximum count value represents the maximum oscillation duration, as long as the maximum oscillation duration represented by the maximum count value of counter 11 is less than or equal to the preset duration represented by a preset value. For example, counter 11 can be a 4-bit counter, an 8-bit counter, or a 32-bit counter, etc.

[0051] In addition, the counter 11 has a reset terminal, which is also activated by receiving the power-on signal.

[0052] Continue to refer to Figure 3 In some embodiments, the pulse generation unit 12 may include a decoding unit 1201 configured to receive a count value B. <n:0>and in count value B <n:0>When a preset value is reached, a decoding signal is generated. The decoding signal is a pulse signal. The output unit 1202 is configured to generate an enable signal TSEn0 and a first reset signal CntRst in response to the decoding signal. The pulse width of the enable signal TSEn0 is greater than the pulse width of the decoding signal. The first reset signal CntRst is used to control the count value B of the counter 11. <n:0>Reset to zero.

[0053] Specifically, the count value B <n:0>Upon reaching a preset value, the decoding unit 1201 generates a pulse of the decoding signal. In a specific example, the pulse of the decoding signal generated by the decoding unit 1201 can be a high-level pulse, and the decoding signal has a rising edge and a falling edge. The output unit 1202 can be triggered by the rising edge of the decoding signal to generate a pulse of the enable signal TSEn0. In a specific example, the pulse of the enable signal TSEn0 generated by the output unit 1202 can be a high-level pulse. It is understood that the output unit 1202 can also be triggered by the falling edge of the decoding signal to generate a pulse of the enable signal TSEn0. After receiving the first reset signal CntRst, the counter 11 increments the count value B. <n:0>The count is reset to zero so that the counting can be restarted, thereby enabling the decoding unit 1201 to generate the next pulse of the decoding signal, and the output unit 1202 to output the next pulse of the enable signal TSEn0.

[0054] Reference Figure 3 and Figure 4 In some embodiments, the time interval between receiving the power-on signal Poweron and generating the first pulse of the enable signal TSEn0 is a first interval t1, and the time interval between the remaining pulses of the enable signal TSEn0 is a second interval t2. The first interval t1 may be less than the second interval t2. Accordingly, the preset value may include a first preset value and a second preset value, and the first preset value is less than the second preset value. The decoding unit 1201 may include a first decoding unit 21 configured to receive the count value B. <n:0>and in count value B <n:0>When the first preset value is reached, a first decoding signal En1ms is generated. The first decoding signal En1ms is used to control the generation of the first pulse of the enable signal TSEn0. The second decoding unit 22 is configured to receive the count value B. <n:0>and in count value B <n:0>When the second preset value is reached, a second decoding signal En32ms is generated. The second decoding signal is used to control the generation of the remaining pulses of the enable signal TSEn0. The output unit 1202 is also configured to generate a shutdown signal En1msDis in response to the first pulse of the enable signal TSEn0. The shutdown signal En1msDis controls the first decoding unit 21 to stop working.

[0055] The output unit 1202 receives the first decoding signal En1ms and generates the first pulse of the enable signal TSEn0; the output unit 1202 receives the second decoding signal En32ms and generates the remaining pulses of the enable signal TSEn0.

[0056] In a specific example, the first interval t1 can be 1ms and the second interval t2 can be 32ms. It is understood that in other embodiments, the first interval t1 can be the same as the second interval t2, or the time interval between adjacent pulses, i.e., the second time interval, can have multiple different parameters. The decoding unit 1201 is configured with multiple sub-decoding units that generate different decoding signals, and each sub-decoding unit has a different preset value. That is, each sub-decoding unit generates a corresponding decoding signal when it counts to a different preset value. Correspondingly, the output unit controls at least one of the multiple sub-decoding units to start based on a preset program, for example, according to the number of received pulse signals. It is understandable that since the sub-decoding unit with the smaller preset value will block the sub-decoding unit with the larger preset value, controlling at least one sub-decoding unit to be turned on essentially means that the output unit needs to turn off other sub-decoding units with preset values ​​less than the target preset value. At least other sub-decoding units with preset values ​​greater than the target preset value can be turned on or off based on actual needs, such as current conditions. It should be further noted that the actual order in which the sub-decoding units that output the decoding signal are turned on can be independent of their corresponding preset values, even if the time interval of the signal TSEn0 is not necessarily from large to small.

[0057] Reference Figure 3 and Figure 4 Upon receiving the power-on signal Poweron (i.e., when Poweron is a high-level signal), the oscillation circuit 111 generates a periodic oscillation signal OSC. The counter 11 starts counting. Taking a 16-bit counter 11 as an example, the first preset value corresponding to the first count value B<15:0> represents an oscillation duration of 1ms, and the second preset value corresponding to the second and subsequent count values ​​B<15:0> represents an oscillation duration of 32ms. When the first count value B<15:0> reaches the first preset value, a pulse of the first decoding signal En1ms is generated. When the first count value B<15:0> reaches the second preset value, a pulse of the second decoding signal En32ms is generated. The output unit 1202 generates the first pulse of the enable signal TSEn0 in response to the first decoding signal En1ms, and generates the off signal En1msDis after generating the first pulse of TSEn0. It generates the remaining pulses of the enable signal TSEn0 in response to the second decoding signal En32ms, and generates the first reset signal CntRst during the pulse of the enable signal TSEn0. At this time, the count value B<15:0> of the counter 11 is reset to zero.

[0058] refer to Figure 1 The mode control module 102 has a first node net1 and a second node net2. In the working mode, the first node net1 outputs an enable signal TSEn0, and the enable signal TSEn0 output by the first node net1 serves as the first enable signal TSEn. In the test mode, the second node net2 outputs an enable signal, and the enable signal TSEn0 output by the second node net2 serves as the second enable signal TmTSEn.

[0059] Specifically, in operating mode, mode control module 102 can cut off the transmission path of enable signal TSEn0 to the second node net2, or mode control module 102 can have the function of pulling down the potential of the second node net2, so that the enable signal TSEn0 output by the second node net2 directly becomes a low-level signal, that is, an invalid enable signal TSEn0. In test mode, mode control module 102 can cut off the transmission path of enable signal TSEn0 to the first node net1, or mode control module 102 can have the function of pulling down the potential of the first node net1, so that the enable signal TSEn0 output by the first node net1 directly becomes a low-level signal, that is, an invalid enable signal TSEn0.

[0060] Figure 5 This is a schematic diagram of a circuit structure for the mode control module 102 and the second signal module 103 in the temperature detection and control circuit provided in this embodiment of the present disclosure. Figure 6 The signal timing diagram of each signal in the temperature detection and control circuit provided in the embodiments of this disclosure is shown.

[0061] Reference Figure 5 and Figure 6 In some embodiments, the mode control module 102 includes: a first control unit 112 having a first node net1, configured to receive a test signal TmTSProbe and an enable signal TSEn0, and output the enable signal TSEn0 through the first node net1 during the invalid period of the test signal TmTSProbe; and during the valid period of the test signal TmTSProbe, shut down the transmission path from the enable signal TSEn0 provided by the first signal module 101 to the first node net1, or, during the valid period of the test signal TmTSProbe, enable the first node net1 to have a first preset level.

[0062] During the period when the test signal TmTSProbe is invalid, the first control unit 112 uses the enable signal TSEn0 output by the first node net1 as the first enable signal TSEn. During the period when the test signal TmTSProbe is valid, the enable signal TSEn0 cannot be transmitted to the first node net1, and correspondingly, the first enable signal TSEn is invalid; or, the first control unit 112 can directly pull the first node net1 low to a first preset level, and correspondingly, the first enable signal TSEn is invalid, and the first preset level can be a low level.

[0063] Continue to refer to Figure 5 and Figure 6 The mode control unit 102 may further include: a second control unit 122 having a second node net2, configured to receive a test signal TmTSProbe and an enable signal TSEn0, and output the enable signal TSEn0 through the second node net2 during the valid period of the test signal TmTSProbe; and to shut off the transmission path of the enable signal TSEn0 provided by the first signal module 101 to the second node net2 during the invalid period of the test signal TmTSProbe, or to enable the second node net2 to have a second preset level during the invalid period of the test signal TmTSProbe.

[0064] During the validity period of the test signal TmTSProbe, the second control unit 122 uses the enable signal TSEn0 output by the second node net2 as the second enable signal TmTSEn. During the invalid period of the test signal TmTSProbe, the enable signal TSEn0 cannot be transmitted to the second node net2, and correspondingly, the second enable signal TmTSEn is invalid; or, the second control unit 122 can directly pull the second node net2 low to the second preset level, and correspondingly, the second enable signal TmTSEn is invalid, and the second preset level can be a low level.

[0065] refer to Figure 6 In some examples, the test signal TmTSProbe is high (logo "1"), indicating that the test signal TmTSProbe is valid; conversely, it is low (logo "0"), indicating that the test signal TmTSProbe is invalid. "High" and "low" refer to the levels relative to the valid and invalid periods.

[0066] refer to Figure 5 In some embodiments, the first control unit 112 may include: a first inverter inv1, the input of which receives a test signal TmTSProbe; a first NAND gate AN1, having a first input and a second input, the first input receiving an enable signal TSEn0, and the second input connected to the output of the first inverter inv1; and a second inverter inv2, the input of which is connected to the output of the first NAND gate AN1, and the output of the second inverter inv2 serving as a first node net1.

[0067] Reference Figure 5 and Figure 6 In operating mode, the test signal TmTSProbe is low (logic "0"), the output of the first inverter inv1 is high (logic "1"), the second input of the first NAND gate AN1 is 1, and the output of the first NAND gate AN1 is inverted compared to its first input, meaning the output of the first NAND gate AN1 outputs the inverted enable signal TSEn0. The input of the second inverter inv2 receives the inverted enable signal TSEn0, and correspondingly, the output of the second inverter inv2 outputs the same enable signal TSEn0, thus outputting a valid first enable signal TSEn0. In test mode, the test signal TmTSProbe is high (logic "1"), the output of the first inverter inv1 is low (logic "0"), and the output of the first NAND gate AN1 is high (logic "1"). The input of the second inverter inv2 receives logic "1" and correspondingly outputs logic "0", meaning the first node net1 outputs a low signal, and the first enable signal TSEn output by the first node net1 is invalid.

[0068] Continue to refer to Figure 5 In some embodiments, the second control unit 122 may include: a second NAND gate AN2 having a third input and a fourth input, the third input receiving an enable signal TSEn0 and the fourth input receiving a test signal TmTSProbe; and a third inverter inv3, the input of which is connected to the output of the second NAND gate AN2, and the output of which serves as the second node net2.

[0069] Reference Figure 5 and Figure 6 In operating mode, when the test signal TmTSProbe is low (logic "0"), and the fourth input of the second NAND gate AN2 is also low (logic "0"), the output of the second NAND gate AN2 is high (logic "1"). The input of the third inverter inv3 receives "1", and correspondingly, the output of the third inverter inv3 is low (logic "0"). This means the second node net2 outputs a low-level signal, and the second enable signal TmTSEn from the second node net2 is invalid. In test mode, when the test signal TmTSProbe is high (logic "1"), the output of the second NAND gate AN2 is inverted compared to its third input, meaning the output of the second NAND gate AN2 outputs the inverted enable signal TSEn0. The input of the third inverter inv3 receives the inverted enable signal TSEn0, and correspondingly, the output of the third inverter inv3 outputs the same enable signal TSEn0, thus outputting a valid second enable signal TmTSEn.

[0070] During the invalid period of the test signal TmTSProbe, the second signal module 103 receives a valid first enable signal TSEn and generates a temperature measurement enable signal TSCoreEn; during the valid period of the test signal TmTSProbe, the second signal module 103 receives a valid second enable signal TmTSEn and generates a temperature measurement enable signal TSCoreEn. In one example, the rising edge of the first enable signal TSEn can be used as the trigger edge for generating the temperature measurement enable signal TSCoreEn pulse; in another example, the falling edge of the first enable signal TSEn can be used as the trigger edge for generating the temperature measurement enable signal TSCoreEn pulse. In one example, the rising edge of the second enable signal TmTSEn can be used as the trigger edge for generating the temperature measurement enable signal TSCoreEn pulse; in another example, the falling edge of the second enable signal TmTSEn can be used as the trigger edge for generating the temperature measurement enable signal TSCoreEn pulse. In one example, the rising edge of the temperature measurement end signal TSDone can be used as the trigger edge for the end of the temperature measurement enable signal TSCoreEn pulse; in another example, the falling edge of the temperature measurement receive signal TSDone can be used as the trigger edge for the end of the temperature measurement enable signal TSCoreEn pulse.

[0071] In some embodiments, reference Figure 5 The second signal module 103 may include: a logic circuit 113 configured to receive a first enable signal TSEn and a second enable signal TmTSEn, and generate a trigger signal, wherein the trigger signal is a pulse signal; a reset circuit 123 configured to receive a temperature measurement end signal TSDone to generate a second reset signal; wherein the temperature measurement end signal TSDone indicates that temperature detection has not ended, in which case the second reset signal is invalid; the temperature measurement end signal TSDone indicates that temperature detection has ended, in which case the second reset signal is valid; and a trigger circuit 133 configured to receive the trigger signal and the second reset signal, and generate a temperature measurement enable signal TSCoreEn; wherein during the period when the second reset signal is invalid, the temperature measurement enable signal TSCoreEn is used to control the temperature detection module to perform temperature detection, and during the period when the second reset signal is valid, the temperature measurement enable signal TSCoreEn is used to control the temperature detection module to end temperature detection.

[0072] Reference Figure 5 and Figure 6 The rising edge of the first enable signal TSEn and the rising edge of the second enable signal TmTSEn serve as the trigger edge for generating the rising edge of the temperature measurement enable signal TSCoreEn; the rising edge of the temperature measurement end signal TSDone serves as the trigger edge for generating the falling edge of the temperature measurement enable signal TSCoreEn.

[0073] refer to Figure 6 In some embodiments, logic circuit 113 may include: a first logic circuit 31 having a third node na, configured to receive a first enable signal TSEn and output a first trigger signal via the third node na; wherein, during the validity period of the test signal TmTSProbe, the first trigger signal has a third preset level, and during the invalid period of the test signal TmTSProbe, the first trigger signal is a pulse signal; a second logic circuit 32 having a fourth node nb, configured to receive a second enable signal TmTSEn and output a second trigger signal via the fourth node nb; wherein, during the validity period of the test signal TmTSProbe, the second trigger signal is a pulse signal, and during the invalid period of the test signal TmTSProbe, the second trigger signal has a fourth preset level; and an AND gate circuit 33, with two input terminals connected to the third node na and the fourth node nb respectively, performing an AND operation on the first trigger signal and the second trigger signal to output a trigger signal, which is then output through a fifth node nc. The AND gate circuit 33 may consist of a NAND gate and an inverter connected to the output terminal of the NAND gate.

[0074] The third preset level can be high, and the corresponding first trigger signal is a low-level pulse. The fourth preset level can also be high, and the corresponding second trigger signal is a low-level pulse. During the valid test signal period, if the first trigger signal is high, the second trigger signal is output as the trigger signal via the fifth node nc, meaning the trigger signal output by the fifth node nc is a low-level pulse signal. During the invalid test signal period, if the second trigger signal is high, the first trigger signal is output as the trigger signal via the fifth node nc, meaning the trigger signal output by the fifth node nc is a low-level pulse signal.

[0075] Figure 7 A schematic diagram of the specific circuit structure of the first logic circuit in the temperature detection and control circuit provided in this embodiment of the disclosure, along with timing diagrams of each signal, are shown. (Reference) Figure 7 In some examples, the pulse signal output by the fifth node nc can be a low-level pulse. Correspondingly, the first logic circuit 31 may include: a third NAND gate AN3, having a fifth input in1 and a sixth input. The fifth input in1 receives a first enable signal TSEn. The sixth input is connected to the fifth input in1 via an odd number of fourth inverters inv4. The output out1 of the third NAND gate AN3 is the third node na. The first trigger signal output by the third node na is a low-level pulse signal.

[0076] Figure 8 A schematic diagram of the specific circuit structure of the second logic circuit in the temperature detection and control circuit provided in this embodiment of the disclosure, along with timing diagrams of each signal, are shown. (Reference) Figure 8 The second logic circuit 32 may include: a fourth NAND gate AN4, having a seventh input in2 and an eighth input. The seventh input in2 receives a second enable signal TmTSEn. The eighth input and the seventh input in2 are connected via an odd number of fifth inverters inv5. The output out2 of the fourth NAND gate AN4 is the fourth node nb. The second trigger signal output by the fourth node nb is a low-level pulse signal.

[0077] Figure 9 This document provides a schematic diagram of a specific circuit structure and timing diagram of each signal in the reset circuit of the temperature detection and control circuit provided in an embodiment of this disclosure. (Reference) Figure 9 The reset circuit 123 may include: a fifth NAND gate AN5, having a ninth input terminal in3 and a tenth input terminal, the ninth input terminal in3 receiving a temperature measurement end signal TSDone, the tenth input terminal and the ninth input terminal in3 being connected via an odd number of sixth inverters inv6, and the output terminal out3 of the fifth NAND gate AN5 outputting a second reset signal.

[0078] Continue to refer to Figure 5 The trigger circuit 133 may include an RS flip-flop, the trigger terminal S of the RS flip-flop receives a trigger signal, the reset terminal R of the RS flip-flop receives a second reset signal, and the output terminal of the RS flip-flop outputs a temperature measurement enable signal TSCoreEn.

[0079] Continue to refer to Figure 5 In some embodiments, the second signal module 103 may further include: a sixth NAND gate AN6, having an eleventh input and a twelfth input, the eleventh input being connected to the output of the trigger circuit 133, and the twelfth input receiving the power-on signal Poweron; and a seventh inverter inv7, the input of which is connected to the output of the sixth NAND gate AN6, and the output of which outputs a temperature measurement enable signal TSCoreEn.

[0080] The sixth NAND gate AN6 and the seventh inverter inv7 serve as driving circuits on the transmission path of the temperature measurement enable signal TSCoreEn, thereby improving the transmission capability of the temperature measurement enable signal TSCoreEn output from the output terminal of the trigger circuit 33 to the temperature detection module.

[0081] The following will combine Figures 5 to 9 The working principle of the temperature detection and control circuit is explained below:

[0082] In test mode, the test signal TmTSProbe is logic "1", the first enable signal TSEn is invalid, and the second enable signal TmTSEn is valid, i.e., the second enable signal TmTSEn is a high-level pulse signal. The level change edge of the second enable signal TmTSEn triggers the fourth node nb and the fifth node nc to output low-level pulse signals, and the output terminal of the trigger circuit 133 outputs a high-level pulse signal temperature measurement enable signal TSCoreEn. After the temperature detection ends, the temperature measurement end signal TSDone has a level change edge, and a second reset signal, which is a low-level pulse signal, is generated accordingly. After receiving the low-level pulse of the second reset signal, the trigger circuit 133 resets the output terminal of the trigger circuit 133 so that the temperature measurement enable signal TSCoreEn is reset to an invalid signal.

[0083] In operating mode, the test signal TmTSProbe is logic "0", the first enable signal TSEn is valid, that is, the first enable signal TSEn is a high-level pulse signal, and the second enable signal TmTSEn is an invalid signal; the level change edge of the first enable signal TSEn triggers the third node na and the fifth node nc to output a low-level pulse signal, and the output terminal of the trigger circuit 133 outputs a high-level pulse signal temperature measurement enable signal TSCoreEn; after the temperature detection ends, the temperature measurement end signal TSDone has a level change edge, and a second reset signal, which is a low-level pulse signal, is generated accordingly; after receiving the low-level pulse of the second reset signal, the trigger circuit 133 resets the output terminal of the trigger circuit 133 so that the temperature measurement enable signal TSCoreEn is reset to an invalid signal.

[0084] This disclosure also provides a storage device, which includes the temperature detection and control circuit provided in the foregoing embodiments. The storage device provided in this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the descriptions of the foregoing embodiments, and will not be repeated hereafter. Figure 10 This is a block diagram of a storage device provided in an embodiment of the present disclosure. Figure 11 Another block diagram of a storage device provided in an embodiment of this disclosure.

[0085] Reference Figure 6 , Figure 10 and Figure 11 The storage device includes: a storage array 300; a temperature detection and control circuit 301; and a temperature detection module 302, which is used to detect the temperature of the storage array in response to the temperature detection enable signal TSCoreEn and output the temperature detection value TSOut.

[0086] The storage device can be a DRAM storage device, such as a DDR5 DRAM storage device or a DDR4 DRAM storage device. In other embodiments, the storage device can also be an SRAM storage device, an SDRAM storage device, a ROM storage device, or a flash memory storage device.

[0087] In some embodiments, the power-on signal received by the temperature detection control circuit 301 and the storage array 300 can be the same power-on signal, poweron, and the poweron signal can also power the temperature detection module 302. The temperature detection control circuit 301 generates a temperature measurement enable signal TSCoreEn, and the temperature detection module 302, in response to the temperature measurement enable signal TSCoreEn, performs temperature detection on the storage array 300, acquires and outputs the temperature detection value TSOut. After completing the temperature detection, the temperature detection module 302 generates a temperature measurement end signal TSDone, which is transmitted to the temperature detection control circuit 301 so that the temperature detection control circuit 301 controls the temperature measurement enable signal TSCoreEn to be in an invalid state.

[0088] refer to Figure 11 The storage device may further include: a refresh module 303, which generates a refresh signal Srefclk corresponding to the temperature detection value TSOut in response to the temperature detection value TSOut, and the storage array 300 receives the refresh signal Srefclk and adjusts the refresh frequency. In a specific example, if the temperature detection value TSOut is too high, the refresh control module 303 generates a refresh signal Srefclk to control the storage array 300 to reduce the refresh frequency; if the temperature detection value TSOut is within the allowable range, the refresh signal Srefclk generated by the refresh control module to control the refresh frequency of the storage array 300 can remain unchanged.

[0089] In some embodiments, the first signal module 101 can be integrated with the refresh module 303, for example, both can be integrated into a self-refresh module (not shown). This helps ensure that the first signal module 101, which initially generates the enable signal, can effectively drive the refresh module 303. In other words, when the two are integrated, if the first signal module 101 is powered on and enabled normally, it can be assumed that the refresh module 303 will also be powered on and enabled normally. This helps ensure that the enable signal generated by the first signal module 101 can be effectively executed. If the two are integrated, there may be a situation where the first signal module 101 is powered on normally but the refresh module 303 is not powered on normally, which will result in unnecessary current consumption. However, if the two are integrated, the first signal module 101 will most likely not be powered on normally when the refresh module 303 is not powered on normally. This helps save unnecessary current consumption of the mode control circuit 102, the second signal module 103, and the temperature detection module 302.

[0090] The storage device may further include: a register 305 for storing the temperature detection value TSOut; and a test circuit 306 for outputting the temperature detection value TSOut to the test pad 307.

[0091] The storage device may also include a decoder 304, which decodes the temperature detection value TSOut and stores the decoded temperature detection value TSOut in register 305. In one example, register 305 may be mode register 4 (MR4), and decoder 304 may be the decoder (MR4Decoder) corresponding to mode register 4.

[0092] The test circuit 306 transmits the temperature detection value TSOut to the pad 307 so that the temperature detection value TSOut can be directly obtained from the pad 307.

[0093] As can be seen from the foregoing analysis, the storage device provided in this embodiment can perform temperature detection of the storage array 300 in both test mode and working mode.

[0094] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A temperature detection and control circuit, characterized in that, include: The first signal module is configured to generate an enable signal in response to a power-on signal, wherein the enable signal is a pulse signal; The mode control module is configured to receive a test signal, transmit the enable signal in segments, output the enable signal and use the enable signal as a first enable signal during the invalid period of the test signal, and output the enable signal and use the enable signal as a second enable signal during the valid period of the test signal; wherein the test signal is valid in the test mode and invalid in the working mode. The second signal module is configured to receive the first enable signal, the second enable signal, and the temperature measurement end signal; generate a temperature measurement enable signal based on the first enable signal and the temperature measurement end signal; and generate the temperature measurement enable signal based on the second enable signal and the temperature measurement end signal. The temperature measurement enable signal is used to control the temperature detection module to perform temperature detection.

2. The temperature detection and control circuit as described in claim 1, characterized in that, The first signal module includes: An oscillating circuit is configured to generate an oscillating signal in response to the power-on signal; An enable signal generation circuit is configured to receive the oscillation signal and generate the enable signal based on the number of oscillations of the oscillation signal.

3. The temperature detection and control circuit as described in claim 2, characterized in that, The enable signal generation circuit includes: The counter is configured to receive the oscillation signal and count the number of oscillations of the oscillation signal to obtain a count value, and to restart counting the number of oscillations of the oscillation signal after the count value is reset to zero; A pulse generation unit is configured to receive the count value, generate the enable signal when the count value reaches a preset value, and control the count value of the counter to return to zero.

4. The temperature detection and control circuit as described in claim 3, characterized in that, The pulse generation unit includes: The decoding unit is configured to receive the count value and generate a decoding signal when the count value reaches the preset value, wherein the decoding signal is a pulse signal. The output unit is configured to generate an enable signal and a first reset signal in response to the decoded signal, wherein the pulse width of the enable signal is greater than the pulse width of the decoded signal, and the first reset signal is used to control the counter to return to zero.

5. The temperature detection and control circuit as described in claim 4, characterized in that, The preset value includes a first preset value and a second preset value, wherein the first preset value is less than the second preset value; the decoding unit includes; The first decoding unit is configured to receive the count value and generate a value when the count value reaches the first preset value. A first decoding signal, wherein the first decoding signal is used to control the generation of the first pulse of the enable signal; The second decoding unit is configured to receive the count value and generate a second decoding signal when the count value reaches the second preset value. The second decoding signal is used to control the generation of the remaining pulses of the enable signal. The output unit is also configured to generate a shutdown signal in response to the first pulse of the enable signal, the shutdown signal controlling the first decoding unit to stop working.

6. The temperature detection and control circuit as described in claim 1, characterized in that, The mode control module includes: A first control unit, having a first node, is configured to receive the test signal and the enable signal, and output the enable signal through the first node during a period when the test signal is invalid; during a period when the test signal is valid, to shut off the transmission path from the enable signal provided by the first signal module to the first node, or to enable the first node to have a first preset level during a period when the test signal is valid. The second control unit, having a second node, is configured to receive the test signal and the enable signal, and output the enable signal through the second node during the validity period of the test signal; and during the invalid period of the test signal, to shut off the transmission path of the enable signal provided by the first signal module to the second node, or to enable the second node to have a second preset level during the invalid period of the test signal.

7. The temperature detection and control circuit as described in claim 6, characterized in that, The first control unit includes: A first inverter, the input of which receives the test signal; A first NAND gate has a first input terminal and a second input terminal, wherein the first input terminal receives the enable signal, and the second input terminal is connected to the output terminal of the first inverter. The second inverter has its input connected to the output of the first NAND gate, and its output serves as the first node. The second control unit includes: The second NAND gate has a third input terminal and a fourth input terminal, wherein the third input terminal receives the enable signal and the fourth input terminal receives the test signal; The third inverter has its input connected to the output of the second NAND gate, and its output serves as the second node.

8. The temperature detection and control circuit as described in claim 1, characterized in that, The second signal module includes: A logic circuit is configured to receive the first enable signal and the second enable signal, and generate a trigger signal, wherein the trigger signal is a pulse signal; A reset circuit is configured to receive the temperature measurement end signal to generate a second reset signal; wherein the temperature measurement end signal indicates that temperature detection has not ended, in which case the second reset signal is invalid; and the temperature measurement end signal indicates that temperature detection has ended, in which case the second reset signal is valid. The trigger circuit is configured to receive the trigger signal and the second reset signal, and generate the temperature measurement enable signal; wherein, during the period when the second reset signal is invalid, the temperature measurement enable signal is used to control the temperature detection module to perform temperature detection, and during the period when the second reset signal is valid, the temperature measurement enable signal is used to control the temperature detection module to end temperature detection.

9. The temperature detection and control circuit as described in claim 8, characterized in that, The logic circuit includes: A first logic circuit, having a third node, is configured to receive the first enable signal and output a first trigger signal via the third node; wherein, during the valid period of the test signal, the first trigger signal has a third preset level, and during the invalid period of the test signal, the first trigger signal is a pulse signal; A second logic circuit, having a fourth node, is configured to receive the second enable signal and output a second trigger signal via the fourth node; wherein, during the valid period of the test signal, the second trigger signal is a pulse signal, and during the invalid period of the test signal, the second trigger signal has a fourth preset level; An AND gate circuit is used, with its two input terminals connected to the third node and the fourth node respectively. It performs an AND operation on the first trigger signal and the second trigger signal to output the trigger signal.

10. The temperature detection and control circuit as described in claim 9, characterized in that, The first logic circuit includes: The third NAND gate has a fifth input and a sixth input. The fifth input receives the first enable signal. The sixth input is connected to the fifth input via an odd number of fourth inverters. The output of the third NAND gate is the third node. The second logic circuit includes: The fourth NAND gate has a seventh input and an eighth input. The seventh input receives the second enable signal. The eighth input is connected to the seventh input via an odd number of fifth inverters. The output of the fourth NAND gate is the fourth node.

11. The temperature detection and control circuit as described in claim 8, characterized in that, The reset circuit includes: The fifth NAND gate has a ninth input and a tenth input. The ninth input receives the temperature measurement end signal. The tenth input is connected to the ninth input via an odd number of sixth inverters. The output of the fifth NAND gate outputs the second reset signal.

12. The temperature detection and control circuit as described in claim 8, characterized in that, The trigger circuit includes an RS flip-flop, the trigger terminal of which receives the trigger signal, the reset terminal of which receives the second reset signal, and the output terminal of which outputs the temperature measurement enable signal.

13. The temperature detection and control circuit as described in claim 12, characterized in that, The second signal module also includes: The sixth NAND gate has an eleventh input and a twelfth input. The eleventh input is connected to the output of the RS flip-flop, and the twelfth input receives the power-on signal. The seventh inverter has its input connected to the output of the sixth NAND gate, and its output outputs the temperature measurement enable signal.

14. A storage device, characterized in that, include: Storage array; The temperature detection and control circuit as described in any one of claims 1-13; A temperature detection module is used to detect the temperature of the storage array in response to the temperature measurement enable signal and output the temperature detection value.

15. The storage device as claimed in claim 14, characterized in that, Also includes: A register, the register being used to store the temperature detection value; A test circuit is provided, which outputs the temperature detection value to the test pad.

Images