Memory command assignment based on command processor workload

Abstract

The embodiments described herein relate to memory command assignment based on command processor workload. In some embodiments, the memory device may determine a first command type for a first memory command. The memory device may identify a first command processor associated with the first command type, which is one of a plurality of command processors configured to execute memory commands. The first command processor may be configured to execute only commands of the first command type, unless a computational credit condition associated with another command processor is met. The memory device may determine that a cumulative computational credit value associated with the first command processor does not meet the condition. The memory device may assign the first memory command to the first command processor for execution based on the determination that the cumulative computational credit value associated with the first command processor does not meet the condition.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, memory device operations, and, for example, to memory command assignment based on command processor workloads. Background Technology

[0002] Memory devices are widely used to store information in various electronic devices. A memory device comprises memory cells. A memory cell is an electronic circuit that can be programmed into one of two or more data states. For example, a memory cell can be programmed to represent a single binary value, typically represented by a binary "1" or a binary "0". As another example, a memory cell can be programmed to represent a small number of data states (e.g., 0.5, 1.5, etc.). To store information, an electronic device can write to or program a set of memory cells. To access the stored information, the electronic device can read from or sense the stored states from the set of memory cells.

[0003] Various types of memory devices exist, including Random Access Memory (RAM), Read-Only Memory (ROM), Dynamic RAM (DRAM), Static RAM (SRAM), Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Holographic RAM (HRAM), Flash Memory (e.g., NAND and NOR memory), and so on. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for a long time, even without an external power supply. Volatile memory (e.g., DRAM) may lose stored data over time unless the volatile memory is refreshed by power. Summary of the Invention

[0004] In one aspect, this disclosure relates to a memory device comprising: one or more components configured to: detect a memory command to be executed; determine a command type of the memory command, wherein the command type is one of a first command type or a second command type; identify a primary command processor associated with the command type, wherein the primary command processor is one of a plurality of command processors configured to execute memory commands of the memory device, and wherein the primary command processor is configured to execute only commands having the first command type unless a first computational credit condition associated with another command processor of the plurality of command processors is satisfied; determine a cumulative computational credit value associated with the primary command processor based on the memory command assigned to the primary command processor; and selectively assign the memory command to the primary command processor or an auxiliary command processor of the plurality of command processors based on whether the cumulative computational credit value satisfies a threshold, wherein the auxiliary command processor is configured to execute only commands having the second command type unless a second computational credit condition associated with another command processor of the plurality of command processors is satisfied.

[0005] In another aspect, this disclosure relates to a method comprising: determining, via a memory device, a first command type of a first memory command to be executed by the memory device; identifying, via the memory device, a first command processor associated with the first command type, wherein the first command processor is one of a plurality of command processors configured to execute memory commands of the memory device, and wherein the first command processor is configured to execute only commands having the first command type, unless a computational credit condition associated with another of the plurality of command processors is satisfied; determining, via the memory device, that a cumulative computational credit value associated with the first command processor does not satisfy the condition, wherein the cumulative computational credit value is based on one or more computational credit values ​​corresponding to one or more memory commands assigned to the first command processor for execution; and, based on determining that the cumulative computational credit value associated with the first command processor does not satisfy the condition, assigning the first memory command to the first command processor for execution via the memory device.

[0006] In another aspect, this disclosure relates to an apparatus comprising: means for identifying historical workload information of a plurality of command processors configured to execute memory commands of the apparatus, wherein the historical workload information indicates a plurality of memory commands received or detected by the apparatus; means for determining a percentage of memory commands having a first command type included in the plurality of memory commands; means for determining a ratio, based on the percentage, to allocate memory commands of the first command type to a first command processor or a second command processor, wherein the first command processor is included in the plurality of command processors and configured to execute commands having the first command type, and wherein the second command processor is included in the plurality of command processors and configured to execute only commands having a second command type different from the first command type, unless historical workload conditions associated with the historical workload information are met; and means for allocating a plurality of incoming memory commands between the first command processor and the second command processor based on the ratio. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating an example system capable of assigning memory commands based on the command processor workload.

[0008] Figure 2 It is a diagram of instance components contained in a memory device.

[0009] Figures 3A-3D This is a diagram of an instance of memory command assignment based on the command processor workload.

[0010] Figures 4A-4B This is a diagram of another instance of memory command assignment based on command processor workload.

[0011] Figure 5-7 This is a flowchart of an instance method associated with memory command assignment based on command processor workloads.

[0012] Figure 8 This is a diagram illustrating an example system in which the memory devices described herein can be used. Detailed Implementation

[0013] Input / output (I / O) operations per second (IOPS) is a common performance metric for storage devices such as solid-state drives (SSDs). IOPS refers to the total number of I / O operations a storage device can perform per second. A higher IOPS count indicates better performance and lower latency for memory operations (such as read and write operations). Instance IOPS performance metrics include random read IOPS (e.g., for small data transfers), random write IOPS (for writing data to non-contiguous memory locations), sequential read IOPS (e.g., for large data transfers), and sequential write IOPS (for writing data to contiguous memory locations).

[0014] Memory devices can be manufactured to meet one or more IOPS requirements, such as a random read IOPS requirement of 1,500,000 (1.5 million) IOPS. High IOPS requirements can be difficult to meet. For example, if the memory device's command processor (sometimes called a "processor") executes instructions at a frequency of 900 MHz and has a random read requirement of 1.5 million IOPS, then the memory device needs to process one random read command every 600 processor cycles (900,000,000 Hz / 1.5 million IOPS). The memory device's processor may have difficulty or be unable to complete the read operation within 600 processor cycles, especially for random read operations that require retrieving data from non-contiguous memory locations and / or for large data transfer sizes.

[0015] To help meet read and write IOPS requirements, some memory devices (e.g., SSDs) include multiple processors. For example, one processor may be dedicated to handling (e.g., executing) read commands, while another is dedicated to handling write commands. This can result in more IOPS and better performance, especially for SSDs capable of parallel processing, such as parallel processing on different dies and / or parallel processing using the Non-Volatile Memory High Speed ​​(NVMe) specification. Even for non-parallel (e.g., sequential) processing, this configuration can produce higher IOPS compared to a configuration where each processor handles multiple different types of memory commands (e.g., read and write commands), while saving processing resources required for prioritizing memory commands. For example, using dedicated processors, the performance of a memory device can be controlled by controlling several commands processed by a specific processor (e.g., a read dedicated processor) before another processor (e.g., a write dedicated processor) executes one or more commands. To achieve this fine-grained control over non-dedicated processors handling multiple command types (e.g., read and write commands), queue management is needed to prioritize read or write operations in the command queue executed by the non-dedicated processor and / or identify which command in the queue should be processed next (e.g., the command may not be the earliest command in the queue). Therefore, using dedicated processors for specific types of memory commands can reduce the processing required for queue management and reduce latency, thereby increasing IOPS.

[0016] However, in some situations, using a dedicated processor to handle memory commands can be inefficient. For example, if the memory device has a high read workload and a low write workload, the dedicated read processor may become overloaded when the dedicated write processor is idle. One way to address this is to add another dedicated read processor to the memory device. However, this leads to increased manufacturing costs, higher power consumption, and wasted resources because the other processors are idle.

[0017] Some of the embodiments described herein enable the dynamic scheduling of memory commands to processors that are by default dedicated to a specific type of memory command. Under normal operation, when the workload conditions of any processor are not met, each processor executes only memory commands of the type (e.g., read or write) associated with that processor. When workload conditions are met, such as when a dedicated processor is overloaded, memory commands that would normally be assigned only to that dedicated processor can be assigned to one or more other processors that would not normally handle commands of that type. In this way, the performance requirements of the memory device (e.g., IOPS requirements) can be met, and the performance of the memory device can be improved (e.g., latency reduced) without adding additional dedicated processors to the memory device. Therefore, some of the embodiments described herein improve performance by better utilizing processor resources without increasing manufacturing costs or power consumption.

[0018] Figure 1 This is a diagram illustrating an example system 100 capable of assigning memory commands based on command processor workload. System 100 may include one or more means, devices, and / or components for performing the operations described herein. For example, system 100 may include a host device 110 and a memory device 120. Memory device 120 may include a controller 130 and a memory 140. Host device 110 may communicate with memory device 120 (e.g., the controller 130 of memory device 120) via host interface 150. Controller 130 and memory 140 may communicate via memory interface 160.

[0019] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, mobile phone, wired or wireless communication device, network device, server, device in a data center, device in a cloud computing environment, vehicle (e.g., car or airplane), and / or Internet of Things (IoT) device. Host device 110 may include one or more processors configured to execute instructions and store data in memory 140. For example, host device 110 may include a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or another type of processing component.

[0020] Memory device 120 can be any electronic device or apparatus configured to store data in memory. In some embodiments, memory device 120 can be an electronic device configured to persistently store data in non-volatile memory. For example, memory device 120 can be a hard disk drive, solid-state drive (SSD), flash memory device (e.g., NAND flash memory device or NOR flash memory device), universal serial bus (USB) flash drive, memory card (e.g., Secure Digital (SD) card), secondary storage device, non-volatile memory high speed (NVMe) device, and / or embedded multimedia card (eMMC) device. In this case, memory 140 may include non-volatile memory configured to retain stored data after power loss of memory device 120. For example, memory 140 may include NAND memory or NOR memory. In some implementations, memory 140 may include volatile memory that requires power to maintain stored data and loses stored data after power is lost from memory device 120, such as one or more latches and / or random access memory (RAM), such as dynamic RAM (DRAM) and / or static RAM (SRAM). For example, the volatile memory may cache data read from or written to non-volatile memory, and / or cache instructions executed by controller 130.

[0021] Controller 130 can be any device configured to communicate with a host device (e.g., via host interface 150) and memory 140 (e.g., via memory interface 160). Alternatively or additionally, controller 130 can be configured to control the operation of memory device 120 and / or memory 140. For example, controller 130 may include a memory controller, system controller, ASIC, FPGA, processor, microcontroller, and / or one or more processing components. In some embodiments, controller 130 may be a high-level controller that can communicate directly with host device 110 and can instruct one or more low-level controllers regarding memory operations to be performed in conjunction with memory 140. In some embodiments, controller 130 may be a low-level controller that can receive instructions regarding memory operations from a high-level controller that directly interfaces with host device 110. As an example, the high-level controller may be an SSD controller, and the low-level controller may be a non-volatile memory controller (e.g., a NAND controller) or a volatile memory controller (e.g., a DRAM controller). In some implementations, a set of operations described herein as being performed by controller 130 may be performed by a single controller (e.g., the entire set of operations may be performed by a single high-level controller or a single low-level controller). Alternatively, a set of operations described herein as being performed by controller 130 may be performed by more than one controller (e.g., a first subset of the operations may be performed by a high-level controller, and a second subset of the operations may be performed by a low-level controller).

[0022] Host interface 150 enables communication between host device 110 and storage device 120. Host interface 150 may include, for example, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, NVMe interface, USB interface, Universal Flash Storage (UFS) interface and / or an Embedded Multimedia Card (eMMC) interface.

[0023] Memory interface 160 enables communication between memory device 120 and memory 140. Memory interface 160 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Alternatively, memory interface 160 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a Double Data Rate (DDR) interface.

[0024] In some embodiments, memory device 120 and / or controller 130 may be configured to detect a memory command to be executed; determine the command type of the memory command, wherein the command type is one of a first command type or a second command type; identify a primary command processor associated with the command type, wherein the primary command processor is one of a plurality of command processors configured to execute memory commands of memory device 120, and wherein the primary command processor is configured to execute only commands of the first command type unless a first computational credit condition associated with another command processor of the plurality of command processors is satisfied; determine a cumulative computational credit value associated with the primary command processor based on the memory command assigned to the primary command processor; and selectively assign memory commands to a primary command processor or an auxiliary command processor of the plurality of command processors based on whether the cumulative computational credit value meets a threshold, wherein the auxiliary command processor is configured to execute only commands of the second command type unless a second computational credit condition associated with another command processor of the plurality of command processors is satisfied.

[0025] Alternatively or concurrently, the memory device 120 and / or controller 130 may be configured to determine a first command type of a first memory command to be executed by the memory device 120; identify a first command processor associated with the first command type, wherein the first command processor is one of a plurality of command processors configured to execute memory commands of the memory device 120, and wherein the first command processor is configured to execute only commands having the first command type unless a computational credit condition associated with another of the plurality of command processors is satisfied; determine that a cumulative computational credit value associated with the first command processor does not meet the condition, wherein the cumulative computational credit value is based on one or more computational credit values ​​corresponding to one or more memory commands assigned to the first command processor for execution; and assign the first memory command to the first command processor for execution based on the determination that the cumulative computational credit value associated with the first command processor does not meet the condition.

[0026] Alternatively, the memory device 120 and / or controller 130 may be configured to identify historical workload information of a plurality of command processors configured to execute memory commands of the memory device 120, wherein the historical workload information indicates a plurality of memory commands received or detected by the memory device 120; determine a percentage of memory commands of a first command type included in the plurality of memory commands; determine a ratio for allocating memory commands of the first command type to a first command processor or a second command processor, wherein the first command processor is included in the plurality of command processors and configured to execute commands of the first command type, and wherein the second command processor is included in the plurality of command processors and configured to execute only commands of a second command type different from the first command type, unless historical workload conditions associated with the historical workload information are met; and allocate a plurality of incoming memory commands between the first command processor and the second command processor based on the ratio.

[0027] As pointed out above, Figure 1 Provided as an example. Other examples are available in the section about Figure 1 The content is different.

[0028] Figure 2 This is a diagram of an instance component contained in memory device 120. (As described above...) Figure 1 As described, memory device 120 may include controller 130 and memory 140. For example... Figure 2As shown, memory 140 may include one or more non-volatile memory arrays 210, such as one or more NAND memory arrays and / or one or more NOR memory arrays. Alternatively, memory 140 may include one or more volatile memory arrays 220, such as one or more SRAM arrays and / or one or more DRAM arrays. Controller 130 may use non-volatile memory interface 230 to transmit signals to and receive signals from non-volatile memory array 210. Controller 130 may use volatile memory interface 240 to transmit signals to and receive signals from volatile memory array 220.

[0029] Controller 130 can control the operation of memory 140, for example, by executing one or more instructions. For example, memory device 120 can store one or more instructions as firmware in memory 140, and controller 130 can execute said one or more instructions. Alternatively, controller 130 can receive one or more instructions from host device 110 via host interface 150, and can execute said one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) can store a set of instructions (e.g., one or more instructions or codes) for controller 130 to execute. Controller 130 can execute said set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of said set of instructions by controller 130 causes controller 130 and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, a hard-wired circuitry system is used instead of said one or more instructions or in combination with them to perform one or more operations or methods described herein. Alternatively, one or more components of the controller 130 and / or memory device 120 may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as “commands”.

[0030] For example, controller 130 may transmit signals to and / or receive signals from memory 140 based on one or more instructions to transfer data (e.g., write or program) to all or part of memory 140 (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of memory 140), transfer data from it (e.g., read) and / or erase it. Alternatively or additionally, controller 130 may be configured to control access to memory 140 and / or provide a translation layer (e.g., for mapping logical addresses of the memory array to physical addresses) between host device 110 and memory 140. In some embodiments, controller 130 may translate host interface commands (e.g., commands received from host device 110) into memory interface commands (e.g., commands for performing operations on the memory array).

[0031] like Figure 2As shown, memory device 120 may include multiple (e.g., a plurality of) command processors 250, shown as command processors 250a to 250x (x≥2). Command processors 250 (sometimes referred to as processors) may include one or more processors configured to execute memory commands of memory device 120, such as read commands, write commands, and / or erase commands. For example, command processor 250 may include a CPU, a processor core (e.g., a CPU core), and / or another type of processing component. In some embodiments, command processor 250 is a dedicated processor for processing (e.g., executing) a specific command type or a specific set of command types (e.g., a subset of all command types that memory device 120 can execute).

[0032] For example, a first command processor 250 may be dedicated to processing only read commands and may be referred to as a read-dedicated command processor (or read-only processor). As another example, a second command processor 250 may be dedicated to processing only write commands and may be referred to as a write-dedicated command processor (or write-only processor). As another example, a third command processor 250 may be dedicated to processing only Flash Translation Layer (FTL) commands and may be referred to as an FTL-dedicated command processor (or FTL-only processor). In some embodiments, the memory device 120 may include a command processor 250 dedicated to processing all command types not handled by any of the other dedicated command processors 250, sometimes referred to as a common service command processor 250. Continuing with the above examples, the memory device 120 may include a fourth command processor 250 dedicated to processing non-read, non-write, and non-FTL commands.

[0033] According to some embodiments described herein, under default operating conditions, such as when the workload conditions of any command processor 250 are not met, each command processor 250 may process only the command type associated with command processor 250 (e.g., command types dedicated to command processor 250). For example, the first command processor 250 may process only commands with a first command type (e.g., read-only commands), and the second command processor 250 may process only commands with a second command type (e.g., write-only commands). Under high workload conditions, such as when the workload conditions of the first command processor 250 are met, the second command processor 250 may be assigned and may process command types that are by default processed only by the first command processor 250 (and / or not by the second command processor 250). For example, if the workload conditions of a read-dedicated command processor that processes only read commands under default operating conditions are met, then the memory device 120 and / or the controller 130 may assign one or more read commands to a write-dedicated command processor that processes only write commands under default operating conditions. In this way, the performance requirements of the memory device (e.g., IOPS requirements) can be met, and the performance of the memory device can be improved (e.g., latency reduced) without adding an additional dedicated processor to the memory device. Therefore, some of the embodiments described herein improve performance by better utilizing processor resources without increasing manufacturing costs or power consumption.

[0034] Controller 130 may assign commands to command processor 250 based on workload conditions, as described in more detail elsewhere herein. For example, command processor 250 may be associated with a command queue (e.g., stored in memory 140, such as volatile memory array 220 and / or a cache associated with command processor 250), and controller 130 may place commands into appropriate queues (e.g., associated with command processor 250 that processes commands in said queues) based on workload conditions. Command processor 250 may execute commands in the queues associated with it sequentially (e.g., in a first-in, first-out manner). For example, command processor 250 may execute a command by signaling to memory 140, such as to one or more non-volatile memory arrays 210. In some embodiments, command processor 250 may notify controller 130 of the command execution completion time.

[0035] like Figure 2 As shown, controller 130 may include memory management component 260, command assignment component 270, and / or workload determination component 280. In some embodiments, one or more of these components are implemented as one or more instructions (e.g., firmware) executed by controller 130. Alternatively, one or more of these components may be implemented as an application-specific integrated circuit (ASIC) different from controller 130.

[0036] Memory management component 260 may be configured to manage the performance of memory device 120. For example, memory management component 260 may perform wear leveling, bad block management, block retirement, read interference management, and / or other memory management operations. In some embodiments, memory device 120 may (e.g., in memory 140) store one or more memory management tables. Memory management tables may store information that can be used or updated by memory management component 260, such as information about memory block usage time, memory block erase counts, and / or error information associated with memory partitions (e.g., memory cells, memory rows, memory blocks, etc.).

[0037] Command assignment component 270 can be configured to detect memory commands to be executed, determine the command type of the command, and identify a primary command processor (sometimes referred to as a first command processor) associated with the command type, such as a primary command processor dedicated to processing commands of the command type. Command assignment component 270 can selectively assign memory commands to the primary command processor or to an auxiliary command processor (sometimes referred to as a second command processor) dedicated to processing commands with different command types. For example, command assignment component 270 can determine whether to assign memory commands to the primary command processor or the auxiliary command processor based on workload conditions. In some embodiments, command assignment component 270 can receive an indication from workload determination component 280 as to whether workload conditions are met. Command assignment component 270 can selectively assign memory commands to the primary command processor or the auxiliary command processor based on whether workload conditions are met. Alternatively or additionally, based on an indication from workload determination component 280, such as an indication of allocation ratio, command assignment component 270 can distribute commands among or between two or more command processors.

[0038] The workload determination component 280 may be configured to determine whether workload conditions associated with command processor 250 are met. For example, the workload determination component 280 may determine a computational credit value associated with a command and / or may determine a cumulative computational credit value associated with command processor 250 (e.g., by modifying or updating the cumulative computational credit value based on the computational credit value associated with the command), as described in more detail elsewhere herein. The workload determination component 280 may determine whether workload conditions are met based on the cumulative computational credit value (e.g., based on whether the cumulative computational credit value meets a threshold). Alternatively or additionally, the workload determination component 280 may determine or identify historical workload information of memory device 120 (e.g., command processor 250). Based on historical workload information, such as whether the percentage of commands of a particular command type meets a threshold, the workload determination component 280 may determine whether workload conditions are met. In some embodiments, the workload determination component 280 may determine an allocation ratio for assigning commands to command processor 250 and may indicate the allocation ratio to command assignment component 270. Alternatively, the workload determination component 280 may indicate to the command assignment component 270 whether the workload conditions are met.

[0039] Figure 2 The one or more devices or components shown may be configured to perform the operations described elsewhere herein, for example... Figures 3A-3D and / or one or more operations of 4A-4B and / or Figure 5-7 One or more process blocks of the method. For example, controller 130, one or more command processors 250, memory management component 260, command assignment component 270 and / or workload determination component 280 may be configured to perform one or more operations and / or methods of memory device 120.

[0040] Figure 2 The number and arrangement of components shown are provided as examples. In fact, compared to... Figure 2 The components shown may include additional components, fewer components, different components, or components arranged in different ways. Furthermore, Figure 2 The two or more components shown can be implemented within a single component, or Figure 2 The single component shown can be implemented as multiple distributed components. Alternatively, Figure 2 The set of components shown (e.g., one or more components) can be performed as described by Figure 2 The other set of components shown performs one or more operations.

[0041] Figures 3A-3D This is a diagram of instance 300 of memory command assignment based on the command processor workload. Combined with... Figures 3A-3DThe described operations may be performed by memory device 120 and / or one or more components of memory device 120 (e.g., controller 130).

[0042] As indicated by reference numeral 305, controller 130 can detect memory commands, such as read commands, write commands, erase commands, or other types of commands. As indicated by reference numeral 305a, memory commands can be host memory commands. Alternatively, as indicated by reference numeral 305b, memory commands can be non-host memory commands. Host memory commands can be memory commands received from host device 110 (e.g., via host interface 150). Non-host memory commands can be memory commands not received from host device 110, such as memory commands generated by memory device 120 and / or controller 130 (e.g., for performing one or more internally initiated operations).

[0043] As shown by reference numeral 310 in the attached figure, controller 130 can determine the memory command type of the memory command. Example memory command types include read commands (with read command type), host read commands (with host read command type), non-host read commands (with non-host read command type), write commands (with write command type), host write commands (with host write command type), non-host write commands (with non-host write command type), alignment commands (with alignment command type), aligned read commands (with aligned read command type), aligned write commands (with aligned write command type), misaligned commands (with misaligned command type), misaligned read commands (with misaligned read command type), misaligned write commands (with misaligned write command type), erase commands (with erase command type), FTL commands (with FTL command type), and garbage collection (GC) commands (with GC command type). The commands include: read commands (with GC read command type), GC write commands (with GC write command type), data integrity scan read commands (with data integrity scan read command type), FTL commands (with FTL command type), FTL read commands (with FTL read command type), FTL write commands (with FTL write command type), trim commands (with trim command type), file system area (FSA) commands (with FSA command type), FSA read commands (with FSA read command type), FSA write commands (with FSA write command type), independent NAND redundant array (RAIN) write commands (with RAIN write command type), non-read, non-write, non-erase commands (with non-read, non-write, non-erase command type), or another type of command (with another command type). In Example 300, the memory command is shown as "Command A" with "Command Type A". As an example, Command A can be a read command with a read command type.

[0044] A read command of type read command may include a command to read data stored in memory device 120 (e.g., in memory 140). A host read command may include a command to read data stored in memory device 120 received from host device 110. A non-host read command may include a command to read data stored in memory device 120 that is not received from host device 110 (e.g., generated internally by memory device 120). Non-host read commands may include, for example, GC read commands, data integrity scan read commands, FTL read commands, or FSA read commands. A GC read command may include a command to read valid data from a first memory block such that the valid data can be written to a second memory block, for example, before erasing the first memory block. A data integrity scan read command may include a command to read data from memory for data verification and / or error checking. An FTL read command may include a command to read information from an address table (e.g., a physical address to logical address translation table, a block address table, and / or a logical block address table). An FSA read command may include a command to read log data (e.g., a log file) from memory.

[0045] Write commands (sometimes called programming commands) may include commands to write (or program) data to memory device 120 (e.g., in memory 140). Host write commands may include commands received from host device 110 to write data to memory device 120. Non-host write commands may include commands not received from host device 110 (e.g., generated internally by memory device 120) to write data to memory device 120. Non-host write commands may include, for example, GC write commands, FTL write commands, trim commands, FSA write commands, or RAIN write commands. A GC write command may include, for example, a command to write valid data from a first memory block to a second memory block before erasing the first memory block. An FTL write command may include a command to write information to an address table. A trim command may include a command to write an indication that data stored at a memory address is invalid to an address table. An FSA write command may include a command to write log data (e.g., a log file) to memory. A RAIN write command may include a command to write the RAIN parity bit to memory. An erase command may contain a command to erase data stored by memory device 120 (e.g., in memory 140). In some cases, an erase command is considered a type of write command because an erase command writes an erase data state (e.g., "1") to a memory cell.

[0046] An alignment command may include a command to read data from memory or write data to memory, wherein the data transfer size of the data to be read or written matches the logical block address (LBA) size used by memory device 120. For example, if memory device 120 uses an LBA size of 4 kilobytes (e.g., for all LBAs or the requested LBA), and if a read command requests to read 4 kilobytes of data from memory, then the read command is an aligned read command. Similarly, if memory device 120 uses an LBA size of 4 kilobytes, and if a write command requests to write 4 kilobytes of data to memory, then the write command is an aligned write command.

[0047] An unaligned command may include a command to read data from memory or write data to memory, wherein the data transfer size of the data to be read or written does not match the LBA size used by memory device 120. For example, if memory device 120 uses an LBA size of 4 kilobytes, and if a read command requests to read 512 bytes of data from memory, then the read command is an unaligned read command. Similarly, if memory device 120 uses an LBA size of 4 kilobytes, and if a write command requests to write 512 bytes of data to memory, then the write command is an unaligned write command. Unaligned commands (e.g., unaligned read commands and unaligned write commands) may be computationally more expensive than aligned commands (e.g., aligned read commands and aligned write commands) because additional operations are required to read from or write to a smaller data transfer size (e.g., 512 bytes) of a larger LBA size (e.g., 4 kilobytes). For example, for an unaligned read command, after reading 4 kilobytes of data, 512 bytes of data need to be extracted from said 4 kilobytes of data.

[0048] Non-read, non-write, and non-erase commands are sometimes referred to as out-of-band (OOB) commands. OOB commands may contain commands for operations that are not performed on the memory array of memory device 120 (e.g., not writing data to the memory array, not reading data from the memory array, and not erasing the memory array). For example, OOB commands may include requests to obtain a unique identifier for memory device 120, requests for on-demand paging (ODP), requests to obtain the temperature of memory device 120, and / or management commands (e.g., requests to obtain or set characteristics).

[0049] As shown by reference numeral 315 in the attached figure, controller 130 can identify the main command processor associated with the determined command type of the detected memory command, shown as main command processor 250a. (As described above...) Figure 2As described, the main command processor can be a dedicated command processor specifically designed to process commands of a defined command type. For example, the main command processor may only process commands of a defined command type unless workload conditions associated with another command processor 250 (e.g., calculating credit conditions and / or historical workload conditions) are met. As an example, if the memory command is a read command, then the main command processor could be a read-dedicated command processor that only processes (e.g., executes) read commands unless workload conditions associated with another command processor, such as a write-dedicated command processor, are met. As another example, if the memory command is a write command, then the main command processor could be a write-dedicated command processor that only processes (e.g., executes) write commands unless workload conditions associated with another command processor, such as a read-dedicated command processor, are met.

[0050] A specific command processor 250 may be dedicated to a single command type described herein, or it may be dedicated to a set of command types described herein. Furthermore, command types can be defined at various granularities. For example, command processor 250 may be dedicated to host read commands, in which case command processor 250 does not execute non-host read commands (unless workload conditions are met). As another example, command processor 250 may be dedicated to read commands, which includes both host and non-host read commands. As yet another example, command processor 250 may be dedicated to write and erase commands.

[0051] As indicated by reference numeral 320, in addition to the main command processor, the memory device 120 may also include one or more auxiliary command processors, shown as auxiliary command processor 250b, auxiliary command processor 250c, and auxiliary command processor 250d. The auxiliary command processors are not associated with the determined command type of the detected memory command. For example, an auxiliary command processor may be a dedicated command processor specifically designed to process commands having one or more command types other than the determined command type. For example, an auxiliary command processor may process commands with the determined command type only if workload conditions associated with another command processor 250 (e.g., calculating credit conditions and / or historical workload conditions) are met. As an example, if the memory command is a read command, then the auxiliary command processor may be a write-dedicated command processor that only processes (e.g., executes) write commands unless workload conditions associated with another command processor, such as a read-dedicated command processor, are met. As another example, if the memory command is a write command, then the auxiliary command processor may be a read-dedicated command processor that only processes (e.g., executes) read commands unless workload conditions associated with another command processor, such as a write-dedicated command processor, are met.

[0052] Therefore, in some implementations, the primary command processor is configured to execute only commands of the first command type unless a first workload condition is met. In some implementations, the first workload condition is a first computational credit condition associated with another command processor 250 (e.g., other than the primary command processor), such as the cumulative computational credit value associated with another command processor 250 (e.g., other than the primary command processor) meeting a threshold, as described in more detail below. Alternatively, the first workload condition may be a first historical workload condition, as described below in conjunction with... Figures 4A-4B As described. Similarly, an auxiliary command processor may be configured to execute only commands with a second command type (e.g., different from the first command type) unless a second workload condition is met. In some embodiments, the second workload condition is a second computational credit condition associated with another command processor 250 (e.g., other than the auxiliary command processor, such as the main command processor), such as the cumulative computational credit value associated with another command processor 250 (e.g., other than the auxiliary command processor, such as the main command processor) meeting a threshold, as described in more detail below. Alternatively or additionally, the second workload condition may be a second historical workload condition, as described below in conjunction with Figures 4A-4B As described.

[0053] exist Figure 3A In example 300, controller 130 identifies main command processor 250a, shown as "processor A". For example, main command processor 250a (sometimes referred to as the first command processor) may be dedicated to a first command type, auxiliary command processor 250b (sometimes referred to as the second command processor) may be dedicated to a second command type, auxiliary command processor 250c (sometimes referred to as the third command processor) may be dedicated to a third command type, and auxiliary command processor 250d (sometimes referred to as the fourth command processor) may be dedicated to a fourth command type. Although... Figure 3A Four command processors 250 are shown, but the memory device 120 may contain a different number of command processors 250, such as two, three, or more than four. In some embodiments where the memory device 120 includes two (or more) command processors 250, a first command processor 250 may be dedicated to a first command type (e.g., a read command type or a write command type), and a second command processor 250 may be dedicated to a second command type (e.g., a read command type or another write command type).

[0054] As shown by reference numeral 325 in the accompanying drawings, in some embodiments, the controller 130 may determine a cumulative calculated credit value associated with the identified master command processor 250a. (See the following text in conjunction with...) Figure 3BIn more detail, the cumulative computed credit value of a particular command processor 250 may be based on all memory commands assigned to said particular command processor 250 (e.g., and not yet executed by it). In some embodiments, each command processor 250 may be associated with a corresponding cumulative computed credit value; for example, a first cumulative computed credit value 330a may be associated with a first command processor 250a, a second cumulative computed credit value 330b with a second command processor 250b, a third cumulative computed credit value 330c with a third command processor 250c, and a fourth cumulative computed credit value 330d with a fourth command processor 250d. The controller 130 may determine whether to assign a detected memory command to the main command processor 250a based on whether the cumulative computed credit value of the main command processor 250a (e.g., the first cumulative computed credit value 330a) meets a threshold 335.

[0055] like Figure 3B As shown in the figure, and as indicated by reference numeral 340, the cumulative computational credit value of the main command processor 250a may be based on all memory commands assigned to the main command processor 250a (e.g., and not yet executed by it). For example, a memory command may be associated with a computational credit value, which may be based on the command type of the memory command and / or the data transfer size associated with the memory command. The cumulative computational credit value of the command processor 250 may be based on all computational credit values ​​corresponding to all memory commands assigned to the command processor 250 for execution (e.g., and not yet executed). For example, the cumulative computational credit value of the command processor 250 may represent a combination of all computational credit values ​​corresponding to all memory commands assigned to the command processor 250, such as the sum of all those computational credit values.

[0056] As an example, and as Figure 3B As shown, the main command processor 250a has been assigned a first read command, shown as "Read Command 1," which contains a request to read data from three logical block addresses (LBAs) of memory. As further shown, the main command processor 250a is also assigned a second read command, shown as "Read Command 2," which contains a request to read data from one LBA of memory. The main command processor 250a may also be assigned one or more other memory commands, and the cumulative calculated credit value 330a of the main command processor 250a may be the sum of the calculated credit values ​​of the memory commands assigned to the main command processor 250a. Figure 3B As shown, the cumulative calculated credit value 330a of the main command processor 250a is less than the threshold 335 (sometimes referred to as the calculated credit threshold or the cumulative calculated credit threshold).

[0057] As noted above, the calculated credit value associated with a memory command can be based on the command type of the memory command and / or the data transfer size associated with the memory command. In some embodiments, the calculated credit value can be based on the command type of the memory command, regardless of the data transfer size associated with the memory command. This reduces complexity and saves processing resources of controller 130. For example, a read command type can be associated with calculating a credit value, regardless of the data transfer size. In this case, a first read command (“Read Command 1”) can be associated with calculating a credit value, and a second read command (“Read Command 2”) can also be associated with calculating a credit value, even if the second read command has a larger data transfer size (e.g., 3 LBAs) compared to the first read command (e.g., 1 LBA).

[0058] In some implementations, the computed credit value associated with a memory command may be based on the data transfer size associated with the memory command, regardless of the command type associated with the memory command. This reduces complexity and saves processing resources of controller 130. The data transfer size may be indicated in the memory command, such as an indication of the number of LBAs associated with the memory command (e.g., the number of LBAs from which data will be read or written). Alternatively, the data transfer size may be based on the storage size (e.g., 4 kilobytes, 8 kilobytes, 1 megabyte, or 2 megabytes) associated with the number of LBAs indicated in the memory command. As an example, the computed credit value of a memory command may be based on the number of LBAs indicated in the memory command. In this case, a first read command (“Read Command 1”) may be associated with computed credit value 3 (e.g., based on a request to read data from three LBAs), and a second read command (“Read Command 2”) may be associated with computed credit value 1 (e.g., based on a request to read data from one LBA). In some implementations, the computed credit value associated with a memory command indicates or is based on the computational complexity of executing the memory command. Therefore, the calculated credit value associated with a command that is associated with a larger data transfer size is greater than the calculated credit value associated with a command that is associated with a smaller data transfer size (e.g., because a command associated with a larger data transfer size may be computationally more expensive than a command associated with a smaller data transfer size).

[0059] In some implementations, the computational credit value associated with a memory command may be based on both the command type of the memory command and the data transfer size associated with the memory command. In some implementations, different memory command types may be associated with different computational credit values. As an example, a first command type may be associated with a first computational credit value, and a second command type may be associated with a second computational credit value that is different from the first computational credit value. For example, the magnitude of the computational credit value associated with a write command type may be greater than the computational credit value associated with a read command type (e.g., because a write command may be computationally more expensive than a read command). As an example, a write command type may be associated with computational credit value two, and a read command type may be associated with computational credit value one.

[0060] In some implementations, the amount of computational credit associated with a read command type may be lower than that of a write command type (e.g., because read commands are computationally less expensive than write commands), and / or the amount of computational credit associated with a trim command type may be lower than that of both write and read command types (e.g., because trim commands are computationally less expensive than both read and write commands). Alternatively or additionally, the amount of computational credit associated with an misaligned read command type may be lower than that of an misaligned write command type (e.g., because misaligned read commands are computationally less expensive than misaligned write commands), the amount of computational credit associated with an aligned write command type may be lower than that of a misaligned write command type (e.g., because aligned commands are computationally less expensive than misaligned commands), and / or the amount of computational credit associated with an aligned read command type may be lower than that of both misaligned read and aligned write command types (e.g., because aligned commands are computationally less expensive than misaligned commands, and read commands are computationally less expensive than write commands).

[0061] In some implementations, a type-based computed credit value (e.g., based on command type) of a memory command can be combined with a size-based computed credit value (e.g., based on data transfer size) of the memory command to determine the total computed credit value of the memory command. As an example, controller 130 can add the type-based computed credit value and the size-based computed credit value of the memory command to determine the total computed credit value of the memory command. In this case, based on the fact that a first read command is a read command (e.g., having a type-based computed credit value one) and is associated with the data transfer size of three LBAs (e.g., having a size-based computed credit value three), the first read command can be associated with computed credit value four, and based on the fact that a second read command is a read command (e.g., having a type-based computed credit value one) and is associated with the data transfer size of one LBA (e.g., having a size-based computed credit value one), the second read command can be associated with computed credit value two.

[0062] Alternatively, controller 130 may multiply the type-based calculated credit value of the memory command and the size-based calculated credit value of the memory command to determine the total calculated credit value of the memory command. In this case, the first read command may be associated with calculated credit value three based on the fact that the first read command is a read command (e.g., having a type-based calculated credit value one) and is associated with the data transfer size of three LBAs (e.g., having a size-based calculated credit value three), and the second read command may be associated with calculated credit value one based on the fact that the second read command is a read command (e.g., having a type-based calculated credit value one) and is associated with the data transfer size of one LBA (e.g., having a size-based calculated credit value one).

[0063] As shown by reference numeral 345 in the accompanying drawings, controller 130 may assign a memory command to main command processor 250a based on the determination that the accumulated calculated credit value 330a of main command processor 250a does not meet a threshold 335 (e.g., is less than or equal to threshold 335). In other words, controller 130 may assign a memory command to main command processor 250a based on the failure to meet a workload condition associated with main command processor 250a. In example 300, the workload condition is whether the accumulated calculated credit value meets threshold 335. In this case, the workload condition may be referred to as the calculated credit condition. In example 300, the workload condition (and the calculated credit condition) are not met because the accumulated calculated credit value does not meet threshold 335.

[0064] As indicated by reference numeral 350 in the accompanying drawings, controller 130 may modify the accumulated computed credit value 330a associated with main command processor 250a based on assigning a memory command to main command processor 250a. For example, controller 130 may modify the accumulated computed credit value 330a based on the computed credit value associated with the assigned memory command. In example 300, the assigned memory command is a read command, shown as "Read Command A," which contains a request to read data from two LBAs of memory. Controller 130 may determine a new accumulated computed credit value (sometimes referred to as a modified accumulated computed credit value or an updated accumulated computed credit value) based on a previous accumulated computed credit value and the computed credit value associated with the assigned memory command. For example, controller 130 may combine the previous accumulated computed credit value and the computed credit value associated with the assigned memory command (e.g., add them together).

[0065] In some cases, assigning memory commands to command processor 250 and modifying the accumulated calculated credit value associated with said command processor 250 can make the accumulated calculated credit value meet a threshold 335 (e.g., greater than or equal to threshold 335), such as Figure 3B As shown in the image. Figure 3CThis illustrates an example of assigning a memory command to command processor 250 when threshold 335 is met.

[0066] like Figure 3C As shown in the figure, and as indicated by reference numeral 355, controller 130 can detect memory commands, as described above. Figure 3A The reference numeral 305 describes the memory command. For example, the memory command described above in conjunction with reference numeral 305 may be a first memory command detected at an earlier time, while the memory command detected in conjunction with reference numeral 355 may be a second memory command detected at a later time. For example, the controller 130 may detect the second memory command after the first memory command has been assigned to the main command processor 250a, such that the cumulative computational credit value 330a associated with the main command processor 250a exceeds the threshold 335.

[0067] As shown by reference numeral 360 in the attached figure, the controller 130 can determine the memory command type of the second memory command, as described above. Figure 3A The figure is described by reference numeral 310. In example 300, the second memory command has the same command type as the first memory command. In example 300, the first memory command is shown as "Command A" with "Command Type A", and the second memory command is shown as "Command B" with the same "Command Type A". As an example, both the first memory command and the second memory command can be read commands with a read command type.

[0068] As shown by reference numeral 365 in the attached figure, the controller 130 can identify the main command processor associated with the determined command type of the second memory command, as described above. Figure 3A As described by reference numeral 315 in the accompanying drawings. Figure 3C In instance 300, controller 130 identifies the main command processor 250a, shown as “processor A”, as the command processor 250 associated with the determined command type (e.g., read command).

[0069] As indicated by reference numeral 370 in the attached figure, the controller 130 can determine the cumulative calculated credit value associated with the identified master command processor 250a, as described above. Figure 3A As described by reference numeral 325 in the accompanying drawings. For example, controller 130 may determine the current cumulative computational credit value of master command processor 250a (e.g., the cumulative computational credit value associated with master command processor 250a when controller 130 is determining the command processor to which a memory command will be assigned). As shown, controller 130 may determine that the cumulative computational credit value 330a associated with master command processor 250a meets threshold 335 (e.g., after a first memory command is assigned to master command processor 250a, as described above). Figure 3B (As described).

[0070] As indicated by reference numeral 375 in the accompanying drawings, based on the determination that the accumulated calculated credit value 330a of the main command processor 250a meets a threshold 335 (e.g., is greater than or equal to threshold 335), the controller 130 may assign a second memory command to an auxiliary command processor (e.g., instead of the main command processor 250a). In other words, the controller 130 may assign a memory command to an auxiliary command processor based on the satisfaction of a workload condition associated with the main command processor 250a. In example 300, the workload condition is whether the accumulated calculated credit value meets threshold 335. In this case, the workload condition may be referred to as the calculated credit condition. In example 300, the workload condition (and the calculated credit condition) are satisfied because the accumulated calculated credit value meets threshold 335.

[0071] If the memory device 120 includes a single auxiliary command processor, then the controller 130 may assign the second memory command to the single auxiliary command processor. However, if the memory device 120 includes multiple auxiliary command processors (e.g., a second command processor 250b, a third command processor 250c, and a fourth command processor 250d, as shown), then the controller 130 may select one of the multiple auxiliary command processors to process (e.g., execute) the second memory command. In some embodiments, the controller 130 selects a default auxiliary command processor. The default auxiliary command processor may be an auxiliary command processor that handles all overflow memory commands when workload conditions (e.g., for any primary command processor) are met, or an auxiliary command processor that handles the overflow memory commands of a specific primary command processor when workload conditions of that specific primary command processor are met. For example, a first pair of command processors may be configured to handle each other's overflow memory commands, a second pair of command processors may be configured to handle each other's overflow memory commands, and so on.

[0072] As another example, a second command processor 250b can handle overflow memory commands from a first command processor 250a, a third command processor 250c can handle overflow memory commands from a second command processor 250b, a fourth command processor 250d can handle overflow memory commands from a third command processor 250c, and a first command processor 250a can handle overflow memory commands from a fourth command processor 250d. Similar "cascaded" configurations can be used for different numbers of command processors 250, in addition to four. An "overflow memory command" is a memory command that is not assigned to a particular command processor because the cumulative computational credit value of that particular command processor meets a threshold.

[0073] In some implementations, controller 130 may select an auxiliary command processor that has the smallest cumulative calculated credit value among all auxiliary command processors. Alternatively, controller 130 may select an auxiliary command processor that has the largest difference between its cumulative calculated credit value and a threshold 335 associated with it, among all auxiliary command processors. In this way, controller 130 can balance the workload across command processors, thereby reducing latency. Although a single threshold 335 (e.g., a common threshold) is shown associated with all command processors (e.g., the main command processor and all auxiliary command processors) in example 300, in some implementations, each command processor may be associated with a different threshold (or at least one command processor may be associated with a threshold different from at least one other command processor).

[0074] exist Figure 3C In Example 300, controller 130 assigns a second memory command to auxiliary command processor 250b. Therefore, controller 130 may selectively assign memory commands to either the main command processor or the auxiliary command processor based on whether a workload condition is met (e.g., whether the accumulated computational credit value of the main command processor meets a threshold). As used herein, “selectively” assigning a memory command to either the main command processor or the auxiliary command processor means assigning the memory command to either the main command processor or the auxiliary command processor. For example, selectively assigning a memory command to either the main command processor or the auxiliary command processor based on a condition (e.g., a workload condition or a computational credit condition) means assigning the memory command to the main command processor if the condition is not met, and assigning the memory command to the auxiliary command processor if the condition is met (or vice versa). Therefore, “selectively assigning” a memory command may include determining whether to assign the memory command to the main command processor or the auxiliary command processor, and then assigning the memory command to either the main command processor or the auxiliary command processor based on that determination.

[0075] As shown by reference numeral 380 in the attached figure, the controller 130 may assign a second memory command to the auxiliary command processor 250b in accordance with the above description. Figure 3BThe accumulated computational credit value 330b associated with the auxiliary command processor 250b is modified in a similar manner to that described by reference numeral 350. For example, controller 130 may modify the current accumulated computational credit value 330b based on the computational credit value associated with a second memory command (e.g., the accumulated computational credit value when controller 130 is determining the command processor to which a memory command will be assigned). In example 300, the second memory command is a read command, shown as "Read Command B," which contains a request to read data from two LBAs of memory. Controller 130 may determine a new accumulated computational credit value (sometimes referred to as a modified accumulated computational credit value or an updated accumulated computational credit value) based on a previous accumulated computational credit value and the computational credit value associated with the second memory command. For example, controller 130 may combine the previous accumulated computational credit value and the computational credit value associated with the assigned memory command (e.g., add them together).

[0076] exist Figure 3C In Example 300, a write command assigned to the auxiliary command processor 250b (which may be a write-dedicated command processor) is shown as requesting an LBA. The write command (“Write Command 1”) and the read command (“Read Command B”) are shown as having the same computed credit value, even though the number of LBAs requested by the write command is smaller than that of the read command. This is because in some implementations, since the write command is computationally more complex than the read command, the computed credit value associated with the write command may be greater than that of the read command, as described above.

[0077] like Figure 3D As shown in the figure, and as indicated by reference numeral 385, in some embodiments, controller 130 may determine that an assigned memory command has been executed, for example, by receiving an indication when the assigned memory command has been executed (e.g., when the execution of the assigned memory command has completed). For example, command processor 250 may notify controller 130 when a memory command was executed. In some embodiments, command processor 250 may indicate a command identifier (e.g., a command label) that identifies an executed memory command. Controller 130 may use the command identifier to identify an executed memory command.

[0078] As shown by reference numeral 390 in the figure, controller 130 can remove the computed credit value associated with the executed memory command from the accumulated computed credit value associated with the command processor 250 (e.g., the command processor 250 from which an instruction is received).

[0079] As an example, the main command processor 250a may indicate to the controller 130 that a memory command labeled "Read Command 1" has been executed. The controller 130 may then remove the computed credit value associated with "Read Command 1" from the accumulated computed credit value 330a associated with the main command processor 250a. As shown, this may cause the accumulated computed credit value 330a to no longer meet the threshold 335 (e.g., drop below the threshold 335). Therefore, if the controller 130 detects a subsequent memory command associated with the main command processor 250a (e.g., a third memory command), the controller 130 may assign the subsequent memory command to the main command processor 250a (e.g., based on further updating the accumulated computed credit value to remove the computed credit value associated with "Read Command 1").

[0080] In this way, the memory device 120 can enable performance requirements (e.g., IOPS requirements) to be met and / or enable the performance of the memory device 120 to be improved (e.g., reduced latency) without adding an additional dedicated processor to the memory device 120. Therefore, the memory device 120 described herein improves performance by better utilizing command processor resources without increasing manufacturing costs or power consumption.

[0081] As pointed out above, Figures 3A-3D Provided as an example. Other examples are available in the section about Figures 3A-3D The content is different.

[0082] Figures 4A-4B This is a diagram of instance 400 of memory command assignment based on the command processor workload. Combined with... Figures 4A-4B The described operations may be performed by memory device 120 and / or one or more components of memory device 120, such as controller 130 and / or one or more components of controller 130.

[0083] As indicated by reference numeral 405 in the accompanying drawings, controller 130 can identify historical workload information associated with memory device 120. Historical workload information may include information about the historical workload of memory device 120, such as memory commands that have been received and / or processed (e.g., executed) by memory device 120. For example, historical workload information may indicate commands processed (e.g., executed) by any command processor 250 contained within memory device 120. In some embodiments, historical workload information may indicate one or more command types of commands received, detected, or processed within a historical time period (e.g., the most recent 250 milliseconds), and / or may indicate one or more command types of a specific number of recently received, detected, or processed commands (e.g., the most recent 100 commands).

[0084] In some implementations, historical workload information may indicate (e.g., within a historical time period or within a specific number of recent commands) a first number of memory commands of a first command type that were received, detected, assigned, or executed, a second number of memory commands of a second command type that were received, detected, or executed (e.g., within the historical time period or within the specific number of recent commands), and so on. As an example, such as Figure 4A As shown, historical workload information can indicate the number of historical read commands (e.g., a count), the number of historical write commands, and / or the number of other historical commands. In Example 400 of Figure 4, the historical workload information indicates that 91 read commands, 6 write commands, and 3 other commands (e.g., non-read, non-write commands) were detected and / or executed within a historical time period (e.g., associated with a time window or a certain number of commands). These command types are provided as examples, and the historical workload information may include information on one or more other command types, such as those mentioned above. Figures 3A-3D The type of command described.

[0085] As indicated by reference numeral 410 in the accompanying drawings, controller 130 may determine the percentage of historical memory commands corresponding to a particular command type among a plurality of historical memory commands indicated in the historical workload information. For example, controller 130 may determine a first percentage of historical memory commands having a first command type, a second percentage of historical memory commands having a second command type, and so on. In some embodiments, controller 130 may determine a single percentage of a single command type (e.g., a read command). Alternatively, controller 130 may determine multiple percentages corresponding to multiple command types (e.g., a read percentage of read commands, a write percentage of write commands, and so on).

[0086] As indicated by reference numeral 415 in the accompanying drawings, controller 130 may determine a ratio for allocating memory commands (e.g., for a specific command type) to a first command processor or a second command processor. This ratio is sometimes referred to as the "allocation ratio." In some embodiments, controller 130 may determine the allocation ratio based on this percentage. For example, based on the percentage of read commands indicated in historical workload information, controller 130 may determine an allocation ratio for allocating read commands to a primary command processor (e.g., a read-dedicated command processor) or an auxiliary command processor (e.g., a dedicated command processor) for read commands. Alternatively, based on the percentage of write commands indicated in historical workload information, controller 130 may determine an allocation ratio for allocating write commands to a primary command processor (e.g., a write-dedicated command processor) or an auxiliary command processor (e.g., a read-dedicated command processor) for write commands. More generally, based on the percentage of commands of a specific command type indicated in historical workload information, controller 130 may determine an allocation ratio for allocating commands of that specific command type to a primary command processor (e.g., dedicated to that specific command type) or an auxiliary command processor (e.g., not dedicated to that specific command type).

[0087] In some embodiments, memory device 120 may store a data structure (e.g., a table) in memory 140. The table may contain multiple entries, each indicating a specific percentage (e.g., 100%) or a percentage range (e.g., 90% to 100%, 80% to 90%, or less than 80%) and a specific allocation ratio corresponding to said specific percentage or percentage range. Controller 130 can identify the allocation ratio by looking up the determined percentage in the table and identifying the allocation ratio corresponding to said percentage.

[0088] As an example, Table 420 (e.g., a read allocation ratio table) indicates a 2:1 allocation ratio for read percentages equal to 100%, a 4:1 allocation ratio for read percentages less than 100% but greater than or equal to 90%, an 8:1 allocation ratio for read percentages less than 90% but greater than or equal to 80%, and a 1:0 allocation ratio for read percentages less than 80%. A 2:1 allocation ratio for read commands means that for every two read commands assigned to a dedicated read command processor (e.g., the primary command processor), one read command is assigned to a non-dedicated read command processor (e.g., an auxiliary command processor). A 4:1 allocation ratio for read commands means that for every four read commands assigned to a dedicated read command processor, one read command is assigned to a non-dedicated read command processor, and so on. A 1:0 allocation ratio for read commands means that all read commands are assigned to dedicated read command processors (e.g., no read commands are assigned to non-dedicated read command processors).

[0089] As another example, the second table 425 (e.g., a write allocation ratio table) indicates a 2:1 allocation ratio equal to 100% of the write percentage, a 3:1 allocation ratio for write percentages less than 100% but greater than or equal to 90%, a 4:1 allocation ratio for write percentages less than 90% but greater than or equal to 80%, a 5:1 allocation ratio for write percentages less than 80% but greater than or equal to 70%, and a 1:0 allocation ratio for write percentages less than 70%. Therefore, in some embodiments, different command types may be associated with different allocation tables and different correspondences between percentages (or percentage ranges) and allocation ratios. However, in some embodiments, the same table and / or the same correspondence between percentages (or percentage ranges) and allocation ratios may be used for different command types.

[0090] In Example 400, 91% of the historical commands were read commands. Therefore, as indicated by reference numeral 430, controller 130 can look up entries in Table 420 corresponding to the percentage range of 91%, shown as entries indicating a percentage less than 100% and greater than or equal to 90%. Controller 130 can identify the allocation ratio indicated in these entries, shown as an allocation ratio of 4:1. Therefore, based on the historical workload associated with memory device 120, controller 130 can assign four incoming read commands to a dedicated read command processor, then assign one incoming read command to a dedicated write command processor, then assign the next four incoming read commands to a dedicated read command processor, and so on.

[0091] Similarly, in instance 400, 6% of the historical commands are write commands. Therefore, as indicated by reference numeral 435, controller 130 can look up entries in table 425 corresponding to the percentage range of 6%, shown as entries indicating a percentage less than 70%. Controller 130 can identify the allocation ratio indicated in said entries, shown as an allocation ratio of 1:0. Therefore, based on the historical workload associated with memory device 120, controller 130 can assign all incoming write commands to a dedicated write command processor.

[0092] In this way, the memory device 120 can enable performance requirements (e.g., IOPS requirements) to be met and / or enable the performance of the memory device 120 to be improved (e.g., reduced latency) without adding an additional dedicated processor to the memory device 120. Therefore, the memory device 120 described herein improves performance by better utilizing command processor resources without increasing manufacturing costs or power consumption.

[0093] like Figure 4BAs shown in the figure, and as indicated by reference numeral 440, controller 130 can detect incoming commands, shown as six read commands (read commands 1 to 6), followed by a write command (write command 1), followed by another read command (read command 7), followed by another write command (write command 2), followed by three read commands (read commands 8 to 10). As indicated by reference numeral 445, controller 130 can distribute these incoming commands between the first command processor 250a and the second command processor 250b based on a determined allocation ratio of 4:1 for read commands and 1:0 for write commands, as described above. Figure 4A As described.

[0094] The first command processor 250a is a primary command processor for a first command type (e.g., a read command) and an auxiliary command processor for a second command type (e.g., a write command). Therefore, the first command processor 250a only processes (e.g., executes) read commands unless a workload condition is met. In Example 400, the workload condition is a historical workload condition. In some embodiments, the historical workload condition is a percentage satisfaction threshold of memory commands with command types other than the first command type (e.g., other than the read command type) indicated in historical workload information. Alternatively, the historical workload condition may be a percentage satisfaction threshold of memory commands with the second command type (e.g., the write command type) indicated in historical workload information. In Example 400, the first command processor 250a is a dedicated read command processor.

[0095] Similarly, the second command processor 250b is the primary command processor for the second command type (e.g., a write command) and an auxiliary command processor for the first command type (e.g., a read command). Therefore, the second command processor 250b only processes (e.g., executes) write commands unless a workload condition, such as a historical workload condition, is met. In some embodiments, the historical workload condition is a percentage satisfaction threshold of memory commands with command types other than the second command type (e.g., other than the write command type), as indicated in historical workload information. Alternatively, the historical workload condition may be a percentage satisfaction threshold of memory commands with the first command type (e.g., the read command type), as indicated in historical workload information. In Example 400, the second command processor 250b is a dedicated write command processor.

[0096] Therefore, the memory device 120 may include a plurality of command processors 250, as described elsewhere herein. Each of the plurality of command processors 250 may be configured to execute only commands contained in a set of commands (e.g., a set of one or more commands) associated with the command processor 250, unless historical workload conditions are met.

[0097] like Figure 4B As shown, when a read command is detected by the controller 130, the controller 130 can allocate those read commands between the first command processor 250a and the second command processor 250b in a ratio of 4:1 (e.g., for every one read command assigned to the second command processor 250b, four read commands are assigned to the first command processor 250a). Therefore, as indicated by reference numeral 450, the controller 130 can assign the first four read commands (read commands 1 to 4) to the first command processor 250a. As indicated by reference numeral 455, after assigning four read commands to the first command processor 250a, the controller 130 can assign the next read command (read command 5) to the second command processor 250b. As shown by reference numeral 460 in the attached figure, after assigning a read command to the second command processor 250b, the controller 130 then assigns a read command to the first command processor 250a, shown as read command 6 (for example, one of four read commands is assigned to the first command processor 250a before assigning the read command to the second command processor 250b).

[0098] The next command after read command 6 is a write command, shown as write command 1. Because controller 130 allocates write commands between the second command processor 250b and the first command processor 250a at an allocation ratio of 1:0 (e.g., all write commands are assigned to the second command processor 250b), controller 130 assigns write command 1 to the second command processor 250b, as shown by reference numeral 465. The next command is a read command, shown as read command 7, which controller 130 assigns to the first command processor 250a (e.g., assigning two of the four read commands to the first command processor 250a before assigning the read command to the second command processor 250b), as shown by reference numeral 470. The next command is a write command, shown as write command 2, which controller 130 also assigns to the second command processor 250b according to the 1:0 allocation ratio, as shown by reference numeral 475.

[0099] The three subsequent commands following write command 2 are read commands, shown as read commands 8 through 10. According to a 4:1 allocation ratio, controller 130 assigns read commands 8 and 9 to the first command processor 250a (e.g., assigning four of the four read commands to the first command processor 250a before assigning them to the second command processor 250b), as shown by reference numeral 480. As shown by reference numeral 485, according to the 4:1 allocation ratio, controller 130 then assigns read command 10 to the second command processor 250b.

[0100] In this way, the memory device 120 can enable performance requirements (e.g., IOPS requirements) to be met and / or enable the performance of the memory device 120 to be improved (e.g., reduced latency) without adding an additional dedicated processor to the memory device 120. Therefore, the memory device 120 described herein improves performance by better utilizing command processor resources without increasing manufacturing costs or power consumption.

[0101] As pointed out above, Figures 4A-4B Provided as an example. Other examples are available in the section about Figures 4A-4B The content is different.

[0102] Figure 5 This is a flowchart of an instance method 500 associated with memory command assignment based on a command processor workload. In some embodiments, the memory device (e.g., memory device 120) is executable or configurable to perform... Figure 5 One or more process blocks. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), may perform or be configured to perform the process. Figure 5 One or more process frames. Alternatively, one or more components of the memory device (e.g., controller 130, command processor 250, memory management component 260, command assignment component 270, and / or workload determination component 280) may be executable or configurable to execute... Figure 5 One or more process frames.

[0103] like Figure 5 As shown, method 500 may include detecting a memory command to be executed (block 510). Figure 5 As further shown, method 500 may include determining the command type of a memory command, wherein the command type is one of a first command type or a second command type (box 520). Figure 5As further shown, method 500 may include identifying a primary command processor associated with a command type, wherein the primary command processor is one of a plurality of command processors configured to execute memory commands of a memory device, and wherein the primary command processor is configured to execute only commands having a first command type, unless a first computational credit condition associated with another command processor of the plurality of command processors is satisfied (block 530). Figure 5 As further shown, method 500 may include determining a cumulative calculated credit value associated with the main command processor based on a memory command assigned to the main command processor (box 540). Figure 5 As further shown, method 500 may include selectively assigning memory commands to a primary command processor or an auxiliary command processor among the plurality of command processors based on whether the accumulated calculated credit value meets a threshold, wherein the auxiliary command processor is configured to execute only commands with a second command type unless a second calculated credit condition associated with another command processor among the plurality of command processors is met (block 550).

[0104] although Figure 5 An instance box of method 500 is shown, but in some implementations, compared to Figure 5 The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner in method 500. Alternatively, two or more boxes in method 500 may be executed simultaneously. Method 500 is an example of a method that can be performed by one or more means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein, such as in combination with... Figures 3A-3D The operations described in 4A-4B, 6 and / or 7.

[0105] Figure 6 This is a flowchart of an instance method 600 associated with memory command assignment based on a command processor workload. In some embodiments, the memory device (e.g., memory device 120) is executable or configurable to perform... Figure 6 One or more process blocks. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), may perform or be configured to perform the process. Figure 6 One or more process frames. Alternatively, one or more components of the memory device (e.g., controller 130, command processor 250, memory management component 260, command assignment component 270, and / or workload determination component 280) may be executable or configurable to execute... Figure 6 One or more process frames.

[0106] like Figure 6As shown, method 600 may include determining a first command type (block 610) of a first memory command to be executed by the memory device. Figure 6 As further shown, method 600 may include identifying a first command processor associated with a first command type, wherein the first command processor is one of a plurality of command processors configured to execute memory commands of a memory device, and wherein the first command processor is configured to execute only commands having the first command type, unless a computational credit condition associated with another command processor of the plurality of command processors is satisfied (block 620). Figure 6 As further shown, method 600 may include determining that a cumulative computed credit value associated with the first command processor does not meet a condition, wherein the cumulative computed credit value is based on one or more computed credit values ​​corresponding to one or more memory commands assigned to the first command processor for execution (box 630). Figure 6 As further shown, method 600 may include assigning a first memory command to the first command processor for execution based on determining that the accumulated calculated credit value associated with the first command processor does not meet the conditions (block 640).

[0107] although Figure 6 An example box of method 600 is shown, but in some implementations, compared to Figure 6 The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner in method 600. Alternatively, two or more boxes in method 600 may be executed simultaneously. Method 600 is an example of a method that can be performed by one or more means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein, such as in combination with... Figures 3A-3D The operations described in 4A-4B, 5 and / or 7.

[0108] Figure 7 This is a flowchart of an instance method 700 associated with memory command assignment based on a command processor workload. In some embodiments, the memory device (e.g., memory device 120) is executable or configurable to perform... Figure 7 One or more process blocks. In some embodiments, another device or set of devices, separate from or including the memory device (e.g., system 100), may perform or be configured to perform the process. Figure 7 One or more process frames. Alternatively, one or more components of the memory device (e.g., controller 130, command processor 250, memory management component 260, command assignment component 270, and / or workload determination component 280) may be executable or configurable to execute... Figure 7 One or more process frames.

[0109] like Figure 7 As shown, method 700 may include historical workload information identifying multiple command processors configured to execute memory commands of the device, wherein the historical workload information indicates multiple memory commands received or detected by the device (block 710). Figure 7 As further shown, method 700 may include determining the percentage of memory commands of a first command type included in the plurality of memory commands (block 720). Figure 7 As further shown, method 700 may include determining a ratio based on the percentage to allocate memory commands of the first command type to a first command processor or a second command processor, wherein the first command processor is included in the plurality of command processors and configured to execute commands having the first command type, and wherein the second command processor is included in the plurality of command processors and configured to execute only commands having a second command type different from the first command type, unless historical workload conditions associated with historical workload information are met (block 730). Figure 7 As further shown, method 700 may include allocating a plurality of incoming memory commands between a first command processor and a second command processor based on the ratio (block 740).

[0110] although Figure 7 An example box of method 700 is shown, but in some implementations, compared to Figure 7 The boxes depicted herein may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner in method 700. Alternatively, two or more boxes in method 700 may be executed simultaneously. Method 700 is an example of a method that can be performed by one or more means described herein. The one or more means may perform or be configured to perform one or more other methods based on the operations described herein, such as in combination with... Figures 3A-3D The operations described in 4A-4B, 5 and / or 6.

[0111] Figure 8 This is a diagram illustrating an example system in which the memory device 120 described herein can be used. In some embodiments, one or more memory devices 120 may be contained within memory chips. Multiple memory chips may be packaged together and contained in a higher-level system, such as a solid-state drive (SSD) or another type of memory drive. Each SSD may contain, for example, up to five memory chips, up to ten memory chips, or more. Data center or cloud computing environments may contain multiple SSDs to store large amounts of data. For example, a data center may contain hundreds, thousands, or more SSDs.

[0112] As described above, some of the embodiments described herein reduce the power consumption of memory device 120. For example... Figure 8As shown, this reduced power consumption drives the sustainability of the data center and generates energy savings due to the large number of memory devices 120 contained in the data center.

[0113] As pointed out above, Figure 8 Provided as an example. Other examples are available in the section about Figure 8 The content is different.

[0114] In some embodiments, a memory device includes one or more components configured to: detect a memory command to be executed; determine a command type of the memory command, wherein the command type is one of a first command type or a second command type; identify a primary command processor associated with the command type, wherein the primary command processor is one of a plurality of command processors configured to execute memory commands of the memory device, and wherein the primary command processor is configured to execute only commands of the first command type unless a first computational credit condition associated with another command processor of the plurality of command processors is satisfied; determine a cumulative computational credit value associated with the primary command processor based on the memory command assigned to the primary command processor; and selectively assign the memory command to the primary command processor or an auxiliary command processor of the plurality of command processors based on whether the cumulative computational credit value meets a threshold, wherein the auxiliary command processor is configured to execute only commands of the second command type unless a second computational credit condition associated with another command processor of the plurality of command processors is satisfied.

[0115] In some embodiments, a method includes: determining, via a memory device, a first command type of a first memory command to be executed by the memory device; identifying, via the memory device, a first command processor associated with the first command type, wherein the first command processor is one of a plurality of command processors configured to execute memory commands of the memory device, and wherein the first command processor is configured to execute only commands having the first command type, unless a computational credit condition associated with another of the plurality of command processors is satisfied; determining, via the memory device, that a cumulative computational credit value associated with the first command processor does not satisfy the condition, wherein the cumulative computational credit value is based on one or more computational credit values ​​corresponding to one or more memory commands assigned to the first command processor for execution; and, based on determining that the cumulative computational credit value associated with the first command processor does not satisfy the condition, assigning the first memory command to the first command processor for execution via the memory device.

[0116] In some embodiments, a device includes: means for identifying historical workload information of a plurality of command processors configured to execute memory commands of the device, wherein the historical workload information indicates a plurality of memory commands received or detected by the device; means for determining a percentage of memory commands of a first command type included in the plurality of memory commands; means for determining a ratio for allocating memory commands of the first command type to a first command processor or a second command processor based on the percentage, wherein the first command processor is included in the plurality of command processors and configured to execute commands of the first command type, and wherein the second command processor is included in the plurality of command processors and configured to execute only commands of a second command type different from the first command type, unless historical workload conditions associated with the historical workload information are met; and means for allocating a plurality of incoming memory commands between the first command processor and the second command processor based on the ratio.

[0117] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the implementation schemes to the precise forms disclosed. Modifications and variations can be made based on the foregoing disclosure, or from the practice of the implementation schemes described herein.

[0118] As used in this article, “meeting the threshold” can refer to a value that is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, etc., depending on the context.

[0119] Even if a specific combination of features is recited in the claims and / or disclosed in the specification, such combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, this disclosure includes each dependent claim in the claim set, as well as each other individual claim in the claim set and each combination of multiple claims. As used herein, the phrase “at least one of” in the list of items refers to any combination of these items containing a single member. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, and any combination of multiples of the same element (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other order of a, b, and c).

[0120] Unless explicitly stated otherwise, no element, action, or instruction used herein should be considered critical or necessary. Furthermore, as used herein, “a” (articles “a” and “an”) is intended to include one or more items and is interchangeable with “one or more”. Similarly, as used herein, “the” (article “the”) is intended to include one or more items referenced in conjunction with “the” and is interchangeable with “the one or more”. If only one item is expected, then the phrase “only one,” “single,” or similar language is used. Furthermore, as used herein, terms such as “has / have / having” are expected to be open-ended terms and do not limit the elements they modify (e.g., an element “having” A may also have B). Additionally, unless explicitly stated otherwise, the phrase “based on” means “at least partially based on.” As used herein, the term “multiple” can be replaced with “a plurality of” or vice versa. Furthermore, as used herein, unless otherwise explicitly stated (e.g., if and only one of which is used), the term “or” is intended to be inclusive when used in series and is interchangeable with “and / or”.

Claims

1. A memory device comprising: One or more components configured as follows: Detect the memory command to be executed; Determine the command type of the memory command. The command type is either a first command type or a second command type; Identify the main command processor associated with the command type. The primary command processor is one of a plurality of command processors configured to execute memory commands of the memory device, and The primary command processor is configured to execute only commands of the first command type, unless a first computational credit condition associated with another command processor among the plurality of command processors is met; Based on the memory commands assigned to the main command processor, a cumulative calculated credit value associated with the main command processor is determined; as well as Based on whether the accumulated credit value meets the threshold, the memory command is selectively assigned to the main command processor or the auxiliary command processor among the plurality of command processors. The auxiliary command processor is configured to execute only commands of the second command type, unless a second computational credit condition associated with another command processor among the plurality of command processors is met.

2. The memory device of claim 1, wherein the cumulative computed credit value associated with the main command processor is based on all computed credit values ​​corresponding to all memory commands assigned to the main command processor for execution.

3. The memory device of claim 1, wherein, in order to selectively assign the memory command to the main command processor or the auxiliary command processor, the one or more components are configured to: Based on the determination that the accumulated credit value does not meet the threshold, the memory command is assigned to the main command processor; and The one or more components are further configured to: The memory command is assigned to the main command processor, and the accumulated calculated credit value associated with the main command processor is modified based on the calculated credit value associated with the memory command.

4. The memory device of claim 3, wherein the calculated credit value associated with the memory command is based on at least one of the following: The command type of the memory command, or The data transfer size indicated in the memory command.

5. The memory device of claim 3, wherein the memory command is a first memory command; and The one or more components are further configured to: Detect a second memory command to be executed, wherein the second memory command is of the same command type as the first memory command; Based on the modification of the accumulated credit value, determine the current accumulated credit value associated with the main command processor; as well as Based on whether the current accumulated credit value meets the threshold, the second memory command is selectively assigned to the main command processor or the auxiliary command processor.

6. The memory device of claim 1, wherein the cumulative calculated credit value is a first cumulative calculated credit value; In order to selectively assign the memory commands to the main command processor or the auxiliary command processor, the one or more components are configured to: Based on the determination that the first accumulated credit value meets the threshold, the memory command is assigned to the auxiliary command processor; and The one or more components are further configured to: The memory command is assigned to the auxiliary command processor, and the second cumulative calculated credit value associated with the auxiliary command processor is modified based on the calculated credit value associated with the memory command.

7. The memory device of claim 6, wherein the second calculated credit condition is that the first cumulative calculated credit value satisfies the threshold.

8. The memory device of claim 1, wherein the first computational credit condition is that another cumulative computational credit value associated with a command processor other than the main command processor satisfies the threshold.

9. The memory device of claim 1, wherein the first command type is associated with a first calculated credit value, and the second command type is associated with a second calculated credit value that is different from the first calculated credit value.

10. The memory device of claim 1, wherein the first command type is one of a read command type or a write command type, and The second command type is either the read command type or the write command type.

11. The memory device of claim 10, wherein the magnitude of the calculated credit value associated with the write command type is greater than the calculated credit value associated with the read command type.

12. A method comprising: The command type of the first memory command to be executed is determined by the memory device from either the first command type or the second command type. The memory device identifies the main command processor associated with the command type from among a plurality of command processors configured to execute memory commands of the memory device. The master command processor is configured to execute only commands of the first command type, unless a first computational credit condition associated with another command processor among the plurality of command processors is met; Based on the memory commands assigned to the main command processor, the accumulated calculated credit value associated with the main command processor is determined through the memory device, and Based on whether the accumulated credit value meets the threshold, the memory command is assigned to the main command processor or auxiliary command processor among the plurality of command processors. The auxiliary command processor is configured to execute only commands of the second command type, unless a second computational credit condition associated with another command processor among the plurality of command processors is met.

13. The method of claim 12, wherein the cumulative calculated credit value is based on a calculated credit value corresponding to all memory commands assigned to the master command processor.

14. The method of claim 12, wherein assigning the memory command to the main command processor or the auxiliary command processor comprises: The memory command is assigned to the main command processor if the accumulated credit value does not meet the threshold.

15. The method of claim 14, further comprising: The accumulated calculated credit value associated with the main command processor is modified based on assigning the memory command to the main command processor.

16. The method of claim 12, wherein assigning the memory command to the main command processor or the auxiliary command processor comprises: Based on the accumulated credit value meeting the threshold, the memory command is assigned to the auxiliary command processor.

17. The method of claim 16, further comprising: The second cumulative credit value associated with the auxiliary command processor is modified based on assigning the memory command to the auxiliary command processor.

18. The method of claim 12, wherein the calculation of the credit value is based on the first command type or the second command type.

19. The method of claim 12, wherein the calculated credit value is based on the data transfer size associated with the memory command, the data transfer size being based on the number of logical block addresses indicated in the memory command or the storage size associated with the number of logical block addresses.

20. An apparatus comprising: A component used to determine the type of memory command to be executed; A component for identifying a first command processor associated with the command type from among a plurality of command processors associated with executing a memory command; The first command processor is configured to execute only commands of the first command type, unless a first computational credit condition associated with another command processor among the plurality of command processors is met; A component for determining a cumulative calculated credit value associated with the first command processor based on a memory command assigned to the first command processor; as well as A component for determining whether to assign the memory command to the first or second command processor among the plurality of command processors based on whether the accumulated credit value meets a threshold. The second command processor is configured to execute only commands of the second command type, unless a second computational credit condition associated with another command processor among the plurality of command processors is met.

21. The apparatus of claim 20, wherein the apparatus further comprises: A component for detecting a second memory command having the same command type as the memory command; Components used to modify the cumulative calculated credit value; as well as A component for determining whether to assign the second memory command to the first command processor or the second command processor based on whether the modified cumulative credit value meets the threshold.

22. The device of claim 20, wherein the first command type is associated with a first calculated credit value and the second command type is associated with a second calculated credit value.

23. The device according to claim 20, wherein: The first command type is a read command type and the second command type is a write command type, or the first command type is a write command type and the second command type is a read command type, wherein the calculated credit value of the write command type is greater than the calculated credit value of the read command type.

24. The apparatus of claim 20, wherein the calculated credit value is based on a memory command assigned to the first command processor but not yet executed by the first command processor.

25. The device of claim 20, wherein the calculated credit value is based on: The command type of the memory command, and The data transfer size indicated in the memory command.

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