A memory verification system

Abstract

The present application relates to a memory verification system, which belongs to the field of memory verification technology, including a control module connected to a memory chip for receiving and sending signals and processing data; a device detection module connected to a control module for performing station detection on the memory chip; a verification module connected to the control module for performing functional testing on the memory chip; an indication module connected to the control module for indicating according to the signals fed back by the device detection module and the verification module; and a power supply module connected to the control module for providing power to the control module. The present application has the effect of improving the test efficiency of the memory chip.

Description

Technical Field

[0001] The present application relates to the technical field of memory verification, and in particular to a memory verification system. Background Art

[0002] Memory, also known as semiconductor memory chip, is a memory component used to store information and data. As a chip, memory is prone to failure, so it is essential to test and verify the function of the memory before using it.

[0003] The traditional memory verification method is to verify through ATE equipment, which is costly and can only verify a single chip, which is time-consuming and inefficient. The memory can also be verified through programmer software. Although this method is less costly, it can also only verify a single chip. Therefore, it is necessary to develop a method that can verify multiple memories at the same time. Summary of the invention

[0004] In order to implement verification of multiple memories simultaneously, the present application provides a memory verification system.

[0005] The memory verification system provided by the present application adopts the following technical solution:

[0006] A memory verification system includes a control module, a device detection module, a verification module, an indication module and a power supply module;

[0007] The control module is connected to the memory chip and is used for receiving and sending signals and processing data;

[0008] The device detection module is connected to the control module and is used to perform station detection on the memory chip;

[0009] The verification module is connected to the control module and is used to perform a functional test on the memory chip;

[0010] The indication module is connected to the control module and is used to give indications according to the signals fed back by the device detection module and the verification module;

[0011] The power supply module is connected to the control module and is used to provide electrical energy to the control module.

[0012] In a preferred example, the present application can be further configured as follows: the model of the control module is STM32F407VGT6; the model of the memory chip is S29GL01; the IO pins PD0-PD15 of the control module are connected to the pins DQ0-DQ15 of the memory chip; the IO pins PB0-PB15 of the control module are connected to the pins A0-A15 of the memory chip; the IO pins PC0-PC19 of the control module are connected to the pins A16-A25 of the memory chip for sending address signals; the pin PC12 of the control module is connected to the pin WE# of the memory chip; the pin PC10 of the control module is connected to the pin OE# of the memory chip; the pins PA0-PA7 of the control module are connected to the enable pin of the memory chip; the pins PE0-PE15 of the control module are connected to the pin RY / BY# of the memory chip.

[0013] In a preferred example, the present application may be further configured as follows: the device detection module is connected to the PA11 pin of the control module;

[0014] The device detection module includes a detection resistor, a detection capacitor and a detection button; the detection resistor and the detection capacitor are connected in series to a power supply, and one end of the detection capacitor away from the detection resistor is grounded; the detection button is connected in parallel to both ends of the detection capacitor;

[0015] The PA11 pin of the control module is connected to the common end of the detection resistor and the detection button.

[0016] In a preferred example, the present application can be further configured as follows: the verification module includes an erasing unit, a burning unit, and a blank checking unit;

[0017] The erasing module is connected to the A29 pin of the control module; the burning unit is connected to the A30 pin of the control module; the blank checking unit is connected to the A31 pin of the control module;

[0018] The erasing unit includes a first resistor, a first capacitor and a first button; the first resistor and the first capacitor are connected in series to a power supply, and one end of the first capacitor away from the first resistor is grounded; the first button is connected in parallel to both ends of the first capacitor; the A29 pin of the control module is connected to the common end of the first resistor and the first button;

[0019] The programming unit comprises a second resistor, a second capacitor and a second button; the second resistor and the second capacitor are connected in series to a power supply, and two ends of the second capacitor away from the second resistor are grounded; the second button is connected in parallel to both ends of the second capacitor; the A30 pin of the control module is connected to the common end of the second resistor and the second button;

[0020] The blank checking unit includes a third resistor, a third capacitor and a third button; the third resistor and the third capacitor are connected in series to a power supply, and the three ends of the third capacitor away from the third resistor are grounded; the third button is connected in parallel to the two ends of the third capacitor; the A31 pin of the control module is connected to the common end of the third resistor and the third button.

[0021] In a preferred example, the present application can be further configured as follows: the indication module includes a status indication unit and a result indication unit; the status indication unit includes a status indication resistor and a status indicator light; one end of the status indication resistor is connected to the pin RY / BY# of the memory chip, and the other end is connected to the status indicator light; the end of the status indicator light away from the status indication resistor is grounded; the result indication unit includes a result indication resistor and a result indicator light; one end of the result indicator light is connected to the control module, and the other end is connected to the result indication resistor; the end of the result indication resistor away from the result indicator light is connected to a power supply.

[0022] In a preferred example, the present application can be further configured as follows: it also includes a crystal oscillator module; the crystal oscillator module is connected to the control module to provide a clock signal.

[0023] In a preferred example, the present application can be further configured as follows: it also includes a reset module; the reset module is connected to the NRST pin of the control module; the reset module includes SW5, a reset switch, a reset capacitor and a reset resistor; one end of the SW5 is connected to the NRST pin of the control module, and the other end is connected to the common end of the reset resistor and the reset capacitor; the reset switch is connected in parallel to both ends of the reset capacitor; one end of the reset resistor is connected to a power supply, and the other end is connected to the common end of the reset capacitor and the reset switch; the end of the reset capacitor away from the reset resistor is grounded.

[0024] In a preferred example, the present application can be further configured as follows: the control module executes the following method:

[0025] Get the number and priority of memory chips;

[0026] Determine the test results of the memory chips at each station, and determine the station and number of memory chips that failed to connect according to the test results;

[0027] Determining a processing time according to the number of memory chips that failed to connect;

[0028] The replacement quantity is obtained based on the processing time and the preset verification time threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural diagram of a memory verification system in an embodiment of the present application.

[0030] Figure 2 Schematic diagram of a circuit of a memory chip according to an embodiment of the present application.

[0031] Figure 3-Figure 6 Schematic diagram of a control module according to an embodiment of the present application.

[0032] Figure 7 Schematic diagram of a circuit of a device detection module according to an embodiment of the present application.

[0033] Figure 8 It is a circuit diagram of the verification module of an embodiment of the present application.

[0034] Fig. 9 Schematic diagram of a circuit of a result indicating unit according to an embodiment of the present application.

[0035] Fig.10 Schematic diagram of a circuit of a crystal oscillator module according to an embodiment of the present application.

[0036] Fig.11 Schematic diagram of a reset module according to an embodiment of the present application.

[0037] Explanation of the accompanying drawings: 1. control module; 2. device detection module; 21. detection resistor; 22. detection capacitor; 23. detection button; 3. verification module; 31. erasing unit; 311. first resistor; 312. first capacitor; 313. first button; 32. burning unit; 321. second resistor; 322. second capacitor; 323. second button; 33. blank checking unit; 331. third resistor; 332. third capacitor; 333. third button; 4. indication module; 41. status indication unit; 411. status indication resistor; 412. status indicator light; 42. result indication unit; 421. result indication resistor; 422. result indicator light; 5. power module; 6. crystal oscillator module; 7. reset module; 71. reset switch; 72. reset capacitor; 73. reset resistor; 8. debugging interface module; 9. UART module; 10. memory chip. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] The embodiments of the present application are further described in detail below in conjunction with the drawings in the specification.

[0040] The present application embodiment discloses a memory verification system. Figure 1-Figure 11 A memory verification system includes a control module 1, a device detection module 2, a verification module 3, an indication module 4, a power module 5, a crystal oscillator module 6, a reset module 7 and a serial port module; wherein the control module 1 is connected to a memory chip 10 for receiving and sending signals and processing data; the device detection module 2 is connected to the control module 1 for performing station detection on the memory chip 10; the verification module 3 is connected to the control module 1 for performing functional test on the memory chip 10; the indication module 4 is connected to the control module 1 for indicating according to the signals fed back by the device detection module 2 and the verification module 3; the power module 5 is connected to the control module 1 for providing power to the control module 1; the crystal oscillator module 6 is connected to the control module 1 for providing a clock signal; the reset module 7 is connected to the control module 1 for realizing the reset function; the serial port module is connected to the control module 1 for interacting with the host computer; through the cooperation between the above modules, the memory chip 10 can be detected, and the functions of the memory chip 10 can be tested from three aspects: erasing, burning and checking.

[0041] In the embodiment of the present application, the control module 1 adopts an STM chip, specifically the model STM32F407VGT6; and the model of the memory chip 10 is S29GL01; this scheme aims to use the control module 1 to perform parallel testing on multiple memory chips 10, so as to achieve functional testing of multiple memory chips 10 at a lower cost and higher efficiency.

[0042] Specifically, the IO pins PD0-PD15 of the control module 1 are connected to the pins DQ0-DQ15 of the memory chip 10; the IO pins PB0-PB15 of the control module 1 are connected to the pins A0-A15 of the memory chip 10; the IO pins PC0-PC19 of the control module 1 are connected to the pins A16-A25 of the memory chip 10 for sending address signals; the pin PC12 of the control module 1 is connected to the pin WE# of the memory chip 10; the pin PC10 of the control module 1 is connected to the pin OE# of the memory chip 10; the pins PA0-PA1 ... 7 is connected to the enable pin of the memory chip 10; the pins PE0-PE15 of the control module 1 are connected to the pins RY / BY# of the memory chip 10; the above is a pin connection description for a memory chip 10; if multiple memory chips 10 need to be tested in parallel, the vacant IO pins can be used for configuration to control the enable end of the newly added memory chip 10; after the control module 1 receives the start signal, the corresponding instructions are sent to the memory chip 10 to verify the status of the device; after the verification is completed, the verification result will be fed back to the indication module 4 for display.

[0043] After the control module 1 is connected to the memory chip 10, the device detection module 2 performs station detection on the memory chips 10 on each station to determine whether each memory chip 10 has an abnormal situation; specifically, the device detection module 2 is connected to the PA11 pin of the control module 1; the device detection module 2 includes a detection resistor 21, a detection capacitor 22 and a detection button 23; the detection resistor 21 and the detection capacitor 22 are connected in series to the power supply, and the end of the detection capacitor 22 away from the detection resistor 21 is grounded; the detection button 23 is connected in parallel to both ends of the detection capacitor 22; the PA11 pin of the control module 1 is connected to the common end of the detection resistor 21 and the detection button 23; the number of memory chips 10 on the station can be detected by the device detection module 2, and then the detection signal is sent to the control module 1; after receiving the detection signal, the control module 1 operates the memory chip 10 on the station and monitors the indication bit of the memory chip 10. If the indication bit changes, it means that the memory chip 10 does not exist and the station is empty, and the information is written into the control module 1. In subsequent operations, the empty station will be skipped.

[0044] After the memory chip 10 on each workstation is inspected, the memory chip 10 is verified by the verification module 3; wherein the verification module 3 includes an erasing unit 31, a burning unit 32 and a blanking unit 33; the erasing unit 31 is connected to the A29 pin of the control module 1; the burning unit 32 is connected to the A30 pin of the control module 1; the blanking unit 33 is connected to the A31 pin of the control module 1.

[0045] The erasing unit 31 includes a first resistor 311, a first capacitor 312 and a first button 313; the first resistor 311 and the first capacitor 312 are connected in series to the power supply, and the end of the first capacitor 312 away from the first resistor 311 is grounded; the first button 313 is connected in parallel to both ends of the first capacitor 312; the A29 pin of the control module 1 is connected to the common end of the first resistor 311 and the first button 313; the burning unit 32 includes a second resistor 321, a second capacitor 322 and a second button 323; the second resistor 321 and the second capacitor 322 are connected in series to the power supply, and the second capacitor 322 is away from the second The two ends of the resistor 321 are grounded; the second button 323 is connected in parallel to the two ends of the second capacitor 322; the A30 pin of the control module 1 is connected to the common end of the second resistor 321 and the second button 323; the blank checking unit 33 includes a third resistor 331, a third capacitor 332 and a third button 333; the third resistor 331 and the third capacitor 332 are connected in series to the power supply, and the three ends of the third capacitor 332 away from the third resistor 331 are grounded; the third button 333 is connected in parallel to the two ends of the third capacitor 332; the A31 pin of the control module 1 is connected to the common end of the third resistor 331 and the third button 333.

[0046] It can be understood that in the embodiment of the present application, the erasing unit 31, the burning unit 32 and the blank checking unit 33 all include buttons, so the erasing unit 31, the burning unit 32 and the blank checking unit 33 all belong to the button circuit; by operating different buttons, the corresponding functions can be realized; wherein, the function of the erasing unit 31 is to erase the memory chip 10, when the first button 313 is pressed, the erasing unit 31 sends an erasing instruction to the control module 1, and then the control module 1 executes the erasing operation on the memory chip 10; the function of the burning unit 32 is to burn the data inside the memory chip 10, when the second button 323 is pressed, the burning unit 32 sends a burning instruction to the control module 1, and then the control module 1 executes the burning operation on the memory chip 10; the function of the blank checking unit 33 is to check whether the data inside the memory chip 10 is blank, when the third button 333 is pressed, the blank checking unit 33 sends a blank checking instruction, and then the control module 1 executes the blank checking operation on the memory chip 10.

[0047] Through the above process, operations such as station detection, erasing, blank checking and burning of the memory chip 10 can be realized; and after performing the above operations, the operation results are displayed through the indication module 4; specifically, the indication module 4 includes a state indication unit 41 and a result indication unit 42; the state indication unit 41 includes a state indication resistor 411 and a state indicator light 412, one end of the state indication resistor 411 is connected to the pin RY / BY# of the memory chip 10, and the other end is connected to the state indicator light 412; the end of the state indicator light 412 away from the state indication resistor 411 is connected to the power supply; the result indication unit 42 includes a result indication resistor 421 and a result indicator light 422; one end of the result indicator light 422 is connected to the control module 1, and the other end is connected to the result indication resistor 421; the end of the result indication resistor 421 away from the result indicator light 422 is connected to the power supply.

[0048] In the embodiment of the present application, the crystal oscillator module 6 is used to provide a clock signal; the reset module 7 is used to implement the reset function; the memory verification system of the present scheme also includes a debugging interface module 8 and a UART module 9, both of which are used to implement functions such as burning programs, debugging systems and expanding resources, and can also interact with the host computer; through a serial port debugging assistant, the burned content can be changed, and the content of the memory chip 10 can be read.

[0049] In the embodiment of the present application, the reset module 7 is connected to the NRST pin of the control module 1; the reset module 7 includes SW5, a reset switch 71, a reset capacitor 72 and a reset resistor 73; one end of SW5 is connected to the NRST pin of the control module 1, and the other end is connected to the common end of the reset resistor 73 and the reset capacitor 72; the reset switch 71 is connected in parallel to both ends of the reset capacitor 72; one end of the reset resistor 73 is connected to the power supply, and the other end is connected to the common end of the reset capacitor 72 and the reset switch 71; the end of the reset capacitor 72 away from the reset resistor 73 is grounded; the reset function of the control module 1 can be realized by the reset module 7; the reset switch 71 here is a push switch, that is, a reset button; and the NRST pin of the control module 1 has a pull-up resistor inside, so there is no need for a separate pull-up resistor, and the reset function can be realized by simply grounding the reset switch 71.

[0050] In the embodiment of the present application, when the memory chip 10 is tested using the memory verification system of the present solution, the 5V power supply is first turned on, and then the chip to be tested is placed in the corresponding test station. After confirming that the memory chip 10 has good contact, the power switch is turned on, and the memory verification system enters the standby state; then the detection button is pressed, and the control module 1 will issue a corresponding test instruction to operate the memory chips 10 of all stations, and then read back the working status of the memory chip 10; if the memory chip 10 is abnormal, the status indicator light 412 of the corresponding station will light up, indicating that the memory chip 10 is abnormal, and this station will be marked at the same time, and subsequent operations will no longer operate on this station until the reset button is pressed. , clear the failure information of the memory chip 10; and for the memory chip 10 that has no problem in the detection, subsequent operations can be performed, including burning, erasing and blank checking; among them, burning is used to verify the read and write functions of the memory chip 10, erasing is used to restore the memory chip 10 to the default state, and blank checking is used to detect whether the memory chip 10 is in a blank state; after the operation of these three steps, the function of the memory chip 10 can be confirmed to ensure that the memory chip 10 that has passed the test can read and write normally; after the verification is completed, by observing the busy position of each station, it is confirmed whether the operation of the memory chip 10 is completed; when all are completed, the system's total status indicator light 412 will light up, indicating that all stations have been tested.

[0051] In the embodiment of the present application, the following method is also executed in the control module 1, obtaining the number and priority of the memory chips 10; determining the detection results of the memory chips 10 at each workstation, and determining the workstation and number of the memory chips 10 that failed to connect based on the detection results; determining the processing time based on the number of memory chips 10 that failed to connect; and obtaining the replacement quantity based on the processing time and a preset verification time threshold.

[0052] It can be understood that in the process of parallel testing of multiple memory chips 10, the device detection module 2 is first used to detect the connection status between the memory chip 10 at each workstation and the control module 1. If the connection between the memory chip 10 and the control module 1 fails, the workstation and number of the memory chips 10 that failed to connect can be obtained through the indication module 4; for the workstation corresponding to the memory chip 10 that failed to connect, it is necessary to wait until the memory chips 10 at other workstations complete the verification process and then reset them before they can continue to be used; this will result in a problem of waste of workstations. In order to solve this problem, the following method is adopted in this solution.

[0053] The processing time is determined according to the number of memory chips 10 that fail to connect; the processing time here includes the station replacement time and the station test time; it can be understood that in the embodiment of the present application, the control module 1 is used to implement functional testing of multiple identical memory chips 10, so for the memory chips 10 on all stations, the time to connect the memory chip 10 to the station is the same, and the time to remove the memory chip 10 from the station is also the same; then it can be obtained that the time for station replacement is also the same; station replacement refers to the process of removing the memory chip 10 on the station that fails to connect from the station and reconnecting the new memory chip 10 to the empty station; and the time for connection testing of the newly replaced memory chip 10 on the station is also the same; therefore, the station replacement time mentioned above refers to the number of stations that fail to connect multiplied by the preset time for replacing the memory chip 10 at each station, and similarly, the station test time refers to the number of stations that fail to connect multiplied by the preset time for testing the memory chip 10 at each station; the processing time can be determined through the above process.

[0054] After the processing time is obtained, the sub-processing times of different quantities are determined according to the processing time; for example, the processing time refers to the overall replacement and testing time of 5 workstations with failed connections, then the replacement and testing times corresponding to 1, 2, 3, and 4 workstations with failed connections are determined according to the processing time, and the replacement time and test time of the corresponding quantity are added together to obtain the sub-processing time of the corresponding quantity; after obtaining multiple sub-processing times, they are sorted in order from short to long according to the length of different sub-processing times.

[0055] It can be understood that, for the workstation that is successfully connected, it executes the verification process of the memory chip 10 normally; for the workstation that fails to connect, it is necessary to replace the connected memory chip 10 with a new memory chip 10 and retest it; at this time, the memory chip 10 is being verified at the workstation that is successfully connected, and the verification progress at this time is obtained and the verification progress is analyzed to obtain the analysis result; the analysis result refers to the current stage of the verification progress; in the process of verifying the memory chip 10, the memory chips 10 on all workstations are erased, burned and checked in turn, then when the verification progress is obtained, the verification progress may be performing a certain operation, or it may have completed a certain operation; for example, if the verification progress is erasing, then the remaining erasure time is obtained, and the remaining erasure time is obtained here by the verification start time and the preset verification time threshold; the verification start time here refers to the time when the verification of the memory chip 10 on the workstation starts, and the preset verification time threshold here refers to the preset time corresponding to different operations; the remaining erase time Compare with each sub-processing time and processing time to obtain the sub-processing time or processing time closest to the remaining erasing time; then compare the remaining erasing time with the closest sub-processing time or processing time. If the remaining erasing time is longer, it means that a corresponding number of memory chips 10 can be replaced in the remaining erasing time; if the erasing time is 2 minutes, the closest sub-processing time is 1 minute, and 1 minute corresponds to the total replacement and testing time of the memory chips 10 on the two stations, then two stations with failed connection can be selected to replace and test the memory chips 10; after completing the replacement and testing of the memory chips 10 on these two stations, after the memory chips 10 on the remaining stations complete the erasing operation, the memory chips 10 on these two stations enter the burning operation together with the memory chips 10 on the other stations; in this way, the stations with failed connection can be fully utilized, so that they do not have to wait until all operations on the stations with successful connection are completed before being reset and used again; in this way, the success rate and efficiency of parallel testing of multiple memory chips 10 can also be improved, and the operation time can be reduced.

[0056] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the aforementioned disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present application (but not limited to) by each other to form a technical solution.

Claims

1. A memory verification system, characterized in that: It comprises a control module (1), a device detection module (2), a verification module (3), an indication module (4) and a power supply module (5); The control module (1) is connected to the memory chip (10) and is used for receiving and sending signals and processing data; The device detection module (2) is connected to the control module (1) and is used to perform station detection on the memory chip (10); The verification module (3) is connected to the control module (1) and is used to perform a functional test on the memory chip (10); The indication module (4) is connected to the control module (1) and is used to provide indication according to the signals fed back by the device detection module (2) and the verification module (3); The power supply module (5) is connected to the control module (1) and is used to provide electrical energy to the control module (1); The model of the control module (1) is STM32F407VGT6; the model of the memory chip (10) is S29GL01; the IO pins PD0-PD15 of the control module (1) are connected to the pins DQ0-DQ15 of the memory chip (10); the IO pins PB0-PB15 of the control module (1) are connected to the pins A0-A15 of the memory chip (10); the IO pins PC0-PC19 of the control module (1) are connected to the pins A0-A19 of the memory chip (10); 0), for sending address signals; the pin PC12 of the control module (1) is connected to the pin WE# of the memory chip (10); the pin PC10 of the control module (1) is connected to the pin OE# of the memory chip (10); the pins PA0-PA7 of the control module (1) are connected to the enable pin of the memory chip (10); the pins PE0-PE15 of the control module (1) are connected to the pin RY / BY# of the memory chip (10); The device detection module (2) is connected to the PA11 pin of the control module (1); The device detection module (2) comprises a detection resistor (21), a detection capacitor (22) and a detection button (23); the detection resistor (21) and the detection capacitor (22) are connected in series to a power supply, and one end of the detection capacitor (22) away from the detection resistor (21) is grounded; the detection button (23) is connected in parallel to both ends of the detection capacitor (22); The PA11 pin of the control module (1) is connected to the common end of the detection resistor (21) and the detection button (23).

2. The memory verification system according to claim 1, characterized in that: The verification module (3) comprises an erasing unit (31), a burning unit (32) and a blank checking unit (33); The erasing unit (31) is connected to the A29 pin of the control module (1); the burning unit (32) is connected to the A30 pin of the control module (1); and the blank checking unit (33) is connected to the A31 pin of the control module (1); The erasing unit (31) comprises a first resistor (311), a first capacitor (312) and a first button (313); the first resistor (311) and the first capacitor (312) are connected in series to a power supply, and one end of the first capacitor (312) away from the first resistor (311) is grounded; the first button (313) is connected in parallel to both ends of the first capacitor (312); the A29 pin of the control module (1) is connected to the common end of the first resistor (311) and the first button (313); The burning unit (32) comprises a second resistor (321), a second capacitor (322) and a second button (323); the second resistor (321) and the second capacitor (322) are connected in series to a power supply, and two ends of the second capacitor (322) away from the second resistor (321) are grounded; the second button (323) is connected in parallel to both ends of the second capacitor (322); the A30 pin of the control module (1) is connected to the common end of the second resistor (321) and the second button (323); The blank checking unit (33) comprises a third resistor (331), a third capacitor (332) and a third button (333); the third resistor (331) and the third capacitor (332) are connected in series to a power supply, and three ends of the third capacitor (332) away from the third resistor (331) are grounded; the third button (333) is connected in parallel to two ends of the third capacitor (332); and the A31 pin of the control module (1) is connected to a common end of the third resistor (331) and the third button (333).

3. The memory verification system according to claim 1, characterized in that: The indication module (4) comprises a state indication unit (41) and a result indication unit (42); the state indication unit (41) comprises a state indication resistor (411) and a state indicator light (412); one end of the state indication resistor (411) is connected to the pin RY / BY# of the memory chip (10), and the other end is connected to the state indicator light (412); the end of the state indicator light (412) away from the state indication resistor (411) is grounded; the result indication unit (42) comprises a result indication resistor (421) and a result indicator light (422); one end of the result indicator light (422) is connected to the control module (1), and the other end is connected to the result indication resistor (421); the end of the result indication resistor (421) away from the result indicator light (422) is connected to a power source.

4. The memory verification system according to claim 1, characterized in that: It also includes a crystal oscillator module (6); the crystal oscillator module (6) is connected to the control module (1) and is used to provide a clock signal.

5. The memory verification system according to claim 1, wherein: The invention also comprises a reset module (7); the reset module (7) is connected to the NRST pin of the control module (1); the reset module (7) comprises a SW5, a reset switch (71), a reset capacitor (72) and a reset resistor (73); one end of the SW5 is connected to the NRST pin of the control module (1), and the other end is connected to the common end of the reset resistor (73) and the reset capacitor (72); the reset switch (71) is connected in parallel to the two ends of the reset capacitor (72); one end of the reset resistor (73) is connected to a power supply, and the other end is connected to the common end of the reset capacitor (72) and the reset switch (71); one end of the reset capacitor (72) away from the reset resistor (73) is grounded.

6. The memory verification system according to claim 1, characterized in that: The control module (1) executes the following method: Obtaining the number and priority of memory chips (10); Determining the detection results of the memory chips (10) at each station, and determining the stations and number of the memory chips (10) that failed to connect according to the detection results; determining a processing time according to the number of memory chips (10) that failed to connect; The replacement quantity is obtained based on the processing time and the preset verification time threshold.

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