A differential VGA applied to the closed-loop drive of a micro gyroscope

Abstract

The present invention relates to the field of analog integrated circuits, and specifically to a differential VGA applied to the closed-loop drive of a micro gyroscope. The present invention is designed such that the gain change has a general linear relationship with the control voltage. Through the design, the signal can be linearly attenuated or amplified with the control voltage. Compared with the dB linear relationship, it is more suitable for precisely and stably adjusting and controlling the signal amplitude under the sinusoidal closed-loop drive of the micro gyroscope. This also avoids a large change in the 3dB bandwidth of the VGA, making the system more stable. Secondly, the design of the fully differential structure and the special operational amplifier OP1 ensures the high linearity and low distortion of the VGA. The VGA provided by the present invention realizes the precise and stable adjustment and control of the signal amplitude under the sinusoidal closed-loop drive of the micro gyroscope, effectively solving the problem of precisely and stably adjusting and controlling the amplitude existing in the existing closed-loop drive circuit of the micro gyroscope.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, and particularly to a differential VGA applied to the closed-loop drive of a micro gyroscope. Background Art

[0002] As the core circuit of an automatic gain control system, a Variable Gain Amplifier (VGA) is widely used in related fields such as communication, aerospace, and biomedical detection. A micro gyroscope is a new type of inertial device that has developed rapidly in recent years. It has many advantages such as light weight, small area, easy integration, low power consumption, fast startup, high reliability, and large-scale mass production, and has become a research hotspot in the field of inertial sensing. A micro gyroscope closed-loop drive circuit with a variable gain amplifier can achieve a sinusoidal closed-loop drive for the micro gyroscope. A sinusoidal closed-loop drive circuit with high stability and high precision can greatly improve the stability and resolution of the micro gyroscope.

[0003] The micro gyroscope drive loop consists of a sensitive structure and a drive circuit, and the two work together to form a closed-loop self-excited drive loop. Taking the capacitive silicon gyroscope in the micro gyroscope as an example, there are two sets of symmetric drive electrodes in the drive direction of the capacitive silicon gyroscope sensitive structure. These two sets of drive electrodes are fixed on the silicon gyroscope housing, and between them is a movable mass block. These two sets of symmetric drive electrodes are two sets of comb-tooth capacitors. Alternating current signals with the same amplitude and opposite polarities are applied to the two sets of drive electrodes respectively, and with the DC bias on the mass block, the two sets of comb-tooth capacitors are alternately charged and discharged, thereby generating an electrostatic driving force. The drive circuit converts the motion signal in the drive direction of the sensitive structure into an electrical signal, and after operations such as amplification, automatic gain adjustment, filtering, and offset elimination, it is fed back to the drive electrodes of the sensitive structure to generate an electrostatic driving force, thereby forming a complete closed-loop self-excited loop. The silicon gyroscope drive loop is in a resonant state during operation. Through the phase control of the interface circuit and the high-precision frequency selection characteristics of the sensitive structure, the weak disturbance signals in the loop are continuously amplified and frequency selected, and finally a high-quality drive voltage locked at the characteristic frequency in the drive direction is obtained. The above-mentioned sinusoidal closed-loop drive of the micro gyroscope requires the drive circuit to control the frequency, phase, and amplitude of the drive voltage to be stable and accurate. For the control of the amplitude, it is particularly important, as it ensures that the detection module of the silicon gyroscope system has a stable scale factor.

[0004] For the amplitude control of the sine closed-loop drive of the micro gyroscope, the VGA plays a key role in the control loop, and the performance of the VGA determines whether the amplitude control of the sine closed-loop drive is accurate and stable. For a general automatic gain control (AGC) process, it is required that the gain change of the VGA shows a dB-linear relationship with the control voltage. This dB-linear relationship makes the gain of the VGA very sensitive to the control voltage, and the control voltage has an exponential impact on the gain. However, for the sine closed-loop drive of the micro gyroscope, since the amplitude of the sine signal during self-excited oscillation is relatively stable and the disturbance change range is not large, this exponential voltage control is not required. This large change range of the exponential voltage adjustment gain is not conducive to achieving more precise adjustment and control of the sine closed-loop drive of the micro gyroscope. Moreover, the dB-linear relationship causes the bandwidth BW (3dB bandwidth) to change greatly when the VGA changes the gain (assuming the gain-bandwidth product GBW remains unchanged), resulting in a huge change in the system transfer function, which is not conducive to system stability and system design. Summary of the Invention

[0005] In view of the above problems, the present invention provides a differential VGA applied to the closed-loop drive of a micro gyroscope to solve the problem of accurately and stably adjusting and controlling the amplitude of the closed-loop drive circuit of the micro gyroscope.

[0006] A differential VGA applied to the closed-loop drive of a micro gyroscope, the specific structure includes: 4 NMOS transistors M1, M2, M3, M4, 2 resistors R D1 , R D2 , and a special operational amplifier OP1, as shown in Figure 1 . The VGA of the present invention is a differentially structured design that is symmetric left and right. The gate lengths and widths of M1 and M2 are the same, the gate lengths and widths of M3 and M4 are the same, and the resistance values of R D1 and R D2 are the same. The input signals are the VGA input differential voltages V INN , V INP , the control voltage V CTL , the power supply VDD, and the ground GND; the output signals are the VGA output differential signals V O1 , V O2 . Its function is to control the overall gain A CTL of the operational amplifier by the control voltage V V to achieve variable gain of the operational amplifier.

[0007] The gate of M1 is connected to the input differential voltage V INP , and the source of M1 is connected to the ground GND; the drain of M1 is connected to the source of M3 and the negative input terminal of the special operational amplifier OP1, and this node is denoted as node "X2" and the node voltage is denoted as "V X2 ".

[0008] The gate of M2 is connected to the input differential voltage V INN , the source of M2 is connected to the ground GND; the drain of M2 is connected to the source of M4 and the positive input terminal of the special operational amplifier OP1, and this node is denoted as node "X1" and the node voltage is denoted as "V X1 ".

[0009] The source of M3 is connected to node X2, and the gate of M3 is connected to the positive output terminal of the special operational amplifier OP1; the drain of M3 is connected to one end of the resistor R D2 and serves as one end of the differential output of the VGA. This node is denoted as node "O2" and the node voltage is denoted as "V O2 ". The other end of the resistor R D2 is connected to the power supply VDD.

[0010] The source of M4 is connected to node X1, and the gate of M4 is connected to the negative output terminal of the special operational amplifier OP1; the drain of M4 is connected to one end of the resistor R D1 and serves as the other end of the differential output of the VGA. This node is denoted as node "O1" and the node voltage is denoted as "V O1 ". The other end of the resistor R D1 is also connected to the power supply VDD.

[0011] The negative input terminal of the special operational amplifier OP1 is connected to node X2, the positive input terminal is connected to node X1, the positive output terminal is connected to the gate of M3, and the negative output terminal is connected to the gate of M4. In addition, there is a control voltage V CTL input to the special operational amplifier OP1. The special operational amplifier OP1 makes the node voltages V X1 and V X2 both stable and accurately follow the change of the control voltage V CTL , that is, the node voltages V X1 and V X2 are equal to the control voltage V CTL . By designing the control voltage V CTL such that both MOS transistors M1 and M2 operate in the triode region.

[0012] A differential VGA applied to the closed-loop drive of a micro gyroscope, and its working principle is as follows:

[0013] Since the entire VGA is a differential structure with a left-right symmetric design, the gate lengths and widths of M1 and M2 are the same, the gate lengths and widths of M3 and M4 are the same, and the resistance values of R D1 and R D2 are the same, so one side can be analyzed, and the other side is the same. Its right-side structure is as follows:

[0014] According to the MOS transistor triode region current formula I = u n C OX (W / L)[(VGS -V TH )V DS -0.5×V DS 2 It can be seen that at this time, the gate-source voltage V of M2 GS = V INN , and the drain-source voltage V DS = V CTL , that is, the drain-source current of M1 is I = u n C OX (W / L)[(V INN -V T H )V CTL -0.5×V CTL 2 .

[0015] The VGA outputs a voltage at node O1. At this time, the output resistance R at node O1 OUT is the resistance R seen looking up from node O1 D1 in parallel with the resistance formed by M4 and M2 seen looking down. The resistance seen looking down is much larger than the resistance seen looking up. Therefore, the output resistance R OUT = R D1 , and the output voltage V O1 = VDD - I×R OUT = VDD - I×R D1 . From this, the derivative of the VGA output voltage V O1 with respect to the VGA input voltage V INN can be obtained, and the voltage amplification factor, that is, the gain A V = d(V O1 ) / d(V INN ) = u n C OX (W / L)R D1 ×V CTL . That is, the control voltage V CTL is used to control the magnitude of the overall operational amplifier gain A V . And it can be seen that the coefficient u CTL of the control voltage V n C OX (W / L)R D1 is a process parameter and a design parameter, which is very stable and does not change with the circuit state. Through the above design, the control voltage V CTL can control the gain A V to be less than 1, and the control voltage V CTL can control the gain A V to be greater than 1. That is, the signal is linearly attenuated or amplified with the control voltage, and the control voltage V CTL realizes stable and precise control of the gain A V .

[0016] Furthermore, the special operational amplifier OP1 is of a fully differential structure, and its internal structure is specifically as follows Figure 2 shown. The special operational amplifier OP1 includes: 18 MOS transistors M5 to M22, where M5 to M15 are PMOS transistors and M16 to M22 are NMOS transistors. I B is a bias current source; M5 to M15 all operate in the saturation region.

[0017] Its function is to make the node voltages V X1 and V X2 both stably and accurately follow the control voltage V CTL variation, that is, the voltages of the node voltages V X1 and V X2 are equal to the control voltage V CTL . The input signals of the special operational amplifier OP1 are the input differential voltages VIP and VIN of the special operational amplifier OP1, the control voltage V CTL , the power supply VDD, and the ground GND; the output signals are the output differential signals VOP and VON of the special operational amplifier OP1.

[0018] As Figure 2 shown, from left to right, the connection relationships of the longitudinal branches in the special operational amplifier OP1 are described in sequence.

[0019] The source of M10 is connected to the power supply VDD, the gate of M10 is short-circuited to its drain and connected to one end of the bias current source I B , and the other end of the bias current source I B is connected to the ground GND.

[0020] The source of M11 is connected to the power supply VDD, the gate of M11 is connected to the gate of M10, the drain of M11 is connected to the drain of M16, the gate-drain of M16 is short-circuited and connected to the gates of M17 and M18, and the source of M16 is grounded.

[0021] The source of M12 is connected to the power supply VDD, the gate of M12 is connected to the gate of M10, the drain of M12 is connected to the sources of M5, M6, and M7; the gate of M5 is connected to the control voltage V CTL , the drain of M5 is connected to the drain of M19; the gate-drain of M19 is short-circuited, and the source of M19 is grounded. The gate of M6 is connected to the input differential voltage VIN of the special operational amplifier OP1, the drain of M6 is connected to the drain of M20; the gate of M7 is connected to the input differential voltage VIP of the special operational amplifier OP1, the drain of M7 is connected to the drain of M20; the gate-drain of M20 is short-circuited, and the source of M20 is grounded.

[0022] The source of M13 is connected to the power supply VDD, the gate of M13 is connected to the gate of M10, and the drain of M13 is connected to the sources of M8 and M9; the gate of M8 is connected to the input differential voltage VIP of the special operational amplifier OP1, and the drain of M8 is connected to the drain of M21; the gate of M21 is connected to the drain of M19 and the gate of M22, and the source of M21 is grounded; the gate of M9 is connected to the input differential voltage VIN of the special operational amplifier OP1, and the drain of M9 is connected to the drain of M22; the gate of M22 is connected to the drain of M19 and the gate of M21, and the source of M22 is grounded.

[0023] The source of M14 is connected to the power supply VDD, the gate of M14 is connected to the gate of M10, the drain of M14 is connected to the drain of M17, and the connection between the drain of M14 and the drain of M17 serves as the output differential signal VON of the special operational amplifier OP1; the gate of M17 is connected to the gates of M16 and M18, and the source of M17 is connected to the drains of M21 and M8.

[0024] The source of M15 is connected to the power supply VDD, the gate of M15 is connected to the gate of M10, the drain of M15 is connected to the drain of M18, and the connection between the drain of M15 and the drain of M18 serves as the output differential signal VOP of the special operational amplifier OP1; the gate of M18 is connected to the gates of M16 and M17, and the source of M18 is connected to the drains of M22 and M9. The gates of M10, M11, M12, M13, M14, and M15 are all connected together.

[0025] In the special operational amplifier OP1, M10 to M15 form a current mirror, and M11 to M15 copy the unit current of M10, that is, the bias current source I B , and the current magnitude is denoted as Ib. It is designed that the gate lengths of M10 to M15 are the same, and the gate widths are different and proportional, that is, the replication ratios of the current mirror are different. It is designed that the gate width ratio of M10:M11:M12:M13:M14:M15 is 1:1:2:2:1:1, that is, the drain-source current ratios flowing through M10 to M15 are 1:1:2:2:1:1. The drain-source current of M10 is Ib, the drain-source current of M11 is Ib, the drain-source current of M12 is 2Ib, the drain-source current of M13 is 2Ib, the drain-source current of M14 is Ib, and the drain-source current of M15 is Ib. M19, M21, and M22 also form a current mirror. Then, it is designed that the gate lengths of M19, M20, M21, and M22 are the same, and the gate width ratio of M19:M20:M21:M22 is 1:1:2:2. To achieve the purpose that both the VIP and VIN voltages are stable and accurately follow the control voltage V CTL , it is designed that the gate lengths of M5 to M9 are the same, and the gate widths are different and proportional. It is designed that the gate width ratio of M5:M6:M7:M8:M9 is 2:1:1:1:1.

[0026] Analyze the currents in each vertical branch: For the currents flowing through M8 and M9, according to the MOS transistor saturation region current formula I = 0.5u p C OX (W / L)(V GS -V TH ) 2 it can be known that since VIP and VIN have the same common-mode voltage, the MOS transistor width-to-length ratios of M8 and M9 are the same, the process parameters are the same, and the gate-source voltages are the same. Therefore, the currents flowing through M8 and M9 are the same, both being Ib. For the current flowing through M21, it is the sum of the currents flowing through M14 and M8, which is 2Ib. Similarly, for the current flowing through M22, it is the sum of the currents flowing through M15 and M9, which is 2Ib. For the current flowing through M19, the current mirror formed by M19, M21, and M22 makes the current flowing through M19 be Ib. For the current flowing through M20, the sum of the currents flowing through M20 and M19 is the current value of M12, which is 2Ib. Then the current flowing through M20 is 2Ib - Ib = Ib. Furthermore, according to the ratio of the gate widths of M5 to M9, the drain-source currents flowing through M5 to M9 can be calculated. The drain-source current of M5 is Ib, the drain-source current of M6 is 0.5Ib, the drain-source current of M7 is 0.5Ib, the drain-source current of M8 is Ib, and the drain-source current of M9 is Ib. The above M5 to M15 all operate in the saturation region.

[0027] According to the MOS transistor saturation region current formula I = 0.5u p C OX (W / L)(V GS -V TH ) 2 it can be known that from the above current relationship and MOS transistor width-to-length ratio relationship, for M5 to M9, the gate-source voltages are the same, and the sources of M5 to M9 are connected together. Then the gate voltages of M5 to M9 are the same, that is, the control voltage V CTL , VIP, and VIN voltages are the same. Thus, the voltages of VIP and VIN are both stable and accurately follow the control voltage V CTL , that is, the external node voltages V X1 and V X2 are both stable and accurately follow the control voltage V CTL .

[0028] This special operational amplifier OP1 is a fully differential structure. The input stage consists of M6 to M9 forming a folded input pair transistor. M8, M9 and M17, M18 form a Cascode structure. M21 and M22 are the load transistors of the branch. This Cascode structure makes the gain of the operational amplifier higher and the performance better. At the same time, M5, M6, M7, M19, M20, M21, and M22 also form a common-mode negative feedback (CMFB) loop. The common-mode negative feedback makes the common-mode of the operational amplifier more stable.

[0029] For the VGA of the present invention, in order to achieve precise and stable regulation and control of the signal amplitude under the sinusoidal closed-loop drive of the micro gyroscope, the VGA is designed such that the gain change has a general linear relationship with the control voltage. This general linear relationship means that the VGA gain, i.e., the amplification factor, changes linearly with the control voltage V CTL changes in a linear function. Through design, the signal can be linearly attenuated or amplified with the control voltage. Compared with the dB linear relationship, when the control voltage of the VGA changes, it will not exponentially affect the gain change significantly, so the signal waveform and amplitude will not change greatly, making it more suitable for precise and stable regulation and control of the signal amplitude under the sinusoidal closed-loop drive of the micro gyroscope. At the same time, assuming that the gain-bandwidth product GBW remains unchanged, since the VGA is designed such that the gain change has a general linear relationship with the control voltage, the change in the control voltage will not cause the bandwidth BW (3dB bandwidth) to change as much as in the dB linear relationship. This design can ensure better system stability, that is, the system transfer function is more stable, which is beneficial to the design of the overall micro gyroscope closed-loop drive system.

[0030] The VGA of the present invention has a variety of special designs to ensure high linearity and low distortion of the VGA. The VGA of the present invention is a fully differential structure, which effectively suppresses common-mode interference. Secondly, due to the special operational amplifier OP1, the node voltages V X1 and V X2 are both stable and accurately follow the control voltage V CTL , that is, when the control voltage V CTL remains unchanged, the drain-source voltages VDS of M1 and M2 remain unchanged, and M1 and M2 are both in the triode region. According to the MOS transistor triode region current formula I = u n C OX (W / L)[(V GS -V TH )V DS -0.5×V DS 2 , it can be seen that the current is uniquely determined by the changing gate-source voltage V GS . For a general MOS transistor, when the gate-source voltage V GS changes, the drain-source voltage VDS will change. The input signal VIN from the gate of the MOS transistor will cause both the gate-source voltage V GS and the drain-source voltage VDS to be functions of the input signal VIN, that is, the current I is a function of the input signal VIN. From the above triode region current formula, it can be seen that this function is not a linear relationship. This non-linearity will cause distortion of the input signal. In the VGA of the present invention, the current is determined by the changing gate-source voltages V GSThe unique determination is that other values are fixed values. The input signal is input from the gates of M1 and M2, that is, the current I is a first-order linear function of the input signal VIN. This linear relationship can greatly improve the linearity of the output signal and suppress the distortion of the output signal. The linearity of this output signal and the degree of distortion can be obtained by performing a Fourier transform on the output signal to obtain a spectrogram, and calculating the Total Harmonic Distortion (THD) and the Spurious Free Dynamic Ratio (SFDR) for intuitive representation.

[0031] Further, a resistive feedback operational amplifier is connected to the next stage of the differential VGA applied to the closed-loop drive of the micro gyroscope to improve the gain of the overall VGA. The resistive feedback operational amplifier is specifically as Figure 1 shown, including: 4 resistors R IN1 , R IN2 , R F1 , R F2 , and an operational amplifier OP2; the input signal of the resistive feedback operational amplifier is the differential output signal V O1 , V O2 of the VGA, and the input common-mode signal is V CM ; the output signal is the overall VGA output signal V OUT . Its function is to form a stable amplification gain through the negative feedback of the resistor network to achieve signal amplification.

[0032] The VGA output node O1 is connected to one end of the resistor R IN1 , the other end of the resistor R IN1 is connected to the positive input end of the operational amplifier OP2 and one end of the resistor R F1 , and the other end of the resistor R F1 is connected to the negative output end of the operational amplifier OP2; the VGA output node O2 is connected to one end of the resistor R IN2 , the other end of the resistor R IN2 is connected to the negative input end of the operational amplifier OP2 and one end of the resistor R F2 , and the other end of the resistor R F2 is connected to the positive output end of the operational amplifier OP2. The differential signal between the positive and negative output ends of the operational amplifier OP2 is the output signal V OUT of the overall VGA. V CM is input into the operational amplifier OP2 to stabilize its output common-mode voltage.

[0033] The input end of the resistive feedback operational amplifier forms a cross with the output end of the VGA to ensure that the input phase and the output phase of the overall VGA do not flip. V CM is input into the operational amplifier OP2 to ensure the common-mode stability of the overall VGA output signal V OUT .

[0034] Design resistor R IN1 = R IN2 、R F1 = R F2 Four resistors R IN1 、R IN2 、R F1 、R F2 form a resistor negative feedback network, determining that the amplification factor of the resistive feedback operational amplifier is A V2 = R F1 / R IN1 = R F2 / R IN2 。Combined with the previous stage VGA, the output resistance R at the output node O1 of the VGA at this time OUT is the resistance looking up from node O1 in parallel with the resistance looking down and then in parallel with R IN1 (or R IN2 ), the resistance looking down is much larger than the resistance looking up and R IN1 (or R IN2 ), so the output resistance R OUT = R D1 / / R IN1 = R D2 / / R IN2 , the output voltage V O1 = VDD - I×R OUT = VDD - I×(R D1 / / R IN1 ) = VDD - I×(R D2 / / R IN2 ), then the gain A of the previous stage VGA V = u n C OX (W / L)(R D1 / / R IN1 )×V CTL , the overall VGA gain can be calculated as A V _total = A V ×A V2 = u n C OX (W / L)(R D1 / / R IN1 )×(R F1 / R IN1 )×V CTL 。It can be seen that by setting the ratio of appropriate R F1 and R IN1 , a larger gain can be obtained without changing the linear control relationship of the VGA.

[0035] In summary, the differential VGA applied to the closed-loop drive of a micro-gyroscope provided by the present invention is designed such that the gain change has a general linear relationship with the control voltage. Through the design, the signal can be linearly attenuated or amplified with the control voltage. Compared with the dB linear relationship, it is more suitable for accurately and stably adjusting and controlling the signal amplitude under the sinusoidal closed-loop drive of the micro-gyroscope. This also avoids a large change in the 3dB bandwidth of the VGA, making the system more stable. Secondly, the design of the fully differential structure and the special operational amplifier OP1 ensures the high linearity and low distortion of the VGA. Therefore, the VGA of the present invention can achieve accurate and stable adjustment and control of the signal amplitude under the sinusoidal closed-loop drive of the micro-gyroscope. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of the overall structure of the present invention.

[0037] Figure 2 is a schematic diagram of the internal structure of the special operational amplifier OP1 of the present invention.

[0038] Figure 3 is a diagram of the AC simulation results of the embodiment.

[0039] Figure 4 is a diagram of the Tran simulation results of the embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0041] A differential VGA applied to the closed-loop drive of a micro-gyroscope has a structure as Figure 1 shown, including four NMOS transistors M1, M2, M3, M4, two resistors R D1 , R D2 , and a special operational amplifier OP1, which is a differentially structured design symmetric about the left and right. Among them, M1 and M2 have the same gate length and width, M3 and M4 have the same gate length and width, and R D1 and R D2 have the same width and length. The input signals are the VGA input differential voltages V INN , V INP , the control voltage V CTL , the power supply VDD, and the ground GND; the output signals are the VGA output differential signals V O1 , V O2 . By controlling the control voltage V CTL , the magnitude of the overall op-amp gain A V is controlled to achieve variable gain of the operational amplifier.

[0042] The gate of M1 is connected to the input differential voltage V INP, the source of M1 is connected to the ground GND; the drain of M1 is connected to the source of M3 and the negative input terminal of the special operational amplifier OP1, and this node is denoted as node X2, and the node voltage is denoted as V X2 .

[0043] The gate of M2 is connected to the input differential voltage V INN , the source of M2 is connected to the ground GND; the drain of M2 is connected to the source of M4 and the positive input terminal of the special operational amplifier OP1, and this node is denoted as node X1, and the node voltage is denoted as V X1 .

[0044] The source of M3 is connected to node X2, and the gate of M3 is connected to the positive output terminal of the special operational amplifier OP1; the drain of M3 is connected to one end of the resistor R D2 and serves as one end of the differential output of the VGA, and this node is denoted as node O2, and the node voltage is denoted as V O2 ; the other end of the resistor R D2 is connected to the power supply VDD.

[0045] The source of M4 is connected to node X1, and the gate of M4 is connected to the negative output terminal of the special operational amplifier OP1; the drain of M4 is connected to one end of the resistor R D1 and serves as the other end of the differential output of the VGA, and this node is denoted as node O1, and the node voltage is denoted as V O1 ; the other end of the resistor R D1 is also connected to the power supply VDD.

[0046] The negative input terminal of the special operational amplifier OP1 is connected to node X2, the positive input terminal is connected to node X1, the positive output terminal is connected to the gate of M3, and the negative output terminal is connected to the gate of M4. In addition, there is a control voltage V CTL input to the special operational amplifier OP1; the special operational amplifier OP1 makes the node voltages V X1 and V X2 both stable and accurately follow the control voltage V CTL change, that is, the node voltages V X1 and V X2 are equal to the control voltage V CTL , and by designing the control voltage V CTL it is ensured that both MOS transistors M1 and M2 operate in the triode region.

[0047] In this embodiment, the internal structure of the special operational amplifier OP1 is as Figure 2 shown, which is a fully differential structure, specifically including 18 MOS transistors M5 to M22. M5 to M15 are PMOS transistors, and M16 to M22 are NMOS transistors. I B is a bias current source; M5 to M15 all operate in the saturation region. The input signals of OP1 are the input differential voltages VIP and VIN, and the control voltage V CTL, power supply VDD, ground GND; the output signals are output differential signals VOP and VON.

[0048] In the special operational amplifier OP1, M10 to M15 form a current mirror, and M11 to M15 copy the unit current of M10, that is, the bias current source I B , and the current magnitude is denoted as Ib. It is designed that the gate lengths of M10 to M15 are the same, and the gate widths are different and proportional, that is, the replication ratio of the current mirror is different; the gate width ratio of M10:M11:M12:M13:M14:M15 is 1:1:2:2:1:1, that is, the drain-source current ratio flowing through M10 to M15 is 1:1:2:2:1:1. The drain-source current of M10 is Ib, the drain-source current of M11 is Ib, the drain-source current of M12 is 2Ib, the drain-source current of M13 is 2Ib, the drain-source current of M14 is Ib, and the drain-source current of M15 is Ib. M19, M21, and M22 also form a current mirror. Then, it is designed that the gate lengths of M19, M20, M21, and M22 are the same, and the gate width ratio of M19:M20:M21:M22 is 1:1:2:2. To achieve the purpose that both VIP and VIN voltages are stable and accurately follow the control voltage V CTL , it is designed that the gate lengths of M5 to M9 are the same, and the gate widths are different and proportional. The gate width ratio of M5:M6:M7:M8:M9 is designed to be 2:1:1:1:1.

[0049] In this embodiment, a resistive feedback operational amplifier is connected to the stage after the VGA to improve the gain of the overall VGA. The resistive feedback operational amplifier is specifically as Figure 1 shown. The input signal of the resistive feedback operational amplifier is the VGA output differential signals V O1 , V O2 , and the input common-mode signal V CM ; the output signal is the overall VGA output signal V OUT . Its function is to form a stable amplification gain through the negative feedback of the resistor network to achieve signal amplification.

[0050] Design the resistor R IN1 = R IN2 , R F1 = R F2 . The four resistors R IN1 , R IN2 , R F1 , R F2 form a resistor negative feedback network, which determines the amplification coefficient of the resistive feedback operational amplifier as A V2 = R F1 / R IN1 = R F2 / R IN2。The input terminal of the resistive feedback operational amplifier forms a crossover with the output terminal of the VGA to ensure that the input phase and output phase of the overall VGA do not flip. V CM Input to the inside of the operational amplifier OP2 to ensure the overall VGA output signal V OUT Common-mode stability.

[0051] In the previous-stage VGA, both M1 and M2 operate in the triode region. Taking the right side as an example, from the MOS transistor triode-region current formula I = u n C OX (W / L)[(V GS -V TH )V DS -0.5×V DS 2 , it can be known that at this time, the gate-source voltage V GS = V INN , and the drain-source voltage V DS = V CTL , that is, the drain-source current of M1 is I = u n C OX (W / L)[(V INN -V TH )V CTL -0.5×V CTL 2 . The VGA outputs a voltage at node O1. At this time, the output resistance R OUT at the VGA output node O1 is the resistance looking up from node O1 in parallel with the resistance looking down and then in parallel with R IN1 (or R IN2 ). The resistance looking down is much larger than the resistance looking up and R IN1 (or R IN2 ). Therefore, the output resistance R OUT = R D1 / / R IN1 = R D2 / / R IN2 . The output voltage V O1 = VDD - I×R OUT = VDD - I×(R D1 / / R IN1 ) = VDD - I×(R D2 / / R IN2 ). From this, the derivative of the VGA output voltage V O1 with respect to the VGA input voltage V INN can be obtained, and the voltage amplification factor, that is, the gain A V = d(V O1 ) / d(V INN ) = u n C OX (W / L)(R D1 / / RIN1 ) × V CTL 。

[0052] The amplification factor of the resistor-type feedback operational amplifier at the subsequent stage is A V2 = R F1 / R IN1 = R F2 / R IN2 . The overall VGA gain can be calculated as A V _total = A V × A V2 = u n C OX (W / L)(R D1 / / R IN1 ) × (R F1 / R IN1 ) × V CTL 。

[0053] Using the Cadence Spectre simulation design environment for verification demonstrates the feasibility of the present invention

[0054] Design the width-to-length ratios of M1 and M2. Through simulation, the u n C OX (W / L) of M1 and M2 is approximately 10.2u. Then design R D1 = R D2 = R IN1 = R IN2 = 100K, R F1 = R F2 = 1000K, that is, R D1 / / R IN1 = 50K, R F1 / R IN1 = 10. By calculation, A V _total = A V × A V2 = u n C OX (W / L)(R D1 / / R IN1 ) × (R F1 / R IN1 ) × V CTL = 10.2u × 50K × 10 = 5.1, that is, the first-order coefficient of the control voltage V CTL should be approximately 5.1

[0055] Perform an AC simulation on the VGA. The excitation source is a sinusoidal voltage with a stable amplitude and phase. Perform a sampling simulation on the control voltage V CTL from 0 to 2V, and extract the magnitude of the low-frequency gain in the Bode plot under each AC simulation to obtain A V -VCTL Relationship diagram. The simulation results of this embodiment are as Figure 3 shown, Figure 3 is A V -V CTL relationship diagram. A V and V CTL show a linear relationship. The vertical axis A V has a numerical change range of approximately 0 to 10, and its straight-line slope is approximately 5.018, which is close to the first-order coefficient 5.1 of the above theoretical derivation, indicating that the theoretical analysis is correct. The gain change of the VGA shows a general linear relationship with the control voltage, and through design, the signal can be linearly attenuated or amplified with the control voltage.

[0056] Secondly, perform a Tran simulation on the VGA, perform a Fourier transform on the output waveform to obtain a spectrogram, and calculate the total harmonic distortion THD and the spurious-free dynamic range SFDR. The simulation results are as Figure 4 shown, Figure 4 is the spectrogram of the output signal. It can be calculated that THD = 0.00175% (including the harmonic contribution within 10th order), and SFDR = 104.15 dB. This indicates that the theoretical analysis is correct, and the VGA of the present invention has high linearity and low distortion.

[0057] As can be seen from the above embodiments, a differential VGA applied to the closed-loop drive of a micro-gyroscope according to the present invention is designed such that the gain change shows a general linear relationship with the control voltage, and through design, the signal can be linearly attenuated or amplified with the control voltage. Compared with the dB linear relationship, it is more suitable for accurately and stably adjusting and controlling the signal amplitude under the sinusoidal closed-loop drive of the micro-gyroscope, which also avoids a large change in the 3dB bandwidth of the VGA and makes the system more stable. Secondly, the design of the fully differential structure and the special operational amplifier OP1 ensures the high linearity and low distortion of the VGA. Combining the above theoretical analysis and simulation verification, the VGA of the present invention effectively realizes the accurate and stable adjustment and control of the signal amplitude under the sinusoidal closed-loop drive of the micro-gyroscope.

Claims

1. A differential VGA applied to the closed-loop drive of a micro-gyroscope, characterized in that: It includes four NMOS transistors M1, M2, M3, M4, and two resistors R D1 , R D2 , and a special operational amplifier OP1; it is a differential structure designed symmetrically left and right. The gate lengths and widths of M1 and M2 are the same, the gate lengths and widths of M3 and M4 are the same, and the resistance values of R D1 and R D2 are the same; the input signals are the VGA input differential voltages V INN , V INP , the control voltage V CTL , the power supply VDD, and the ground GND; the output signals are the VGA output differential signals V O1 , V O2 ; its function is to control the gain A CTL of the overall operational amplifier by controlling the voltage V V , so as to achieve variable gain of the operational amplifier; The gate of M1 is connected to the input differential voltage V INP , the source of M1 is connected to the ground GND; the drain of M1 is connected to the source of M3 and the negative input terminal of the special operational amplifier OP1, and this node is denoted as node X2, and the node voltage is denoted as V X2 ; The gate of M2 is connected to the input differential voltage V INN , the source of M2 is connected to the ground GND; the drain of M2 is connected to the source of M4 and the positive input terminal of the special operational amplifier OP1, and this node is denoted as node X1, and the node voltage is denoted as V X1 ; The source of M3 is connected to node X2, the gate of M3 is connected to the positive output terminal of the special operational amplifier OP1; the drain of M3 is connected to one end of the resistor R D2 and serves as one end of the differential output of the VGA. This node is denoted as node O2, and the node voltage is denoted as V O2 ; the resistor R D2 's other end is connected to the power supply VDD; The source of M4 is connected to node X1, and the gate of M4 is connected to the negative output terminal of the special operational amplifier OP1; the drain of M4 is connected to one end of resistor R D1 and serves as the other end of the differential output of the VGA. This node is denoted as node O1, and the node voltage is denoted as V O1 ; the other end of resistor R D1 is also connected to the power supply VDD; The special operational amplifier OP1 has a negative input terminal connected to the node X2, a positive input terminal connected to the node X1, a positive output terminal connected to the gate of M3, and a negative output terminal connected to the gate of M4. In addition, there is a control voltage V CTL Input to the special operational amplifier OP1; the special operational amplifier OP1 makes the node voltage V X1 With V X2 Equal to the control voltage V CTL and by designing the control voltage V CTL This makes the MOS tubes M1 and M2 both work in the triode region.

2. The differential VGA applied to the closed-loop drive of a micro gyroscope according to claim 1, wherein The working principle is: The entire VGA is a differential structure with left-right symmetry design, and both sides are the same. Its right structure includes: From the MOS transistor triode region current formula I = u n C OX (W / L)[(V GS -V TH )V DS -0.5×V DS 2 , it can be seen that the gate-source voltage V GS = V INN , and the drain-source voltage V DS = V CTL , that is, the drain-source current of M1 is I = u n C OX (W / L)[(V INN -V TH )V CTL -0.5×V CTL 2 ; The VGA outputs voltage at node O1, and the output resistance R at node O1 at this time OUT is the resistance looking up from node O1 D1 in parallel with the resistance formed by looking down at resistors M4 and M2. The resistance looking down is much larger than the resistance looking up, so the output resistance R OUT = R D1 , and the output voltage V O1 = VDD - I × R OUT = VDD - I × R D1 ; From this, the derivative of the VGA output voltage V O1 with respect to the VGA input voltage V INN can be taken to obtain the voltage amplification factor, i.e., the gain A V = d(V O1 ) / d(V INN ) = u n C OX (W / L)R D1 × V CTL ; That is, the control voltage V CTL is used to control the gain A V of the overall operational amplifier. The coefficient u CTL of the control voltage V n C OX (W / L)R D1 is a process parameter and a design parameter, which does not change with the circuit state; thus, the control voltage V CTL controls the gain A V to be less than 1, and the control voltage V CTL controls the gain A V to be greater than 1. That is, the signal is linearly attenuated or amplified with the control voltage, and the control voltage V CTL stably and accurately controls the gain A V .

3. The differential VGA applied to the closed-loop drive of a micro-gyroscope according to claim 1, characterized in that: The special operational amplifier OP1 has a fully differential structure, and its internal structure is specifically as follows: it includes 18 MOS transistors M5 to M22, where M5 to M15 are PMOS transistors and M16 to M22 are NMOS transistors, and I B is a bias current source; M5 to M15 all operate in the saturation region; The input signals are respectively the input differential voltages VIP and VIN of the special operational amplifier OP1, the control voltage V CTL , the power supply VDD, and the ground GND; the output signals are the output differential signals VOP and VON of the special operational amplifier OP1; The source of M10 is connected to the power supply VDD, the gate of M10 is shorted to its drain and connected to one end of the bias current source I B ; the other end of the bias current source I B is connected to the ground GND; The source of M11 is connected to the power supply VDD, the gate of M11 is connected to the gate of M10, the drain of M11 is connected to the drain of M16, the gate and drain of M16 are short-circuited and connected to the gates of M17 and M18, and the source of M16 is grounded; The source of M12 is connected to the power supply VDD, the gate of M12 is connected to the gate of M10, and the drain of M12 is connected to the sources of M5, M6, and M7; the gate of M5 is connected to the control voltage V CTL , the drain of M5 is connected to the drain of M19; the gate and drain of M19 are shorted, and the source of M19 is grounded; the gate of M6 is connected to the input differential voltage VIN of the special operational amplifier OP1, and the drain of M6 is connected to the drain of M20; the gate of M7 is connected to the input differential voltage VIP of the special operational amplifier OP1, and the drain of M7 is connected to the drain of M20; The gate and drain of M20 are short-circuited, and the source of M20 is grounded; The source of M13 is connected to the power supply VDD, the gate of M13 is connected to the gate of M10, and the drain of M13 is connected to the sources of M8 and M9; The gate of M8 is connected to the input differential voltage VIP of the special operational amplifier OP1, and the drain of M8 is connected to the drain of M21; The gate of M21 is connected to the drain of M19 and the gate of M22, and the source of M21 is grounded; the gate of M9 is connected to the input differential voltage VIN of the special operational amplifier OP1, and the drain of M9 is connected to the drain of M22; the gate of M22 is connected to the drain of M19 and the gate of M21, and the source of M22 is grounded; The source of M14 is connected to the power supply VDD, the gate of M14 is connected to the gate of M10, the drain of M14 is connected to the drain of M17, and the connection between the drain of M14 and the drain of M17 is used as the output differential signal VON of the special operational amplifier OP1; the gate of M17 is connected to the gates of M16 and M18, and the source of M17 is connected to the drains of M21 and M8; The source of M15 is connected to the power supply VDD, the gate of M15 is connected to the gate of M10, the drain of M15 is connected to the drain of M18, and the connection between the drain of M15 and the drain of M18 is used as the output differential signal VOP of the special operational amplifier OP1; the gate of M18 is connected to the gates of M16 and M17, and the source of M18 is connected to the drains of M22 and M9; The gates of the above M10, M11, M12, M13, M14, and M15 are all connected together; Among them, M10 to M15 form a current mirror, and M11 to M15 copy the unit current of M10, that is, the bias current source I B , and the magnitude of the current is denoted as Ib; the gate lengths of M10 to M15 are the same, and the gate widths are different and proportional, that is, the copying ratios of the current mirror are different. The gate width ratio of M10:M11:M12:M13:M14:M15 is 1:1:2:2:1:1; the drain-source current of M10 is Ib, the drain-source current of M11 is Ib, the drain-source current of M12 is 2Ib, the drain-source current of M13 is 2Ib, the drain-source current of M14 is Ib, and the drain-source current of M15 is Ib; M19, M21, and M22 also form a current mirror. The gate lengths of M19, M20, M21, and M22 are the same, and the gate width ratio of M19:M20:M21:M22 is 1:1:2:2; the gate lengths of M5 to M9 are the same, the gate widths are different and in proportion, and the gate width ratio of M5:M6:M7:M8:M9 is 2:1:1:1:1; The input stage is composed of M6 to M9 to form a folded input pair tube. M8, M9 and M17, M18 form a Cascode structure. M21 and M22 are the load tubes of the branch. The Cascode structure makes the amplifier gain higher and the performance better; at the same time, M5, M6, M7, M19, M20, M21, and M22 form a common-mode negative feedback CMFB loop, and the common-mode negative feedback makes the amplifier common-mode more stable.

4. The differential VGA applied to the closed-loop drive of a micro-gyroscope according to claim 1, characterized in that: The next stage also connects to a resistive feedback operational amplifier to increase the gain of the overall VGA. The resistive feedback operational amplifier includes four resistors R IN1 , R IN2 , R F1 , R F2 , and an operational amplifier OP2. The input signal of the resistive feedback operational amplifier is the VGA output differential signals V O1 , V O2 , the input common-mode signal V CM , and the output signal is the overall VGA output signal V OUT . The VGA output node O1 is connected to one end of the resistor R IN1 ; the other end of the resistor R IN1 is connected to the positive input end of the operational amplifier OP2 and one end of the resistor R F1 ; the other end of the resistor R F1 is connected to the negative output end of the operational amplifier OP2; the VGA output node O2 is connected to one end of the resistor R IN2 ; the other end of the resistor R IN2 is connected to the negative input end of the operational amplifier OP2 and one end of the resistor R F2 ; the other end of the resistor R F2 is connected to the positive output end of the operational amplifier OP2; the differential signal between the positive and negative output ends of the operational amplifier OP2 is the output signal V of the overall VGA OUT , V CM is input into the operational amplifier OP2 to stabilize its output common-mode voltage inside; The input terminal of the resistive-feedback operational amplifier forms a crossover with the output terminal of the VGA to ensure that the input phase and output phase of the overall VGA do not flip; V CM is input into the operational amplifier OP2 to ensure the overall VGA output signal V OUT common-mode stability; Design resistor R IN1 = R IN2 、R F1 = R F2 , four resistors R IN1 、R IN2 、R F1 、R F2 form a resistor negative feedback network, determining that the amplification factor of the resistive feedback operational amplifier is A V2 = R F1 / R IN1 = R F2 / R IN2 ; then combined with the previous stage VGA, the output resistance R OUT at the output node O1 of the VGA at this time is the resistance looking up from node O1 in parallel with the resistance looking down and then in parallel with R IN1 or R IN2 , the resistance looking down is much larger than the resistance looking up and R IN1 or R IN2 , so the output resistance R OUT = R D1 / / R IN1 = R D2 / / R IN2 , the output voltage V O1 = VDD - I×R OUT = VDD - I×(R D1 / / R IN1 ) = VDD - I×(R D2 / / R IN2 ), then the gain A V of the previous stage VGA is n u OX C D1 (W / L)(R IN1 / / R CTL )×V V , then the overall VGA gain is A V _total = A V2 ×A n = u OX C D1 (W / L)(R IN1 )×(R F1 / R IN1 )×V CTL .

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